AD5684RBCPZ-RL7 [ADI]
Quad, 16-/14-/12-Bit nanoDAC; 四， 16位/ 14位/ 12位属于nanoDAC
| 型号： | AD5684RBCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Quad, 16-/14-/12-Bit nanoDAC |
| 文件： | 总32页 (文件大小：824K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, 16-/14-/12-Bit nanoDAC+
with 2 ppm/°C Reference, SPI Interface
Data Sheet
AD5686R/AD5685R/AD5684R
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High relative accuracy (INL): 2 LSB maximum @ 16 bits
Low drift 2.5 V reference: 2 ppm/°C typical
V
GND
V
REF
DD
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
2.5V
REFERENCE
AD5686R/AD5685R/AD5684R
V
LOGIC
Total unadjusted error (TUE): 0.1ꢀ of FSR maximum
Offset error: 1.5 mV maximum
STRING
DAC A
INPUT
DAC
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
REGISTER
REGISTER
SCLK
SYNC
SDIN
SDO
BUFFER
BUFFER
BUFFER
BUFFER
Gain error: 0.1ꢀ of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
INPUT
REGISTER
DAC
REGISTER
POWER-ON
RESET
GAIN
×1/×2
POWER-
DOWN
LOGIC
LDAC RESET
RSTSEL
GAIN
2.7 V to 5.5 V power supply
Figure 1.
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base-station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit
GENERAL DESCRIPTION
14-Bit
12-Bit
The AD5686R/AD5685R/AD5684R, members of the
nanoDAC+® family, are low power, quad, 16-/14-/12-bit
buffered voltage output DACs. The devices include a 2.5 V,
2 ppm/°C internal reference (enabled by default) and a gain
select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V
(gain = 2). All devices operate from a single 2.7 V to 5.5 V
supply, are guaranteed monotonic by design, and exhibit less
than 0.1% FSR gain error and 1.5 mV offset error performance.
The devices are available in a 3 mm × 3 mm LFCSP and a
TSSOP package.
SPI
I2C
Internal
Internal
AD5686R
AD5696R
AD5685R AD5684R
AD5695R AD5694R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5686R (16-bit): 2 LSB maximum
AD5685R (14-bit): 1 LSB maximum
AD5684R (12-bit): 1 LSB maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
The AD5686R/AD5685R/AD5684R also incorporate a power-
on reset circuit and a RSTSEL pin that ensures that the DAC
outputs power up to zero scale or midscale and remains there
until a valid write takes place. Each part contains a per-channel
power-down feature that reduces the current consumption of
the device to 4 μA at 3 V while in power-down mode.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
The AD5686R/AD5685R/AD5684R employ a versatile SPI
interface that operates at clock rates up to 50 MHz, and all
devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
AD5686R/AD5685R/AD5684R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Write and Update Commands.................................................. 22
Daisy-Chain Operation............................................................. 23
Readback Operation .................................................................. 23
Power-Down Operation............................................................ 24
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Daisy-Chain and Readback Timing Characteristics ............... 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 20
Digital-to-Analog Converter .................................................... 20
Transfer Function....................................................................... 20
DAC Architecture....................................................................... 20
Serial Interface ............................................................................ 21
Standalone Operation................................................................ 22
LDAC
Load DAC (Hardware
Pin)........................................... 25
Mask Register ................................................................. 25
Hardware Reset ( ) .......................................................... 26
LDAC
RESET
Reset Select Pin (RSTSEL) ........................................................ 26
Internal Reference Setup ........................................................... 26
Solder Heat Reflow..................................................................... 26
Long-Term Temperature Drift ................................................. 26
Thermal Hysteresis .................................................................... 27
Applications Information.............................................................. 28
Microprocessor Interfacing....................................................... 28
AD5686R/AD5685R/AD5684R to ADSP-BF531 Interface.. 28
AD5686R/AD5685R/AD5684R to SPORT Interface............ 28
Layout Guidelines....................................................................... 28
Galvanically Isolated Interface ................................................. 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 31
REVISION HISTORY
4/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
B Grade1
Typ
A Grade1
Typ
Parameter
STATIC PERFORMANCE2
Min
Max
Min
Max
Unit
Test Conditions/Comments
AD5686R
Resolution
Relative Accuracy
16
16
Bits
LSB
2
2
8
8
1
1
1
2
3
1
Gain = 2
Gain = 1
Differential Nonlinearity
AD5685R
LSB
Guaranteed monotonic by design
Resolution
14
12
14
12
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5684R
0.5
4
1
0.5
1
1
Guaranteed monotonic by design
Resolution
Bits
LSB
LSB
mV
mV
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
0.12
2
1
0.12
1
1
1.5
1.5
0.1
Guaranteed monotonic by design
All zeros loaded to DAC register
0.4
+0.1
+0.01
4
0.4
+0.1
+0.01
4
0.2
Full-Scale Error
% of
FSR
All ones loaded to DAC register
Gain Error
0.02
0.01
0.2
0.02
0.01
0.1
0.1
0.2
% of
FSR
% of
FSR
% of
FSR
Total Unadjusted Error
0.25
0.25
External reference; gain = 2; TSSOP
Internal reference; gain = 1; TSSOP
Offset Error Drift3
Gain Temperature
Coefficient3
1
1
1
1
µV/°C
ppm
Of FSR/°C
DC Power Supply Rejection
Ratio3
0.15
0.15
mV/V
DAC code = midscale; VDD = 5 V 10%
DC Crosstalk3
2
2
µV
Due to single channel, full-scale
output change
3
2
3
2
µV/mA
µV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
0
VREF
2 × VREF
0
0
VREF
2 × VREF
V
V
nF
Gain = 1
Gain = 2, see Figure 34
RL = ∞
Capacitive Load Stability
2
2
10
10
nF
kΩ
µV/mA
RL = 1 kΩ
Resistive Load4
Load Regulation
1
1
80
80
80
80
5 V 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ 30 mA
3 V 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ 20 mA
µV/mA
Short-Circuit Current5
Load Impedance at Rails6
Power-Up Time
40
25
2.5
40
25
2.5
mA
Ω
µs
See Figure 34
Coming out of power-down mode;
VDD = 5 V
Rev. 0 | Page 3 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
B Grade1
Typ
A Grade1
Typ
Parameter
Min
Max
Min
Max
Unit
Test Conditions/Comments
REFERENCE OUTPUT
Output Voltage7
Reference TC8, 9
Output Impedance3
Output Voltage Noise3
Output Voltage Noise
Density3
2.4975
2.5025
20
2.4975
2.5025
5
V
At ambient
5
0.04
12
2
0.04
12
ppm/°C See the Terminology section
Ω
0.1 Hz to 10 Hz
µV p-p
nV/√Hz
240
240
At ambient; f = 10 kHz, CL = 10 nF
Load Regulation Sourcing3
At ambient
At ambient
VDD ≥ 3 V
20
40
±5
20
40
±5
µV/mA
µV/mA
mA
Load Regulation Sinking3
Output Current Load
Capability3
Line Regulation3
Long-Term Stability/Drift3
Thermal Hysteresis3
100
12
100
12
µV/V
ppm
ppm
ppm
At ambient
After 1000 hours at 125°C
First cycle
125
25
125
25
Additional cycles
LOGIC INPUTS3
Input Current
2
2
µA
V
V
Per pin
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
0.3 × VLOGIC
0.3 × VLOGIC
0.7 × VLOGIC
0.7 × VLOGIC
2
4
2
4
pF
0.4
0.4
V
ISINK = 200 μA
ISOURCE = 200 μA
VLOGIC − 0.4
VLOGIC − 0.4
V
Floating State Output
Capacitance
pF
POWER REQUIREMENTS
VLOGIC
ILOGIC
1.8
5.5
3
1.8
5.5
3
V
µA
V
V
VDD
VDD
2.7
VREF + 1.5
5.5
5.5
2.7
VREF + 1.5
5.5
5.5
Gain = 1
Gain = 2
IDD
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off
Internal reference on, at full scale
−40°C to +85°C
Normal Mode10
0.59
1.1
1
0.7
1.3
4
0.59
1.1
1
0.7
1.3
4
mA
mA
µA
All Power-Down
Modes11
6
6
µA
−40°C to +105°C
1 Temperature range: A and B grade: −40°C to +105°C.
2 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5686R), 64 to 16,320 (AD5685R), and 12 to 4080 (AD5684R).
3 Guaranteed by design and characterization; not production tested.
4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 34).
7 Initial accuracy presolder reflow is 750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
8 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
9 Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
10 Interface inactive. All DACs active. DAC outputs unloaded.
11 All DACs powered down.
Rev. 0 | Page 4 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise
noted.1
Table 3.
Parameter2
Min
Typ
Max
Unit
Test Conditions/Comments3
Output Voltage Settling Time
AD5686R
AD5685R
5
5
5
8
8
7
µs
µs
µs
¼ to ¾ scale settling to 2 LSB
¼ to ¾ scale settling to 2 LSB
¼ to ¾ scale settling to 2 LSB
AD5684R
Slew Rate
0.8
0.5
0.13
0.1
0.2
0.3
−80
300
6
V/µs
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion4
Output Noise Spectral Density
Output Noise
1 LSB change around major carry
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz; gain = 2
0.1 Hz to 10 Hz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
SNR
SFDR
SINAD
90
83
80
dB
dB
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
4 Digitally generated sine wave @ 1 kHz.
Rev. 0 | Page 5 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
DD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
V
Table 4.
1.8 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter1
Symbol Min
Max
Min
20
10
10
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
t1
t2
t3
t4
33
16
16
15
5
t5
Data Hold Time
t6
t7
5
5
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single, Combined or All Channel Update)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
15
20
16
25
30
20
30
30
4.5
10
20
10
15
20
20
30
30
4.5
t8
t9
t10
t11
t12
t13
t14
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
Power-Up Time2
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
2 Time to exit power-down to normal mode of AD5686R/AD5685R/AD5684R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
t9
t1
SCLK
t2
t8
t7
t3
t4
SYNC
SDIN
t6
t5
DB23
DB0
t12
t10
1
LDAC
t11
2
LDAC
t13
RESET
t14
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. 0 | Page 6 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD
=
2.7 V to 5.5 V.
Table 5.
1.8 V ≤ VLOGIC < 2.7 V
2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter1
Symbol
Min
66
33
33
33
5
Max
Min
40
20
20
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Data Hold Time
5
5
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
Minimum SYNC High Time
SDO Data Valid from SCLK Rising Edge
SCLK Falling Edge to SYNC Rising Edge
15
60
60
10
30
30
36
25
5
t11
15
15
10
10
5
SYNC Rising Edge to SCLK Rising Edge
t12
ns
1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
200µA
I
OL
TO OUTPUT
PIN
V
(MIN)
OH
C
L
20pF
200µA
I
OH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
24
48
t11
t8
t12
t4
SYNC
SDIN
t6
t5
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t10
DB23
DB0
SDO
UNDEFINED
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 7 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
t1
SCLK
24
24
1
1
t3
t7
t9
t4
t2
t8
SYNC
t6
t5
DB23
DB23
DB0
DB23
DB0
SDIN
SDO
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t10
DB0
DB23
DB0
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. Readback Timing Diagram
Rev. 0 | Page 8 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VLOGIC to GND
−0.3 V to +7 V
VOUT to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +105°C
−65°C to +150°C
125°C
ESD CAUTION
16-Lead TSSOP, θJA Thermal
112.6°C/W
Impedance, 0 Airflow (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
Reflow Soldering Peak
70°C/W
260°C
Temperature, Pb Free (J-STD-020)
ESD1
4 kV
FICDM
1.5 kV
1 Human body model (HBM) classification.
Rev. 0 | Page 9 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5686R/AD5685R/AD5684R
V
V
A 1
12 SDIN
11 SYNC
10 SCLK
OUT
GND 2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
RSTSEL
RESET
SDIN
REF
V
3
DD
V
V
B
A
OUT
9
V
LOGIC
C 4
AD5686R/
AD5685R/
AD5684R
TOP VIEW
(Not to Scale)
OUT
OUT
GND
SYNC
SCLK
V
DD
V
V
C
D
V
LOGIC
OUT
OUT
TOP VIEW
(Not to Scale)
GAIN
LDAC
SDO
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 6. 16-Lead LFCSP Pin Configuration
Figure 7. 16-Lead TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic Description
1
2
3
3
4
5
VOUT
GND
VDD
A
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4
5
6
6
7
8
VOUT
VOUT
SDO
C
D
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Serial Data Output. Can be used to daisy-chain a number of AD5686R/AD5685R/AD5684R devices
together or can be used for readback. The serial data is transferred on the rising edge of SCLK and is
valid on the falling edge of the clock.
7
8
9
LDAC
GAIN
LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows
any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs
to simultaneously update. This pin can also be tied permanently low.
10
Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. If this
pin is tied to VDD, all four DACs output a span of 0 V to 2 × VREF
.
9
10
11
12
VLOGIC
SCLK
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
11
12
13
13
14
15
SYNC
SDIN
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC
pulses are ignored. When RESET is activated, the input register and the DAC register are updated with
zero scale or midscale, depending on the state of the RSTSEL pin.
RESET
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
VDD powers up all four DACs to midscale.
Reference Voltage. The AD5686R/AD5685R/AD5684R have a common reference pin. When using
the internal reference, this is the reference output pin. When using an external reference, this is the
reference input pin. The default for this pin is as a reference output.
14
15
16
1
RSTSEL
VREF
16
17
2
N/A
VOUT
EPAD
B
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
Rev. 0 | Page 10 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
TYPICAL PERFORMANCE CHARACTERISTICS
2.5020
V
= 5.5V
0 HOUR
DD
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
V
= 5V
DD
168 HOURS
500 HOURS
1000 HOURS
60
50
40
30
20
10
0
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
2.498
2.499
2.500
(V)
2.501
2.502
–40
–20
0
20
40
60
80
100
120
V
TEMPERATURE (°C)
REF
Figure 8. Internal Reference Voltage vs. Temperature (Grade B)
Figure 11. Reference Long-Term Stability/Drift
1600
1400
1200
1000
800
600
400
200
0
2.5020
V
= 5V
= 25°C
DD
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
T
A
2.5015
DEVICE 5
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
V
= 5V
120
DD
2.4980
–40
10
100
1k
10k
100k
1M
–20
0
20
40
60
80
100
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 9. Internal Reference Voltage vs. Temperature (Grade A)
Figure 12. Internal Reference Noise Spectral Density vs. Frequency
90
V
= 5V
DD
V
= 5V
= 25°C
T
DD
80
70
60
50
40
30
20
10
0
T
A
1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
CH1 10µV
M1.0s
A
CH1
160mV
TEMPERATURE DRIFT (ppm/°C)
Figure 13. Internal Reference Noise, 0.1 Hz to 10 Hz
Figure 10. Reference Output Temperature Drift Histogram
Rev. 0 | Page 11 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
2.5000
10
8
V
= 5V
= 25°C
DD
T
A
2.4999
2.4998
2.4997
2.4996
2.4995
2.4994
2.4993
6
4
2
0
–2
–4
–6
–8
–10
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
2500 5000 7500
CODE
–0.005
–0.003
–0.001
I
0.001
(A)
0.003
0.005
0
10000
12500
15000 16348
LOAD
Figure 17. AD5685R INL
Figure 14. Internal Reference Voltage vs. Load Current
2.5002
10
8
T
= 25°C
A
D1
D3
2.5000
2.4998
2.4996
2.4994
2.4992
2.4990
6
4
2
0
–2
–4
–6
–8
–10
D2
(V)
V
= 5V
DD
T
= 25°C
A
INTERNAL REFERENCE = 2.5V
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
625
1250
1875
CODE
2500
3125
3750 4096
V
DD
Figure 18. AD5684R INL
Figure 15. Internal Reference Voltage vs. Supply Voltage
1.0
0.8
10
8
6
0.6
0.4
4
0.2
2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
–10
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
DD
DD
A
A
INTERNAL REFERENCE = 2.5V
10000 20000 30000
CODE
INTERNAL REFERENCE = 2.5V
10000 20000 30000
CODE
0
40000
50000
60000
0
40000
50000
60000
Figure 19. AD5686R DNL
Figure 16. AD5686R INL
Rev. 0 | Page 12 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
10
8
1.0
0.8
6
0.6
4
0.4
2
0.2
INL
0
0
DNL
–2
–4
–6
–8
–10
–0.2
–0.4
–0.6
V = 5V
DD
V
= 5V
= 25°C
DD
–0.8
–1.0
T = 25°C
T
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
2500 5000 7500
CODE
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
10000
12500
15000 16383
3750 4096
110
V
(V)
REF
Figure 20. AD5685R DNL
Figure 23. INL Error and DNL Error vs. VREF
10
8
1.0
0.8
6
0.6
4
0.4
2
0.2
INL
0
0
DNL
–2
–4
–6
–8
–10
–0.2
–0.4
–0.6
–0.8
–1.0
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
DD
DD
A
A
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE = 2.5V
4.2
4.7
5.2
0
625
1250
1875
CODE
2500
3125
Figure 24. INL Error and DNL Error vs. Supply Voltage
Figure 21. AD5684R DNL
10
8
0.10
0.08
0.06
0.04
0.02
0
6
4
FULL-SCALE ERROR
GAIN ERROR
2
INL
0
DNL
–2
–4
–6
–8
–10
–0.02
–0.04
–0.06
–0.08
–0.10
V
= 5V
= 25°C
V
= 5V
DD
DD
T
T = 25°C
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
–40 –20 20 40
TEMPERATURE (°C)
–40 10
60
0
60
80
100
120
TEMPERATURE (°C)
Figure 22. INL Error and DNL Error vs. Temperature
Figure 25. Gain Error and Full-Scale Error vs. Temperature
Rev. 0 | Page 13 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
DD
DD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
ZERO-CODE ERROR
OFFSET ERROR
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 26. Zero-Code Error and Offset Error vs. Temperature
Figure 29. TUE vs. Temperature
0.10
0.08
0.06
0.04
0.02
0
0.10
0.08
0.06
0.04
0.02
0
GAIN ERROR
FULL-SCALE ERROR
–0.02
–0.04
–0.06
–0.08
–0.10
–0.02
–0.04
–0.06
–0.08
–0.10
V
= 5V
= 25°C
V
= 5V
DD
DD
T
T = 25°C
A
A
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
4.2
4.7
5.2
4.2
4.7
5.2
Figure 27. Gain Error and Full-Scale Error vs. Supply
Figure 30. TUE vs. Supply, Gain = 1
1.5
1.0
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
0.5
ZERO-CODE ERROR
OFFSET ERROR
0
–0.5
–1.0
–1.5
V
= 5V
= 25°C
DD
T
A
V
= 5V
DD
INTERNAL REFERENCE = 2.5V
T
= 25°C
A
INTERNAL REFERENCE = 2.5V
10000 20000 30000
CODE
2.7
3.2
3.7
4.2
4.7
5.2
0
40000
50000
60000 65535
SUPPLY VOLTAGE (V)
Figure 28. Zero-Code Error and Offset Error vs. Supply
Figure 31. TUE vs. Code
Rev. 0 | Page 14 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
7
6
V
T
= 5V
V
T
= 5V
= 25°C
DD
= 25°C
DD
25
20
15
10
5
A
A
EXTERNAL
REFERENCE = 2.5V
GAIN = 2
INTERNAL
REFERENCE = 2.5V
0xFFFF
5
4
0xC000
0x8000
0x4000
0x0000
3
2
1
0
–1
0
–2
–0.06
540
560
580
600
620
640
–0.04
–0.02
0
0.02
0.04
0.06
I
(V)
DD
LOAD CURRENT (A)
Figure 32. IDD Histogram with External Reference, 5 V
Figure 35. Source and Sink Capability at 5 V
5
4
V
= 5V
= 25°C
DD
V
= 5V
DD
30
T
A
T = 25°C
A
INTERNAL
REFERENCE = 2.5V
EXTERNAL REFERENCE = 2.5V
GAIN = 1
25
20
15
10
5
0xFFFF
3
0xC000
0x8000
2
1
0x4000
0x0000
0
–1
–2
0
1000
1020
1040
1060
1080
1100
1120
1140
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
I
FULLSCALE (V)
DD
LOAD CURRENT (A)
Figure 33. IDD Histogram with Internal Reference, VREFOUT = 2.5 V, Gain = 2
Figure 36. Source and Sink Capability at 3 V
1.0
0.8
0.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
FULL-SCALE
ZERO CODE
0.4
SINKING 2.7V
0.2
SINKING 5V
0
EXTERNAL REFERENCE, FULL-SCALE
–0.2
SOURCING 5V
–0.4
–0.6
–0.8
–1.0
SOURCING 2.7V
15
–40
10
60
110
0
5
10
20
25
30
TEMPERATURE (°C)
LOAD CURRENT (mA)
Figure 34. Headroom/Footroom vs. Load Current
Figure 37. Supply Current vs. Temperature
Rev. 0 | Page 15 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
2.5008
2.5003
2.4998
2.4993
2.4988
4.0
DAC A
DAC B
DAC C
3.5
DAC D
3.0
2.5
2.0
1.5
1.0
CHANNEL B
T
= 25°C
A
V
= 5.25V
V
T
= 5V
= 25°C
DD
DD
INTERNAL REFERENCE
CODE = 7FFF TO 8000
ENERGY = 0.227206nV-sec
0.5
0
A
INTERNAL REFERENCE = 2.5V
¼ TO ¾ SCALE
0
2
4
6
8
10
12
10
20
40
80
160
320
TIME (µs)
TIME (µs)
Figure 38. Settling Time, 5.25 V
Figure 41. Digital-to-Analog Glitch Impulse
0.06
0.05
0.04
0.03
0.02
0.01
0
6
0.003
0.002
0.001
0
CH A
CH B
CH C
CH D
CH B
CH C
CH D
5
V
DD
4
3
2
1
–0.001
–0.002
0
T
= 25°C
A
INTERNAL REFERENCE = 2.5V
–0.01
–1
15
–10
–5
0
5
10
0
5
10
15
20
25
TIME (µs)
TIME (µs)
Figure 39. Power-On Reset to 0 V
Figure 42. Analog Crosstalk, Channel A
3
2
1
0
CH A
CH B
CH C
CH D
SYNC
T
GAIN = 2
GAIN = 1
1
V
= 5V
= 25°C
DD
V
= 5V
DD
= 25°C
T
A
T
A
INTERNAL REFERENCE = 2.5V
EXTERNAL REFERENCE = 2.5V
–5
0
5
10
TIME (µs)
CH1 10µV M1.0s
A
CH1
802mV
Figure 40. Exiting Power-Down to Midscale
Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Rev. 0 | Page 16 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
0nF
V
= 5V
= 25°C
DD
0.1nF
10nF
0.22nF
4.7nF
T
A
T
INTERNAL REFERENCE = 2.5V
1
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
1.590 1.595 1.600 1.605 1.610 1.615 1.620 1.625 1.630
TIME (ms)
CH1 10µV M1.0s
A
CH1
802mV
Figure 47. Settling Time vs. Capacitive Load
Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
0
1600
V
= 5V
= 25°C
DD
FULL-SCALE
MIDSCALE
ZERO-SCALE
T
A
1400
1200
1000
800
600
400
200
0
–10
INTERNAL REFERENCE = 2.5V
–20
–30
–40
–50
–60
V
T
= 5V
= 25°C
DD
A
EXTERNAL REFERENCE = 2.5V, ±0.1V p-p
10k 100k 1M
FREQUENCY (Hz)
10M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 48. Multiplying Bandwidth, External Reference = 2.5 V, 0.1 V p-p,
10 kHz to 10 MHz
Figure 45. Noise Spectral Density
20
0
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
–20
–40
–60
–80
–100
–120
–140
–160
–180
0
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
FREQUENCY (Hz)
Figure 46. Total Harmonic Distortion @ 1 kHz
Rev. 0 | Page 17 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 16.
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the rising edge of SYNC.
Digital-to-Analog Glitch Impulse
Differential Nonlinearity (DNL)
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 41).
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 19.
Zero-Code Error
Digital Feedthrough
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5686R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV. A plot
of zero-code error vs. temperature can be seen in Figure 26.
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range (% of FSR). A plot of full-scale error
vs. temperature can be seen in Figure 25.
Noise Spectral Density
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. A plot
of noise spectral density is shown in Figure 45.
Gain Error
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from the ideal
expressed as % of FSR.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC kept
at midscale. It is expressed in μV.
Offset Error Drift
This is a measurement of the change in offset error with a
change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in ppm of FSR/°C.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5686R
with Code 512 loaded in the DAC register. It can be negative
or positive.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-sec.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in mV/V. VREF is held at 2 V, and VDD is varied by 10%.
Rev. 0 | Page 18 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
Analog Crosstalk
Total Harmonic Distortion (THD)
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa). Then execute a software LDAC
and monitor the output of the DAC whose digital code was not
changed. The area of the glitch is expressed in nV-sec.
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Voltage Reference TC
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given tempera-
ture range expressed in ppm/°C, as follows;
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent analog output
change of another DAC. It is measured by loading the attack
channel with a full-scale code change (all 0s to all 1s and vice
versa), using the write to and update commands while monitor-
ing the output of the victim channel that is at midscale. The
energy of the glitch is expressed in nV-sec.
V
REFmax −VREFmin
TC =
×106
V
×TempRange
REFnom
where:
REFmax is the maximum reference output measured over the
total temperature range.
REFmin is the minimum reference output measured over the total
temperature range.
REFnom is the nominal reference output voltage, 2.5 V.
Multiplying Bandwidth
V
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
V
V
TempRange is the specified temperature range of −40°C to
+105°C.
Rev. 0 | Page 19 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
THEORY OF OPERATION
V
REF
DIGITAL-TO-ANALOG CONVERTER
The AD5686R/AD5685R/AD5684R are quad 16-/14-/12-bit,
serial input, voltage output DACs with an internal reference.
The parts operate from supply voltages of 2.7 V to 5.5 V. Data is
written to the AD5686R/AD5685R/AD5684R in a 24-bit word
format via a 3-wire serial interface. The AD5686R/AD5685R/
AD5684R incorporate a power-on reset circuit to ensure that the
DAC output powers up to a known output state. The devices also
have a software power-down mode that reduces the typical
current consumption to typically 4 µA.
R
R
R
TO OUTPUT
AMPLIFIER
TRANSFER FUNCTION
R
R
The internal reference is on by default. To use an external
reference, only a nonreference option is available. Because the
input coding to the DAC is straight binary, the ideal output
voltage when using an external reference is given by
Figure 50. Resistor String Structure
D
2
VOUT =VREF ×Gain
N
Internal Reference
The AD5686R/AD5685R/AD5684R on-chip reference is on at
power-up but can be disabled via a write to a control register.
See the Internal Reference Setup section for details.
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows:
0 to 4,095 for the 12-bit device.
0 to 16,383 for the 14-bit device.
0 to 65,535 for the 16-bit device.
The AD5686R/AD5685R/AD5684R have a 2.5 V, 2 ppm/°C
reference, giving a full-scale output of 2.5 V or 5 V, depending
on the state of the GAIN pin. The internal reference associated
with the device is available at the VREF pin. This buffered
reference is capable of driving external loads of up to 10 mA.
N is the DAC resolution.
Gain is the gain of the output amplifier and is set to 1 by default.
This can be set to ×1 or ×2 using the gain select pin. When this
pin is tied to GND, all four DAC outputs have a span from 0 V
to VREF. If this pin is tied to VDD, all four DACs output a span of
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, offset error,
and gain error. The GAIN pin selects the gain of the output.
0 V to 2 × VREF
.
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 49 shows a block diagram of the DAC
architecture.
•
If this pin is tied to GND, all four outputs have a gain of 1
and the output range is 0 V to VREF
If this pin is tied to VLOGIC, all four outputs have a gain of 2
and the output range is 0 V to 2 × VREF
.
•
V
REF
.
2.5V
REF
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale
settling time of 5 µs.
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
X
OUT
REF (–)
GAIN
(GAIN = 1 OR 2)
GND
Figure 49. Single DAC Channel Architecture Block Diagram
The resistor string structure is shown in Figure 50. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
Rev. 0 | Page 20 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
Table 7. Command Definitions
SERIAL INTERFACE
Command
The AD5686R/AD5685R/AD5684R have a 3-wire serial
C3
0
0
C2 C1 C0 Description
SYNC
interface (
, SCLK, and SDIN) that is compatible with
0
0
0
0
0
1
0
1
0
No operation
SPI, QSPI, and MICROWIRE interface standards as well as
most DSPs. See Figure 2 for a timing diagram of a typical
write sequence. The AD5686R/AD5685R/AD5684R contain
an SDO pin to allow the user to daisy-chain multiple devices
together (see the Daisy-Chain Operation section) or for
readback.
LDAC
)
Write to Input Register n (dependent on
0
Update DAC Register n with contents of Input
Register n
0
0
0
0
0
1
1
1
…
1
0
1
1
1
1
0
0
0
…
1
1
0
0
1
1
0
0
1
…
1
1
0
1
0
1
0
1
0
…
1
Write to and update DAC Channel n
Power down/power up DAC
LDAC
Hardware
mask register
Software reset (power-on reset)
Internal reference setup register
Set up DCEN register (daisy-chain enable)
Set up readback register (readback enable)
Reserved
Input Shift Register
The input shift register of the AD5686R/AD5685R/AD5684R is
24 bits wide. Data is loaded MSB first (DB23) and the first four
bits are the command bits, C3 to C0 (see Table 7), followed by
the 4-bit DAC address bits, DAC A, DAC B, DAC C, DAC D
(see Table 8), and finally the bit data-word.
Reserved
Reserved
The data-word comprises 16-bit, 14-bit, or 12-bit input code,
followed by zero, two or four don’t care bits for the AD5686R,
AD5685R, and AD5684R, respectively (see Figure 51, Figure 52,
and Figure 53). These data bits are transferred to the input
register on the 24 falling edges of SCLK and are updated on the
Table 8. Address Commands
Address (n)
DAC D DAC C DAC B DAC A Selected DAC Channel1
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
1
1
0
0
0
1
1
DAC A
DAC B
DAC C
DAC D
DAC A and DAC B
All DACs
SYNC
rising edge of
.
Commands can be executed on individual DAC channels,
combined DAC channels, or on all DACs, depending on the
address bits selected.
1 Any combination of DAC channels can be selected using the address bits.
DB23 (MSB)
DB0 (LSB)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
DAC DAC DAC DAC
C3 C2 C1 C0
D
C
B
A
COMMAND BITS
ADDRESS BITS
Figure 51. AD5686R Input Shift Register Content
DB23 (MSB)
DB0 (LSB)
DAC DAC DAC DAC
C3 C2 C1 C0
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
X
X
D
C
B
A
COMMAND BITS
ADDRESS BITS
Figure 52. AD5685R Input Shift Register Content
DB23 (MSB)
DB0 (LSB)
DAC DAC DAC DAC
C3 C2 C1 C0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
X
X
X
X
D
C
B
A
COMMAND BITS
ADDRESS BITS
Figure 53. AD5684R Input Shift Register Content
Rev. 0 | Page 21 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
STANDALONE OPERATION
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on
)
LDAC
SYNC
The write sequence begins by bringing the
line low. Data
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of 24 data bits is
Command 0001 allows the user to write to each DAC’s
LDAC
dedicated input register individually. When
the input register is transparent (if not controlled by the
LDAC
is low,
SYNC
clocked in,
function is then executed, that is, an
in DAC register contents and/or a change in the mode of
should be brought high. The programmed
LDAC
-dependent change
mask register).
Update DAC Register n with Contents of Input Register n
th
SYNC
operation. If
it is considered a valid frame and invalid data may be loaded to
SYNC
is taken high at a clock before the 24 clock,
Command 0010 loads the DAC registers/outputs with the
contents of the input registers selected and updates the DAC
outputs directly.
the DAC.
20 ns (single channel, see t8 in Figure 2) before the next write
SYNC
must be brought high for a minimum of
Write to and Update DAC Channel n (Independent of
sequence so that a falling edge of
can initiate the next
should be idled at rails between write
sequences for even lower power operation of the part.
SYNC
)
LDAC
SYNC
write sequence.
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.
The
line is kept low for 24 falling edges of SCLK, and the
SYNC
DAC is updated on the rising edge of
.
When the data has been transferred into the input register of
the addressed DAC, all DAC registers and outputs can be
LDAC
SYNC
updated by taking
low while the
line is high.
Rev. 0 | Page 22 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
SYNC
DAC. When the serial transfer to all devices is complete,
DAISY-CHAIN OPERATION
is taken high. This latches the input data in each device in the
daisy chain and prevents any further data from being clocked
into the input shift register. The serial clock can be continuous or
a gated clock. A continuous SCLK source can be used only
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together and is enabled
through a software executable daisy-chain enable (DCEN)
command. Command 1000 is reserved for this DCEN function
(see Table 7). The daisy-chain mode is enabled by setting
Bit DB0 in the DCEN register. The default setting is standalone
mode, where DB0 = 0. Table 9 shows how the state of the bit
corresponds to the mode of operation of the device.
SYNC
if
can be held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
SYNC
of clock cycles must be used, and
the final clock to latch the data.
must be taken high after
READBACK OPERATION
Table 9. Daisy-Chain Enable (DCEN) Register
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisy-
chain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one of
address bits, DAC A to DAC D, selects the register to read. Note
that only one DAC register can be selected during readback.
The remaining three address bits must be set to Logic 0. The
remaining data bits in the write sequence are don’t care bits. If
more than one or no bits are selected, DAC Channel A is read
back by default. During the next SPI write, the data appearing
on the SDO output contains the data from the previously
addressed register.
DB0
Description
0
1
Standalone mode (default)
DCEN mode
AD5686R/
AD5685R/
AD5684R
68HC11*
SDIN
MOSI
SCK
PC7
SCLK
SYNC
LDAC
PC6
SDO
MISO
SDIN
AD5686R/
AD5685R/
AD5684R
For example, to read back the DAC register for Channel A, the
following sequence should be implemented:
SCLK
SYNC
LDAC
1. Write 0x900000 to the AD5686R/AD5685R/AD5684R
input register. This configures the part for read mode with
the DAC register of Channel A selected. Note that all data
bits, DB15 to DB0, are don’t care bits.
SDO
2. Follow this with a second write, a NOP condition,
0x000000. During this write, the data from the register is
clocked out on the SDO line. DB23 to DB20 contain
undefined data, and the last 16 bits contain the DB19 to
DB4 DAC register contents.
SDIN
AD5686R/
AD5685R/
AD5684R
SCLK
SYNC
LDAC
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 54. Daisy-Chaining the AD5686R/AD5685R/AD5684R
The SCLK pin is continuously applied to the input shift register
SYNC
when
is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
SDIN input on the next DAC in the chain, a daisy-chain interface
is constructed. Each DAC in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,
where N is the total number of devices that are updated.
SYNC
If
is taken high at a clock that is not a multiple of 24, it is
considered a valid frame and invalid data may be loaded to the
Rev. 0 | Page 23 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
power-down options. The output is connected internally to
GND through either a 1 kΩ or a 100 kΩ resistor, or it is left
open-circuited (three-state). The output stage is illustrated in
Figure 55.
POWER-DOWN OPERATION
The AD5686R/AD5685R/AD5684R contain three separate
power-down modes. Command 0100 is designated for the power-
down function (see Table 7). These power-down modes are
software-programmable by setting eight bits, Bit DB7 to Bit DB0,
in the input shift register. There are two bits associated with each
DAC channel. Table 10 shows how the state of the two bits
corresponds to the mode of operation of the device.
Table 10. Modes of Operation
AMPLIFIER
V
X
DAC
OUT
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
PDx1
PDx0
0
0
0
1
1
1
0
1
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 55. Output Stage During Power-Down
Any or all DACs (DAC A to DAC D) can be powered down to
the selected mode by setting the corresponding bits. See
Table 11 for the contents of the input shift register during the
power-down/power-up operation.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The DAC register can be
updated while the device is in power-down mode. The time
required to exit power-down is typically 4.5 µs for VDD = 5 V.
When both Bit PDx1 and Bit PDx0 (where x is the channel
selected) in the input shift register are set to 0, the parts work
normally with its normal power consumption of 4 mA at 5 V.
However, for the three power-down modes, the supply current
falls to 4 μA at 5 V. Not only does the supply current fall, but the
To reduce the current consumption further, the on-chip reference
can be powered off. See the Internal Reference Setup section.
Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1
DB15
to
DB8
DB0
(LSB)
DB23 DB22
DB21
DB20
DB19 to DB16
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
1
0
0
X
X
PDD1
PDD0
PDC1
PDC0
PDB1
PDB0 PDA1
PDA0
Command bits (C3 to C0)
Address bits
Don’t care
Power-Down
Select DAC D
Power-Down
Select DAC C
Power-Down
Select DAC B
Power-Down
Select DAC A
1 X = don’t care.
Rev. 0 | Page 24 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
LOAD DAC (HARDWARE LDAC PIN)
LDAC MASK REGISTER
The AD5686R/AD5685R/AD5684R DACs have double
buffered interfaces consisting of two banks of registers:
input registers and DAC registers. The user can write to
any combination of the input registers. Updates to the DAC
LDAC
function.
Command 0101 is reserved for this software
Address bits are ignored. Writing to the DAC, using Command
LDAC
0101, loads the 4-bit
for each channel is 0; that is, the
Setting the bits to 1 forces this DAC channel to ignore transitions
LDAC LDAC
register (DB3 to DB0). The default
LDAC
pin works normally.
LDAC
register are controlled by the
pin.
OUTPUT
AMPLIFIER
on the
pin. This flexibility is useful in applications where the user
LDAC
pin, regardless of the state of the hardware
V
16-/14-/12-BIT
REF
V
X
OUT
DAC
wishes to select which channels respond to the
LDAC
pin.
Table 12.
Load LDAC Register
LDAC Bits
Overwrite Definition
DAC
REGISTER
LDAC
LDAC Pin LDAC Operation
(DB3 to DB0)
INPUT
REGISTER
0
1
1 or 0
X1
Determined by the LDAC pin.
DAC channels update and
override the LDAC pin. DAC
channels see LDAC as 1.
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
1 X = don’t care.
Figure 56. Simplified Diagram of Input Loading Circuitry for a Single DAC
LDAC
The
over the hardware
bits (DB0 to DB3) to 0 for a DAC channel means that this
LDAC
register gives the user extra flexibility and control
LDAC
Instantaneous DAC Updating (
Held Low)
is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
LDAC LDAC
pin (see Table 12). Setting the
LDAC
channel’s update is controlled by the hardware
pin.
SYNC
the DAC register are updated on the rising edge of
the output begins to change (see Table 13).
and
LDAC
Deferred DAC Updating (
is Pulsed Low)
is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
LDAC SYNC
LDAC
updated by taking
The update now occurs on the falling edge of
low after
has been taken high.
LDAC
.
1
LDAC
Table 13. Write Commands and
Pin Truth Table
Hardware LDAC
Pin State
Input Register
Contents
Commands Description
DAC Register Contents
No change (no update)
Data update
0001
Write to Input Register n (dependent on LDAC)
VLOGIC
GND2
Data update
Data update
No change
0010
Update DAC Register n with contents of Input
Register n
VLOGIC
Updated with input register
contents
GND
No change
Updated with input register
contents
0011
Write to and update DAC Channel n
VLOGIC
GND
Data update
Data update
Data update
Data update
1
LDAC
A high to low hardware
pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that
LDAC
are not masked (blocked) by the
mask register.
2 When LDAC is permanently tied low, the LDAC mask bits are ignored.
Rev. 0 | Page 25 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
HARDWARE RESET (
)
RESET
SOLDER HEAT REFLOW
RESET
is an active low reset that allows the outputs to be
cleared to either zero scale or midscale. The clear code value is
RESET
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test called precondition to
mimic the effect of soldering a device to a board. The output
voltage specification quoted previously includes the effect of
this reliability test.
user selectable via the
RESET
operation (see Figure 2). When the
high, the output remains at the cleared value until a new value is
programmed. The outputs cannot be updated with a new value
select pin. It is necessary to keep
low for a minimum amount of time to complete the
RESET
signal is returned
Figure 57 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).
RESET
while the
pin is low. There is also a software executable
reset function that resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function
POSTSOLDER
HEAT REFLOW
60
50
40
30
20
10
0
LDAC RESET
(see Table 7). Any events on
reset are ignored.
or
during power-on
PRESOLDER
HEAT REFLOW
RESET SELECT PIN (RSTSEL)
The AD5686R/AD5685R/AD5684R contain a power-on reset
circuit that controls the output voltage during power-up. By
connecting the RSTSEL pin low, the output powers up to zero
scale. Note that this is outside the linear region of the DAC; by
connecting the RSTSEL pin high, VOUT powers up to midscale.
The output remains powered up at this level until a valid write
sequence is made to the DAC.
2.498
2.499
2.500
(V)
2.501
2.502
V
REF
INTERNAL REFERENCE SETUP
Figure 57. SHR Reference Voltage Shift
The on-chip reference is on at power-up by default. To reduce the
supply current, this reference can be turned off by setting
software programmable bit, DB0, in the control register.
Table 14 shows how the state of the bit corresponds to the mode
of operation. Command 0111 is reserved for setting up the
internal reference (see Figure 9). Table 14 shows how the state
of the bits in the input shift register corresponds to the mode of
operation of the device during internal reference setup.
LONG-TERM TEMPERATURE DRIFT
Figure 58 shows the change in VREF value after 1000 hours in life
test at 150°C.
0 HOUR
168 HOURS
500 HOURS
1000 HOURS
60
50
40
30
20
10
0
Table 14. Reference Setup Register
Internal Reference
Setup Register (DB0) Action
0
1
Reference on (default)
Reference off
2.498
2.499
2.500
(V)
2.501
2.502
V
REF
Figure 58. Reference Drift Through to 1000 Hours
Rev. 0 | Page 26 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
9
8
7
6
5
4
3
2
1
THERMAL HYSTERESIS
FIRST TEMPERATURE SWEEP
SUBSEQUENT TEMPERATURE SWEEPS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
Thermal hysteresis data is shown in Figure 59. It is measured
by sweeping the temperature from ambient to −40°C, then
to +105°C, and returning to ambient. The VREF delta is then
measured between the two ambient measurements and
shown in blue in Figure 59. The same temperature sweep
and measurements were immediately repeated and the
results are shown in red in Figure 59.
0
–200
–150
–100
–50
0
50
DISTORTION (ppm)
Figure 59. Thermal Hysteresis
Table 15. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1
DB23
(MSB)
DB22 DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
X
DB0 (LSB)
0
1
1
1
X
X
X
X
1/0
Command bits (C3 to C0)
Address bits (A2 to A0)
Don’t care
Reference setup register
1 X = don’t care.
Rev. 0 | Page 27 of 32
AD5686R/AD5685R/AD5684R
Data Sheet
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
LAYOUT GUIDELINES
Microprocessor interfacing to the AD5686R/AD5685R/
AD5684R is via a serial bus that uses a standard protocol that
is compatible with DSP processors and microcontrollers.
The communications channel requires a 3- or 4-wire interface
consisting of a clock signal, a data signal, and a synchronization
signal. The devices require a 24-bit data-word with data valid
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performance. The PCB on which the AD5686R/
AD5685R/AD5684R are mounted should be designed so that
the AD5686R/AD5685R/AD5684R lie on the analog plane.
The AD5686R/AD5685R/AD5684R should have ample
supply bypassing of 10 µF in parallel with 0.1 µF on each
supply, located as close to the package as possible, ideally right
up against the device. The 10 µF capacitors are the tantalum
bead type. The 0.1 µF capacitor should have low effective series
resistance (ESR) and low effective series inductance (ESI) such
as the common ceramic types, which provide a low impedance
path to ground at high frequencies to handle transient currents
due to internal logic switching.
SYNC
on the rising edge of
.
AD5686R/AD5685R/AD5684R TO ADSP-BF531
INTERFACE
The SPI interface of the AD5686R/AD5685R/AD5684R is
designed to be easily connected to industry-standard DSPs and
microcontrollers. Figure 60 shows the AD5686R/AD5685R/
AD5684R connected to the Analog Devices Blackfin® DSP. The
Blackfin has an integrated SPI port that can be connected
directly to the SPI pins of the AD5686R/AD5685R/AD5684R.
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
AD5686R/
AD5685R/
AD5684R
The AD5686R/AD5685R/AD5684R have an exposed paddle
beneath the device. Connect this paddle to the GND supply for
the part. For optimum performance, use special considerations
to design the motherboard and to mount the package. For
enhanced thermal, electrical, and board level performance,
solder the exposed paddle on the bottom of the package to the
corresponding thermal land paddle on the PCB. Design thermal
vias into the PCB land paddle area to further improve heat
dissipation.
ADSP-BF531
SPISELx
SCK
SYNC
SCLK
SDIN
MOSI
PF9
PF8
LDAC
RESET
Figure 60. ADSP-BF531 Interface
AD5686R/AD5685R/AD5684R TO SPORT
INTERFACE
The GND plane on the device can be increased (as shown in
Figure 62) to provide a natural heat sinking effect.
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 61 shows how one SPORT interface can be used to
control the AD5686R/AD5685R/AD5684R.
AD5686R/
AD5685R/
AD5684R
AD5686R/
AD5685R/
AD5684R
ADSP-BF527
GND
PLANE
SPORT_TFS
SPORT_TSCK
SPORT_DTO
SYNC
SCLK
SDIN
BOARD
GPIO0
GPIO1
LDAC
RESET
Figure 62. Paddle Connection to Board
Figure 61. SPORT Interface
Rev. 0 | Page 28 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
ADuM14001
CONTROLLER
GALVANICALLY ISOLATED INTERFACE
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
TO
SERIAL
In many process control applications, it is necessary to
provide an isolation barrier between the controller and
the unit being controlled to protect and isolate the controlling
circuitry from any hazardous common-mode voltages that
may occur. iCoupler® products from Analog Devices provide
voltage isolation in excess of 2.5 kV. The serial loading struc-
ture of the AD5686R/AD5685R/AD5684R makes the part
ideal for isolated interfaces because the number of interface
lines is kept to a minimum. Figure 63 shows a 4-channel
isolated interface to the AD5686R/AD5685R/AD5684R
using an ADuM1400. For further information, visit
http://www.analog.com/icouplers.
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
SCLK
CLOCK IN
TO
SDIN
SERIAL
DATA OUT
TO
SYNC
SYNC OUT
LOAD DAC
OUT
TO
LDAC
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 63. Isolated Interface
Rev. 0 | Page 29 of 32
AD5686R/AD5685R/AD5684R
OUTLINE DIMENSIONS
Data Sheet
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 65. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. 0 | Page 30 of 32
Data Sheet
AD5686R/AD5685R/AD5684R
ORDERING GUIDE
Reference
Tempco
(ppm/°C)
Temperature
Range
Package
Description
Package
Option
Model1
Resolution
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
14 Bits
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
Accuracy
8 LSB INL
2 LSB INL
8 LSB INL
8 LSB INL
2 LSB INL
2 LSB INL
1 LSB INL
4 LSB INL
4 LSB INL
1 LSB INL
1 LSB INL
1 LSB INL
2 LSB INL
2 LSB INL
1 LSB INL
1 LSB INL
Branding
DJM
DJN
AD5686RACPZ-RL7
AD5686RBCPZ-RL7
AD5686RARUZ
AD5686RARUZ-RL7
AD5686RBRUZ
AD5686RBRUZ-RL7
AD5685RBCPZ-RL7
AD5685RARUZ
AD5685RARUZ-RL7
AD5685RBRUZ
AD5685RBRUZ-RL7
AD5684RBCPZ-RL7
AD5684RARUZ
AD5684RARUZ-RL7
AD5684RBRUZ
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
5 (typ)
5 (max)
5 (typ)
5 (typ)
5 (max)
5 (max)
5 (max)
5 (typ)
5 (typ)
5 (max)
5 (max)
5 (max)
5 (typ)
5 (typ)
5 (max)
5 (max)
16-Lead LFCSP_WQ CP-16-22
16-Lead LFCSP_WQ CP-16-22
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
RU-16
RU-16
RU-16
RU-16
16-Lead LFCSP_WQ CP-16-22
DJK
DJG
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
RU-16
RU-16
RU-16
RU-16
16-Lead LFCSP_WQ CP-16-22
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
RU-16
RU-16
RU-16
RU-16
AD5684RBRUZ-RL7
EVAL-AD5686RSDZ
AD5686R TSSOP
Evaluation Board
EVAL-AD5684RSDZ
AD5684R TSSOP
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 31 of 32
AD5686R/AD5685R/AD5684R
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10485-0-4/12(0)
Rev. 0 | Page 32 of 32
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