AD5697R [ADI]
Dual, 12-Bit nanoDAC with 2 ppm/°C Reference, I2C Interface; 双通道， 12位属于nanoDAC与2 PPM / A ° C参考， I2C接口
| 型号： | AD5697R |
| 厂家： | 
ADI |
| 描述： | Dual, 12-Bit nanoDAC with 2 ppm/°C Reference, I2C Interface |
| 文件： | 总28页 (文件大小：1547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, 12-Bit nanoDAC+
with 2 ppm/°C Reference, I2C Interface
Data Sheet
AD5697R
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
REF
DD
GND
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): 0.1% of full-scale range (FSR)
maximum
AD5697R
2.5V
REFERENCE
V
LOGIC
SCL
INPUT
DAC
STRING
DAC A
V
V
A
B
OUT
SDA
A1
REGISTER
REGISTER
Offset error: 1.5 mV maximum
BUFFER
BUFFER
Gain error: 0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
OUT
A0
POWER-ON
RESET
GAIN =
×1/×2
POWER-
DOWN
LOGIC
Low glitch: 0.5 nV-sec
400 kHz I2C-compatible serial interface
Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
LDAC RESET
RSTSEL
GAIN
Figure 1.
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Base station power amplifiers
Process controls (programmable logic controller [PLC] I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5697R, a member of the nanoDAC+™ family, is a low power,
dual, 12-bit buffered voltage output digital-to-analog converter
(DAC). The device includes a 2.5 V, 2 ppm/°C internal reference
(enabled by default) and a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5697R operates from
a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design,
and exhibits less than 0.1% FSR gain error and 1.5 mV offset
error performance. The device is available in a 3 mm × 3 mm
LFCSP and a TSSOP package.
Table 1. Dual nanoDAC+ Devices
Interface
Reference
Internal
External
Internal
External
16-Bit
12-Bit
SPI
AD5689R
AD5689
AD5687R
AD5687
I2C
AD5697R
PRODUCT HIGHLIGHTS
1. Precision DC Performance.
TUE: 0.1% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.1% of FSR maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
The AD5697R also incorporates a power-on reset circuit and a
RSTSEL pin that ensure that the DAC outputs power up to zero
scale or midscale and remain there until a valid write takes
place. It contains a per channel power-down feature that reduces
the current consumption of the device to 4 µA at 3 V while in
power-down mode.
The AD5697R uses a versatile 2-wire serial interface that operates
at clock rates up to 400 kHz and includes a VLOGIC pin intended
for 1.8 V/3 V/5 V logic.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. 0
Document Feedback
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
AD5697R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Operation ......................................................................... 19
Write Operation.......................................................................... 19
Read Operation........................................................................... 20
Multiple DAC Readback Sequence.......................................... 20
Power-Down Operation............................................................ 21
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 17
Digital-to-Analog Converter .................................................... 17
Transfer Function ....................................................................... 17
DAC Architecture....................................................................... 17
Serial Interface ............................................................................ 18
Write and Update Commands.................................................. 18
LDAC
Load DAC (Hardware
Pin)........................................... 22
Mask Register ................................................................. 22
Hardware Reset ( ) .......................................................... 23
LDAC
RESET
Reset Select Pin (RSTSEL) ........................................................ 23
Internal Reference Setup ........................................................... 23
Solder Heat Reflow..................................................................... 23
Long-Term Temperature Drift ................................................. 23
Thermal Hysteresis .................................................................... 24
Applications Information .............................................................. 25
Microprocessor Interfacing....................................................... 25
AD5697R-to-ADSP-BF531 Interface ...................................... 25
Layout Guidelines....................................................................... 25
Galvanically Isolated Interface ................................................. 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
2/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
AD5697R
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; and all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; and CL = 200 pF.
Table 2.
Parameter
STATIC PERFORMANCE1
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
12
Bits
LSB
LSB
mV
mV
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
0.12
1
1
Guaranteed monotonic by design
All 0s loaded to DAC register
0.4
1.5
1.5
0.1
0.1
0.1
0.2
+0.1
+0.01
0.02
0.01
% of FSR All 1s loaded to DAC register
% of FSR
% of FSR External reference; gain = 2; TSSOP
% of FSR Internal reference; gain = 1; TSSOP
μV/°C
Total Unadjusted Error
Offset Error Drift2
1
1
0.15
Gain Temperature Coefficient2
DC Power Supply Rejection Ratio2
DC Crosstalk2
ppm
mV/V
Of FSR/°C
DAC code = midscale; VDD = 5 V 10%
2
3
2
μV
μV/mA
μV
Due to single channel, full-scale output change
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS2
Output Voltage Range
0
0
VREF
2 × VREF
V
V
nF
Gain = 1
Gain = 2, see Figure 26
RL = ∞
Capacitive Load Stability
2
10
nF
kΩ
μV/mA
RL = 1 kΩ
Resistive Load3
Load Regulation
1
80
80
5 V 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ +30 mA
3 V 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ +20 mA
μV/mA
Short-Circuit Current4
Load Impedance at Rails5
Power-Up Time
40
25
2.5
mA
Ω
μs
See Figure 26
Coming out of power-down mode; VDD = 5 V
REFERENCE OUTPUT
Output Voltage6
Reference Temperature Coefficient7, 8
Output Impedance2
Output Voltage Noise2
Output Voltage Noise Density2
Load Regulation Sourcing2
Load Regulation Sinking2
Output Current Load Capability2
Line Regulation2
2.4975
2.5025
5
V
At ambient
See the Terminology section
2
0.04
12
240
20
40
ppm/°C
Ω
μV p-p
nV/√Hz
μV/mA
μV/mA
mA
μV/V
ppm
ppm
ppm
0.1 Hz to 10 Hz
At ambient; f = 10 kHz, CL = 10 nF
At ambient
At ambient
VDD ≥ 3 V
At ambient
After 1000 hours at 125°C
First cycle
5
100
12
125
25
Long-Term Stability/Drift2
Thermal Hysteresis2
Additional cycles
LOGIC INPUTS2
Input Current
2
μA
V
V
Per pin
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
0.3 × VLOGIC
0.7 × VLOGIC
2
pF
Rev. 0 | Page 3 of 28
AD5697R
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC OUTPUTS (SDA)2
Output Low Voltage, VOL
0.4
V
ISINK = 3 mA
Floating State Output Capacitance
4
pF
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
1.8
5.5
3
5.5
5.5
V
µA
V
2.7
VREF + 1.5
Gain = 1
Gain = 2
V
IDD
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off
Internal reference on, at full scale
−40°C to +85°C
Normal Mode9
0.59
1.1
1
0.7
1.3
4
mA
mA
µA
All Power-Down Modes10
6
µA
−40°C to +105°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 12 to 4080.
2 Guaranteed by design and characterization; not production tested.
3 Channel A can have an output current of up to 30 mA. Similarly, Channel B can have an output current of up to 30 mA up to a junction temperature of 100°C.
4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output device.
For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 26).
6 Initial accuracy presolder reflow is 750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
8 Reference temperature coefficient is calculated as per the box method. See the Terminology section for further information.
9 Interface inactive. Both DACs active. DAC outputs unloaded.
10 Both DACs powered down.
Rev. 0 | Page 4 of 28
Data Sheet
AD5697R
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise
noted. Guaranteed by design and characterization; not production tested.
Table 3.
Parameter1
Min Typ Max Unit
Test Conditions/Comments2
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
5
7
µs
V/µs
¼ to ¾ scale settling to 2 LSB
0.8
0.5
0.13
0.1
0.2
0.3
−80
300
6
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
dB
1 LSB change around major carry
DAC-to-DAC Crosstalk
Total Harmonic Distortion (THD)3
Output Noise Spectral Density
Output Noise
At ambient, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
nV/√Hz DAC code = midscale, 10 kHz; gain = 2
µV p-p
dB
dB
dB
0.1 Hz to 10 Hz
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Signal-to-Noise-and-Distortion Ratio (SINAD)
90
83
80
At ambient, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
1 See the Terminology section.
2 Temperature range is −40°C to +105°C, typical at 25°C.
3 Digitally generated sine wave at 1 kHz.
Rev. 0 | Page 5 of 28
AD5697R
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 4.
Parameter1
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
pF
Test Conditions/Comments
SCL cycle time
SCL high time, tHIGH
SCL low time, tLOW
Start/repeated start condition hold time, tHD,STA
Data setup time, tSU,DAT
Data hold time, tHD,DAT
Setup time for repeated start, tSU,STA
Stop condition setup time, tSU,STO
Bus free time between a stop and a start condition, tBUF
Rise time of SCL and SDA when receiving, tR
Fall time of SDA and SCL when transmitting/receiving, tF
LDAC pulse width
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
Max
t1
t2
t3
t4
t5
2
t6
0.9
t7
t8
t9
t10
t11
t12
t13
0
300
300
3
20 + 0.1CB
20
400
SCL rising edge to LDAC rising edge
Capacitive load for each bus line
3
CB
400
1 Guaranteed by design and characterization; not production tested.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the
falling edge of the SCL.
3 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD
.
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
SDA
SCL
t9
t10
t11
t4
t3
t4
t2
t1
t6
t5
t7
t8
t12
1
2
t13
LDAC
LDAC
t12
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
2
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. 0 | Page 6 of 28
Data Sheet
AD5697R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VLOGIC to GND
−0.3 V to +7 V
VOUT to GND
VREF to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to +7 V
−40°C to +105°C
−65°C to +150°C
125°C
Digital Input Voltage to GND1
SDA and SCL to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD CAUTION
16-Lead TSSOP, θJA Thermal Impedance,
0 Airflow (4-Layer Board)
112.6°C/W
16-Lead LFCSP, θJA Thermal Impedance,
0 Airflow (4-Layer Board)
Reflow Soldering Peak Temperature,
Pb Free (J-STD-020)
ESD2
70°C/W
260°C
3.5 kV
1.5 kV
FICDM
1 Excluding SDA and SCL.
2 Human body model (HBM) classification.
Rev. 0 | Page 7 of 28
AD5697R
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
RSTSEL
RESET
A1
V
A 1
12 A1
11 SCL
10 A0
REF
NC
OUT
GND 2
AD5697R
V
3
V
V
A
DD
OUT
AD5697R
9
V
LOGIC
NC 4
GND
SCL
TOP VIEW
(Not to Scale)
V
A0
DD
NC
V
LOGIC
B
GAIN
LDAC
OUT
TOP VIEW
(Not to Scale)
SDA
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
2. NC = NO CONNECT. DO NOT CONNECT TO
THIS PIN.
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO
THIS PIN.
Figure 3. 16-Lead LFCSP Pin Configuration
Figure 4. 16-Lead TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP TSSOP
Mnemonic Description
1
16
2
3
2
4
5
VOUT
NC
GND
VDD
A
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
No Connect. Do not connect to this pin.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. This part can be operated from 2.7 V to 5.5 V. Decouple the supply with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
3
4
5
6
6
7
8
NC
VOUT
SDA
No Connect. Do not connect to this pin.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the
24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the
supply with an external pull-up resistor.
B
7
8
9
LDAC
GAIN
LDAC can be operated in two modes, asynchronous and synchronous. Pulsing this pin low allows
either or both DAC registers to be updated if the input registers have new data. This allows both DAC
outputs to simultaneously update. This pin can also be tied permanently low.
10
Gain Select. When this pin is tied to GND, both DAC outputs have a span from 0 V to VREF. If this pin
is tied to VLOGIC, both DACs output a span of 0 V to 2 × VREF
.
9
10
11
11
12
13
VLOGIC
A0
SCL
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Address Input. Sets the first LSB of the 7-bit slave address.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit
input register.
12
13
14
15
A1
RESET
Address Input. Sets the second LSB of the 7-bit slave address.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC
pulses are ignored. When RESET is activated, the input register and the DAC register are updated
with zero scale or midscale, depending on the state of the RSTSEL pin.
Power-On Reset Select. Tying this pin to GND powers up both DACs to zero scale. Tying this pin to
VLOGIC powers up both DACs to midscale.
Reference Voltage. The AD5697R has a common reference pin. When using the internal reference,
this is the reference output pin. When using an external reference, this is the reference input pin.
The default for this pin is as a reference output.
14
15
16
1
RSTSEL
VREF
17
Not applicable EPAD
Exposed Pad. The exposed pad must be tied to GND.
Rev. 0 | Page 8 of 28
Data Sheet
AD5697R
TYPICAL PERFORMANCE CHARACTERISTICS
2.5020
1600
1400
1200
1000
800
600
400
200
0
V
= 5V
= 25°C
DD
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
V
= 5V
DD
T
A
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
–40
–20
0
20
40
60
80
100
120
10
100
1k
10k
100k
1M
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 5. Internal Reference Voltage vs. Temperature
Figure 8. Internal Reference Noise Spectral Density vs. Frequency
90
80
70
60
50
40
30
20
10
0
V
= 5V
DD
V
= 5V
= 25°C
T
DD
T
A
1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TEMPERATURE DRIFT (ppm/°C)
CH1 10µV
M1.0s
A
CH1
160mV
Figure 6. Reference Output Temperature Drift Histogram
Figure 9. Internal Reference Noise, 0.1 Hz to 10 Hz
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
2.4994
2.4993
V
= 5.5V
0 HOUR
V
= 5V
= 25°C
DD
DD
168 HOURS
500 HOURS
1000 HOURS
60
50
40
30
20
10
0
T
A
2.498
2.499
2.500
(V)
2.501
2.502
–0.005
–0.003
–0.001
I
0.001
(A)
0.003
0.005
V
REF
LOAD
Figure 7. Reference Long-Term Stability/Drift
Figure 10. Internal Reference Voltage vs. Load Current
Rev. 0 | Page 9 of 28
AD5697R
Data Sheet
2.5002
2.5000
2.4998
2.4996
2.4994
2.4992
T
= 25°C
A
10
8
D1
D3
6
4
2
INL
0
DNL
–2
–4
–6
–8
–10
D2
(V)
V
= 5V
= 25°C
DD
T
A
2.4990
2.5
INTERNAL REFERENCE = 2.5V
3.0
3.5
4.0
4.5
5.0
5.5
–40 10
60
110
V
DD
TEMPERATURE (°C)
Figure 14. INL Error and DNL Error vs. Temperature
Figure 11. Internal Reference Voltage vs. Supply Voltage
10
8
10
8
6
6
4
4
2
2
INL
0
0
DNL
–2
–4
–6
–8
–10
–2
–4
–6
–8
–10
V
= 5V
= 25°C
DD
V
= 5V
= 25°C
DD
T
A
T
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
625 1250 1875
CODE
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
2500
3125
3750 4096
V
(V)
REF
Figure 15. INL Error and DNL Error vs. VREF
Figure 12. Integral Nonlinearity (INL) vs. Code
1.0
0.8
10
8
0.6
6
0.4
4
0.2
2
INL
0
0
DNL
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
–10
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
DD
DD
A
A
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE = 2.5V
625 1250 1875
CODE
4.2
4.7
5.2
0
2500
3125
3750 4096
Figure 16. INL Error and DNL Error vs. Supply Voltage
Figure 13. Differential Nonlinearity (DNL) vs. Code
Rev. 0 | Page 10 of 28
Data Sheet
AD5697R
1.5
1.0
0.10
0.08
0.06
0.04
0.02
0
0.5
ZERO-CODE ERROR
FULL-SCALE ERROR
GAIN ERROR
0
OFFSET ERROR
–0.02
–0.04
–0.06
–0.5
–1.0
–1.5
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
DD
DD
–0.08
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
–20 20 40
TEMPERATURE (°C)
–0.10
–40
0
60
80
100
120
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
Figure 17. Gain Error and Full-Scale Error vs. Temperature
Figure 20. Zero-Code Error and Offset Error vs. Supply Voltage
0.10
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
DD
DD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
ZERO-CODE ERROR
OFFSET ERROR
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Zero-Code Error and Offset Error vs. Temperature
Figure 21. Total Unadjusted Error vs. Temperature
0.10
0.08
0.06
0.04
0.02
0
0.10
0.08
0.06
0.04
0.02
0
GAIN ERROR
FULL-SCALE ERROR
–0.02
–0.04
–0.06
–0.08
–0.10
–0.02
–0.04
–0.06
–0.08
–0.10
V
T
= 5V
= 25°C
V
= 5V
DD
DD
T
= 25°C
A
A
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
4.2
4.7
5.2
4.2
4.7
5.2
Figure 19. Gain Error and Full-Scale Error vs. Supply Voltage
Figure 22. Total Unadjusted Error vs. Supply Voltage, Gain = 1
Rev. 0 | Page 11 of 28
AD5697R
Data Sheet
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
1.0
0.8
0.6
0.4
SINKING 2.7V
0.2
SINKING 5V
0
–0.2
–0.4
–0.6
–0.8
–1.0
SOURCING 5V
SOURCING 2.7V
15
V
= 5V
= 25°C
DD
–0.09
–0.10
T
A
INTERNAL REFERENCE = 2.5V
10000 20000 30000
CODE
0
40000
50000
60000 65535
0
5
10
20
25
30
LOAD CURRENT (mA)
Figure 23. Total Unadjusted Error vs. Code
Figure 26. Headroom/Footroom vs. Load Current
7
6
V
= 5V
= 25°C
DD
V
= 5V
= 25°C
25
20
15
10
5
DD
T
A
T
A
EXTERNAL
REFERENCE = 2.5V
GAIN = 2
INTERNAL
REFERENCE = 2.5V
FULL SCALE
5
4
THREE-QUARTER SCALE
3
MIDSCALE
ONE-QUARTER SCALE
ZERO SCALE
2
1
0
–1
0
–2
–0.06
540
560
580
600
620
640
–0.04
–0.02
0
0.02
0.04
0.06
I
FULL SCALE (V)
DD
LOAD CURRENT (A)
Figure 24. IDD Histogram with External Reference
Figure 27. Source and Sink Capability at VDD = 5 V
5
V
= 5V
= 25°C
DD
30
V
= 3V
= 25°C
DD
T
A
T
A
INTERNAL
EXTERNAL REFERENCE = 2.5V
GAIN = 1
4
3
REFERENCE = 2.5V
25
20
15
10
5
FULL SCALE
2
THREE-QUARTER SCALE
MIDSCALE
1
ONE-QUARTER SCALE
ZERO SCALE
0
–1
0
–2
–0.06
1000
1020
1040
1060
1080
1100
1120
1140
–0.04
–0.02
0
0.02
0.04
0.06
I
FULL SCALE (V)
DD
LOAD CURRENT (A)
Figure 25. IDD Histogram with Internal Reference, VREFOUT = 2.5 V, Gain = 2
Figure 28. Source and Sink Capability at VDD = 3 V
Rev. 0 | Page 12 of 28
Data Sheet
AD5697R
3
2
1
0
CHANNEL A
CHANNEL B
SYNC
1.4
1.2
1.0
0.8
GAIN = 2
FULL SCALE
ZERO CODE
GAIN = 1
EXTERNAL REFERENCE, FULL SCALE
0.6
0.4
0.2
0
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
–5
0
5
10
–40
10
60
110
TIME (µs)
TEMPERATURE (°C)
Figure 32. Exiting Power-Down to Midscale
Figure 29. Supply Current vs. Temperature
4.0
2.5008
2.5003
2.4998
2.4993
2.4988
DAC A
DAC B
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CHANNEL B
T
= 25°C
A
V
T
= 5V
DD
V
= 5.25V
DD
= 25°C
INTERNAL REFERENCE = 2.5V
POSITIVE MAJOR CODE TRANSITION
ENERGY = 0.227206nV-sec
A
INTERNAL REFERENCE = 2.5V
¼ TO ¾ SCALE
0
2
4
6
8
10
12
10
20
40
80
160
320
TIME (µs)
TIME (µs)
Figure 33. Digital-to-Analog Glitch Impulse
Figure 30. Settling Time
0.003
0.002
0.001
0
0.06
6
CHANNEL A
CHANNEL B
DD
CHANNEL B
V
0.05
0.04
0.03
0.02
0.01
0
5
4
3
2
1
–0.001
–0.002
0
T
= 25°C
A
INTERNAL REFERENCE = 2.5V
–0.01
–1
–10
–5
0
5
10
15
0
5
10
15
20
25
TIME (µs)
TIME (µs)
Figure 31. Power-On Reset to 0 V
Figure 34. Analog Crosstalk, Channel A
Rev. 0 | Page 13 of 28
AD5697R
Data Sheet
20
0
V
T
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
–20
–40
–60
–80
1
–100
–120
–140
–160
–180
V
= 5V
= 25°C
DD
T
A
EXTERNAL REFERENCE = 2.5V
0
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
FREQUENCY (Hz)
CH1 10µV M1.0s
A
CH1
802mV
Figure 35. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 38. Total Harmonic Distortion at 1 kHz
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
0nF
V
T
= 5V
= 25°C
DD
0.1nF
10nF
0.22nF
4.7nF
T
A
INTERNAL REFERENCE = 2.5V
1
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
1.590 1.595 1.600 1.605 1.610 1.615 1.620 1.625 1.630
CH1 10µV M1.0s
A
CH1
802mV
TIME (ms)
Figure 36. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
Figure 39. Settling Time vs. Capacitive Load
1600
0
V
T
= 5V
= 25°C
FULL SCALE
MIDSCALE
ZERO SCALE
DD
A
1400
1200
1000
800
600
400
200
0
INTERNAL REFERENCE = 2.5V
–10
–20
–30
–40
–50
–60
V
= 5V
DD
T
= 25°C
A
EXTERNAL REFERENCE = 2.5V, ±0.1V p-p
10k 100k 1M
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 37. Noise Spectral Density
Figure 40. Multiplying Bandwidth, External Reference = 2.5 V, 0.1 V p-p,
10 kHz to 10 MHz
Rev. 0 | Page 14 of 28
Data Sheet
AD5697R
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL vs. code plot is shown in Figure 12.
Output Voltage Settling Time
Output voltage settling time is the time it takes for the output of a
DAC to settle to a specified level for a ¼ to ¾ full-scale input
change.
Digital-to-Analog Glitch Impulse
Differential Nonlinearity (DNL)
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB at
the major carry transition, 0x7FFF to 0x8000 (see Figure 33).
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 13.
Digital Feedthrough
Zero-Code Error
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. It is specified
in nV-sec, and measured with a full-scale code change on the
data bus, that is, from all 0s to all 1s and vice versa.
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5697R because the output of the DAC cannot go less than
0 V due to a combination of the offset errors in the DAC and the
output amplifier. Zero-code error is expressed in mV. A plot of
the zero-code error vs. the temperature can be seen in Figure 18.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Full-Scale Error
Full-scale error is a measurement of the output error when the
full-scale code is loaded to the DAC register. Ideally, the output
should be VDD − 1 LSB. Full-scale error is expressed in percent of
full-scale range (% of FSR). A plot of the full-scale error vs. the
temperature can be seen in Figure 17.
Noise Spectral Density
This is a measurement of the internally generated random noise.
Random noise is characterized as a spectral density (nV/√Hz).
It is measured by loading the DAC to midscale and measuring
noise at the output. It is measured in nV/√Hz. A plot of noise
spectral density is shown in Figure 37.
Gain Error
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from the ideal expressed
as % of FSR.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in μV.
Offset Error Drift
This is a measurement of the change in offset error with a change
in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in ppm of FSR/°C.
DC crosstalk due to load current change is a measure of the impact
that a change in load current on one DAC has to another DAC
kept at midscale. It is expressed in μV/mA.
Offset Error
Digital Crosstalk
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5697R with
Code 512 loaded in the DAC register. It can be negative or positive.
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-sec.
DC Power Supply Rejection Ratio (PSRR)
Analog Crosstalk
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in mV/V. VREF is held at 2 V, and VDD is varied by 10%.
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa). Then execute a software LDAC
and monitor the output of the DAC whose digital code was not
changed. The area of the glitch is expressed in nV-sec.
Rev. 0 | Page 15 of 28
AD5697R
Data Sheet
DAC-to-DAC Crosstalk
Voltage Reference Temperature Coefficient (TC)
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent analog output change
of another DAC. It is measured by loading the attack channel
with a full-scale code change (all 0s to all 1s and vice versa), using
the write to and update commands while monitoring the output
of the victim channel that is at midscale. The energy of the glitch is
expressed in nV-sec.
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given temperature
range expressed in ppm/°C as follows;
V
REFmax −VREFmin
TC =
×106
V
×TempRange
REFnom
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
where:
REFmax is the maximum reference output measured over the total
temperature range.
REFmin is the minimum reference output measured over the total
temperature range.
REFnom is the nominal reference output voltage, 2.5 V.
TempRange is the specified temperature range of −40°C to +105°C.
V
V
V
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measurement of the harmonics
present on the DAC output. It is measured in dB.
Rev. 0 | Page 16 of 28
Data Sheet
AD5697R
THEORY OF OPERATION
The resistor string structure is shown in Figure 42. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is tapped
off by closing one of the switches connecting the string to the
amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
DIGITAL-TO-ANALOG CONVERTER
The AD5697R is a dual, 12-bit, serial input, voltage output DAC
with an internal reference. The part operates from supply voltages
of 2.7 V to 5.5 V. Data is written to the AD5697R in a 24-bit word
format via a 2-wire serial interface. The AD5697R incorporates a
power-on reset circuit to ensure that the DAC output powers up to
a known output state. The device also has a software power-down
mode that reduces the typical current consumption to 4 µA.
V
REF
R
TRANSFER FUNCTION
The internal reference is on by default. To use an external reference,
only a nonreference option is available. Because the input coding
to the DAC is straight binary, the ideal output voltage when using
an external reference is given by
R
R
TO OUTPUT
AMPLIFIER
D
2
VOUT =VREF ×Gain
N
where:
Gain is the gain of the output amplifier and is set to 1 by default.
This can be set to ×1 or ×2 using the gain select pin. When this
pin is tied to GND, both DAC outputs have a span from 0 V to
R
R
VREF. If this pin is tied to VLOGIC, both DAC output a span of 0 V to
2 × VREF
.
D is the decimal equivalent of the binary code that is loaded to the
DAC register as 0 to 4,095 for the 12-bit device.
N is the DAC resolution.
Figure 42. Resistor String Structure
Internal Reference
The AD5697R on-chip reference is on at power-up but can
be disabled via a write to a control register. See the Internal
Reference Setup section for details.
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 41 shows a block diagram of the DAC
architecture.
The AD5697R has a 2.5 V, 2 ppm/°C reference, giving a full-scale
output of 2.5 V or 5 V depending on the state of the GAIN pin.
The internal reference associated with the device is available at
the VREF pin. This buffered reference is capable of driving external
loads of up to 10 mA.
V
REF
2.5V
REF
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
X
OUT
Output Amplifiers
REF (–)
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, the offset error,
and the gain error. The GAIN pin selects the gain of the output.
GAIN
(GAIN = 1 OR 2)
GND
Figure 41. Single DAC Channel Architecture Block Diagram
•
If GAIN is tied to GND, both outputs have a gain of 1, and
the output range is 0 V to VREF
If GAIN is tied to VLOGIC, both outputs have a gain of 2, and
the output range is 0 V to 2 × VREF
.
•
.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale
settling time of 5 µs.
Rev. 0 | Page 17 of 28
AD5697R
Data Sheet
Table 8. Address Commands
SERIAL INTERFACE
Address (n)
The AD5697R has a 2-wire I2C-compatible serial interface (refer
to I2C-Bus Specification, Version 2.1, January 2000, available from
Philips Semiconductor). See Figure 2 for a timing diagram of a
typical write sequence. The AD5697R can be connected to an I2C
bus as a slave device, under the control of a master device. The
AD5697R can support standard (100 kHz) and fast (400 kHz) data
transfer modes. Support is not provided for 12-bit addressing
and general call addressing.
DAC B
0
0
0
0
0
0
0
0
DAC A
Description
0
1
1
1
0
1
DAC A
DAC B
DAC A and DAC B
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on
)
LDAC
Command 0001 allows the user to write to the dedicated input
LDAC
Input Shift Register
register of each DAC individually. When
is low, the input
LDAC
The input shift register of the AD5697R is 24 bits wide. Data is
loaded into the device as a 24-bit word under the control of
a serial clock input, SCL. The first eight MSBs make up the
command byte. The first four bits are the command bits (C3, C2,
C1, and C0) that control the mode of operation of the device
(see Table 7). The last four bits of the first byte are the address bits
(DAC B, 0, 0, and DAC A, see Table 8).
register is transparent (if not controlled by the
register).
mask
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers/outputs with the contents
of the input registers selected and updates the DAC outputs
directly.
Write to and Update DAC Channel n (Independent of
)
LDAC
The data-word comprises 12-bit input code, followed by four don’t
care bits for the AD5697R. These data bits are transferred to the
input register on the 24 falling edges of SCL.
Command 0011 allows the user to write to the DAC registers and
update the DAC outputs directly.
Commands can be executed on individual DAC channels or
both DAC channels, depending on the address bits selected.
Table 7. Command Definitions
Command
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
1
No operation
Write to Input Register n (dependent
on LDAC)
0
0
1
0
Update DAC Register n with contents of
Input Register n
0
0
0
0
1
1
1
0
0
1
0
1
Write to and update DAC Channel n
Power down/power up DAC
Hardware LDAC mask register
Software reset (power-on reset)
Internal reference setup register
Reserved
0
0
1
1
1
0
1
1
0
0
1
0
…
1
…
1
…
1
…
1
Reserved
Reserved
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1 C0 DAC A D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DAC B
0
0
X
X
X
X
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 43. Input Shift Register Content
Rev. 0 | Page 18 of 28
Data Sheet
AD5697R
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
3. When all data bits have been read or written, a stop condition
is established. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a stop condition.
In read mode, the master issues a no acknowledge for the
9th clock pulse (that is, the SDA line remains high). The
master then brings the SDA line low before the 10th clock
pulse, and then high during the 10th clock pulse to establish
a stop condition.
SERIAL OPERATION
The AD5697R has a 7-bit slave address. The five MSBs are 00011
and the two LSBs (A1 and A0) are set by the state of the A0 and
A1 address pins. The ability to make hardwired changes to A0
and A1 allows the user to incorporate up to four of these devices
on one bus, as outlined in Table 9.
Table 9. Device Address Selection
A0 Pin Connection
A1 Pin Connection
A0
0
1
A1
0
0
GND
VLOGIC
GND
GND
GND
VLOGIC
0
1
VLOGIC
VLOGIC
1
1
WRITE OPERATION
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
When writing to the AD5697R, the user must begin with a start
W
command followed by an address byte (R/ = 0), after which
the DAC acknowledges that it is prepared to receive data by
pulling SDA low. The AD5697R requires two bytes of data for the
DAC and a command byte that controls various DAC functions.
Three bytes of data must, therefore, be written to the DAC with the
command byte followed by the most significant data byte and
the least significant data byte, as shown in Figure 44. All these data
bytes are acknowledged by the AD5697R. A stop condition follows.
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the 9th clock pulse (this is termed
the acknowledge bit). At this stage, all other devices on the
bus remain idle while the selected device waits for data to
be written to, or read from, its shift register.
1
9
1
9
SCL
SDA
0
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK. BY
ACK. BY
AD5697R
START BY
MASTER
AD5697R
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB8
STOP BY
MASTER
ACK. BY
AD5697R
ACK. BY
AD5697R
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 44. I2C Write Operation
Rev. 0 | Page 19 of 28
AD5697R
Data Sheet
READ OPERATION
MULTIPLE DAC READBACK SEQUENCE
When reading data back from the AD5697R DACs, the user
W
The user begins with an address byte (R/ = 0), after which the
W
begins with an address byte (R/ = 0), after which the DAC
DAC acknowledges that it is prepared to receive data by pulling
SDA low. This address byte must be followed by the control byte,
which is also acknowledged by the DAC. The user configures
which channel to start the readback using the control byte.
Following this, there is a repeated start condition by the master,
acknowledges that it is prepared to receive data by pulling SDA
low. This address byte must be followed by the control byte that
determines both the read command that is to follow and the
pointer address to read from, which is also acknowledged by the
DAC. The user configures which channel to read back and sets
the readback command to active using the control byte. Following
this, there is a repeated start condition by the master and the
W
and the address is resent with R/ = 1. This is acknowledged
by the DAC, indicating that it is prepared to transmit data. The
first two bytes of data are then read from DAC Input Register A
that is selected using the control byte, most significant byte first,
as shown in Figure 45. The next four bytes read back are don’t care
bytes, and the next two bytes of data are the contents of DAC
Input Register B. Data continues to be read from the DAC input
registers in this auto-incremental fashion, until a NACK followed
by a stop condition follows. If the contents of DAC Input Register B
are read out, the next bytes of data that are read are from the
contents of DAC Input Register A.
W
address is resent with R/ = 1. This is acknowledged by the
DAC, indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC, as shown in Figure 45. A
NACK condition from the master, followed by a STOP condition,
completes the read sequence. Default readback is Channel A if
both DACs are selected.
1
9
1
9
SCL
SDA
0
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK. BY
ACK. BY
AD5697R
START BY
MASTER
AD5697R
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
SDA
0
0
0
1
1
A1
A0
R/W
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
REPEATED START BY
MASTER
ACK. BY
AD5697R
ACK. BY
AD5697R
FRAME 3
SLAVE ADDRESS
FRAME 4
MOST SIGNIFICANT
DATA BYTE n
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7 DB6
DB5 DB4
DB3 DB2
DB1
DB0
ACK. BY
MASTER
NACK. BY STOP BY
AD5697R MASTER
FRAME 3
FRAME 4
MOST SIGNIFICANT
DATA BYTE n – 1
SLAVE ADDRESS
SIGNIFICANT DATA BYTE n
Figure 45. I2C Read Operation
Rev. 0 | Page 20 of 28
Data Sheet
AD5697R
amplifier to a resistor network of known values. This has the
POWER-DOWN OPERATION
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different power-
down options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 46.
The AD5697R contains three separate power-down modes.
Command 0100 is designated for the power-down function (see
Table 7). These power-down modes are software programmable
by setting eight bits, Bit DB7 to Bit DB0, in the shift register. There
are two bits associated with each DAC channel. Table 10 shows
how the state of the two bits corresponds to the mode of operation
of the device.
AMPLIFIER
V
X
DAC
OUT
Table 10. Modes of Operation
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
PDx1
PDx0
0
0
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
0
1
1
1
0
1
Figure 46. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The DAC register can be
updated while the device is in power-down mode. The time
required to exit power-down is typically 4.5 µs for VDD = 5 V.
Either or both DACs (DAC A and DAC B) can be powered down
to the selected mode by setting the corresponding bits. See Table 11
for the contents of the input shift register during the power-down/
power-up operation.
When both Bit PDx1 and Bit PDx0 (where x is the channel
selected) in the input shift register are set to 0, the part works
normally with its normal power consumption of 4 mA at 5 V.
However, for the three power-down modes, the supply current
falls to 4 µA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
To reduce the current consumption further, the on-chip reference
can be powered off. See the Internal Reference Setup section.
Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1
DB23
(MSB)
DB0
(LSB)
DB22 DB21 DB20 DB19 to DB16
DB15 to DB8
DB7
DB6
DB5 DB4 DB3 DB2 DB1
0
1
0
0
X
X
PDB1
PDB0
1
1
1
1
PDA1 PDA0
Command bits (C3 to C0)
Address bits, don’t care
Power-down,
select DAC B
Power-down,
select DAC A
1 X = don’t care.
Rev. 0 | Page 21 of 28
AD5697R
Data Sheet
LOAD DAC (HARDWARE LDAC PIN)
LDAC MASK REGISTER
The AD5697R DACs have double buffered interfaces consisting
of two banks of registers: input registers and DAC registers. The
user can write to any combination of the input registers. Updates to
LDAC
mask function,
Command 0101 is reserved for this software
which allows the address bits to be ignored. Writing to the DAC
LDAC
using Command 0101 loads the 4-bit
The default for each channel is 0; that is, the
normally. Setting the bits to 1 forces this DAC channel to ignore
LDAC
register (DB3 to DB0).
LDAC
the DAC register are controlled by the
pin.
LDAC
pin works
OUTPUT
AMPLIFIER
transitions on the
pin, regardless of the state of the
pin. This flexibility is useful in applications where
12-BIT
DAC
V
V
REF
OUT
LDAC
hardware
LDAC
the user wishes to select which channels respond to the
pin.
DAC
REGISTER
LDAC
LDAC
Table 12.
Overwrite Definition
Load
Register
LDAC
INPUT
REGISTER
Bits
(DB3 or DB0)
LDAC
Pin
Operation
LDAC
LDAC
1 or 0
X1
SCL
SDO
INPUT SHIFT
REGISTER
0
1
Determined by the LDAC pin.
DAC channels update and
override the LDAC pin. DAC
channels see LDAC pin as 1.
Figure 47. Simplified Diagram of Input Loading Circuitry for a Single DAC
LDAC
Instantaneous DAC Updating (
Held Low)
1 X = don’t care.
LDAC
is held low while data is clocked into the input register
LDAC
The
the hardware
(DB3 or DB0) to 0 for a DAC channel means that the update of the
register gives the user extra flexibility and control over
using Command 0001. Both the addressed input register and
the DAC register are updated on the 24th clock, and the output
begins to change (see Table 14).
LDAC LDAC
pin (see Table 12). Setting the
bits
LDAC
channel is controlled by the hardware
pin.
LDAC
Deferred DAC Updating (
is Pulsed Low)
LDAC
is held high while data is clocked into the input register
using Command 0001. Both DAC outputs are asynchronously
th
LDAC
updated by taking
low after the 24 clock. The update
LDAC
then occurs on the falling edge of
.
1
LDAC
Table 13. 24-Bit Input Shift Register Contents for
Operation
DB23
(MSB)
DB0
(LSB)
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DBB15 to DB4 DB3
DAC B
DB2
DB1
0
0
0
1
X
X
X
X
X
0
0
DAC A
Command bits (C3 to C0)
Address bits,
don’t care
Don’t care
Setteing LDAC to 1 overrides
the LDAC pin
1 X = don’t care.
1
LDAC
Table 14. Write Commands and
Pin Truth Table
Hardware LDAC
Pin State
VLOGIC
Input Register
Contents
Command Description
DAC Register Contents
No change (no update)
Data update
0001
0010
0011
Write to Input Register n (dependent on LDAC)
Data update
Data update
No change
No change
Data update
Data update
GND2
Update DAC Register n with contents of
Input Register n
VLOGIC
GND
VLOGIC
GND
Updated with input register contents
Updated with input register contents
Data update
Write to and update DAC Channel n
Data update
1
LDAC
A high-to-low hardware
pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
mask register.
pin is permanently tied low, the
LDAC
(blocked) by the
2
LDAC
LDAC
mask bits are ignored.
When the
Rev. 0 | Page 22 of 28
Data Sheet
AD5697R
HARDWARE RESET (
)
SOLDER HEAT REFLOW
RESET
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test called precondition to
mimic the effect of soldering a device to a board. The output
voltage specification quoted in Table 2 includes the effect of this
reliability test.
RESET
is an active low reset that allows the outputs to be
cleared to either zero scale or midscale. The clear code value is
user selectable via the power-on reset select (RSTSEL) pin. It is
necessary to keep
to complete the operation . When the
high, the output remains at the cleared value until a new value
is programmed. The outputs cannot be updated with a new
RESET
low for a minimum amount of time
RESET
signal is returned
Figure 48 shows the effect of solder heat reflow (SHR) as measured
through the reliability test (precondition).
RESET
value while the
pin is low. Also, a software executable
reset function can reset the DAC to the power-on reset code.
Command 0110 is designated for this software reset function
POSTSOLDER
HEAT REFLOW
60
PRESOLDER
HEAT REFLOW
LDAC RESET
(see Table 7). Any events on
reset are ignored.
or
during power-on
50
40
30
20
10
0
RESET SELECT PIN (RSTSEL)
The AD5697R contains a power-on reset circuit that controls the
output voltage during power-up. By connecting the RSTSEL pin
low, the output powers up to zero scale. Note that this is outside
the linear region of the DAC; by connecting the RSTSEL pin
high, VOUT powers up to midscale. The output remains powered
up at this level until a valid write sequence is made to the DAC.
2.498
2.499
2.500
(V)
2.501
2.502
INTERNAL REFERENCE SETUP
V
REF
Command 0111 is reserved for setting up the internal reference
(see Table 7). By default, the on-chip reference is on at power-up.
To reduce the supply current, this reference can be turned off by
setting the software-programmable bit, DB0, as shown in Table 16.
Table 15 shows how the state of the bit corresponds to the mode
of operation.
Figure 48. SHR Reference Voltage Shift
LONG-TERM TEMPERATURE DRIFT
Figure 49 shows the change in VREF value after 1000 hours in life
test at 150°C.
0 HOUR
168 HOURS
500 HOURS
1000 HOURS
60
50
40
30
20
10
0
Table 15. Reference Setup Register
Internal Reference Setup Register (DB0) Action
0
1
Reference on (default)
Reference off
2.498
2.499
2.500
(V)
2.501
2.502
V
REF
Figure 49. Reference Drift Through to 1000 Hours
Table 16. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1
DB23 (MSB)
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
X
DB0 (LSB)
0
1
1
1
X
X
X
X
0/1
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t care
Reference setup register
1 X = don’t care.
Rev. 0 | Page 23 of 28
AD5697R
Data Sheet
9
8
7
6
5
4
3
2
1
THERMAL HYSTERESIS
FIRST TEMPERATURE SWEEP
SUBSEQUENT TEMPERATURE SWEEPS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
Thermal hysteresis data is shown in Figure 50. It is measured by
sweeping temperature from ambient to −40°C, then to +105°C,
and returning to ambient. The VREF delta is then measured between
the two ambient measurements and shown in blue in Figure 50.
The same temperature sweep and measurements are immediately
repeated, and the results are shown in red in Figure 50.
0
–200
–150
–100
–50
0
50
DISTORTION (ppm)
Figure 50. Thermal Hysteresis
Rev. 0 | Page 24 of 28
Data Sheet
AD5697R
APPLICATIONS INFORMATION
The AD5697R LFCSP model has an exposed paddle beneath
MICROPROCESSOR INTERFACING
the device. Connect this paddle to the GND supply for the part.
For optimum performance, use special considerations to design
the motherboard and to mount the package. For enhanced thermal,
electrical, and board level performance, solder the exposed paddle
on the bottom of the package to the corresponding thermal land
paddle on the PCB. Design thermal vias into the PCB land paddle
area to further improve heat dissipation.
Microprocessor interfacing to the AD5697R is via a serial bus that
uses a standard protocol that is compatible with DSP processors
and microcontrollers. The communications channel requires a
2-wire interface consisting of a clock signal and a data signal.
AD5697R-TO-ADSP-BF531 INTERFACE
The I2C interface of the AD5697R is designed to be easily
connected to industry-standard DSPs and microcontrollers.
Figure 51 shows the AD5697R connected to the Analog Devices
Blackfin® DSP (ADSP-BF531). The Blackfin has an integrated I2C
port that can be connected directly to the I2C pins of the AD5697R.
The GND plane on the device can be increased (as shown in
Figure 52) to provide a natural heat sinking effect.
AD5697R
AD5697R
ADSP-BF531
GND
PLANE
GPIO1
GPIO2
SCL
SDA
PF9
PF8
LDAC
BOARD
RESET
Figure 51. ADSP-BF531 Interface to the AD5338R
Figure 52. Paddle Connection to Board
LAYOUT GUIDELINES
GALVANICALLY ISOLATED INTERFACE
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. Design the printed circuit board (PCB) on
which the AD5697R is mounted so that the AD5697R lies on
the analog plane.
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. iCoupler®
products from Analog Devices provide voltage isolation in
excess of 2.5 kV. The serial loading structure of the AD5697R
makes the part ideal for isolated interfaces because the number of
interface lines is kept to a minimum. Figure 53 shows a 4-channel
isolated interface to the AD5697R using the ADuM1400. For
further information, visit http://www.analog.com/icouplers.
The AD5697R must have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply, located as close to the package
as possible, ideally right up against the device. The 10 µF capacitor
is the tantalum bead type. The 0.1 µF capacitor must have low
effective series resistance (ESR) and low effective series inductance
(ESI), such as the common ceramic types that provide a low
impedance path to ground at high frequencies to handle transient
currents due to internal logic switching.
ADuM14001
CONTROLLER
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
TO
SERIAL
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
SCLK
CLOCK IN
In systems where there are many devices on one board, it is often
useful to provide some heat sinking capability to allow the power
to dissipate easily.
TO
SDIN
SERIAL
DATA OUT
TO
RESET
RESET OUT
LOAD DAC
OUT
TO
LDAC
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 53. Isolated Interface
Rev. 0 | Page 25 of 28
AD5697R
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 54. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 55. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Reference
Temperature
Coefficient
(ppm/°C)
5 (max)
5 (max)
5 (max)
Package
Package Description Option
Model1
Resolution Temperature Range Accuracy
Branding
AD5697RBCPZ-RL7 12 Bits
AD5697RBRUZ 12 Bits
AD5697RBRUZ-RL7 12 Bits
EVAL-AD5697RSDZ
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
1 LSB INL
1 LSB INL
1 LSB INL
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
CP-16-22 DKY
RU-16
RU-16
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
Data Sheet
NOTES
AD5697R
Rev. 0 | Page 27 of 28
AD5697R
NOTES
Data Sheet
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11253-0-2/13(0)
Rev. 0 | Page 28 of 28
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