AD5700BCPZ-R5 [ADI]
Low Power HART Modem; 低功耗HART调制解调器
| 型号： | AD5700BCPZ-R5 |
| 厂家： | 
ADI |
| 描述： | Low Power HART Modem |
| 文件： | 总20页 (文件大小：490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power HART Modem
AD5700/AD5700-1
Data Sheet
FEATURES
GENERAL DESCRIPTION
HART-compliant fully integrated FSK modem
1200 Hz and 2200 Hz sinusoidal shift frequencies
115 μA maximum supply current in receive mode
Suitable for intrinsically safe applications
Integrated receive band-pass filter
Minimal external components required
Clocking optimized for various system configurations
Ultralow power crystal oscillator (60 μA maximum)
External CMOS clock source
Precision internal oscillator (AD5700-1 only)
Buffered HART output—extra drive capability
8 kV HBM ESD rating
2 V to 5.5 V power supply
1.71 V to 5.5 V interface
The AD5700/AD5700-1 are single-chip solutions, designed
and specified to operate as a HART® FSK half-duplex modem,
complying with the HART physical layer requirements. The
AD5700/AD5700-1 integrate all of the necessary filtering, signal
detection, modulating, demodulating and signal generation
functions, thus requiring few external components. The 0.5%
precision internal oscillator on the AD5700-1 greatly reduces
the board space requirements, making it ideal for line-powered
applications in both master and slave configurations. The maxi-
mum supply current consumption is 115 μA, making the AD5700/
AD5700-1 an optimal choice for low power loop-powered applica-
tions. Transmit waveforms are phase continuous 1200 Hz and
2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate
carrier detect circuitry and use a standard UART interface.
−40°C to +125°C operation
4 mm × 4 mm LFCSP package
HART physical layer compliant
UART interface
Table 1. Related Products
Part No.
Description
AD5755-1
Quad-channel, 16-bit, serial input, 4 mA to 20 mA and
voltage output DAC, dynamic power control, HART
connectivity
APPLICATIONS
Field transmitters
AD5421
16-bit, serial input, loop powered, 4 mA to 20 mA DAC
AD5410/
AD5420
AD5412/
AD5422
Single-channel, 12-bit/16-bit, serial input, 4 mA to 20 mA
current source DACs
Single-channel, 12-bit/16-bit, serial input, current
source and voltage output DACs
HART multiplexers
PLC and DCS analog I/O modules
HART network connectivity
FUNCTIONAL BLOCK DIAGRAM
CLKOUT XTAL1 XTAL2 XTAL_EN
V
REG_CAP
CC
IOV
CC
OSC
AD5700/AD5700-1
DUPLEX
CD
BUFFER
FSK
DAC
HART_OUT
MODULATOR
RXD
TXD
RTS
ADC_IP
BAND-PASS
FILTER AND
BIASING
FSK
DEMODULATOR
ADC
HART_IN
CLK_CFG0
CLK_CFG1
VOLTAGE
REFERENCE
RESET
DGND
REF REF_EN
AGND
FILTER_SEL
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
AD5700/AD5700-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 13
FSK Modulator ........................................................................... 13
Connecting to HART_OUT ..................................................... 14
FSK Demodulator ...................................................................... 14
Connecting to HART_IN or ADC_IP .................................... 14
Clock Configuration.................................................................. 15
Power-Down Mode.................................................................... 16
Full Duplex Operation............................................................... 16
Applications Information.............................................................. 17
Supply Decoupling ..................................................................... 17
Typical Connection Diagrams.................................................. 17
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
REVISION HISTORY
4/12—Rev. 0 to Rev. A
RTS
Change to Transmit Impedance Parameter,
Low, Table 2 .. 4
Changes to Figure 3, Figure 4, Figure 5, and Figure 7................. 9
Changes to Figure 10 and Figure 11............................................. 10
Changed AD5755 to AD5755-1 Throughout............................. 17
Change to Figure 27 ....................................................................... 18
2/12—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
AD5700/AD5700-1
SPECIFICATIONS
VCC = 2 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, AGND = DGND, CLKOUT disabled, HART_OUT with 5 nF load, internal and external
receive filter, internal reference, all specifications are from −40°C to +125°C and relate to both A and B models, unless otherwise noted.
Table 2.
Parameter1
POWER REQUIREMENTS2
Min
Typ
Max
Unit
Test Conditions/Comments
VCC
IOVCC
2
1.71
5.5
5.5
V
V
VCC and IOVCC Current Consumption
Demodulator
86
69
115
179
97
μA
μA
μA
B model, external clock, −40°C to +85°C
B model, external clock, −40°C to +125°C
B model, external clock, −40°C to +85°C,
external reference
157
μA
B model, external clock, −40°C to +125 °C,
external reference
260
140
193
96
μA
μA
μA
μA
A model, external clock, −40°C to +125°C
B model, external clock, −40°C to +85°C
B model, external clock, −40°C to +125°C
B model, external clock, −40°C to +85°C,
external reference
Modulator
124
73
153
μA
B model, external clock, −40°C to +125°C,
external reference
270
60
71
μA
μA
μA
μA
A model, external clock, −40°C to +125°C
External crystal, 16 pF at XTAL1 and XTAL2
External crystal, 36 pF at XTAL1 and XTAL2
AD5700-1 only, external crystal not required
RESET = REF_EN = DGND
Crystal Oscillator3
33
44
218
Internal Oscillator4
Power-Down Mode
285
VCC and IOVCC Current Consumption
16
35
75
μA
μA
Internal reference disabled, −40°C to +85°C
Internal reference disabled, −40°C to +125°C
INTERNAL VOLTAGE REFERENCE
Internal Reference Voltage
1.47
2.47
1.5
18
1.52
V
REF_EN = IOVCC to enable use of internal
reference
Tested with 50 μA load
Load Regulation
ppm/μA
OPTIONAL EXTERNAL VOLTAGE
REFERENCE
External Reference Input Voltage
2.5
2.53
V
REF_EN = DGND to enable use of external
reference, VCC = 2.7 V minimum
External Reference Input Current
Demodulator
16
28
21
33
7
μA
μA
μA
μA
Current required by external reference in
receive mode
Current required by external reference in
transmit mode
Current required by external reference if
using internal oscillator
Modulator
Internal Oscillator
5.5
4.6
Power-Down
DIGITAL INPUTS
8.6
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
0.7 × IOVCC
−0.1
V
V
μA
pF
0.3 × IOVCC
+0.1
Input Capacitance5
5
Per pin
Rev. A | Page 3 of 20
AD5700/AD5700-1
Data Sheet
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
CD Assert6
IOVCC − 0.5
85
V
V
0.4
110
100
mV p-p
HART_IN INPUT5
Input Voltage Range
0
0
REF
1.5
V
V
External reference source
Internal reference enabled
HART_OUT OUTPUT
Output Voltage
459
493
505
mV p-p
AC-coupled (2.2 μF), measured at HART_OUT
pin with 160 Ω load (worst-case load), see
Figure 15 and Figure 16 for HART_OUT
voltage vs. load
Mark Frequency7
Space Frequency7
Frequency Error
1200
2200
Hz
Hz
%
%
Degrees
Ω
Internal oscillator
Internal oscillator
Internal oscillator, −40°C to +85°C
Internal oscillator, −40°C to +125°C
−0.5
−1
+0.5
+1
0
Phase Continuity Error5
Maximum Load Current5
160
Worst-case load is 160 Ω, ac-coupled with
2.2 μF, see Figure 19 for recommended
configuration if driving a resistive load
Transmit Impedance
7
Ω
RTS low, at the HART_OUT pin
RTS high, at the HART_OUT pin
70
kΩ
1 Temperature range: −40°C to +125°C; typical at 25°C.
2 Current consumption specifications are based on mean current values.
3 The demodulator and modulator currents are specified using an external clock. If using an external crystal oscillator, the crystal oscillator current specification must be
added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode.
4 The demodulator and modulator currents are specified using an external clock. If using the internal oscillator, the internal oscillator current specification must be
added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode.
5 Guaranteed by design and characterization, but not production tested.
6 Specification set assuming a sinusoidal input signal containing preamble characters at the input and an ideal external filter (see Figure 21).
7 If the internal oscillator is not used, frequency accuracy is dependent on the accuracy of the crystal or clock source used.
Rev. A | Page 4 of 20
Data Sheet
AD5700/AD5700-1
TIMING CHARACTERISTICS
VCC = 2 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, TMIN to TMAX, unless otherwise noted, 1 bit time = 1/1200 Hz = 833.333 μs.
Table 3.
Parameter1
Limit at TMIN, TMAX Unit
Description
t1
1
1
1
Bit time2 max
Carrier start time. Time from RTS falling edge to carrier reaching its first peak. See
Figure 3.
Carrier stop time. Time from RTS rising edge to carrier amplitude dropping to ac
zero. See Figure 4.
Carrier decay time. Time from RTS rising edge to carrier amplitude dropping to ac
zero. See Figure 4.
t2
t3
Bit time2 max
Bit time2 max
t4
t5
t6
6
6
10
Bit times2 max
Bit times2 max
Bit times2 max
Carrier detect on. Time from carrier on to CD rising edge. See Figure 5.
Carrier detect off. Time from carrier off to CD falling edge. See Figure 6.
Carrier detect on when switching from transmit mode to receive mode in the
presence of a constant valid carrier. Time from RTS rising edge to CD rising edge.
See Figure 7.
t7
2.1
ms typ
Crystal oscillator power-up time. On application of a valid power supply voltage at
VCC or on enabling of the oscillator via the XTAL_EN pin. Crystal load capacitors =
8 pF.
t8
t9
6
25
ms typ
μs typ
Crystal oscillator power-up time. Crystal load capacitors = 18 pF.
Internal oscillator power-up time. On application of a valid power supply voltage
at VCC or on enabling of the oscillator via the CLK_CFG0 and CLK_CFG1 pins.
t10
t11
10
30
ms typ
μs typ
Reference power-up time.
Transition time from power-down mode to normal operating mode (external
clock source, external reference).
1 Specifications apply to AD5700/AD5700-1 configured with internal or external receive filter.
2 Bit time is the length of time to transfer one bit of data.
Rev. A | Page 5 of 20
AD5700/AD5700-1
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VCC to GND
IOVCC to GND
−0.3 V to +7 V
−0.3 V to +7 V
Digital Inputs to DGND
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
THERMAL RESISTANCE
Digital Output to DGND
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
HART_OUT to AGND
HART_IN to AGND
−0.3 V to +2.5 V
−0.3 V to VCC + 0.3 V or
+7 V (whichever is less)
Table 5. Thermal Resistance
Package Type
θJA
θJC
Unit
ADC_IP
−0.3 V to VCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to +0.3 V
24-Lead LFCSP
30
3
°C/W
AGND to DGND
ESD CAUTION
Operating Temperature Range (TA)
Industrial
Storage Temperature Range
−40°C to +125°C
−65°C to +150°C
150°C
(TJ MAX – TA)/θJA
JEDEC industry standard
J-STD-020
Junction Temperature (TJ MAX
Power Dissipation
Lead Temperature,
Soldering
)
ESD
Human Body Model
8 kV
(ANSI/ESDA/JEDEC JS-001-2010)
Field Induced Charge Model
(JEDEC JESD22_C101E)
Machine Model
1.5 kV
400 V
(ANSI/ESD S5.2-2009)
Rev. A | Page 6 of 20
Data Sheet
AD5700/AD5700-1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
18 V
CC
XTAL_EN
CLKOUT 2
LK_CFG0 3
17
ADC_IP
AD5700/
16 HART_IN
15 REF
C
AD5700-1
TOP VIEW
(Not to Scale)
CLK_CFG1
RESET
4
5
14
13
HART_OUT
REG_CAP
CD 6
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED
N
TO AGND OR DGND, OR, ALTERNATIVELY, IT CA
IT IS
BE LEFT ELECTRICALLY UNCONNECTED.
RECOMMENDED THAT THE PADDLE BE THERMALLY
CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
Figure 2. AD5700/AD5700-1 Pin Configuration
Table 6. AD5700/AD5700-1 Pin Function Descriptions
Pin No. Mnemonic Description
1
XTAL_EN
Crystal Oscillator Circuit Enable. A low state enables the crystal oscillator circuit, and an external crystal is
required. A high state disables the crystal oscillator circuit, and an external clock source or the internal oscillator
(AD5700-1 only) provides the clock source. This pin is used in conjunction with the CLK_CFG0 and CLK_CFG1
pins in configuring the required clock generation scheme.
2
CLKOUT
Clock Output. If using the crystal oscillator or the internal RC oscillator, a clock output can be configured at the
CLKOUT pin. Enabling the clock output consumes extra current to drive the load on this pin. See the CLKOUT
section for more details.
3
4
5
CLK_CFG0
CLK_CFG1
RESET
Clock Configuration Control. See Table 7.
Clock Configuration Control. See Table 7.
Active Low Digital Input. Holding RESET low places the AD5700/AD5700-1 in power-down mode. A high state on
RESET returns the AD5700/AD5700-1 to their power-on state. If not using this pin, tie this pin to IOVCC.
6
7
8
CD
TXD
RTS
Carrier Detect—Digital Output. A high on CD indicates a valid carrier is detected.
Transmit Data—Digital Input. Data input to the modulator.
Request to Send—Digital Input. A high state enables the demodulator and disables the modulator. A low state
enables the modulator and disables the demodulator.
9
DUPLEX
A high state on this pin enables full duplex operation. See the Theory of Operation section. A low state disables
this feature.
10
11
RXD
IOVCC
Receive Data—UART Interface Digital Data Output. Data output from the demodulator is accessed on this pin.
Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. The applied
voltage can be in the range of 1.71 V to 5.5 V.
12
DGND
Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to
AGND.
13
14
15
REG_CAP
HART_OUT
REF
Capacitor Connection for Internal Voltage Regulator. Connect a 1 μF capacitor from this pin to ground.
HART FSK Signal Output. See the FSK Modulator section and Figure 26 for typical connections.
Internal Reference Voltage Output, or External 2.5 V Reference Voltage Input. Connect a 1 μF capacitor from this
pin to ground. When supplying an external reference, the VCC supply requires a minimum voltage of 2.7 V.
16
17
18
19
HART_IN
ADC_IP
VCC
HART FSK Signal. When using the internal filter, couple the HART input signal into this pin using a 2.2 nF series
capacitor. If using an external band-pass filter as shown in Figure 21, do not connect to this pin.
If using the internal band-pass filter, connect 680 pF to this pin. Alternatively, this pin allows direct connection to
the ADC input, in which case an external band-pass filter network must be used, as shown in Figure 21.
Power Supply Input. 2 V to 5.5 V can be applied to this pin. VCC should be decoupled to ground with low ESR
10 μF and 0.1 μF capacitors (see the Supply Decoupling section).
Analog Circuitry Ground Reference Connection.
AGND
Rev. A | Page 7 of 20
AD5700/AD5700-1
Data Sheet
Pin No. Mnemonic
Description
Connection for External 3.6864 MHz Crystal. Do not connect to this pin if using the internal RC oscillator
(AD5700-1 only) or an external clock source.
Connection for External 3.6864 MHz Crystal or External Clock Source Input. Tie this pin to ground if using the
internal RC oscillator (AD5700-1 only).
Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to
AGND.
20
21
22
23
XTAL2
XTAL1
DGND
REF_EN
Reference Enable. A high state enables the internal 1.5 V reference and buffer. A low state disables the internal
reference and input buffer, and a buffered external 2.5 V reference source must be applied at REF. If REF_EN is
tied low, VCC must be greater than 2.7 V.
24
FILTER_SEL
AGND
Band-Pass Filter Select. A high state enables the internal filter and the HART signal should be applied to the
HART_IN pin. A low state disables the internal filter and an external band-pass filter must then be connected at
the ADC_IP input pin. In this case, the HART signal should be applied to the ADC_IP pin.
EPAD
Analog Ground Reference Connection. For typical operation, it is recommended to connect this pin to AGND.
Rev. A | Page 8 of 20
Data Sheet
AD5700/AD5700-1
TYPICAL PERFORMANCE CHARACTERISTICS
1.4
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
= 25°C; V = IOV = 3.3V; INT V
CC CC REF
T
= 25°C; V = IOV = 3.3V; INT V
CC CC REF
A
A
RTS AND TXD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
CD AND RXD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
1.2
1.0
0.8
0.6
0.4
0.2
0
CD
RTS
TXD
RXD
HART SIGNAL
HART_OUT
–0.2
–0.2
–0.4
–0.3
–0.4
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
–5
–4
–3
–2
–1
0
1
TIME (ms)
TIME (ms)
Figure 3. Carrier Start Time
Figure 6. Carrier Detect Off Timing
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.50
1.25
1.00
0.75
T
= 25°C; V = IOV = 3.3V; INT V
REF
T
= 25°C; V = IOV = 3.3V; INT V
CC CC REF
A
CC
CC
A
RTS AND CD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
RTS AND TXD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
RTS
RTS
TXD
CD
0.50
0.25
0
HART SIGNAL HAS ALSO
BEEN OFFSET BY –0.6V.
HART_OUT
HART_OUT
–0.25
–0.50
–0.75
–1.00
–0.2
–0.4
HART SIGNAL
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
–10
–7.5
–5.0
–2.5
0
2.5
TIME (ms)
TIME (ms)
Figure 4. Carrier Stop/Decay Time
Figure 7. Carrier Detect on When Switching from Transmit Mode to Receive
Mode in the Presence of a Constant Valid Carrier
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
T
V
= 25°C
T
= 25°C; V = IOV = 3.3V; INT V
REF
A
A
CC
CC
= IOV = 2.7V TO 5.5V
CC
CC
CD AND RXD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
90
80
70
60
DEV 1 EXT REF
MOD I AND IOI
CC
CC
CD
DEMOD I AND IOI
CC
CC
RXD
50
40
30
20
10
0
MOD I
REF
DEMOD I
REF
HART SIGNAL
–0.2
–0.4
–0.5
0
0.5
1.0
1.5
2.0
2.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
TIME (ms)
V
= IOV (V)
CC
CC
Figure 5. Carrier Detect On Timing
Figure 8. Supply Currents vs. Supply Voltage—External Reference
Rev. A | Page 9 of 20
AD5700/AD5700-1
Data Sheet
200
180
160
140
120
0
T
V
INT V
= 25°C
T
V
= 25°C
A
A
–2
= IOV = 2V TO 5.5V
= IOV = 3.3V
CC
CC
CC CC
DEV 1 INT REF
REF
–4
–6
–8
MOD I AND IOI
CC
CC
100
80
–10
–12
–14
–16
DEMOD I
AND IOI
CC
CC
EXTERNAL FILTER
INTERNAL FILTER
60
40
20
0
–18
–20
1.0
1.5
2.0
2.5
3.0
V
3.5
4.0
4.5
5.0
5.5
6.0
100
1k
FREQUENCY (Hz)
10k
= IOV (V)
CC
CC
Figure 12. Input Filter Frequency Response
Figure 9. Supply Currents vs. Supply Voltage—Internal Reference
700
1.5012
1.5010
1.5008
1.5006
1.5004
1.5002
1.5000
1.4998
1.4996
T
= 25°C; V = IOV = 3.3V; INT V
CC CC REF
A
T
= 25°C
A
CLK CONFIG = XTAL OSCILLATOR
IOI = 41µA
V
= IOV = 2V TO 5.5V
CC
CC
600
500
CC
400
TXD = 1
TXD = 0
300
200
100
0
2.2µF
HART_OUT
200
22nF
R
LOAD
0
400
600
800
1000
1200
1.0
1.5
2.0
2.5
3.0
3.5
(V)
4.0
4.5
5.0
5.5
6.0
R
(Ω) WITH 22nF TO GND
LOAD
V
CC
Figure 10. Current in Tx Mode vs. Resistive Load
Figure 13. Reference Voltage vs. VCC
1.5006
1.5004
1.5002
1.5000
1.4998
250
V
= IOV = 2.7V
CC
CC
T
= 25°C; V = IOV = 3.3V; INT V
CC CC REF
A
TEMPERATURE = –40°C TO +125°C
225 CLK CONFIG = XTAL OSCILLATOR
CAPACITIVE LOAD ONLY
IOI = 41µA
200
175
150
125
100
75
CC
1.4996
1.4994
TXD = 1
TXD = 0
50
1.4992
1.4990
25
0
0
10
20
30
40
50
60
–40
–20
0
20
40
60
80
100
120
C
(nF)
TEMPERATURE (°C)
LOAD
Figure 14. Reference Voltage vs. Temperature
Figure 11. Current in Tx Mode vs. Capacitive Load
Rev. A | Page 10 of 20
Data Sheet
AD5700/AD5700-1
500
505
504
T
V
INT V
= 25°C
T
= 25°C
A
A
= IOV = 3.3V
V
= IOV = 3.3V
CC
CC
CC
CC
495
490
INT V
REF
REF
503
CAPACITIVE LOAD ONLY
502
501
500
485
1200Hz
2200Hz
480
475
470
465
499
498
497
1200Hz
2200Hz
2.2µF
HART_OUT
22nF
800
R
LOAD
496
495
0
200
400
600
1000
1200
0
10
20
30
40
50
60
R
(Ω) || WITH 22nF TO GND
C
(nF)
LOAD
LOAD
Figure 15. HART_OUT Voltage vs. RLOAD
Figure 16. HART_OUT Voltage vs. CLOAD
Rev. A | Page 11 of 20
AD5700/AD5700-1
TERMINOLOGY
Data Sheet
HART_OUT Output Voltage
VCC and IOVCC Current Consumption
This is the peak-to-peak HART_OUT output voltage. The
specification in Table 2 was set using a worst-case load of 160 Ω,
ac-coupled with a 2.2 μF capacitor. Figure 15 and Figure 16 show
HART_OUT output voltages for both resistive and purely
capacitive loads.
This specification gives a summation of the current consump-
tion of both the VCC and the IOVCC supplies. Figure 11 shows
separate measurements for VCC and IOVCC currents vs. varying
capacitive loads, in transmit mode.
Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/μA.
Mark/Space Frequency
A 1.2 kHz signal represents a digital 1, or mark, whereas a
2.2 kHz signal represents a 0, or space.
CD Assert
Phase Continuity Error
The minimum value at which the carrier detect signal asserts is
85 mV p-p and the maximum value it asserts at is 110 mV p-p. CD
is already high (asserted) for HART input signals greater than
110 mV p-p. This specification was set assuming a sinusoidal
input signal containing preamble characters at the input and an
ideal external filter (see Figure 21).
The DDS engine in this design inherently generates continuous
phase signals, thus avoiding any output discontinuity when
switching between frequencies. This attribute is desirable for
signals that are to be transmitted over a band limited channel,
because discontinuities in a signal introduce wideband fre-
quency components. As the name suggests, for a signal to be
continuous, the phase continuity error must be 0o.
Rev. A | Page 12 of 20
Data Sheet
AD5700/AD5700-1
THEORY OF OPERATION
FSK MODULATOR
Highway Addressable Remote Transducer (HART) Communica-
tion is the global standard for sending and receiving digital
information across analog wires between smart field devices
and control systems. This is a digital two-way communication
system, in which a 1 mA p-p frequency shift keyed (FSK) signal
is modulated on top of a 4 mA to 20 mA analog current signal.
The AD5700/AD5700-1 are designed and specified to operate
as a single-chip, low power, HART FSK half-duplex modem,
complying with the HART physical layer requirements
(Revision 8.1).
The modulator converts a bit stream of UART-encoded HART
data at the TXD input to a sequence of 1200 Hz and 2200 Hz
tones (see Figure 17). This sinusoidal signal is internally buff-
ered and output on the HART_OUT pin. The modulator is
RTS
enabled by bringing the
signal low.
"1" = MARK
1.2kHz
"0" = SPACE
2.2kHz
A single-chip solution, the AD5700/AD5700-1 not only inte-
grate the modulation and demodulation functions, but also
contain an internal reference, an integrated receive band-pass
filter (which has the flexibility of being bypassed if required),
and an internally buffered HART output, giving a high output
drive capability and removing the need for external buffering.
The AD5700-1 option also contains a precision internal RC
oscillator. The block diagram in Figure 1 shows a graphical
illustration of how these circuit blocks are connected together.
As a result of such extensive integration options, minimal
external components are required. The AD5700/AD5700-1
are suitable for use in both HART field instrument and master
configurations.
START
TXD
STOP
HART_OUT
8-BIT DATA + PARITY
Figure 17. AD5700/AD5700-1 Modulator Waveform
The modulator block contains a DDS engine that produces a
1.2 kHz or 2.2 kHz sine wave in digital form and then performs
a digital-to-analog conversion. This DDS engine inherently
generates continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies. For more
information on DDS fundamentals, see MT-085, Fundamentals
of Direct Digital Synthesizers (DDS). Figure 18 demonstrates a
simple implementation of this FSK encoding.
The AD5700/AD5700-1 either transmit or receive 1.2 kHz and
2.2 kHz carrier signals. A 1.2 kHz signal represents a digital 1,
or mark, whereas a 2.2 kHz signal represents a 0, or space.
There are three main clocking configurations supported by
these parts, two of which are available on the AD5700 option,
whereas all three are available on the AD5700-1 device:
External crystal
CMOS clock input
Internal RC oscillator (AD5700-1 only)
1
DATA
0
1.2kHz
WORD
The device is controlled via a standard UART interface. The
RTS
more detail on individual pin descriptions).
relevant signals are
, CD, TXD, and RXD (see Table 6 for
DAC
FSK
DDS
2.2kHz
WORD
CLOCK
Figure 18. DDS-Based FSK Encoder
Rev. A | Page 13 of 20
AD5700/AD5700-1
Data Sheet
CONNECTING TO HART_OUT
FSK DEMODULATOR
The HART_OUT pin is dc biased to 0.75 V and should be
capacitively coupled to the load. The current consumption
specifications in Table 2 are based on driving a 5 nF load. If
the application requires a larger load value, more current is
required. This value can be calculated from the following
formula:
HART_IN
8-BIT DATA + PARITY
RXD
STOP
START
I
TOTAL IAD5700 ILOADRMS
Figure 20. AD5700/AD5700-1 Demodulator Waveform
(Preamble Message 0xFF)
500 mV
ILOAD RMS
(1)
2
RTS
When
is logic high, the modulator is disabled and the
1
2
4 2
RLOAD
demodulator is enabled, that is, the AD5700/AD5700-1 are in
receive mode. A high on CD indicates a valid carrier is detected.
The demodulator accepts an FSK signal at the HART_IN pin
and restores the original modulated signal at the UART
interface digital data output pin, RXD. The combination of the
ADC, digital filtering and digital demodulation results in a
highly accurate output on the RXD pin. The HART bit stream
follows a standard UART frame with a start bit, 8-bit data, one
parity, and a stop bit (see Figure 20).
2 f CLOAD
where:
AD5700 is the current drawn by the AD5700/AD5700-1 in
transmit mode as per specifications (see Table 2). Note that the
specifications in Table 2 assume a 5 nF CLOAD
f is the output frequency (1.2 kHz or 2.2 kHz).
LOAD is the capacitive load to ground on HART_OUT.
LOAD is the resistive load on the loop.
I
.
C
R
CONNECTING TO HART_IN OR ADC_IP
When driving a purely capacitive load, the load should be in the
range of 5 nF to 52 nF. See Figure 11 for a typical plot of supply
current vs. capacitive load.
The AD5700/AD5700-1 have two filter configuration options:
an external filter (HART signal is applied to ACP_IP) and an
internal filter (HART signal is applied to HART_IN).
Example
Assume use of an internal reference, and CLOAD = 52 nF.
The external filter configuration is shown in Figure 21. In this
case, the HART signal is applied to the ADC_IP pin through an
external filter circuit. In safety critical applications, the AD5700/
AD5700-1 must be isolated from the high voltage of the loop
supply. The recommended external band-pass filter includes a
150 kΩ resistor, which limits current to a sufficiently low level
to adhere to intrinsic safety requirements. In this case, the input
has higher transient voltage protection and should, therefore,
not require additional protection circuitry, even in the most
demanding of industrial environments. Assuming the use of a
1% accurate resistor and 10% accurate capacitor components,
the calculated variation in CD trip voltage levels vs. the ideal is
3.5 mV.
ICC + IOICC = 140 μA maximum (from Table 2
specification)
Note that this is incorporating a 5 nF load.
Therefore, to calculate the load current required to drive the
extra 47 nF, use the Equation 1.
Substituting f = 1200 Hz, CLOAD = 47 nF, and RLOAD = 0 Ω into
the formula results in ILOAD of 62.6 μA.
If using the crystal oscillator, this adds 60 μA maximum (see
Table 2 for conditions).
Thus, the total worst-case current in this example is:
140 μA + 62.6 μA + 60 μA = 262.6 μA
HART_OUT
If driving a load with a resistive element, it is recommended to
place a 22 nF capacitor to ground at the HART_OUT pin. The
load should be coupled with a 2.2 μF series capacitor. For low
impedance devices, the RLOAD range is typically 230 Ω to 600 Ω.
HART
AD5700/
REF
NETWORK
AD5700-1
1µF
1.2MΩ
150kΩ
ADC_IP
300pF
1.2MΩ
150pF
2.2µF
HART_OUT
Figure 21. AD5700/AD5700-1 with External Filter on ADC_IP
22nF
R
LOAD
Figure 19. AD5700/AD5700-1 with Resistive Load at HART_OUT
Rev. A | Page 14 of 20
Data Sheet
AD5700/AD5700-1
The internal filter configuration is shown in Figure 22. This
option is beneficial where cost or board space is a large concern
because it removes the need for multiple external components.
This configuration achieves an 8 kV ESD HBM rating but
requires extra external protection circuitry for EMC and surge
protection purposes if used in harsh industrial environments.
CMOS Clock Input
A CMOS clock input can also be used to generate a clock for the
AD5700/AD5700-1. To use this mode, connect an external clock
source to the XTAL 1 pin, and leave XTAL2 open circuit (see
Figure 24).
HART_OUT
HART
NETWORK
2.2nF
AD5700/
AD5700-1
HART_IN
ADC_IP
680pF
AD5700/AD5700-1
Figure 22. AD5700/AD5700-1 Using Internal Filter on HART_IN
CLOCK CONFIGURATION
Figure 24. CMOS Clock Connection
The AD5700/AD5700-1 support numerous clocking configura-
tions to allow the optimal trade-off between cost and power:
Internal Oscillator (AD5700-1 only)
Consuming typically 218 μA, the low power, internal, 0.5 %
precision RC oscillator, available only on the AD5700-1, has an
oscillation frequency of 1.2288 MHz. To use this mode, tie the
XTAL1 pin to ground and leave the XTAL2 pin open circuit
(see Figure 25).
External crystal
CMOS clock input
Internal RC oscillator (AD5700-1 only)
XTAL_EN
The CLK_CFG0, CLK_CFG1, and
pins configure
the clock generation as shown in Table 7. The AD5700/AD5700-1
can also provide a clock output at CLKOUT (for more details,
see the CLKOUT section).
External Crystal
AD5700-1
The typical connection for an external crystal (ABLS-3.6864MHZ-
L4Q-T) is shown in Figure 23. To ensure minimum current
consumption and to minimize stray capacitances, connections
between the crystal, capacitors, and ground should be made as
close to the AD5700/AD5700-1 as possible. Consult individual
crystal vendors for recommended load information and crystal
performance specifications.
Figure 25. Internal Oscillator Connection
CLKOUT
The AD5700/AD5700-1 can provide a clock output at CLKOUT
(see Table 7).
ABLS-3-6864MHZ-L4Q-T
If using the crystal oscillator, this clock output can be
configured as a 3.6864 MHz, 1.8432 MHz, or 1.2288 MHz
buffer clock.
18pF
18pF
If using a CMOS clock, no clock output can be configured
at the CLKOUT pin.
If using the internal RC oscillator, this clock output is only
available as a 1.2288 MHz buffer clock.
AD5700/AD5700-1
The amplitude of the clock output depends on the IOVCC level;
therefore, the clock output can be in the range of 1.71 V p-p to
5.5 V p-p. Enabling the clock output of the AD5700/AD5700-1
increases the current consumption of the device. This increase
is due to the current required to drive any load at the CLKOUT
pin, which should not be more than 30 pF.
Figure 23. Crystal Oscillator Connection
The ABLS-3.6864MHZ-L4Q-T crystal oscillator data sheet
recommended two 18 pF capacitors. Because the crystal current
consumption is dominated by the load capacitance, in an effort
to reduce the crystal current consumption, two 8 pF capacitors
were used on the XTAL1 and XTAL2 pins. The AD5700/AD5700-1
still functioned as expected, even with the resulting reduction in
frequency performance from the crystal due to the smaller
capacitance values. Crystals are available that support 8 pF
capacitors. It is recommended to consult the relevant crystal
manufacturers for this information.
This capacitance should be minimized to reduce current
consumption and provide the clock with the cleanest edges.
The additional current drawn from the IOVCC supply can be
calculated using the following equation:
I = C × V × f
Rev. A | Page 15 of 20
AD5700/AD5700-1
Data Sheet
Table 7. Clock Configuration Options
XTAL_EN CLK_CFG1 CLK_CFG0 CLKOUT
Description
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No output
No output
No output
1.2288 MHz output
No output
3.6864 MHz output
1.8432 MHz output
1.2288 MHz output
3.6864 MHz CMOS clock connected at XTAL1 pin
1.2288 MHz CMOS clock connected at XTAL1 pin
Internal oscillator enabled (AD5700-1 only)
Internal oscillator enabled, CLKOUT enabled (AD5700-1 only)
Crystal oscillator enabled
Crystal oscillator enabled, CLKOUT enabled
Crystal oscillator enabled, CLKOUT enabled
Crystal oscillator enabled, CLKOUT enabled
POWER-DOWN MODE
FULL DUPLEX OPERATION
The AD5700/AD5700-1 can be placed into power-down mode
RESET
Full duplex operation means that the modulator and demodula-
tor of the AD5700/AD5700-1 are enabled at the same time. This
is a powerful feature, enabling a self-test procedure of not only
the HART device but also the complete signal path between the
HART device and the host controller. This provides verification
that the local communications loop is functional. This increased
level of system diagnostics is useful in production self-test and
is advantageous in improving the application’s safety integrity
level (SIL) rating. The full duplex mode of operation is enabled by
connecting the DUPLEX pin to logic high.
by holding the
is recommended to tie the REF_EN pin to the
that it is also powered down. If the reference is not powered
RESET
pin low. If using the internal reference, it
RESET
pin so
down while
approximately 1.7 V until
is low, the output voltage on the REF pin is
RESET
is brought high again.
In this mode, the receive, transmit, and oscillator circuits are all
switched off, and the device consumes a typical current of 16 μA.
Rev. A | Page 16 of 20
Data Sheet
AD5700/AD5700-1
APPLICATIONS INFORMATION
The AD5700/AD5700-1 are designed to interface easily with
Analog Devices, Inc., innovative portfolio of industrial
converters like the AD5421 loop-powered current-output DAC,
the AD5410/AD5420 and AD5412/AD5422 family of line-
powered current-output DACs, and the AD5755-1, a quad DAC
with innovative dynamic power control technology. The
combination of Analog Devices industrial converters and the
AD5700/AD5700-1 greatly simplifies system design, enhancing
reliability while reducing overall PCB size.
SUPPLY DECOUPLING
It is recommended to decouple the VCC and IOVCC supplies with
10 ꢀF in parallel with 0.1 ꢀF capacitors to ground. For many
applications, 1 ꢀF in parallel with 0.1 ꢀF ceramic capacitors to
ground should be sufficient. The REG_CAP voltage of 1.8 V is
used to supply the AD5700/AD5700-1 internal circuitry and is
derived from the VCC supply using a high efficiency clocking
LDO. Decouple this REG_CAP supply with a 1 μF ceramic
capacitor to ground. It is also required to decouple the REF pin
with a 1 μF ceramic capacitor to ground. Place decoupling
capacitors as close to the relevant pins as possible.
Figure 27 shows how the AD5700/AD5700-1 HART modem
can be interfaced with the AD5421 (4 mA to 20 mA loop-powered
DAC) and a microcontroller to construct a loop powered transmit-
ter circuit. The HART signal from HART_OUT is introduced to
the AD5421 via the CIN pin.
For loop-powered applications, it is recommended to connect a
resistance in series with the VCC supply to minimize the effect of
any noise, which may, depending on the system configuration, be
introduced onto the loop as a result of current draw variations
from the AD5700/AD5700-1. For typical applications, 470 Ω of
resistance has proven most effective. However, depending on the
application conditions, alternative values may also be acceptable
(see R1 in Figure 27).
The HART enabled smart transmitter reference demo circuit
(the block diagram shown in Figure 28) was developed by
Analog Devices and uses the AD5421, a 16-bit, loop-powered,
4 mA to 20 mA DAC, and the AD5700 modem. This circuit has
been compliance tested, verified, and registered as an approved
HART solution by the HART Communication Foundation.
Contact your sales representative for further information about
this demo circuit.
TYPICAL CONNECTION DIAGRAMS
Figure 26 shows a typical connection diagram for the AD5700/
AD5700-1 using the external and internal options. See the
Connecting to HART_IN or ADC_IP section for more details.
In conclusion, the AD5700/AD5700-1 enable quick and easy
deployment of a robust HART-compliant system.
1.71V TO 5.5V
+
2V TO 5.5V
10µF
1.71V TO 5.5V
+
2V TO 5.5V
10µF
1µF
1µF
10µF
0.1µF
10µF
0.1µF
0.1µF
0.1µF
IOV
CC
V
IOV
CC
V
CC
CC
HART_OUT
HART_OUT
CD
CD
1µF
REF
REF
RXD
TXD
RTS
RXD
TXD
RTS
1µF
AD5700/AD5700-1
AD5700/AD5700-1
1.2MΩ
1.2MΩ
300pF
680pF
150kΩ
ADC_IP
ADC_IP
150pF
2.2nF
HART_IN
HART_IN
DGND AGND
DGND AGND
CONFIGURATION
PINS
CONFIGURATION
PINS
Figure 26. AD5700/AD5700-1 Typical Connection Diagram for External and Internal Filter Options
Rev. A | Page 17 of 20
AD5700/AD5700-1
Data Sheet
OPTIONAL
EMC FILTER
OPTIONAL
MOSFET
DN2540
10µF
T1
BSP129
4.7µF
0.1µF
200kΩ
IODV
DV
REG
REG
IN
DD
DD
OUT
V
LOOP
RANGE0
RANGE1
DRIVE
19MΩ
1MΩ
R
L
ALARM_CURRENT_DIRECTION
/R
V
LOOP
R
INT EXT
SYNC
SCLK
SDIN
LOOP–
AD5421
V
= 4.7V
Z
SDO
R
R
EXT1
EXT2
FAULT
LDAC
R1
MCU
OPTIONAL
RESISTOR
COM
REFOUT2
C
REFOUT1 REFIN
COM
IN
R1
0.1µF
1µF
470Ω
SETS REGULATOR
VOLTAGE
0.1µF
47nF
168nF
V
CC
AD5700/AD5700-1
TXD
HART_OUT
RXD
REF
RTS
1µF
1.2MΩ
1.2MΩ
CD
300pF
150kΩ
ADC_IP
GND
150pF
Figure 27. Loop-Powered Transmitter Diagram
Rev. A | Page 18 of 20
Data Sheet
AD5700/AD5700-1
3.3V
MCU
AD5421
V
DD
3.3V
REG
IN
+
PRESSURE
SENSOR
SIMULATION
V-REGULATOR
ADC 0
MICRO-
CONTROLLER
V
LOOP
SRAM
FLASH
ADC
DAC
LEXC
CLOCK
TEMPERATURE
SENSOR
SPI
COM
RESET
WATCHDOG
TEMPERATURE
SENSOR
PT100
ADC 1
COM
WATCHDOG
TIMER
50Ω
TEST CONNECTOR
T1: CD
T2: RTS
C
LOOP–
IN
–
T3: COM
T4: TEST
3.3V
V
CC
AD5700
C_HART
HART_OUT
C_SLEW
REF
HART
INPUT
FILTER
HART MODEM
COM
ADC_IP
Figure 28. Block Diagram—Analog Devices HART-Enabled Smart Transmitter Reference Demo Circuit
Rev. A | Page 19 of 20
AD5700/AD5700-1
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
19
24
0.50
BSC
18
1
6
EXPOSED
PAD
2.20
2.10 SQ
2.00
13
12
7
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
Figure 29. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Receive Supply
Package
Option
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Oscillator Options
External clock, crystal
External clock, crystal
External clock, crystal
External clock, crystal
or internal oscillator
Current
157 μA
157 μA
260 μA
442 μA
Package Description
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
AD5700BCPZ-R5
AD5700BCPZ-RL7
AD5700ACPZ-RL7
AD5700-1BCPZ-R5
CP-24-10
CP-24-10
CP-24-10
CP-24-10
AD5700-1BCPZ-RL7
AD5700-1ACPZ-RL7
EVAL-AD5700-1EBZ
−40°C to +125°C
−40°C to +125°C
External clock, crystal
or internal oscillator
External clock, crystal
or internal oscillator
442 μA
540 μA
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
CP-24-10
CP-24-10
Evaluation Board for
AD5700 and AD5700-1
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10435-0-3/12(A)
Rev. A | Page 20 of 20
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