AD5735 [ADI]
Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control; 四通道， 16位，串行输入， 4-20mA的与电压输出DAC ，动态功率控制
| 型号： | AD5735 |
| 厂家： | 
ADI |
| 描述： | Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control |
| 文件： | 总34页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Channel, 16-Bit,
Serial Input, 4-20mA & Voltage Output DAC,
Dynamic Power Control
Preliminary Technical Data
AD5755/AD5735
FEATURES
GENERAL DESCRIPTION
16/12-Bit Resolution and Monotonicity
Dynamic Power Control for Thermal Management
Voltage or Current Output on the Same Pin
IOUT Range: 0mA-20mA, 4mA–20mA or 0mA–24mA
0.05% Total Unadjusted Error (TUE) Max
VOUT Range: 0-5V, 0-10V, 5V, 10V, 6V, 12V
0.04% Total Unadjusted Error (TUE) Max
User programmable Offset and Gain
On Chip Diagnostics
The AD5755/AD5735 is a quad, voltage and current output
DAC, which operates with a power supply range from -26v to
+33v. On chip dynamic power control minimizes package
power dissipation in current mode. This is achieved by
regulating the voltage on the output driver from between 7V-
30V.
The part uses a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and that is compatible with standard
SPI®, QSPI™, MICROWIRE™, DSP and microcontroller
interface standards. The interface also features optional CRC-8
packet error checking as well as a watchdog timer that monitors
activity on the interface.
On-Chip Reference ( 5 ppm/°C)
−40°C to +105°C Temperature Range
APPLICATIONS
Process Control
Actuator Control
PLC’s
Table 1. Complementary Devices
Part No.
Description
ADR445
5V, Ultralow Noise, LDO XFET Voltage
Reference with Current Sink and Source
PRODUCT HIGHLIGHTS
Dynamic Power Control for Thermal management
16bit performance
ADP1871
Synchronous Buck Controller with Constant
On-Time, Valley Current Mode, and Power
Save Mode
Multi-channel
Figure 1.
Rev. PrG
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksare the property oftheir respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
AD5755/AD5735
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Features............................................................................................ 28
Output Fault................................................................................ 28
Voltage Output Short Circuit Protection ................................ 28
Digital Offset and Gain Control............................................... 28
Status Readback During Write ................................................. 28
Asynchronous Clear................................................................... 29
Packet Error Checking............................................................... 29
Watchdog timer.......................................................................... 29
Output Alert................................................................................ 29
Internal Reference ...................................................................... 29
External current setting resistor............................................... 29
Slew rate control ......................................................................... 29
Power Dissipation control......................................................... 30
DC-DC Converters.................................................................... 30
Applications Information.............................................................. 32
Precision Voltage Reference Selection..................................... 32
Driving Inductive Loads............................................................ 32
Transient voltage protection ..................................................... 32
Microprocessor Interfacing....................................................... 32
Layout Guidelines....................................................................... 33
Galvanically Isolated Interface ................................................. 33
Outline Dimensions....................................................................... 34
Ordering Guide .......................................................................... 34
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Performance Characteristics................................................ 6
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 16
DAC Architecture....................................................................... 16
Power On State of AD5755/AD5735 ....................................... 16
Serial Interface ............................................................................ 17
Transfer Function ....................................................................... 17
Registers........................................................................................... 18
Programming Sequence to Write/Enable the Output
Correctly ...................................................................................... 19
Changing and Reprogramming the Range ............................. 19
Data Registers ............................................................................. 20
Control Registers........................................................................ 23
Readback Operation .................................................................. 26
Rev. PrG | Page 2 of 34
Preliminary Technical Data
SPECIFICATIONS
AD5755/AD5735
AVDD = 15V, AVSS = -15V, VBOOSTA,B,C,D = +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND =
GNDSWA,B,C,D = 0 V, REFIN= +5, VOUT : RL = 1kΩ, CL = 220pF, IOUT : RL = 300Ω, all specifications TMIN to TMAX unless otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
VOLTAGE OUTPUT
Output Voltage Ranges
0
0
5
10
V
V
V
V
AVDD needs to have min TBD V headroom on output.
- 5
-10
+ 5
+ 10
AVDD/AVSS need to have min TBD V headroom on
output.
0
0
6
V
V
V
V
12
+6
+2
AVDD needs to have min TBD V headroom on output.
-6
-12
AVDD/AVSS need to have min TBD V headroom on
output.
ACCURACY
Resolution
16
12
Bits
Bits
AD5755
AD5735
Total Unadjusted Error (TUE)
B Version
−0.04
−0.02
−0.25
−0.075
+0.04
+0.02
+0.25
+0.075
% FSR
% FSR
% FSR
% FSR
ppm FSR/°C
typ
TBD
TA = 25°C
TA = 25°C
A Version
TBD
3
TUE TC2
Relative Accuracy (INL)
−0.006
−0.025
−1
−TBD
−0.008
+0.006
+0.025
+1
+TBD
+0.008
% FSR
% FSR
LSB
%FSR
%FSR
ppm FSR/°C
%FSR
%FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
AD5755
AD5735
Guaranteed monotonic
Differential Nonlinearity (DNL)
Bipolar Zero Error
TBD
3
TA = 25°C
TA = 25°C
TA = 25°C
Bipolar Zero TC2
Zero-Scale Error
−TBD
−0.016
+TBD
+0.016
TBD
3
Zero-Scale TC2
Gain Error
−TBD
−TBD
−TBD
−TBD
−TBD
−TBD
+TBD
+TBD
+TBD
+TBD
+TBD
+TBD
TBD
TBD
Gain TC2
Full-Scale Error
TA = 25°C
TA = 25°C
TBD
TBD
Full-Scale TC2
OUTPUT CHARACTERISTICS2
Headroom
1
TBD
V
Output Voltage Drift vs. Time
TB
D
ppm FSR
Drift after 500 hours, TJ = 150°C (this is included in the
TUE specifications)
TB
D
ppm FSR
Drift after 1000 hours, TJ = 150°C (this is included in
the TUE specifications)
Short-Circuit Current
Load
15/8
mA
kΩ
Programmable by user, defaults to 15ma Typ level.
For specified performance
1
Capacitive Load Stability
Rev. PrG | Page 3 of 34
AD5755/AD5735
Preliminary Technical Data
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
RL = ∞
20
nF
RL = 2 kΩ
RL = ∞
TBD
2
nF
µF
External compensation capacitor of min TBD pF
connected.
DC Output Impedance
DC PSRR
0.3
TBD
Ω
µV/V
µV/V
TBD
CURRENT OUTPUT
Output Current Ranges
0
0
4
16
12
24
20
20
mA
mA
mA
Bits
Bits
Resolution
AD5755
AD5735
ACCURACY (External RSet
)
Total Unadjusted Error (TUE)
B Version
−0.05
−0.02
−0.2
−0.05
−TBD
+0.05
+0.02
+0.2
+0.05
+TBD
% FSR
% FSR
% FSR
% FSR
ppm
TBD
TBD
TB
D
TA = 25°C
TA = 25°C
A Version
TUE TC2
Relative Accuracy (INL)
−0.006
−0.025
−1
−0.035
−TBD
+0.006
+0.025
+1
+0.035
+TBD
% FSR
% FSR
LSB
% FSR
% FSR
ppm FSR/°C
AD5755
AD5735
Guaranteed monotonic
Differential Nonlinearity (DNL)
Offset Error
TBD
TB
D
TA = 25°C
Offset Error Drift2
Gain Error
−0.02
−TBD
−TBD
−0.05
−TBD
−TBD
+0.02
+TBD
+TBD
+0.05
+TBD
+TBD
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
TBD
TBD
TA = 25°C
TA = 25°C
Gain TC2
Full-Scale Error
Full-Scale TC2
ppm FSR/°C
ACCURACY (Internal RSet
)
Total Unadjusted Error (TUE)
B Version
−0.12
−0.02
−0.3
−0.75
−TBD
+0.12
+0.02
+0.3
+0.75
+TBD
% FSR
% FSR
% FSR
% FSR
ppm
TBD
TBD
TB
D
TA = 25°C
TA = 25°C
A Version
TUE TC2
Relative Accuracy (INL)
−0.006
−0.025
−1
−0.04
−TBD
+0.006
+0.025
+1
+0.04
+TBD
% FSR
% FSR
LSB
% FSR
% FSR
ppm FSR/°C
AD5755
AD5735
Guaranteed monotonic
Differential Nonlinearity (DNL)
Offset Error
TBD
TB
D
TA = 25°C
TA = 25°C
Offset Error Drift2
Gain Error
−0.08
−TBD
+0.08
+TBD
% FSR
% FSR
TBD
Rev. PrG | Page 4 of 34
Preliminary Technical Data
AD5755/AD5735
Parameter1
Gain TC2
Min
Typ
TBD
TBD
Max
Unit
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
Test Conditions/Comments
−TBD
−0.12
−TBD
−TBD
+TBD
+0.12
+TBD
+TBD
Full-Scale Error
TA = 25°C
Full-Scale TC2
OUTPUT CHARACTERISTICS2
Current Loop Compliance Voltage
AVDD - V max
2.5
Output Current Drift vs. Time
TB
D
ppm FSR
Drift after 500 hours, TJ = 150°C
(this is included in the TUE specifications)
TB
D
ppm FSR
Ω max
Drift after 1000 hours, TJ = 150°C
(this is included in the TUE specifications)
Chosen such that compliance is not exceeded. Plus
see graph on load vs. AVcc and DCDC switching freq.
Resistive Load
Inductive Load
DC PSRR
See
Com
men
t
See
Com
men
t
H max
Will need appropriate cap at higher inductance values.
See Page X of Datasheet.
TBD
µA/V
µA/V
MΩ
TBD
5.05
Output Impedance
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Reference Output
50
4.95
5
5
TBD
V nom
MΩ min
For specified performance
TA = 25°C
Output Voltage
Reference TC2,3
Output Noise (0.1 Hz to 10 Hz)2
Noise Spectral Density2
Output Voltage Drift vs. Time2
4.998
-10
5
5.002
10
V
5
TBD
TBD
TB
D
ppm/°C
µV p-p typ
nV/√Hz typ
ppm
At 10 kHz
Drift after 500 hours, TJ = 150°C
TB
D
ppm
Drift after 1000 hours, TJ = 150°C
Capacitive Load2
Load Current
TBD
nF
mA
5
Short Circuit Current
Line Regulation2
Load Regulation2
Thermal Hysteresis2
DC-DC
7
mA
10
TBD
TBD
ppm/V
ppm/mA
ppm
SWITCH
SWITCH On Resistance
SWITCH Leakage Current
Peak Current Limit
OSCILLATOR
Oscillator Frequency
Maximum Duty Cycle
DIGITAL INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
0.5
TBD
0.8
ohm
uA
A
VIN=TBD, IOUT=TBD, RLOAD=TBD
JEDEC compliant
TBD
2
TBD
TBD
TBD
0.8
KHz
%
V
V
Rev. PrG | Page 5 of 34
AD5755/AD5735
Preliminary Technical Data
Parameter1
Input Current
Pin Capacitance
DIGITAL OUTPUTS2
SDO, ALERT
Min
−1
Typ
Max
+1
Unit
µA
pF
Test Conditions/Comments
Per pin
Per pin
10
VOL, Output Low Voltage
VOH, Output High Voltage
0.4
+1
V
V
sinking 200 µA
sourcing 200 µA
DVDD
−0.5
−1
High Impedance Leakage
Current
High Impedance Output
Capacitance
µA
pF
5
FAULT
VOL, Output Low Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
0.4
V
V
V
10kΩ pull-up resistor to DVDD
At 2.5 mA
0.6
3.6
10kΩ pull-up resistor to DVDD
POWER REQUIREMENTS
AVDD
AVSS
12
−26.4
33
−10.8
V
V
DVDD, AVCC
Input Voltage
2.7
5.5
V
AIDD
AISS
DICC
AIcc
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mW
mW
mW
Output unloaded
Bipolar Supply Mode only, outputs unloaded
VIH = DVDD, VIL = GND
DCDC ’s not enabled
Power Dissipation
TBD
TBD
TBD
AVDD = 33V, AVSS = 0V, outputs unloaded
AVDD = 33V, AVSS = -26.4 V, outputs unloaded
AVDD = 15V, AVSS = -15 V, outputs unloaded
1Temperature range: −40°C to +105°C; typical at +25°C.
2 Guaranteed by design and characterization; not production tested.
3 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +105°C.
AC PERFORMANCE CHARACTERISTICS
AVDD = 15V, AVSS = -15V, VBOOSTA,B,C,D = +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND =
GNDSWA,B,C,D = 0 V, REFIN= +5, VOUT : RL = 1kΩ, CL = 220pF, IOUT : RL = 300Ω, all specifications TMIN to TMAX unless otherwise noted.
Table 3.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Voltage Output
Output Voltage Settling Time
TBD
TBD
1
TBD
TBD
µs typ
µs typ
V/µs
10 V step to 0.03% FSR
100mv step to 1 LSB (16-Bit LSB)
Slew Rate
Power-On Glitch Energy
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Feedthrough
DAC to DAC Crosstalk
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
10
10
20
1
TBD
0.1
nV-sec
nV-sec
mV
nV-sec
nV-sec
LSB p-p
(16-Bit LSB)
Output Noise (100 kHz Bandwidth)
Output Noise Spectral Density
TBD
µV rms
nV/√Hz
TBD
Measured at 10 kHz
Rev. PrG | Page 6 of 34
Preliminary Technical Data
AD5755/AD5735
AC PSRR
AC PSRR
TBD
TBD
dB
dB
100mV 150KHz Sine wave superimposed on
power supply voltage
200mV 50/60Hz Sine wave superimposed on
power supply voltage
Current Output
Output Current Settling Time
TBD
-
0.1
TBD
80
µs typ
ms typ
LSB p-p
To 0.1% FSR
See Figure 7 and Figure 8
(16-Bit LSB)
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
Output Noise (100 kHz Bandwidth)
Output Noise Spectral Density
Slew Rate
µV rms
nV/√Hz
uA/µs
µs
TBD
TBD
TBD
Measured at 10 kHz
To 0.1% FSR. See Figure 7 and Figure 8 for
plots with a channels DC-DC enabled.
1 Guaranteed by characterization, not production tested.
Rev. PrG | Page 7 of 34
AD5755/AD5735
Preliminary Technical Data
TIMING CHARACTERISTICS
AVDD = 15V, AVSS = -15V, VBOOSTA,B,C,D = +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND =
GNDSWA,B,C,D = 0 V, REFIN= +5, VOUT : RL = 1kΩ, CL = 220pF, IOUT : RL = 300Ω, all specifications TMIN to TMAX unless otherwise noted.
Table 4.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
ns min
ns min
ns min
ns min
SCLK cycle time
SCLK high time
SCLK low time
falling edge to SCLK falling edge setup time
SYNC
t5
t6
13
ns min
ns min
24/32nd SCLK falling edge to
rising edge
SYNC
198
high time
SYNC
t7
t8
t9
5
5
20
ns min
ns min
µs min
Data setup time
Data hold time
rising edge to
SYNC
channel has digital slew rate control enabled)
falling edge (all DACs updated or any
LDAC
5
µs min
ns min
ns max
µs max
rising edge to
falling edge (single DAC updated)
SYNC
LDAC
LDAC
LDAC
pulse width low
falling edge to DAC output response time
t10
t11
t12
10
500
See AC Performance
Characteristics
DAC output settling time
t13
t14
t15
t16
10
TBD
25
ns min
µs max
ns max
µs min
CLEAR high time
CLEAR activation time
SCLK rising edge to SDO valid (CL SDO = 35 pF)
rising edge to DAC output response time (LDAC = 0) (all DACs
SYNC
updated)
20
5
µs min
rising edge to DAC output response time (LDAC = 0) (single
SYNC
DAC updated)
t17
t18
t19
500
700
20
ns min
ns min
µs min
µs min
falling edge to
rising edge
SYNC
LDAC
RESET pulse width
high to next
low (Ramp enabled)
low (Ramp disabled)
SYNC
SYNC
SYNC
SYNC
5
high to next
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 2 , Figure 3 , Figure 4 and Figure 5
Rev. PrG | Page 8 of 34
Preliminary Technical Data
AD5755/AD5735
t1
SCLK
1
2
24
t6
t3
t2
t4
t5
SYNC
t8
t19
t7
SDIN
MSB
LSB
t10
t10
t9
LDAC
t17
t12
t11
V
OUT
LDAC = 0
t12
t16
V
OUT
t13
CLEAR
t14
V
OUT
ALERT
RESET
t18
FAULT
Figure 2. Serial Interface Timing Diagram
Rev. PrG | Page 9 of 34
AD5755/AD5735
Preliminary Technical Data
SCLK
1
1
24
24
t6
SYNC
MSB
MSB
LSB
MSB
LSB
SDIN
SDO
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
LSB
MSB
LSB
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
t15
Figure 3. Readback Timing Diagram
MSB
1
2
SCLK
SYNC
SDIN
DUT_
AD1
DUT_
AD0
DB0
DB1
X
R/W
X
X
DB15 DB14
SDO
ENAB
Status
Status
SDO DISABLED
Status
Status
SDO
Status Bits Readout
Figure 4. Status Readback during write
200µA
I
OL
V
V
(MIN) OR
(MAX)
TO OUTPUT
PIN
OH
OL
C
L
50pF
200µA
I
OH
Figure 5. Load Circuit for SDO Timing Diagram
Rev. PrG | Page 10 of 34
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
AD5755/AD5735
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
AVDD to AGND, DGND
AVSS to AGND, DGND
AVDD to AVSS
AVcc to AGND
DVDD to DGND
Digital Inputs to DGND
−0.3 V to +33 V
+0.3 V to −28 V
−0.3 V to +60 V
−0.3 V to +7 V
−0.3 V to +7 V
ESD CAUTION
−0.3 V to DVDD + 0.3 V or
+7 V (whichever is less)
Digital Outputs to DGND
REFIN/REFOUT to AGND
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V or +7
V (whichever is less)
VOUT A,B,C,D to AGND
AVSS to VBOOST or 33V if using
the DC-DC circuitry.
−VSENSEA,B,C,D / +VSENSEA,B,C,D to AGND
AVSS to VBOOST or 33V if using
the DC-DC circuitry.
COMPLVA,B,C,D to AGND
IOUT A,B,C,D to AGND
0.3 V to +5 V
AVSS to VBOOST or 33V if using
the DC-DC circuitry.
RSETA,B,C,D to AGND
−0.3 V to AVDD + 0.3 V or +7
V (whichever is less)
SWA,B,C,D / VBOOSTA,B,C,D to AGND
COMPDCDC_A,B,C,D to AGND
AGND, GNDSWA,B,C,D to DGND
Operating Temperature Range (TA)
Industrial1
Storage Temperature Range
Junction Temperature (TJ max)
64-Lead LFCSP
θJA Thermal Impedance2
Power Dissipation
−0.3 to +33 V
−0.3 V to +5 V
−0.3 V to +0.3 V
−40°C to +105°C
−65°C to +150°C
125°C
20°C/W
(TJ max – TA)/θJA
JEDEC Industry Standard
J-STD-020
Lead Temperature
Soldering
1 Power dissipated on chip must be derated to keep the junction temperature
below 125°C
2 Based on a JEDEC 4 layer test board
Rev. PrG | Page 11 of 34
AD5755/AD5735
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
COMPDCDC_C
48
47 IOUTC
RSETB
RSETA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
46 VBOOSTC
REFGND
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DVDD
DGND
LDAC
45
44
43
42
AVCC
SWC
GND_SWC
GND_SWD
41 SWD
64 LFCSP
AVSS
SWA
GND_SWA
GND_SWB
SWB
AGND
VBOOSTB
IOUTB
40
39
38
37
36
35
34
33
CLEAR
ALERT
FAULT
Figure 6. 64 LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the
IOUT_B temperature drift performance. See the Features section.
1
RSET_B
2
RSET_A
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the
IOUT_A temperature drift performance. See the Features section.
3
4
5
6
7
REFGND
REFGND
ADO
Ground Reference Point for Internal Reference.
Ground Reference Point for Internal Reference.
Address decode for the DUT on the board.
Address decode for the DUT on the board.
Active Low Input. This is the frame synchronization signal for the serial interface. While
transferred in on the falling edge of SCLK.
AD1
is low, data is
SYNC
SYNC
8
SCLK
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock
speeds of up to 30 MHz.
9
SDIN
SDO
DVDD
DGND
LDAC
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 3 and Figure 4.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
10
11
12
13
Digital Ground Pin.
Load DAC. Active Low Input. This is used to update the DAC registers and consequently the analog
outputs. When tied permanently low the addressed DAC register is updated on the rising edge of
. If
SYNC
is held high during the write cycle the DAC input register is updated but the output update only
LDAC
takes place at the falling edge of
. See Figure 2. Using this mode all analog outputs can be updated
LDAC
pin must not be left unconnected.
simultaneously. The
LDAC
14
CLEAR
Active High, Edge Sensitive Input. Asserting this pin sets the Output Current/Voltage to the pre-
programmed CLEAR CODE. Only channels enabled to be cleared will be cleared. See features section for
Rev. PrG | Page 12 of 34
Preliminary Technical Data
AD5755/AD5735
Pin No. Mnemonic
Description
more information. When CLEAR is active, the DAC register cannot be written to.
15
16
ALERT
FAULT
Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a
predetermined time. See features section for more information.
Active Low Output. This pin is asserted low when an open circuit in current mode is detected or a short
circuit in voltage mode is detected or a PEC error is detected or an over temperature is detected (see
Features section). Open Drain Output.
17
POC
Power- On Condition. This pin determines the Power on Condition. If POC=’0’, the device is powered up
with the voltage and current channels in Tri-State mode. If POC=’1’, the device is powered up with a 30k Ω
pull down resistor to GND on the voltage output channel, and the current channels in Tri-State mode.
18
19
20
Hardware Reset. Active Low Input.
RESET
AVDD
COMPLV_A
Positive Analog Supply Pin. Voltage ranges from 10.8 V to 33 V.
Optional compensation capacitor connection for VOUT_A‘s output buffer. Connecting a 220 pF capacitor
between this pin and the VOUT_A pin allows the voltage output to drive up to 1 µF. It should be noted that
the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time.
21
22
23
24
−VSENSE_A
+VSENSE_A
COMPDCDC_A
VBOOST_A
Sense connection for the negative voltage output load connection for VOUT_A. This pin must stay within
3.0 V of ground for correct operation.
Sense connection for the positive voltage output load connection for VOUT_A. This pin must stay within 3.0
V of VOUT_A for correct operation.
DC-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of channel A’s DC-DC converter.
Supply for channel A’s current output stage (See Figure 15). This is also the supply for the VOUT stage, which
is regulated to 15V by the DC-DC. To use the DC-DC feature of the device, connect as shown in Figure 20.
25
26
27
28
VOUT_A
IOUT_A
AVSS
Buffered Analog Output Voltage for DAC Channel A.
Current Output Pin for DAC Channel A.
Negative Analog Supply Pin. Voltage ranges from -10.8 V to -26.4 V.
Optional compensation capacitor connection for VOUT_B‘s output buffer. Connecting a 220 pF capacitor
between this pin and the VOUT_B pin allows the voltage output to drive up to1 µF. It should be noted that
the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time.
COMPLV_B
29
30
−VSENSE_B
+VSENSE_B
Sense connection for the negative voltage output load connection for VOUT_B. This pin must stay within
3.0 V of ground for correct operation.
Sense connection for the positive voltage output load connection for VOUT_B. This pin must stay within 3.0
V of VOUT_B for correct operation.
31
32
VOUT_B
COMPDCDC_B
Buffered Analog Output Voltage for DAC Channel B.
DC-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of channel B’s DC-DC converter.
33
34
IOUT_B
VBOOST_B
Current Output Pin for DAC Channel B.
Supply for channel B’s current output stage (See Figure 15). This is also the supply for the VOUT stage, which
is regulated to 15V by the DC-DC. To use the DC-DC feature of the device, connect as shown in Figure 20.
35
36
AGND
SW_B
Ground Reference Point for Analog Circuitry. This must be connected to 0 V.
Switching output for Channel B’s DC-DC circuitry. To use the DC-DC feature of the device, connect as
shown in Figure 20.
37
38
GNDSW_B
GNDSW_A
Ground connection for DC-DC switching circuit. This pin should always be connected to GND.
Ground connection for DC-DC switching circuit. This pin should always be connected to GND.
39
SW_A
Switching output for Channel A’s DC-DC circuitry. To use the DC-DC feature of the device, connect as
shown in Figure 20.
40
41
AVSS
SW_D
Negative Analog Supply Pin. Voltage ranges from -10.8 V to -26.4 V.
Switching output for Channel D’s DC-DC circuitry. To use the DC-DC feature of the device, connect as
shown in Figure 20.
42
43
44
GNDSW_D
GNDSW_C
SW_C
Ground connections for DC-DC switching circuit. This pin should always be connected to GND.
Ground connections for DC-DC switching circuit. This pin should always be connected to GND.
Switching output for Channel C’s DC-DC circuitry. To use the DC-DC feature of the device, connect as
shown in Figure 20.
45
46
AVCC
VBOOST_C
Supply for DC-DC circuitry.
Supply for channel C’s current output stage (See Figure 15). This is also the supply for the VOUT stage, which
Rev. PrG | Page 13 of 34
AD5755/AD5735
Preliminary Technical Data
Pin No. Mnemonic
Description
is regulated to 15V by the DC-DC. To use the DC-DC feature of the device, connect as shown in Figure 20.
Current Output Pin for DAC Channel C.
DC-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of channel C’s DC-DC converter.
47
48
IOUT_C
COMPDCDC_C
49
50
VOUT_C
+VSENSE_C
Buffered Analog Output Voltage for DAC Channel C.
Sense connection for the positive voltage output load connection for VOUT_C. This pin must stay within 3.0
V of VOUT_C for correct operation.
51
52
−VSENSE_C
Sense connection for the negative voltage output load connection for VOUT_C. This pin must stay within
3.0 V of ground for correct operation.
Optional compensation capacitor connection for VOUT_C‘s output buffer. Connecting a 220 pF capacitor
between this pin and the VOUT_C pin allows the voltage output to drive up to 1 µF. It should be noted that
the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time.
COMPLV_C
53
54
55
56
AVSS
IOUT_D
VOUT_D
VBOOST_D
Negative Analog Supply Pin.
Current Output Pin for DAC Channel D.
Buffered Analog Output Voltage for DAC Channel D.
Supply for channel D’s current output stage (See Figure 15). This is also the supply for the VOUT stage, which
is regulated to 15V by the DC-DC. To use the DC-DC feature of the device, connect as shown in Figure 20.
57
58
59
60
COMPDCDC_D
+VSENSE_D
DC-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of channel D’s DC-DC converter.
Sense connection for the positive voltage output load connection for VOUT_D. This pin must stay within 3.0
V of VOUT_D for correct operation.
Sense connection for the negative voltage output load connection for VOUT_D. This pin must stay within
3.0 V of ground for correct operation.
Optional compensation capacitor connection for VOUT_D‘s output buffer. Connecting a 220 pF capacitor
between this pin and the VOUT_D pin allows the voltage output to drive up to 1 µF. It should be noted that
the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time.
−VSENSE_D
COMPLV_D
61
62
63
REFIN
REFOUT
RSET_D
External Reference Voltage Input.
Internal Reference Voltage Output.
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the
IOUT_D temperature drift performance. See the Features section.
64
RSET_C
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the
IOUT_C temperature drift performance. See the Features section.
Exposed PADDLE
CONNECTED TO AVss
Rev. PrG | Page 14 of 34
Preliminary Technical Data
AD5755/AD5735
TYPICAL PERFORMANCE CHARACTERISTICS
TBD
Figure 7.Iout settling 0-24mA though 1kΩ load, AVcc=3.0V, LDCDC=10uH,
DCDC frequency=250kHz, CDCDC varied. (See Figure 20)
Figure 10.
TBD
Figure 8. Iout settling 0-24mA though 1kΩ load, AVcc=3.0V, LDCDC=10uH,
DCDC frequency=406kHz, CDCDC varied. (See Figure 20)
Figure 11.
TBD
TBD
Figure 9
Figure 12
Rev. PrG | Page 15 of 34
AD5755/AD5735
Preliminary Technical Data
THEORY OF OPERATION
V
BOOST
R3
The AD5755/AD5735 is a quad, precision digital to current
loop and voltage output converter designed to meet the
requirements of industrial process control applications. It
provides a high precision, fully integrated, low cost single-chip
solution for generating current loop and unipolar/bipolar
voltage outputs. The current ranges available are; 0 to 20mA, 0
to 24mA and 4 to 20mA, the voltage ranges available are; 0 to
5V, 5V, 0 to 10V and 10V, the current and voltage outputs are
available on separate pins and only one is active at any one time.
The desired output configuration is user selectable via the DAC
Control Register.
R2
T2
A2
T1
12-/16-BIT
DAC
I
A1
OUT
R
SET
Figure 15. Voltage to Current conversion circuitry
Voltage Output Amplifier
On chip dynamic power control minimizes package power
dissipation in current mode.
The voltage output amplifier is capable of generating both
unipolar and bipolar output voltages. It is capable of driving a
load of 1 kΩ in parallel with 2000 pF to AGND. The source and
sink capabilities of the output amplifier can be seen in Figure
TBD. The slew rate is 1 V/µs with a full-scale settling time of 10
µs.(10V step).
DAC ARCHITECTURE
The DAC core architecture of the AD5755/AD5735 consists of
two matched DAC sections. A simplified circuit diagram is
shown in Figure 13. The 4 MSBs of the 16/12-bit data word are
decoded to drive 15 switches, E1 to E15. Each of these switches
connects 1 of 15 matched resistors to either ground or the
reference buffer output. The remaining 12/8 bits of the data-
word drive switches S0 to S11 /S7 of a 12/8-bit voltage mode R-
2R ladder network.
Driving Large Capacitive Loads
The voltage output amplifier is capable of driving capacitive
loads of up to 1uF with the addition of a non-polarized
compensation capacitors on each channel. Care should be taken
to choose an appropriate value of compensation capacitor. This
capacitor, while allowing the AD5755/AD5735 to drive higher
cap loads and reduce overshoot, will increase the settling time
of the part and therefore effect the bandwidth of the system.
Without the compensation capacitor, up to 20nF capacitive
loads can be driven. See pin list for information on connecting
compensation capacitors.
V
OUT
2R 2R
S0
2R
S1
2R
2R
E1
2R
E2
2R
S7/S11
E15
8-12 BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Reference Buffers
Figure 13. DAC Ladder Structure
The AD5755/AD5735 can operate with either an external or
internal reference. The reference input has an input range of 4 V
to 5 V, 5 V for specified performance. This input voltage is then
buffered before it is applied to the DAC.
The voltage output from the DAC core is either converted to a
current (see Figure 15) which is then mirrored to the supply rail
so that the application simply sees a current source output with
respect to ground or it is buffered and scaled to output a
software selectable unipolar or bipolar voltage range (See
diagram, Figure 14). The current and voltage are output on
separate pins and cannot be output simultaneously. A channels
current and voltage output pins may be tied together.
POWER ON STATE OF AD5755/AD5735
On initial power-up of the AD5755/AD5735 the power-on-reset
circuit powers up in a state that is dependent on the POC (Power
on Control) pin.
+VSENSE
If POC = 0 both the Vout/Iout channels will power up in Tri-state
mode.
RANGE
SCALING
VOUT
DAC
If POC= 1 the Vout channel will Power up with 30k pull down to
Ground, and the IOUT channel will power up to tri-state.
VOUT SHORT FAULT
-VSENSE
Even though the output ranges are not enabled, the default output
range is 0-5V, and the Clear Code Register is loaded with all zeros.
This means if the user CLEARS the part after power-up the output
will be actively driven to zero volts. (If the channel has been
enabled for clear)
Figure 14. Voltage Output
Rev. PrG | Page 16 of 34
Preliminary Technical Data
AD5755/AD5735
OUTPUT
I/V AMPLIFIER
SERIAL INTERFACE
16-BIT
DAC
V
REFIN
V
OUT
The AD5755/AD5735 is controlled over a versatile 3-wire serial
interface that operates at clock rates of up to 30 MHz and is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP
standards. Data coding is always straight binary.
DAC
REGISTER
LDAC
Input Shift Register
INPUT
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of
SCLK.
REGISTER
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
There are two ways in which the DAC outputs can be updated
as outlined below.
Figure 16. Simplified Serial Interface of Input Loading Circuitry for One DAC
Channel
Individual DAC Updating
TRANSFER FUNCTION
In this mode,
is held low while data is being clocked into
LDAC
the DAC Data Register. The addressed DAC output is updated
on the rising edge of
Table 10 shows the input code to ideal output voltage
relationship for the AD5755 for straight binary data coding -
10v output range shown.
.
SYNC
Simultaneous Updating of All DACs
In this mode, is held high while data is being clocked
Table 7. Ideal Output Voltage to Input Code Relationship
Digital Input
Analog Output
LDAC
into the DAC Data Register. Only the first write to each
channels data register will be valid after is brought high.
Straight Binary Data Coding
MSB
LSB VOUT
LDAC
is still held high will be
1111 1111
1111 1111
1000 0000
0000 0000
1111
1111
0000
0000
1111
1110
0000
0001
+2 VREF × (32767/32768)
+2 VREF × (32766/32768)
0 V
Any subsequent writes while
LDAC
ignored. All the DAC outputs are updated by taking
any time after
low
LDAC
has been taken high.
SYNC
−2 VREF × (32766/32768)
0000 0000
0000
0000
−2 VREF × (32767/32768)
Rev. PrG | Page 17 of 34
AD5755/AD5735
Preliminary Technical Data
REGISTERS
Table 8 below shows an overview of the Registers for the AD5755/AD5735.
Table 8. Data and Control Registers for AD5755/AD5735
DATA REGISTERS
Description
DAC Data Register (X4)
Used to write a DAC code to each DAC channel. AD5755 Data bits (D15 to D0),
AD5735 Data Bits (D15 to D4).
There are four DAC Data Registers, one per DAC Channel.
Gain Register (X4)
Used to program gain trim on per channel basis. AD5755 Data bits (D15 to D0),
AD5735 Data Bits (D15 to D4).
There are four Gain Registers, one per DAC channel.
Offset Register (X4)
Clear Code Register (X4)
Used to program offset trim, on per channel basis. AD5755 Data bits (D15 to D0),
AD5735 Data Bits (D15 to D4).
There are four Offset Registers, one per DAC channel.
Used to program Clear Code on per channel basis. AD5755 Data bits (D15 to D0),
AD5735 Data Bits (D15 to D4).
There are four Clear Code Registers, one per DAC channel.
CONTROL REGISTERS
Main Control Register
Used to Configure the part for main operation. Sets functions such as status
readback during write, enable output on all channels simultaneously, power on all
DC-DC blocks simultaneously, enables and sets conditions of watchdog timer. See
Features Section for more details.
Software Register
Has two functions. Used to perform a reset. Is also used as part of the watchdog
timer feature to verify correct data communication operation.
Slew Rate Control Register (X4)
DAC Control Register (X4)
Use to program the slew rate of the output.
There are four Slew Rate Control Registers, one per channel.
These registers are used to control the following…
1) Set the output range, e.g. 4-20ma, 0-10v etc..
2) Set whether Internal/External sense Resistor used
3) Enable/Disable channel for CLEAR..
4) Enable/Disable Over-range.
5) Enable/Disable output on a per channel basis..
6) Power on DC-DC on a per channel basis.
There are four DAC Control Registers, one per DAC channel.
DC-DC Control Register
Use to set the DC-DC Control parameters. Can control DC-DC max voltage, phase
and frequency.
READBACK
Status Register
Rev. PrG | Page 18 of 34
Preliminary Technical Data
AD5755/AD5735
PROGRAMMING SEQUENCE TO WRITE/ENABLE
THE OUTPUT CORRECTLY
CHANGING AND REPROGRAMMING THE RANGE
When changing between ranges the same sequence as above
should be used. It is recommended to set the range to its zero
point (can be mid-scale or zero-scale) prior to disabling the
output. As the DC-DC switching frequency, max voltage and
phase have already been selected, there is no need to reprogram
this. A flow chart of this sequence is shown below.
To correctly write to and set up the part from a power on
condition the sequence below should be followed. It is
recommended to perform a hardware or software reset after
initial power on.
Firstly, the DC-DC supply block needs to be configured. The
user should set the DC-DC switching frequency, max output
voltage allowed and the phase that the 4 DC-DC channels clock
at. Secondly the DAC Control Register should be configured on
a per channel basis. The output range is selected, and the DC-
DC block is enabled (DC-DC). Other control bits may be
configured at this point, however, the output enable bit
(OUTEN) and the INT_ENABLE bit should not be set. Next,
the user writes the required code to the DAC Data Register.
This will implement a full DAC calibration internally. Finally
the user writes to the DAC Control Register again to enable the
output (set the OUTEN bit). A flow chart of this sequence is
shown below.
Channels Output is enabled
Step 1: Write to channels DAC Data Register,
Set the output to 0V (zero or mid-
scale).
Step 2:Write to DAC Control Register. Disable
the output (OUTEN=0), and set the
new output range. Keep the DC-DC
enabled, do not select the
INT_Enable bit.
Power On
Step 3:Write value to the DAC Data Register.
Step 1: Perform a Software/Hardware Reset
Step 4:Write to DAC Control Register. Reload
sequence as in Step 2 above.This time
select the OUTEN bit to enable the
output.
Step 2: Write to DC-DC Control Register to
set DC-DC Clock Frequency, phase
and maximum voltage.
Figure 18. Steps for Changing the Output Range
Step 3:Write to DAC Control Register. Select
the DAC Channel and output Range.
Set the DC_DC bit and other control
bits as required. Do not select OUTEN
bit or the INT_ENABLE bit..
Step 4:Write to each/all DAC Data Registers.
Step 5:Write to DAC Control Register. Reload
sequence as in Step 3 above.This time
select the OUTEN bit to enable the
output.
Figure 17. Programming Sequence for Enabling the Output Correctly
Rev. PrG | Page 19 of 34
AD5755/AD5735
Preliminary Technical Data
DATA REGISTERS
The input register is 24 bits wide. When writing to a data register the following format must be used:
Table 9. AD5755/AD5735 Writing to a Data Register
D23 D22
D21
D20
D19
D18
D17
D16
D15 to D0
R/ DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0
W
Table 10. AD5755/AD5735 Input Register Decode
Register
Function
R/
Indicates a read from or a write to the addressed register.
W
Used in association with External Pins AD1, AD0 to determine which AD5755/AD5735 device is being addressed
by the system controller.
DUT_AD1, DUT_AD0
DUT_AD1 DUT_AD0
Function
0
0
1
1
0
1
0
1
Addresses Part with Pins AD1=0, AD0=0
Addresses Part with Pins AD1=0, AD0=1
Addresses Part with Pins AD1=1, AD0=0
Addresses Part with Pins AD1=1, AD0=1
Selects whether a data register or a control register is written to. If a control register is selected, a further decode
of CREG bits is required to select the particular control register, as detailed below.
DREG2, DREG1,
DREG0
DREG2
DREG1
DREG0
Function
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
Write to DAC Data Register (Individual Channel Write)
Write to Gain Register
Write to Gain Register (ALL DACS)
Write to Offset Register
Write to Offset Register (ALL DACS)
Write to Clear Code Register
Write to a Control Register
DAC_AD1, DAC_AD0
These bits are used to decode the DAC channel
DAC_AD1
DAC_AD0
DAC Channel/ Register Address
0
0
1
1
X
0
1
0
1
X
DAC A
DAC B
DAC C
DAC D
These are don’t cares if they are not relevant to the operation being performed.
DAC DATA REGISTER
Table 11. Programming the AD5755 DAC Data Registers
When writing to the AD5755 DAC Data Registers D15-D0 are used for DAC DATA bits. See Table x for input register decode.
MSB
LSB
D23 D22
D21
D20
D19
D18
D17
D16
D15 to D0
R/
DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DATA
W
Table 12. Programming the AD5735 DAC Data Registers
When writing to the AD5735 DAC Data Registers D15-D4 are used for DAC DATA bits. See Table x for input register decode.
MSB
LSB
D23 D22
D21
D20
D19
D18
D17
D16
D15 to D4 D3 D2 D1 D0
R/
DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DATA
X
X
X
X
W
Rev. PrG | Page 20 of 34
Preliminary Technical Data
AD5755/AD5735
GAIN REGISTER
The Gain Register stores the Gain Code (M) which is used in the DAC transfer function to calculated the overall DAC input code (see
formula below). The Gain Register is addressed by setting DREG bits to ‘0,1,0’. The DAC address bits select which DAC channel the gain
write is addressed to. It is possible to write the same gain code to all 4 DAC channels at the same time by setting the DREG bits to 011.
The AD5755/AD5735 Gain Register is a 16/12 bit register (bits G15.. G0/G3) and allows the user to adjust the gain of each channel in
steps of 1 LSB as shown in the Table below. For the AD5735, the last 4 bits should be set to 1. The Gain Register coding is straight binary.
In theory the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is about 50% of
programmed range in order to maintain accuracy.
Table 13. Programming the AD5755 Gain Register
R/
W
DUT_
AD1
DUT_
AD0
DREG2 DREG1 DREG0 DAC_
AD1
DAC_
AD0
D15-D0
0
DEVICE ADDRESS
010
DAC Channel Address G15 to G0
Table 14. Programming the AD5735 Gain Register
R/
W
DUT_
AD1
DUT_
AD0
DREG2 DREG1 DREG0 DAC_
AD1
DAC_
AD0
D15-D4
D3 D2 D1 D0
0
DEVICE ADDRESS
010
DAC Channel Address G15 to G4
1
1
1
1
Table 15. AD5755 Gain Register
Gain Adjustment
+65535 LSBs
G15
G14
G13
G12 to G4
G3
1
G2
G1
G0
1
1
-
1
1
-
1
1
-
1
1
-
1
1
-
1
0
-
1
0
-
+65534 LSBs
1
-
1 LSBs
0 LSBs
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Table 16. AD5735 Gain Register
Gain Adjustment
+8192 LSBs
G15
G14
G13 to G5
G4
1
G3
X
G2
X
G1
X
G0
X
1
1
-
1
1
-
1
1
-
+8191 LSBs
0
X
X
X
X
-
X
X
X
X
1 LSBs
0 LSBs
0
0
0
0
0
0
1
X
X
X
X
0
X
X
X
X
OFFSET REGISTER
The Offset Register is addressed by setting the DREG BITS to DREG2 =1 DREG1=0, DREG0=0. The DAC address bits select with which
DAC channel the offset write is addressed to. It is possible to write the same offset code to all 4 DAC channels at the same time by setting
the DREG bits to 101. The AD5755/AD5735 offset code is 16/12 bit (bits OF15.. OF0/OF3) and allows the user to adjust the offset of
each channel by −32768/8192 LSBs to +32767/8191 LSBs in steps of 1 LSB as shown in the Table below. For the AD5735, the last 4 bits are
ignored and should be set to zero. The Offset Register coding is straight binary. The default code in the Offset Register is 0x8000/0x800.
This will result in zero offset programmed to the output.
Table 17. Programming the AD5755 Offset Register
R/
DUT_
AD1
DUT_
AD0
DREG2 DREG1 DREG0 DAC_
DAC_
AD0
D15 to D0
W
AD1
0
DEVICE ADDRESS 100
DAC Channel Address OF15 to OF0
Table 18. Programming the AD5735 Offset Register
R/
DUT_
AD1
DUT_
AD0
DREG2 DREG1 DREG0 DAC_
DAC_
AD0
D15 to D4
D3 D2 D1 D0
W
AD1
0
DEVICE ADDRESS 100
DAC Channel Address OF15 to OF4
0
0
0
0
Rev. PrG | Page 21 of 34
AD5755/AD5735
Preliminary Technical Data
Table 19. AD5755 Offset Register options
Offset Adjustment
OF15
OF14
OF13
OF12 to OF4
OF3 OF2
OF1
OF0
+32768 LSBs
1
1
-
1
1
-
1
1
-
1
1
-
1
1
-
1
1
-
1
0
-
1
0
-
+32767 LSBs
No Adjustment (default)
1
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
−32767 LSBs
−32768 LSBs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 20. AD5735 Offset Register options
Offset Adjustment
OF15
OF14
OF13
OF12 to OF4
OF3 OF2
OF1
X
OF0
X
+8192 LSBs
1
1
-
1
1
-
1
1
-
1
1
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
+8191 LSBs
X
X
X
X
No Adjustment (default)
1
-
0
-
0
-
0
-
X
X
X
X
−8191 LSBs
0
0
0
0
0
0
1
0
X
X
−8192 LSBs
X
X
CLEAR CODE REGISTER
There is a per channel Clear Code Register. The Clear Code Register is 16 bits wide and is addressed by setting the DREG bits to’1,1,0’. It
is also possible, via software, to enable/disable on a per channel basis which channels will be cleared when the CLEAR pin is activated.
The default clear code is all 0’s. See Features section for more information.
Table 21. Programming AD5755 Clear Code Register
D23 D22
D21
DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 CLEAR CODE
DEVICE ADDRESS 110 DAC Channel Address DATA
D20
D19
D18
D17
D16
D15 to D0
R/
0
W
Table 22. Programming the AD5735 Offset Register
R/
DUT_
AD1
DUT_
AD0
DREG2 DREG1 DREG0 DAC_
DAC_
AD0
D15 to D4
D3 D2 D1 D0
W
AD1
0
DEVICE ADDRESS 110
DAC Channel Address CLEAR CODE
0
0
0
0
Rev. PrG | Page 22 of 34
Preliminary Technical Data
AD5755/AD5735
CONTROL REGISTERS
When writing to a data register the following format must be used:
Table 23. Writing to a control register
MSB
LSB
D23 D22
D21
D20 D19 D18 D17
D16
D15
D14
D13
D12to D0
R/ DUT_AD1 DUT_AD0
W
1
1
1
DAC_AD1 DAC_AD0 CREG2 CREG1 CREG0
See Table 10 for configuration on bits D23 to D16. The control registers are addressed by setting the DREG bits to DREG2 = 1, DREG1 =
1, DREG0=1 and then setting the CREG2, CREG1 and CREG0 bits to the appropriate decode address for that register as per Table 24
below. These CREG bits select between the various control registers.
Table 24. Register Access Decode
CREG2, (D15)
CREG1, (D14)
CREG0, (D13)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Slew Rate Control Register (one per channel)
Main Control Register
DAC Control Register (one per channel)
DC-DC Control Register
Software Register (one per channel)
MAIN CONTROL REGISTER
CREG2, CREG1, CREG0 are set to ‘0,0,1’ to select the Main Control Register. The Main Control Register options are shown below.
Table 25. Programming the Main Control Register
MSB
D15
0
LSB
D14 D13 D12
POC
D11
STATREAD
D10
EWD
D9
WD1
D8
WD0
D7
X
D6
ShtCctLim
D5
OUTEN ALL
D4
DC-DC ALL
D3 to D0
0
1
X
Table 26. Main Control Register Functions.
Option
Description
POC
The POC bit decides the state of the VOUT channel during normal operation. It’s default value is 0.
POC Bit = 0. The output will go to the value set by the POC pin when the current out channel is enabled.
POC Bit = 1. The output will go to the opposite value of the POC pin if the channels Iout is enabled.
STATREAD
EWD
Enable status readback during a write. See Features section.
STATREAD =1, Enable
STATREAD =0, Disable
Enable Watchdog Timer. See features section for more information.
EWD=1, Enable Watchdog
EWD=0, Disable Watchdog
WD1, WD0
Timeout Select Bits. Used to select timeout period for watchdog timer.
WD1 WD0
0
0
1
1
0
1
0
1
5ms
10ms
100ms
200ms
ShtCctLim
Programmable Short Circuit Limit on Vout pin in the event of a short circuit condition.
0=15ma
1=8ma
OUTEN ALL
DC_DCALL
Enables the output on all 4 DAC simultaneously.
Do not use the OUTEN ALL bit when using the OUTEN bit in the DAC Control Registers.
When set, Powers up the DC-DC on all 4 channels Simultaneously.
To Power down the DC-DCs all channels outputs must first be disabled.
Do not use the DC_DCALL bit when using the DC_DC bit in the DAC Control Registers.
Rev. PrG | Page 23 of 34
AD5755/AD5735
Preliminary Technical Data
DAC CONTROL REGISTER
The DAC Control Register is used to configure each DAC Channel. The DAC Control Register is selected by setting bits CREG2, CREG1,
CREG0 to 0,1,0.
Table 27. Programming DAC Control Register
D15 D14 D13 D12 D11 D10 D9 D8
D7
D6
D5
D4
D3
D2 D1 D0
0
1
0
X
X
X
X
INT_ENABLE CLR_EN OUTEN RSET DC-DC OVRNG R2 R1 R0
Table 28. DAC Control Register Functions
Option
Description
Powers up the DC-DC, DAC and internal amplifiers for the selected channel. Does not enable the output.
Can only be done on a per channel basis.
INT_ENABLE
Per channel Clear Enable bit. Selects if this channel will clear when the CLEAR pin is activated.
CLR_EN=1, channel will clear when part is cleared.
CLR_EN=0, channel will not clear when part is cleared.
CLR_EN
OUTEN
RSET
Enables/Disables the selected output channel
OUTEN=1, Enables channel
OUTEN=0, Disable channel
Selects internal or external current sense resistor for selected DAC channel
RSET = 0 Selects external Resistor
RSET = 1 Selects Internal Resistor
Powers the DC-DC on selected channel.
DC_DC
DC_DC = 1, Power up DC_DC
DC_DC = 0, Power down DC_DC
This allows per channel DC_DC power up/down. To power down the DCDC, OUTEN and INT_ENABLE
bits must also be set to 0.
All DC-DCs can also be powered up simultaneously using DCDC_All bit in the Main Control Register.
Enables 20% over-range on Vout Channel only. No current over-range available.
OVRNG
OVRNG=1, Enabled
OVRNG=0, Disabled
Selects output range enabled.
R2,R1,R0
R2 R1 R0 Output Range Selected
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0 to 5V Voltage Range
0 to 10V Voltage Range
5V Voltage Range
10V Voltage Range
4 to 20 mA Current Range
0 to 20 mA Current Range
0 to 24 mA Current Range
SOFTWARE REGISTER
The Software Register has three functions. It allows the user to perform a software reset to the part. It can be used to set bit D11 in the
Status Register. Lastly it is also used as part of the watchdog feature to ensure that the SPI interface connections are working properly. To
ensure all the datapath lines are working properly (i.e. SDI/SCLK/SYNC), the user must write 0x195 to the Software Register within the
timeout period. If this command is not received within the timeout period, the ALERT pin will signal a fault condition. Note. This is only
required when the Watchdog Timer function is enabled.
Table 29. Programming the Software Register
To program a software reset you need to write 1,0,0 to CREG2, CREG1, CREG0.
MSB
D15
1
LSB
D14
D13
D12
D11 to D0
0
0
User Program Bit
RESET CODE/SPI CODE
Rev. PrG | Page 24 of 34
Preliminary Technical Data
AD5755/AD5735
Table 30. Software Register Functions
User Program Bit
This bit is mapped to bit D11 of the Status Register. When this bit is set to 1 bit D11 of the Status Register is set to
1. Likewise when D12 is set to 0 bit D11 of the Status Register is also set to zero. This feature can be used to
ensure the SPI pins are working correctly by writing known bit to this register and reading back corresponding
bit from the Status Register.
RESET CODE/SPI CODE
Option
Description
RESET CODE
SPI CODE
Writing 0x555 to D11-D0 performs a reset.
If Watchdog Timer feature enabled, 0x195 must be written to the Software Register
(D11-D0) within every timeout period to ensure valid data communication path.
DC-DC CONTROL REGISTER
The DC-DC Control Register allows the user control over the DC-DC Switching Frequency, and of the phase of when the per channel
switching starts. The maximum allowable DC-DC output frequency is also programmable.
Table 31. Programming the DC-DC Control Register
MSB
D15
0
LSB
D1 to D0
DC-DC MaxV
D14
D13
D12 to D7
D5 to D4
D3 to D2
1
1
X
DC-DC Phase
DC-DC Freq
Table 32. DC-DC Control Register Options
Option
Description
DC-DC Phase
User Programmable DC-DC Phase (Between Channels)
00 = All DC-DCs clock on same edge
01 = ChanA, ChanB clock on same edge, ChanC & ChanD clock on opposite edge
10 = ChanA, ChanC clock on same edge, ChanB & ChanD on opposite edge
11 = ChanA, ChanB, ChanC, ChanD clock 90' out of phase from each other
DC-DC Freq
DC-DCMaxV
User Programmable DC-DC Switching Frequency:
00 = 250 Khz
01 = 406 Khz
10 = 649 Khz
11 = 812 Khz
Maximum allowed VBOOST voltage supplied by the DC-DC.
00 = 25V 1V
01 = 27.3 1V
10 = 28.6 1V
11 = 30 1V
SLEW RATE CONTROL REGISTER
This register is used to program the slew rate control for the selected DAC Channel. The CREG bits are set to ‘0,0,0’ to select the Slew
Rate Control Register. SR_CLOCK and SR_STEP allow the user to control the rate of the output SLEW. This feature is available on both
the current and voltage outputs. With the slew rate control feature disabled the output value will change at a rate limited by the output
drive circuitry and the attached load. SE enables output slew rate control. It can be both programmed and enabled/disabled on a per
channel basis. For more information see the features section.
Table 33. Programming the Slew Rate Control Register
D15 D14 D13 D12 D11-D7 D6 to D3
D2 to D0
0
0
0
SE SR_CLOCK
X
SR_STEP
Rev. PrG | Page 25 of 34
AD5755/AD5735
Preliminary Technical Data
READBACK OPERATION
Readback mode is invoked by setting the R/ bit = 1 in the serial input register write. With R/ = 1, bits DUT_AD1, DUT_AD0, in
W
W
association with bits RD4, RD3, RD2, RD1, RD0 (See Table 35), select the register to be read. The remaining data bits in the write
sequence are don’t care. During the next SPI transfer, the data appearing on the SDO output contains the data from the previously
addressed register. The readback diagram in Figure 3 shows the readback sequence.
Table 34. Input Shift Register Contents for a read operation
D23
D22
D21
D20 D19 D18 D17 D16
D15 to D0
X
R/
DUT_AD1 DUT_AD0 RD4 RD3 RD2 RD1 RD0
W
Table 35. Read Address Decoding
RD4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
RD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
RD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
RD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
RD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Function
Read DACA Data Register
Read DACB Data Register
Read DACC Data Register
Read DACD Data Register
Read Control Register DAC A
Read Control Register DAC B
Read Control Register DAC C
Read Control Register DAC D
Read Gain Register A
Read Gain Register B
Read Gain Register C
Read Gain Register D
Read Offset Register A
Read Offset Register B
Read Offset Register C
Read Offset Register D
Clear Code Register DAC A
Clear Code Register DAC B
Clear Code Register DAC C
Clear Code Register DAC D
Slew Rate Control Register DAC A
Slew Rate Control Register DAC B
Slew Rate Control Register DAC C
Slew Rate Control Register DAC D
Read Status Register
Read Main Control Register
Read DC-DC Control Register
Read Back Example
To read back the Gain Register of Device #1 Channel A on the AD5755, the following sequence should be implemented:
1. Write 0xA80000 to the AD5755 input register. This configures the AD5755 device address #1 for read mode with the Gain Register of
channel A selected.. Note that all the data bits, D15 to D0, are don’t care.
2. Follow this with any read/write command. During this command, the data from the selected Gain Register is clocked out on the SDO
line.
Rev. PrG | Page 26 of 34
Preliminary Technical Data
AD5755/AD5735
STATUS REGISTER
The Status Register is a read only register. This register contains any fault information as a well as a RAMP ACTIVE bit and a User Toggle
Bit. By setting the STATREAD bit in the Main Control Register, the Status Register contents can be readback on the SDO pin during every
write sequence.
Table 36. Decoding the Status Register
MSB
LSB
D0
D15
to
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D12
X
DC-
DC-
DC-
DC-
User
PEC
RAMP
OVER
SHORT
SHORT SHORT
SHORT
OPEN OPEN OPEN OPEN
Toggle ERROR ACTIVE TEMP CCT
Bit VD
CCT VC CCT VB CCT
VA
CCT
ID
CCT
IC
CCT
IB
CCT
IA
DCD DCC DCB DCA
Table 37. Status Register Options
Option
Description
DC-DCD
DC-DC Failure on Channel D. This fault indicates that the DCDC is not operating, for example if the boost inductor is
not connected.
DC-DCC
DC-DC Failure on Channel C. This fault indicates that the DCDC is not operating, for example if the boost inductor is
not connected.
DC-DCB
DC-DC Failure on Channel B. This fault indicates that the DCDC is not operating, for example if the boost inductor is
not connected.
DC-DC A
DC-DC Failure on Channel A. This fault indicates that the DCDC is not operating, for example if the boost inductor is
not connected.
User Toggle Bit
User Writable bit that the user can set and readback while doing a Status Register read. This can be used to verify
data communications if needed.
PEC ERROR
Denotes a PEC Error on the SPI Interface Transmit.
RAMP ACTIVE
This bit will be set while any one of the output channels are slewing (slew rate control enabled on at least one
channel)
OVER TEMP
This bit will be set if the AD5755/AD5735 core temperature exceeds approx. 150°C.
This bit will be set if a fault is detected on DACD VOUT pin.
This bit will be set if a fault is detected on DACC VOUT pin.
This bit will be set if a fault is detected on DACB VOUT pin.
This bit will be set if a fault is detected on DACA VOUT pin.
This bit will be set if a fault is detected on DACD IOUT pin.
This bit will be set if a fault is detected on DACC IOUT pin.
This bit will be set if a fault is detected on DACB IOUT pin.
This bit will be set if a fault is detected on DACA IOUT pin.
SHORT CCT VD
SHORT CCT VC
SHORT CCT VB
SHORT CCT VA
OPEN CCT ID
OPEN CCT IC
OPEN CCT IB
OPEN CCT IA
Rev. PrG | Page 27 of 34
AD5755/AD5735
Preliminary Technical Data
FEATURES
the M and C registers. The calibrated DAC data is then stored
in the DAC2 register.
OUTPUT FAULT
The AD5755/AD5735 is equipped with a FAULT pin, this is an
active low open-drain output allowing several AD5755/AD5735
devices to be connected together to one pull-up resistor for
global fault detection. The FAULT pin is forced active by any
one of the following fault scenarios;
INPUT
REGISTER
DAC
REGISTER
DAC
M
REGISTER
1) The Voltage at IOUT attempts to rise above the
compliance range, due to an open-loop circuit or
insufficient power supply voltage. The internal
circuitry that develops the fault output avoids using a
comparator with “window limits” since this would
require an actual output error before the FAULT
output becomes active. Instead, the signal is generated
when the internal amplifier in the output stage has less
than approximately one volt of remaining drive
capability. Thus the FAULT output activates slightly
before the compliance limit is reached. Since the
comparison is made within the feedback loop of the
output amplifier, the output accuracy is maintained by
its open-loop gain and an output error does not occur
before the FAULT output becomes active.
C
REGISTER
Figure 19. Digital Offset and Gain control
Although this diagram indicates a multiplier and adder for each
channel, there is only one multiplier and one adder in the device,
and they are shared among all 4 channels. This has implications
for the update speed when several channels are updated at once.
Each time data is written to the M or C register the output is not
automatically updated. Rather, the next write to the DAC
channel will use these M&C values to perform a new calibration
and automatically update the channel.
Data output from the DAC2 register is routed to the final DAC
register by a multiplexer. Both the Gain Register and the Offset
Register have 16 bits of resolution. The correct method to
calibrate the gain/offset is firstly to calibrate out the gain and
then calibrate the offset.
2) A short is detected on the voltage output pin. Short
circuit current limited to 15ma or 8ma, this is
programmable by the user.
The value (in decimal) that is written to the DAC register can
be calculated by:
3) An interface error is detected due to a PEC failure. See
Packet Error Checking section.
(M +1)
CodeDAC Re gister = D ×
+ C − 215
216
4) If the core temperature of the AD5755/AD5735
exceeds approx. 150°C.
where:
The OPEN CCT and OVER TEMP bits of the Status Register
are used in conjunction with the FAULT output to inform the
user which one of the fault conditions caused the FAULT output
to be activated.
D is the code loaded to the DAC channels input register.
M is the code in Gain Register − default code = 216 – 1
C is the code in Offset Register − default code = 215
STATUS READBACK DURING WRITE
The AD5755/AD5735 has the ability to read back the Status
Register contents during every write sequence. This feature is
enabled via the STATREAD bit in the Main Control Register.
This allows the user to continuously monitor the Status Register
and act quickly in the case of a fault.
VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION
Under normal operation the voltage output will sink/source up
to 10mA and maintain specified operation. The maximum
current that the voltage output will deliver is 15mA, this is the
short circuit current. This short circuit current is programmable
by the user and can be set to 15mA or 8mA. If a short circuit is
detected the FAULT will go low and the relevant SHORT CCT
bit in the Status register will be set.
When Status Readback During Write is enabled the contents of
the 16bit Status register (See Table 37) is outputted on the SDO
pin as indicated in Figure 4.
DIGITAL OFFSET AND GAIN CONTROL
The AD5755/AD5735 will power up with this feature disabled.
When this is enabled the normal readback feature is not
available, except of the status register. To readback any other
register set STATREAD low first before following the readback
sequence. STATREAD may be set high again after the register
read.
Each DAC channel has a gain (M) and offset (C) register, which
allow trimming out of the gain and offset errors of the entire
signal chain. Data from the DAC Data Register is operated on
by a digital multiplier and adder controlled by the contents of
Rev. PrG | Page 28 of 34
Preliminary Technical Data
AD5755/AD5735
The watchdog timer is enabled and the timeout period
(50,100,150 or 200ms) set in the control register (See Table 25).
ASYNCHRONOUS CLEAR
CLEAR is an active high edge sensitive input that allows the
output to be cleared to a pre programmed 16 bit code. This code
is user programmable via a per-channel 16 bit Clear Code
Register.
OUTPUT ALERT
The AD5755/AD5735 is equipped with a ALERT pin, this is An
active high CMOS output. The AD5755/AD5735 has an
internal watchdog timer. If enabled, it will monitor SPI
communications. If 0x195 is not received by the Software
Register within the timeout period, the ALERT pin will go
active.
In order for a channel to clear, that channel must be enabled to
be cleared via the CLR_EN bit in the channels DAC Control
Register. If the channel is not enabled to be cleared then the
output will remain in its current state independent of the
CLEAR pin level.
INTERNAL REFERENCE
When the CLEAR signal is returned low, the relevant outputs
remains cleared until a new value is programmed.
The AD5755/AD5735 contains an integrated +5V voltage
reference with initial accuracy of 2mV max and a temperature
drift coefficient of 5 ppm max. The reference voltage is
buffered and externally available for use elsewhere within the
system.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy
environments, the AD5755/AD5735 offers the option of packet
error checking based on an 8-bit (CRC-8) cyclic redundancy
check. The device controlling the AD5755/AD5735 should
generate an 8-frame check sequence using the polynomial
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 15, R1 is an internal sense resistor as part of
the voltage to current conversion circuitry. The stability of the
output current value over temperature is dependent on the
stability of the value of R1. As a method of improving the
stability of the output current over temperature an external
15kΩ low drift resistor can be connected to the RSET pin of the
AD5755/AD5735 to be used instead of the internal resistor R1.
The external resistor is selected via the DAC Control register.
See Table 27.
C(x) = x8 + x2 + x1 +1
This is added to the end of the data word, and 32 bits are sent to
the AD5755/AD5735 before taking
high. If the
SYNC
AD5755/AD5735 sees a 32-bit frame, it will perform the error
check when goes high. If the check is valid, then the data
SYNC
will be written to the selected register. If the error check fails,
the FAULT pin will go low and the PEC ERROR bit in the Status
Register will be set. After reading the Status Register, FAULT
will return high (assuming there are no other faults) and the
PEC ERROR bit will be cleared automatically.
SLEW RATE CONTROL
The Slew Rate Control feature of the AD5755/AD5735 allows
the user to control the rate at which the output value changes.
This feature is available on both the current and voltage
outputs. With the slew rate control feature disabled the output
value will change at a rate limited by the output drive circuitry
and the attached load. If the user wishes to reduce the slew rate
this can be achieved by enabling the slew rate control feature.
With the feature enabled via the SREN bit of the Slew Rate
Control Register, (See Table 33) the output, instead of slewing
directly between two values, will step digitally at a rate defined
by two parameters accessible via the Slew Rate Control Register
as shown in Table 33. The parameters are SR_CLOCK and
SR_STEP. SR_CLOCK defines the rate at which the digital slew
will be updated, e.g. if the selected update rate is 8KHz the
output will update every 125µs, in conjunction with this the
SR_STEP defines by how much the output value will change at
each update. Together both parameters define the rate of change
of the output value. Table 38 and Table 39 outline the range of
values for both the SR_CLOCK and SR_STEP parameters.
The PEC can be used for both transmit and receive of data
packets. If Status Readback During Write is enabled, the ‘PEC’
values returned during the Status Readback During Write
should be ignored. All other PEC values will be valid though
and the user can still use the normal readback operation to
monitor Status Register activity with PEC.
WATCHDOG TIMER
If enabled, an on chip watchdog timer will generate an alert
signal if 0x195 has not been written to the Software Register
within the programmed timeout period. This feature is useful to
ensure communication has not been lost between the MCU and
the AD5755/AD5735 and that these datapath lines are working
properly (i.e. SDI/SCLK/SYNC). If 0x195 is not received by the
Software Register within the timeout period, the ALERT pin
will signal a fault condition. The ALERT signal is active high
and can be connected directly to the CLEAR pin to enable a
CLEAR in the event that data communications are lost from the
MCU.
Rev. PrG | Page 29 of 34
AD5755/AD5735
Preliminary Technical Data
POWER DISSIPATION CONTROL
Table 38. Slew Rate Update Clock Options
The AD5755/AD5735 contains integrated dynamic power
control using a DC-DC boost circuit allowing reductions in
power consumption from standard designs when using the part
in current output mode.
SR_CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Update Clock Frequency (Hz)*
64K
32K
16K
8k
In standard current input module designs the load resistor
values can range from typically 50 ohm to 750 ohm. Output
module systems must source enough voltage to meet the
compliance voltage requirement across the full range of load
resistor values. For example, in a 4-20ma loop when driving
20ma a compliance voltage of >15V is required. When driving
20ma into a 50 ohm load only 1V compliance is required.
4k
2k
1k
500
250
125
64
The AD5755/AD5735 circuitry senses the output voltage and
regulates this voltage to meet compliance requirements plus a
small headroom voltage.
32
16
8
DC-DC CONVERTERS
The AD5755/AD5735 contains 4 independent DCDC
converters. These are used to provide dynamic control of the
4
0.5Hz
V
BOOST supply voltage for each channel (See Figure 15). Figure
*Clock Frequencies accurate to TDB%.
20 below shows the discreet components needed for the DCDC
circuitry and the following sections describe component
selection and operation of this circuitry.
Table 39. Slew_Rate Step Size Options
SR_STEP
AD5735 (12 BIT)
Step Size (LSBs)
1/16
AD5755 (16 BIT)
Step Size (LSBs)
L DCDC
DDCDC
AVcc
Vboost_x
000
001
010
011
100
101
110
111
1
2
1/8
1/4
½
CDCDC
4
SW_x
Figure 20. DC-DC Circuit
16
32
64
128
256
2
DC-DC Operation
4
8
The on-board DC-DC converters use a constant frequency,
peak current mode control scheme to step-up an AVcc input in
the range 2.7 to 5.5v to drive the AD5755/AD5735 output
channel. These are designed to operate in discontinuous
conduction mode (DCM) with a duty cycle < 85%.
Discontinuous conduction mode refers to a mode of operation
where the inductor current goes to zero for an appreciable % of
the switching cycle. The DCDC converters are non
16
The following equation describes the slew rate as a function of
the step size, the update clock frequency and the LSB size.
Output Change
Slew Time =
Step Size ×Update Clock Frequency × LSB Size
synchronous i.e. they require an external schottky diode.
Where:
DC-DC Output Voltage
Slew T i me is expressed in seconds
Output Change is expressed in Amps for I OUT or V olts for V OUT
W hen the slew rate control feature is enabled, all output
changes will change at the programmed slew rate, for example
if the CLEAR pin is asserted the output will slew to the clear
value at the programmed slew rate (assuming that C lear
channel is enabled to be cleared) . T he update clock
frequency for any given value will be the same for all output
ranges, the step size however will vary across output ranges for
a given value of step size as the L SB size will be different for
each output range.
When a channel current output is enabled the converter
regulates the Vboost supply to 7.5V or (Iout*Rload+2V),
whichever is greater. The maximum Vboost voltage is set in the
DC-DC Control Register (25, 27.3, 28.6 or 30V. See Table 32).
In voltage output mode, or in current output mode with the
output disabled, the converter regulates the VBOOST supply to
+15v ( 8%).
Rev. PrG | Page 30 of 34
Preliminary Technical Data
AD5755/AD5735
Within a channel the Vout & Iout stages share a common Vboost
supply so that the outputs of the Iout & Vout stages can be tied
together.
reverse breakdown expected in operation & that the rectifier
maximum junction temperature is not exceeded. The diode
average current = Iload current.
DC-DC On-Board Switch
DC-DC Compensation Capacitors
The AD5755/AD5735 contains a 0.5ohm internal switch . The
switch current is monitored on a pulse by pulse basis & is
limited to 0.8A peak current.
As the DCDC operates in DCM the uncompensated transfer
function is essentially a single pole transfer function. The pole
frequency is determined by Cout, Vin, Vout & Iload. The
AD5755/AD5735 uses an external capacitor in conjunction
with an internal 150k resistor to compensate the regulator loop.
For typical 4-20mA applications connect a 10nF capacitor from
each of the COMPDCDC_A/_B/_C/_D pins to GND.
DC-DC Switching Frequency and Phase
The AD5755/AD5735 DCDC switching frequency can be
selected from the DCDC Control Register to be 250Khz,
400Khz, 649kHz or 812kHz. The phasing of the channels can
also be adjusted so that the DCDCs can clock on different edges
(See Table 32). For typical applications a 250Khz frequency is
recommended. At light loads (low output current & small load
resistor) the DCDC enters a pulse skipping mode to minimize
switching power dissipation.
DC-DC Input and Output Capacitor Selection
The output capacitor effects ripple voltage of the DCDC
converter & also indirectly limits the maximum slew rate at
which the channel output current can rise. The ripple voltage is
caused by a combination of the capacitance & ESR (equivalent
series resistance) of the capacitor. For the AD5755/AD5735 a
ceramic capacitor of 4.7µF is recommended for typical
applications. Larger capacitors or paralled capacitors will
improve the ripple at the expense of reduced slew rate.
DC-DC Inductor Selection
For typical 4-20mA applications a 10uH inductor combined
with a switching frequency of 250Khz will allow up to 24mA to
be driven into a load resistance of up to 1kΩ with an AVcc
supply from 2.7 to 5.5v. The inductor must be able to handle the
peak current without saturating at the maximum ambient
temperature.
The input capacitor will provide much of the dynamic current
required for the DCDC converter & should also be a low ESR
component. For the AD5755/AD5735 a ceramic capacitor of
10µF is recommended for typical applications. Ceramic
capacitors must be chosen carefully as they can exhibit a large
sensitivity to DC bias voltages & temperature. X5R or X7R
dielectrics are preferred as these capacitors remain stable over
wider operating voltage & temperature ranges.
If an alternative Inductor/Switching frequency is preferred then
one must ensure that the DCDC continues to operates in DCM
mode and that the inductor current is less than 0.8A.
2× IOUT max (VOUT max −VCC min
IPEAK max 2 × FSW
)
Iout Slew Rate when using the DC-DC
When the AD5755/AD5735 is configured in Iout mode & a step
increase in output current is programmed then the DCDC
converter must increase its output voltage so that Vboost ≈
Iout*Rload+2v. This requires that the output capacitor of the
DCDC circuit must also be charge to the new voltage. The
amount of power required to do this is 0.5*C*(Vnew-Vold).
Figure 7. And Figure 8.show Iout settling for a 0 to 24mA step
into a 1kohm load for different caps & inductor/switching
frequency.
VIN min 2 (VOUT max −VIN min )×η
< L <
2× IOUT max ×VOUT max 2 × FSW
Where:
I
PEAK max=Maximum Peak Current (0.8A limit)
SW=Switching Frequency set in the DCDC Control Register.
F
η = efficiency (Assume = 0.8)
DC-DC External schottky selection
The AD5755/AD5735 requires an external schottky for correct
operation. Ensure the schottky is rated to handle the maximum
Rev. PrG | Page 31 of 34
AD5755/AD5735
Preliminary Technical Data
APPLICATIONS INFORMATION
PRECISION VOLTAGE REFERENCE SELECTION
DRIVING INDUCTIVE LOADS
To achieve the optimum performance from the
When driving inductive or poorly defined loads connect a
0.01µF capacitor between IOUT and GND. This will ensure
stability with loads beyond 50mH. There is no maximum
capacitance limit. The capacitive component of the load may
cause slower settling, though this may be masked by the settling
time of the AD5755/AD5735.
AD5755/AD5735 over its full operating temperature range, a
precision voltage reference must be used. Thought should be
given to the selection of a precision voltage reference. The
voltage applied to the reference inputs is used to provide a
buffered reference for the DAC cores. Therefore, any error in
the voltage reference is reflected in the outputs of the device.
TRANSIENT VOLTAGE PROTECTION
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long term drift, and output voltage noise.
The AD5755/AD5735 contains ESD protection diodes which
prevent damage from normal handling. The industrial control
environment can, however, subject I/O circuits to much higher
transients. In order to protect the AD5755/AD5735 from
excessively high voltage transients , external power diodes and a
surge current limiting resistor may be required, as shown in
Figure 21. The constraint on the resistor value is that during
normal operation the output level at IOUT must remain within
its voltage compliance limit of AVDD – 2.5V and the two
protection diodes and resistor must have appropriate power
ratings.
Initial accuracy error on the output voltage of an external
reference could lead to a full-scale error in the DAC. Therefore,
to minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR425, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim
adjustment could be used at temperature to trim out any error.
AV
DD
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
AV
DD
R
P
AD5755
I
OUT
GND
R
LOAD
The temperature coefficient of a reference’s output voltage
affects INL, DNL, and TUE. A reference with a tight
temperature coefficient specification should be chosen to
reduce the dependence of the DAC output voltage on ambient
conditions.
Figure 21. Output Transient Voltage Protection
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5755/AD5735 is via a serial
bus that uses a protocol compatible with microcontrollers and
DSP processors. The communications channel is a 3-wire
minimum interface consisting of a clock signal, a data signal,
and a latch signal. The AD5755/AD5735 require a 24-bit data-
word with data valid on the falling edge of SCLK.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered.
Choosing a reference with as low an output noise voltage as
practical for the system resolution required is important.
Precision voltage references such as the ADR435 (XFET design)
produce low output noise in the 0.1 Hz to 10 Hz region.
However, as the circuit bandwidth increases, filtering the output
of the reference may be required to minimize the output noise.
The DAC output update is initiated on either the rising edge of
or, if
is held low, on the rising edge of
. The
LDAC
LDAC
SYNC
contents of the registers can be read using the readback
function.
Table 40. Some Recommended Precision References
AD5755/AD5735 TO ADSP-BF527 INTERFACE
Part
No.
Initial
Accuracy Drift (ppm
(mV
Max)
Long-Term
Temp
Drift
(ppm/°C
0.1 Hz to 10
Hz Noise
(µV p-p
Typ)
The AD5755/AD5735 can be connected directly to the SPORT
interface of the ADSP-BF527, an Analog Devices, Inc., Blackfin®
D SP. Figure 22 shows how the SPORT interface can be
connected to control the AD5755/AD5735.
Typ)
Max)
ADR435
ADR425
ADR02
6
30
50
50
50
15
3
3.4
3.4
15
5
6
3
5
3
ADR395
AD586
6
25
10
2.5
4
Rev. PrG | Page 32 of 34
Preliminary Technical Data
AD5755/AD5735
routed between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board that has a
separate ground plane, but separating the lines helps). It is
essential to minimize noise on the REFIN line because it
couples through to the DAC output.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feed through the board. A
microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground plane, while signal
traces are placed on the solder side.
Figure 22. AD5755/AD5735 to ADSP-BF527 SPORT Interface
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5755/AD5735 is mounted should be designed so that the
analog and digital sections are separated and confined to certain
areas of the board. If the AD5755/AD5735 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that might occur.
Isocouplers provide voltage isolation in excess of 2.5 kV. The
serial loading structure of the AD5755/AD5735 makes it ideal
for isolated interfaces, because the number of interface lines is
kept to a minimum. Figure 23 shows a 4-channel isolated
interface to the AD5755/AD5735 using an ADuM1400. For
more information, go to www.analog.com.
The AD5755/AD5735 should have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI) such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
1
µCONTROLLER
ADuM1400
V
V
V
V
V
V
V
V
IA
OA
OB
OC
OD
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
SERIAL CLOCK OUT
TO SCLK
TO SDIN
TO SYNC
TO LDAC
IB
IC
ID
SERIAL DATA OUT
SYNC OUT
The power supply lines of the AD5755/AD5735 should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board and
should never be run near the reference inputs. A ground line
CONTROL OUT
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Isolated Interface
Rev. PrG | Page 33 of 34
AD5755/AD5735
Preliminary Technical Data
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
PIN 1
INDICATOR
64
1
49
48
PIN 1
INDICATOR
0.50
BSC
7.25
7.10 SQ
6.95
8.75
BSC SQ
TOP VIEW
EXPOSED PAD
(BOTTOM VIEW)
0.50
0.40
0.30
16
17
33
32
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 24. 64-Lead Frame Chip Scale Package, 9x9 Quad.[LFCSP]
Dimensions shown in millimeters
ORDERING GUIDE
Model
RESOLUTION TUE
ACCURACY
Temperature Range
Package Description
Package Option
AD5755ACPZ
AD5755BCPZx
AD5735ACPZ
16-bit
16-bit
12-bit
0.3% max
0.05% max
0.3% max
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
CP-64-3
CP-64-3
CP-64-3
Rev. PrG | Page 34 of 34
PR07304-0-7/10(PrG)
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