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AD5750-1 [ADI]

Industrial Current/Voltage Output Driver with Programmable Ranges; 用可编程范围工业电流/电压输出驱动器
AD5750-1
型号： AD5750-1
厂家： ADI    ADI
描述：

Industrial Current/Voltage Output Driver with Programmable Ranges
用可编程范围工业电流/电压输出驱动器

驱动器
文件： 总36页 (文件大小：695K)
中文：  中文翻译
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Industrial Current/Voltage Output Driver  
with Programmable Ranges  
AD5750/AD5750-1  
The output current range is programmable across five current  
ranges: 4 mA to 20 mA, 0 mA to 20 mA or 0 mA to 24 mA,  
FEATURES  
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA or  
0 mA to 24 mA, ±20 mA, and ±24 mA  
±0.03% FSR total unadjusted error (TUE)  
±± ppm/°C typical output drift  
20 mA, and 24 mA. An overrange of 2% is available on the  
unipolar current ranges.  
Voltage output is provided from a separate pin that can  
be configured to provide 0 V to 5 V, 0 V to 10 V, 5 V, or  
10 V output ranges. An overrange of 20% is available on the  
voltage ranges.  
Voltage output ranges: 0 V to ± V, 0 V to 10 V, ±± V, and ±10 V,  
with 20% overrange  
±0.02% FSR TUE  
±3 ppm/°C typical output drift  
Flexible serial digital interface  
On-chip output fault detection  
PEC error checking  
Analog outputs are short-circuit and open-circuit protected and  
can drive capacitive loads of 1 μF and inductive loads of 0.1 H.  
The device is specified to operate with a power supply range from  
12 V to 24 V. Output loop compliance is 0 V to AVDD − 2.75 V.  
Asynchronous CLEAR function  
Flexible power-up condition to 0 V or tristate  
Power supply range  
The flexible serial interface is SPI and MICROWIRE  
compatible and can be operated in 3-wire mode to minimize  
the digital isolation required in isolated applications. The  
interface also features an optional PEC error checking feature  
using CRC-8 error checking, useful in industrial environments  
where data communication corruption can occur.  
AVDD: +12 V (± 10%) to +24 V (± 10%)  
AVSS: −12 V (± 10%) to −24 V (± 10%)  
Output loop compliance to AVDD − 2.7± V  
Temperature range: −40°C to +10±°C  
32-lead, ± mm × ± mm LFCSP package  
The device also includes a power-on reset function, ensuring  
that the device powers up in a known state (0 V or tristate),  
and an asynchronous CLEAR pin that sets the outputs to zero  
scale/midscale voltage output or the low end of the selected  
current range.  
APPLICATIONS  
Process control  
Actuator control  
PLCs  
An HW SELECT pin is used to configure the part for hardware  
or software mode on power-up.  
GENERAL DESCRIPTION  
The AD5750/AD5750-1 are single-channel, low cost, precision  
voltage/current output drivers with hardware- or software-  
programmable output ranges. The software ranges are configured  
via an SPI-/MICROWIRE™-compatible serial interface. The  
AD5750/AD5750-1 target applications in PLC and industrial  
process control. The analog input to the AD5750/AD5750-1  
is provided from a low voltage, single-supply digital-to-analog  
converter (DAC) and is internally conditioned to provide the  
desired output current/voltage range. Analog input ranges available  
are 0 V to 2.5 V (AD5750-1) or 0 V to 4.096 V (AD5750).  
Table 1. Related Device  
Part Number Description  
AD5422  
Single-channel, 16-bit, serial input current  
source and voltage output DAC  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2009 Analog Devices, Inc. All rights reserved.  
 
AD5750/AD5750-1  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
OUTEN........................................................................................ 26  
Software Control ........................................................................ 26  
Hardware Control ...................................................................... 28  
Transfer Function....................................................................... 28  
Detailed Description of Features.................................................. 29  
Output Fault Alert—Software Mode ....................................... 29  
Output Fault Alert—Hardware Mode ..................................... 29  
Voltage Output Short-Circuit Protection................................ 29  
Asynchronous Clear (CLEAR)................................................. 29  
External Current Setting Resistor ............................................ 30  
Programmable Overrange Modes............................................ 30  
Packet Error Checking............................................................... 30  
Applications Information.............................................................. 31  
Transient Voltage Protection .................................................... 31  
Thermal Considerations............................................................ 31  
Layout Guidelines....................................................................... 31  
Galvanically Isolated Interface ................................................. 32  
Microprocessor Interfacing....................................................... 32  
Outline Dimensions....................................................................... 33  
Ordering Guide .......................................................................... 33  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Revision History ............................................................................... 2  
Functional Block Diagram .............................................................. 3  
Specifications..................................................................................... 4  
Timing Characteristics ................................................................ 8  
Absolute Maximum Ratings.......................................................... 10  
ESD Caution................................................................................ 10  
Pin Configuration and Function Descriptions........................... 11  
Typical Performance Characteristics ........................................... 13  
Voltage Output............................................................................ 13  
Current Output........................................................................... 17  
Terminology .................................................................................... 22  
Theory of Operation ...................................................................... 23  
Software Mode............................................................................ 23  
Current Output Architecture.................................................... 25  
Driving Inductive Loads............................................................ 25  
Power-On State of AD5750/AD5750-1................................... 25  
Default Registers at Power-On ................................................. 26  
Reset Function ............................................................................ 26  
REVISION HISTORY  
8/09—Rev. 0 to Rev. A  
Added AD5750-1................................................................Universal  
Changes to Features and General Description Sections.............. 1  
Changes to Table 2............................................................................ 4  
Changes to Theory of Operation Section and Figure 51........... 23  
Change to Figure 52 and Table 6 Title ......................................... 24  
Changes to Current Output Architecture Section and Power-On  
State of AD5750/AD5750-1 .......................................................... 25  
Changes to Transfer Function Section......................................... 28  
Changes to Programmable Overrange Modes Section.............. 30  
Changes to Ordering Guide .......................................................... 33  
7/09—Revision 0: Initial Version  
Rev. A | Page 2 of 36  
 
AD5750/AD5750-1  
FUNCTIONAL BLOCK DIAGRAM  
DVCC GND  
AVDD GND COMP1 COMP2  
CLEAR  
AD5750/AD5750-1  
CLRSEL  
VSENSE+  
VOUT  
SCLK/OUTEN*  
SDIN/R0*  
INPUT SHIFT  
REGISTER  
AND  
CONTROL  
LOGIC  
VOUT RANGE  
SCALING  
SYNC/RSET*  
SDO/VFAULT*  
VOUT  
SHORT FAULT  
STATUS  
REGISTER  
HW SELECT  
VSENSE–  
VIN  
R2  
R3  
V
DD  
VREF  
RESET  
IOUT RANGE  
SCALING  
REXT1  
REXT2  
IOUT  
R
SET  
Vx**  
OVERTEMP  
V
SS  
VOUT SHORT FAULT  
IOUT OPEN FAULT  
FAULT/TEMP*  
NC/IFAULT*  
IOUT  
OPEN FAULT  
POWER-  
ON RESET  
AD2/R1*  
AD1/R2*  
AD0/R3*  
AVSS  
*DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT, HARDWARE MODE  
DENOTED BY ITALIC TEXT. FOR EXAMPLE, FOR FAULT/TEMP PIN, IN SOFTWARE MODE, THIS  
PIN TAKES ON FAULT FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ON TEMP FUNCTION.  
**Vx IS AN INTERNAL BIAS VOLTAGE (CAN BE GROUND OR OTHER VOLTAGE) THAT IS USED  
TO GENERATE THE INTERNAL SENSE CURRENTS NEEDED FOR THE CURRENT OUTPUTS.  
Figure 1.  
Rev. A | Page 3 of 36  
 
 
AD5750/AD5750-1  
SPECIFICATIONS  
AVDD/AVSS = 12 V ( 10%) to 24 V ( 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. IOUT: RLOAD = 300 Ω. All specifications TMIN to  
TMAX, unless otherwise noted.  
Table 2.  
Parameter1  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
Output unloaded  
AD5750  
INPUT VOLTAGE RANGE  
0 to  
V
4.096  
0 to 2.5  
AD5750-1  
Input Leakage Current  
REFERENCE INPUT  
Reference Input Voltage  
−1  
+1  
μA  
V
4.096  
AD5750; external reference needs to  
be exactly as stated; otherwise,  
accuracy errors show up as error in  
output  
1.25  
V
AD5750-1; external reference needs to  
be exactly as stated; otherwise,  
accuracy errors show up as error in  
output  
Input Leakage Current  
VOLTAGE OUTPUT  
−1  
+1  
μA  
Output Voltage Ranges  
0
0
5
10  
V
V
AVDD needs to have minimum 1.3 V  
headroom or >11.3 V  
−5  
−10  
+5  
+10  
V
V
AVDD/AVSS needs to have minimum  
1.3 V headroom or > 11.3 V  
Output Voltage Overranges  
0
6
V
Programmable overranges; see the  
Detailed Description of Features  
section  
0
−6  
−12  
−2.5  
12  
+6  
+12  
+2.5  
V
V
V
V
Accuracy  
Total Unadjusted Error (TUE)  
B Version2  
−0.1  
−0.05  
−0.3  
−0.1  
−0.02  
−10  
−8  
+0.1  
+0.05  
+0.3  
+0.1  
+0.02  
+10  
+8  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
mV  
0.02  
TA = 25°C  
TA = 25°C  
A Version2  
0.05  
0.005  
Relative Accuracy (INL)  
Bipolar Zero Error (Offset at Midscale)  
10 V range  
0.5  
mV  
TA = 25°C, 10 V range  
5 V range  
−5  
+5  
mV  
−4  
0.3  
1.5  
+4  
mV  
ppm FSR/°C  
mV  
mV  
mV  
TA = 25°C, 5 V range  
All bipolar ranges  
10 V range  
TA = 25°C, 10 V range  
5 V range  
Bipolar Zero Error TC3  
Zero-Scale Error  
−10  
−8  
−5  
+10  
+8  
+5  
0.5  
−4  
0.3  
1
+4  
mV  
ppm FSR/°C  
mV  
mV  
mV  
TA = 25°C, 5 V range  
All bipolar ranges  
0 V to 10 V range  
TA = 25°C, 0 V to 10 V range  
0 V to 5 V range  
Zero-Scale Error TC3  
Zero-Scale/Offset Error  
−5  
−4  
−3  
+5  
+4  
+3  
0.5  
Rev. A | Page 4 of 36  
 
AD5750/AD5750-1  
Parameter1  
Offset Error TC3  
Min  
Typ  
0.3  
2
Max  
Unit  
Test Conditions/Comments  
−2.2  
+2.2  
mV  
ppm FSR/°C  
% FSR  
TA = 25°C, 0 V to 5 V range  
All unipolar ranges  
All bipolar/unipolar ranges  
TA = 25°C  
Gain Error  
−0.05  
−0.04  
+0.05  
+0.04  
0.015  
% FSR  
Gain Error TC3  
Full-Scale Error  
0.5  
ppm FSR/°C  
% FSR  
% FSR  
−0.05  
−0.04  
+0.05  
+0.04  
All bipolar/unipolar ranges  
TA = 25°C  
0.015  
1.5  
Full-Scale Error TC3  
VOLTAGE OUTPUT CHARACTERISTICS3  
Headroom  
Short-Circuit Current  
Load  
ppm FSR/°C  
1.3  
V
mA  
kΩ  
Output unloaded  
TA = 25°C  
15  
1
Capacitive Load Stability  
RLOAD = ∞  
1
1
2
nF  
nF  
μF  
RLOAD = 2 kΩ  
RLOAD = ∞  
External compensation capacitor  
required; see the Driving Inductive  
Loads section  
DC Output Impedance  
0 V to 5 V range, ¼ to ¾ Step  
0 V to 5 V range, 40 mV Input Step  
Slew Rate  
0.12  
7
4.5  
2
2.5  
45.5  
165  
Ω
μs  
μs  
V/μs  
μV rms  
μV rms  
nV/√Hz  
Specified with 2 kΩ || 220 pF, 0.05%  
Specified with 2 kΩ || 220 pF, 0.05%  
Specified with 2 kΩ || 220 pF  
0.1 Hz to 10 Hz bandwidth  
100 kHz bandwidth  
Measured at 10 kHz; specified with  
2 kΩ || 220 pF  
Output Noise  
Output Noise Spectral Density  
AC PSRR  
−65  
10  
dB  
200 mV, 50 Hz/60 Hz sine wave  
superimposed on power supply  
voltage  
DC PSRR  
μV/V  
Outputs unloaded  
CURRENT OUTPUT  
Output Current Ranges  
0
0
4
−20  
−24  
0
24  
20  
20  
+20  
+24  
24.5  
mA  
mA  
mA  
mA  
mA  
mA  
Output Current Overranges  
See the Detailed Description of  
Features section  
0
4
20.4  
20.4  
mA  
mA  
See the Detailed Description of  
Features section  
See the Detailed Description of  
Features section  
ACCURACY, INTERNAL RSET  
Total Unadjusted Error (TUE)  
B Version2  
−0.2  
−0.08  
−0.5  
+0.2  
+0.08  
+0.5  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
μA  
0.03  
TA = 25°C  
A Version2  
−0.3  
0.15  
0.01  
0.015  
+0.3  
TA = 25°C  
Unipolar ranges  
Bipolar ranges  
4 mA to 20 mA, 0 mA to 20 mA, 0 mA  
to 24 mA ranges  
Relative Accuracy (INL)  
Offset Error  
−0.02  
−0.03  
−16  
+0.02  
+0.03  
+16  
−10  
−50  
−26  
+5  
+8  
+10  
+50  
+26  
μA  
μA  
μA  
TA = 25°C  
20 mA, 24 mA ranges  
TA = 25°C  
Rev. A | Page 5 of 36  
AD5750/AD5750-1  
Parameter1  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
All ranges  
20 mA, 24 mA ranges  
TA = 25°C  
Offset Error TC3  
3
ppm FSR/°C  
μA  
μA  
ppm FSR/°C  
% FSR  
Bipolar Zero Error  
−35  
−24  
+35  
+24  
+15  
0.5  
Bipolar Zero TC3  
Gain Error  
−0.2  
+0.2  
4 mA to 20 mA, 0 mA to 20 mA, 0 mA  
to 24 mA ranges  
−0.25  
−0.03  
+0.25  
+0.03  
% FSR  
% FSR  
ppm FSR/°C  
% FSR  
20 mA, 24 mA ranges  
TA = 25°C  
All ranges  
0.006  
8
Gain TC3  
Full-Scale Error  
−0.2  
+0.2  
All ranges  
−0.125  
0.02  
4
+0.125  
% FSR  
ppm FSR/°C  
TA = 25°C  
All ranges  
Full-Scale TC3  
ACCURACY, EXTERNAL RSET  
Total Unadjusted Error (TUE)  
B Version2  
−0.1  
−0.08  
−0.3  
−0.1  
−0.02  
+0.1  
+0.08  
+0.3  
+0.1  
+0.02  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
0.03  
TA = 25°  
A Version2  
0.02  
0.01  
TA = 25°C  
Relative Accuracy (INL)  
4 mA to 20 mA, 0 mA to 20 mA, 0 mA  
to 24 mA ranges  
−0.03  
−14  
0.015  
+0.03  
+14  
% FSR  
μA  
20 mA, 24 mA ranges  
4 mA to 20 mA, 0 mA to 20 mA, 0 mA  
to 24 mA ranges  
Offset Error  
−11  
−20  
−15  
+5  
+11  
+20  
+15  
μA  
μA  
μA  
TA = 25°C  
20 mA, 24 mA ranges  
TA = 25°C  
All ranges  
All ranges  
+8  
2
Offset Error TC3  
Bipolar Zero Error  
ppm FSR/°C  
μA  
μA  
ppm FSR/°C  
% FSR  
% FSR  
ppm FSR/°C  
% FSR  
% FSR  
ppm FSR/°C  
−32  
−22  
+32  
+22  
+12  
0.5  
TA = 25°C  
Bipolar Zero TC3  
Gain Error  
−0.08  
−0.07  
+0.08  
+0.07  
All ranges  
TA = 25°C  
All ranges  
All ranges  
TA = 25°C  
All ranges  
0.02  
1
Gain TC  
Full-Scale Error  
−0.1  
−0.07  
+0.1  
+0.07  
0.02  
2
Full-Scale TC3  
CURRENT OUTPUT CHARACTERISTICS3  
Current Loop Compliance Voltage  
Resistive Load  
0
AVDD − 2.75  
See test conditions/comments  
column  
V
Chosen such that compliance is not  
exceeded  
Inductive Load  
See test conditions/comments  
column  
Needs appropriate capacitor at higher  
inductance values; see the Driving  
Inductive Loads section  
Settling Time  
4 mA to 20 mA, Full-Scale Step  
4 mA to 20 mA Range, 120 μA Step  
DC PSRR  
8.5  
1.2  
1
μs  
μs  
μA/V  
MΩ  
250 Ω load  
250 Ω load  
Output Impedance  
130  
VOUT/VSENSE− Error  
0.9994  
1.0006 Gain  
Error in VOUT voltage due to changes  
in VSENSE−; specified as gain, for  
example, if VSENSE− moves by 1 V,  
then VOUT moves by 0.9994 V  
Rev. A | Page 6 of 36  
AD5750/AD5750-1  
Parameter1  
Min  
2
Typ  
Max  
Unit  
Test Conditions/Comments  
DIGITAL INPUT  
JEDEC compliant  
Input High Voltage, VIH  
Input Low Voltage, VIL  
Input Current  
V
V
μA  
pF  
0.8  
+1  
−1  
Per pin  
Per pin  
Pin Capacitance  
5
DIGITAL OUTPUTS3  
FAULT, IFAULT, TEMP, VFAULT  
Output Low Voltage, VOL  
0.4  
V
V
V
10 kΩ pull-up resistor to DVCC  
@ 2.5 mA  
10 kΩ pull-up resistor to DVCC  
0.6  
Output High Voltage, VOH  
SDO  
3.6  
0.5  
Output Low Voltage, VOL  
Output High Voltage, VOH  
0.5  
V
V
Sinking 200 μA  
Sourcing 200 μA  
DVCC − 0.5 DVCC − 0.5  
High Impedance Output Capacitance  
High Impedance Leakage Current  
3
pF  
μA  
−1  
+1  
POWER REQUIREMENTS  
AVDD  
AVSS  
12  
−12  
24  
−24  
V
V
10%  
10%  
DVCC  
Input Voltage  
AIDD  
2.7  
4.4  
5.2  
5.2  
2.0  
2.5  
2.5  
0.3  
108  
5.5  
5.2  
6.2  
6.2  
2.5  
3
V
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mW  
Output unloaded, output disabled  
Current output enabled  
Voltage output enabled  
Output unloaded, output disabled  
Current output enabled  
Voltage output enabled  
AISS  
3
1
DICC  
VIH = DVCC, VIL = GND  
AVDD/AVSS = 24 V, outputs unloaded  
Power Dissipation  
1 Temperature range: −40°C to +105°C; typical at +25°C.  
2 Specification includes gain and offset errors over temperature, and drift after 1000 hours, TA = 125°C  
3 Guaranteed by characterization, but not production tested.  
Rev. A | Page 7 of 36  
AD5750/AD5750-1  
TIMING CHARACTERISTICS  
AVDD/AVSS = 12 V ( 10%) to 24 V ( 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ, CL = 200 pF, IOUT: RLOAD  
300 Ω. All specifications TMIN to TMAX, unless otherwise noted.  
=
Table 3.  
Parameter1, 2  
Limit at TMIN, TMAX  
Unit  
Description  
t1  
t2  
t3  
t4  
20  
8
8
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
μs max  
ns min  
ns max  
ns min  
SCLK cycle time  
SCLK high time  
SCLK low time  
5
SYNC falling edge to SCLK falling edge setup time  
16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC)  
Minimum SYNC high time (write mode)  
Data setup time  
t5  
10  
5
t6  
t7  
t8  
t9, t10  
t11  
t12  
t13  
5
5
1.5  
5
Data hold time  
CLEAR pulse low/high activation time  
Minimum SYNC high time (read mode)  
SCLK rising edge to SDO valid (SDO CL = 15 pF)  
RESET pulse low time  
40  
10  
1 Guaranteed by characterization, but not production tested.  
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.  
Rev. A | Page 8 of 36  
 
AD5750/AD5750-1  
Timing Diagrams  
t1  
SCLK  
1
2
16  
t3  
t2  
t6  
t4  
t5  
SYNC  
t8  
t7  
D15  
SDIN  
CLEAR  
VOUT  
D0  
t10  
t9  
RESET  
t13  
Figure 2. Write Mode Timing Diagram  
1
2
16  
SCLK  
SYNC  
t11  
A2  
A1  
A0  
t12  
R = 1  
0
X
X
X
X
X
X
X
X
X
X
X
SDIN  
SDO  
PEC  
OVER  
IOUT  
VOUT  
X
X
X
X
X
R3  
R2  
R1  
R0 CLRSEL OUTEN RSET  
ERROR TEMP FAULT FAULT  
Figure 3. Readback Mode Timing Diagram  
Rev. A | Page 9 of 36  
 
AD5750/AD5750-1  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted.  
Transient currents of up to 100 mA do not cause SCR latch-up.  
Table 4.  
Parameter  
AVDD to GND  
AVSS to GND  
AVDD to AVSS  
DVCC to GND  
VSENSE+ to GND  
VSENSE− to GND  
Digital Inputs to GND  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Rating  
−0.3 V to +30 V  
+0.3 V to −28 V  
−0.3 V to +58 V  
−0.3 V to +7 V  
AVSS to AVDD  
5.0 V  
ESD CAUTION  
−0.3 V to DVCC + 0.3 V or 7 V  
(whichever is less)  
Digital Outputs to GND  
−0.3 V to DVCC + 0.3 V or 7 V  
(whichever is less)  
VREF to GND  
VIN to GND  
VOUT, IOUT to GND  
Operating Temperature Range,  
Industrial  
−0.3 V to +7 V  
−0.3 V to +7 V  
AVSS to AVDD  
−40°C to +105°C  
Storage Temperature Range  
Junction Temperature (TJ max)  
32-Lead LFCSP Package  
θJA Thermal Impedance  
Lead Temperature  
−65°C to +150°C  
125°C  
28°C/W  
JEDEC industry standard  
Soldering  
ESD (Human Body Model)  
J-STD-020  
3 kV  
Rev. A | Page 10 of 36  
 
AD5750/AD5750-1  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
PIN 1  
INDICATOR  
SDO/VFAULT 1  
CLRSEL 2  
24 VSENSE+  
23 VOUT  
22 VSENSE–  
21 AVSS  
20 COMP1  
19 COMP2  
18 IOUT  
CLEAR 3  
AD5750/  
AD5750-1  
DVCC  
4
GND 5  
SYNC/RSET  
6
TOP VIEW  
(Not to Scale)  
SCLK/OUTEN 7  
SDIN/R0  
8
17 AVDD  
NOTES  
1. NC = NO CONNECT.  
2. THE EXPOSED PADDLE IS TIED TO AVSS.  
Figure 4. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
SDO/VFAULT  
Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in  
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin  
is a CMOS output.  
Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is  
asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to  
a pull-up resistor.  
2
3
CLRSEL  
CLEAR  
In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software  
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.  
Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the  
range selected (user-selectable). CLEAR is a logic OR with the internal clear bit.  
In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage  
channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details.  
4
5
6
DVCC  
GND  
SYNC/RSET  
Digital Power Supply.  
Ground Connection.  
Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data  
into the AD5750, also updating the output.  
Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current sense  
resistor is used.  
If RSET = 0, the external sense resistor is chosen.  
If RSET = 1, the internal sense Resistor is chosen.  
7
8
9
SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of  
SCLK. This pin operates at clock speeds up to 50 MHz.  
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.  
SDIN/R0  
AD2/R1  
Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.  
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output  
current/voltage range setting on the part.  
Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight  
devices to be addressed on one bus.  
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output  
current/voltage range setting on the part.  
10  
AD1/R2  
Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0, allows up to eight  
devices to be addressed on one bus.  
Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output  
current/voltage range setting on the part.  
Rev. A | Page 11 of 36  
 
AD5750/AD5750-1  
Pin No.  
Mnemonic  
Description  
11  
AD0/R3  
Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to eight  
devices to be addressed on one bus.  
Range Decode Bit (R3). In hardware mode, this pin, in conjunction with, R0, R1, and R2, selects the output  
current/voltage range setting on the part.  
12, 13  
REXT2, REXT1 A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to improve the  
IOUT temperature drift performance.  
14  
15  
16  
17  
VREF  
VIN  
GND  
AVDD  
IOUT  
Buffered Reference Input.  
Buffered Analog Input (0 V to 4.096 V).  
Ground Connection.  
Positive Analog Supply.  
Current Output.  
18  
19, 20  
COMP2,  
COMP1  
Optional Compensation Capacitor Connections for the Voltage Output Buffer. These are used to drive higher  
capacitive loads on the output. These pins also reduce overshoot on the output. Care should be taken when  
choosing the value of the capacitor connected between the COMP1 and COMP2 pins because it has a direct  
influence on the settling time of the output. See the Driving Large Capacitive Loads section for further details.  
21  
22  
AVSS  
VSENSE−  
Negative Analog Supply.  
Sense Connection for the Negative Voltage Output Load Connection. This pin must stay within 3.0 V of  
ground for correct operation.  
23  
24  
25, 26,  
27, 28  
VOUT  
VSENSE+  
NC  
Buffered Analog Output Voltage.  
Sense Connection for the Positive Voltage Output Load Connection.  
No Connect. Can be tied to GND.  
29  
HW SELECT  
This pin is used to configure the part to hardware or software mode.  
HW SELECT = 0 selects software control.  
HW SELECT = 1 selects hardware control.  
30  
31  
RESET  
Resets the part to its power-on state.  
FAULT/TEMP  
Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an open-  
circuit error, short-circuit error, overtemperature error, or PEC interface error is detected. This pin is an open-  
drain output and must be connected to a pull-up resistor.  
Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is asserted  
low when an overtemperature error is detected. This pin is an open-drain output and must be connected to a  
pull-up resistor.  
32  
NC/IFAULT  
No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND.  
Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is asserted  
low when an open-circuit error is detected. This pin is an open-drain output and must be connected to a pull-  
up resistor.  
33 (EPAD) Exposed  
paddle  
The exposed paddle is tied to AVSS.  
Rev. A | Page 12 of 36  
AD5750/AD5750-1  
TYPICAL PERFORMANCE CHARACTERISTICS  
VOLTAGE OUTPUT  
0.0020  
0.10  
0.08  
0.06  
0.04  
0.02  
0
AV  
= +24V  
DD  
AV = –24V  
SS  
0.0015  
0.0010  
0.0005  
0
–0.0005  
–0.0010  
–0.0015  
–0.0020  
–0.0025  
–0.0030  
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
+5V POSITIVE TUE, NO LOAD  
+10V POSITIVE TUE, NO LOAD  
±5V POSITIVE TUE, NO LOAD  
±10V POSITIVE TUE, NO LOAD  
+5V NEGATIVE TUE, NO LOAD  
+10V NEGATIVE TUE, NO LOAD  
±5V NEGATIVE TUE, NO LOAD  
±10V NEGATIVE TUE, NO LOAD  
+5V  
+10V  
±5V  
±10V  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
–40  
25  
105  
V
TEMPERATURE (°C)  
IN  
Figure 5. Integral Nonlinearity Error vs. VIN  
Figure 8. Total Unadjusted Error vs. Temperature  
0.005  
0.004  
0.003  
0.002  
0.001  
0
0.03  
0.02  
0.01  
0
AV  
= +24V  
+5V LINEARITY, NO LOAD  
DD  
AV = –24V  
+10V LINEARITY, NO LOAD  
±5V LINEARITY, NO LOAD  
±10V LINEARITY, NO LOAD  
SS  
–0.01  
–0.02  
–0.03  
–0.04  
–0.001  
–0.002  
–0.003  
–0.004  
–0.005  
+5V RANGE, FULL-SCALE ERROR  
+10V RANGE, FULL-SCALE ERROR  
±5V RANGE, FULL-SCALE ERROR  
±10V RANGE, FULL-SCALE ERROR  
–40  
25  
TEMPERATURE (°C)  
105  
–40  
25  
105  
TEMPERATURE (°C)  
Figure 6. Integral Nonlinearity Error vs. Temperature  
Figure 9. Full-Scale Error vs. Temperature  
0.006  
0.004  
0.002  
0
2.5  
2.0  
AV  
= +24V  
AV  
= +24V  
DD  
DD  
AV = –24V  
AV = –24V  
SS  
SS  
1.5  
1.0  
±10V ZERO ERROR  
0.5  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
+5V  
+10V  
±5V  
±10V  
±5V ZERO ERROR  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
–40  
25  
105  
V
TEMPERATURE (°C)  
IN  
Figure 10. Bipolar Zero Error vs. Temperature  
Figure 7. Total Unadjusted Error vs. VIN  
Rev. A | Page 13 of 36  
 
 
 
AD5750/AD5750-1  
0.020  
0.015  
0.010  
0.005  
0
0.10  
0.08  
0.06  
0.04  
0.02  
0
AV  
= +24V  
+5V POSITIVE TUE, NO LOAD  
+10V POSITIVE TUE, NO LOAD  
±5V POSITIVE TUE, NO LOAD  
±10V POSITIVE TUE, NO LOAD  
+5V NEGATIVE TUE, NO LOAD  
+10V NEGATIVE TUE, NO LOAD  
±5V NEGATIVE TUE, NO LOAD  
±10V NEGATIVE TUE, NO LOAD  
DD  
AV = –24V  
SS  
–0.005  
–0.010  
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–0.015  
+5V GAIN, NO LOAD  
+10V GAIN, NO LOAD  
–0.020  
±5V GAIN, NO LOAD  
±10V GAIN, NO LOAD  
–0.025  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
–40  
25  
105  
TEMPERATURE (°C)  
SUPPLY VOLTAGES (AV /AV  
)
SS  
DD  
Figure 14. Total Unadjusted Error vs. Supply Voltages  
Figure 11. Gain Error vs. Temperature  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
2.5  
2.0  
AV  
= +24V  
DD  
AV = –24V  
OUTPUT UNLOADED  
SS  
1.5  
1.0  
0.5  
±10V V  
HEADROOM, LOAD OFF  
DD  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
–3.0  
+5V RANGE  
+10V RANGE  
±5V RANGE  
±10V RANGE  
–40  
25  
TEMPERATURE (°C)  
105  
–40  
25  
105  
TEMPERATURE (°C)  
Figure 12. Zero-Scale Error (Offset Error) vs. Temperature  
Figure 15. AVDD Headroom, 10 V Range, Output Set to 10 V, Load Off  
0.003  
0.05  
+5V LINEARITY, NO LOAD  
+10V LINEARITY, NO LOAD  
±5V LINEARITY, NO LOAD  
±10V LINEARITY, NO LOAD  
+5V RANGE  
±10V RANGE  
0.04  
0.03  
0.002  
0.001  
0
0.02  
0.01  
0
–0.01  
–0.02  
–0.03  
–0.04  
–0.05  
–0.001  
–0.002  
–0.003  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
–15 –13 –11 –9 –7 –5 –3 –1  
1
3
5
7
9
11 13 15  
SUPPLY VOLTAGES (AV /AV  
)
SS  
SOURCE/SINK CURRENT (mA)  
DD  
Figure 16. Source and Sink Capability of Output Amplifier  
Figure 13. Integral Nonlinearity Error vs. Supply Voltage  
Rev. A | Page 14 of 36  
 
 
AD5750/AD5750-1  
12  
10  
8
1
6
4
2
2
0
–8  
B
CH1 5.00V CH2 20.0mV  
M1.0µs  
A CH1  
3.00V  
W
–3  
2
7
12  
17  
22  
27  
TIME (µs)  
Figure 17. Full-Scale Positive Step  
Figure 20. VOUT Enable Glitch, Load = 2 kΩ || 1 nF  
12  
10  
8
6
4
2
5µV/DIV  
1s/DIV  
0
–8  
–3  
2
7
12  
17  
22  
27  
TIME (µs)  
Figure 18. Full-Scale Negative Step  
Figure 21. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)  
40  
35  
30  
25  
20  
15  
10  
5
0
100µV/DIV  
1s/DIV  
–5  
–1.0  
–0.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
TIME (ms)  
Figure 19. VOUT vs. Time on Power-Up, Load = 2 kΩ || 200 pF  
Figure 22. Peak-to-Peak Noise (100 kHz Bandwidth)  
Rev. A | Page 15 of 36  
AD5750/AD5750-1  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
1.0  
0.8  
0.6  
0.4  
0.2  
0
V
DD  
V
OUT  
–0.2  
–1.5  
–1.0  
–0.5  
0
0.5  
1.0  
1.5  
2.0  
TIME (ms)  
Figure 23. VDD and VOUT vs. Time on Power-Up  
Rev. A | Page 16 of 36  
AD5750/AD5750-1  
CURRENT OUTPUT  
0.004  
0.010  
0.008  
0.006  
0.004  
0.002  
0
AV  
= +24V  
+4mA TO +20mA INTERNAL R  
LINEARITY  
DD  
AV = –24V  
SET  
SS  
0mA TO +20mA INTERNAL R  
0mA TO +24mA INTERNAL R  
LINEARITY  
LINEARITY  
SET  
SET  
0.002  
0
±20mA INTERNAL R  
±24mA INTERNAL R  
LINEARITY  
LINEARITY  
SET  
SET  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
+4mA TO +20mA  
0mA TO +20mA  
0mA TO +24mA  
±20mA  
±24mA  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
V
SUPPLY VOLTAGES (AV /AV  
DD  
)
IN  
SS  
Figure 24. Integral Nonlinearity Error vs. VIN, External RSET Resistor  
Figure 27. Integral Nonlinearity Error, Current Mode,  
Internal RSET Sense Resistor  
0.004  
0.010  
0.008  
0.006  
0.004  
0.002  
0
AV  
= +24V  
DD  
AV = –24V  
+4mA TO +20mA  
0mA TO +20mA  
0mA TO +24mA  
±20mA  
AV  
= +24V  
DD  
SS  
AV = –24V  
SS  
0.002  
0
±24mA  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
–0.012  
–0.002  
–0.004  
–0.006  
–0.008  
+4mA TO +20mA  
0mA TO +20mA  
0mA TO +24mA  
±20mA  
±24mA  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
V
IN  
V
IN  
Figure 25. Integral Nonlinearity Error vs. VIN, Internal RSET Resistor  
Figure 28. Total Unadjusted Error vs. VIN, External RSET Resistor  
0.010  
0.015  
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
LINEARITY  
SET  
+4mA TO +20mA  
0mA TO +20mA  
0mA TO +24mA  
±20mA  
AV  
= +24V  
DD  
LINEARITY  
LINEARITY  
0.008  
0.006  
0.004  
0.002  
0
SET  
AV = –24V  
SS  
0mA TO +24mA EXTERNAL R  
SET  
0.010  
0.005  
0
±20mA EXTERNAL R  
±24mA EXTERNAL R  
LINEARITY  
LINEARITY  
SET  
SET  
±24mA  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
–0.005  
–0.010  
–0.015  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
SUPPLY VOLTAGES (AV /AV  
DD  
)
SS  
V
IN  
Figure 26. Integral Nonlinearity Error, Current Mode,  
External RSET Sense Resistor  
Figure 29. Total Unadjusted Error vs. VIN, Internal RSET Resistor  
Rev. A | Page 17 of 36  
 
AD5750/AD5750-1  
0.10  
0.010  
0.008  
0.006  
0.004  
0.002  
0
+4mA TO +20mA EXTERNAL R  
POSITIVE TUE  
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
LINEARITY  
LINEARITY  
LINEARITY  
SET  
SET  
0mA TO +20mA EXTERNAL R  
0mA TO +24mA EXTERNAL R  
POSITIVE TUE  
POSITIVE TUE  
0.08  
0.06  
SET  
SET  
SET  
0mA TO +24mA EXTERNAL R  
SET  
±20mA EXTERNAL R  
±24mA EXTERNAL R  
LINEARITY  
LINEARITY  
SET  
SET  
±20mA EXTERNAL R  
±24mA EXTERNAL R  
POSITIVE TUE  
POSITIVE TUE  
SET  
SET  
0.04  
0.02  
0
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
NEGATIVE TUE  
NEGATIVE TUE  
NEGATIVE TUE  
SET  
SET  
0mA TO +24mA EXTERNAL R  
SET  
AV  
= +24V  
±20mA EXTERNAL R  
±24mA EXTERNAL R  
NEGATIVE TUE  
NEGATIVE TUE  
DD  
SET  
SET  
AV = –24V  
SS  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
–40  
25  
TEMPERATURE (°C)  
105  
SUPPLY VOLTAGES (AV /AV  
DD  
)
SS  
Figure 30. Total Unadjusted Error Current Mode, External RSET Sense Resistor  
Figure 33. INL vs. Temperature, External RSET Sense Resistor  
0.10  
0.10  
0.08  
0.06  
0.04  
0.02  
0
+4mA TO +20mA INTERNAL R  
0mA TO +20mA INTERNAL R  
POSITIVE TUE  
+4mA TO +20mA INTERNAL R  
0mA TO +20mA INTERNAL R  
POSITIVE TUE  
SET  
SET  
POSITIVE TUE  
POSITIVE TUE  
POSITIVE TUE  
0.08  
0.06  
SET  
SET  
0mA TO +24mA INTERNAL R  
POSITIVE TUE  
0mA TO +24mA INTERNAL R  
SET  
SET  
±20mA INTERNAL R  
±24mA INTERNAL R  
POSITIVE TUE  
SET  
SET  
±20mA INTERNAL R  
±24mA INTERNAL R  
POSITIVE TUE  
POSITIVE TUE  
SET  
SET  
POSITIVE TUE  
0.04  
0.02  
0
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
+4mA TO +20mA INTERNAL R  
0mA TO +20mA INTERNAL R  
NEGATIVE TUE  
NEGATIVE TUE  
NEGATIVE TUE  
SET  
+4mA TO +20mA INTERNAL R  
0mA TO +20mA INTERNAL R  
NEGATIVE TUE  
SET  
SET  
NEGATIVE TUE  
0mA TO +24mA INTERNAL R  
SET  
SET  
0mA TO +24mA INTERNAL R  
NEGATIVE TUE  
SET  
±20mA INTERNAL R  
±24mA INTERNAL R  
NEGATIVE TUE  
NEGATIVE TUE  
SET  
SET  
±20mA INTERNAL R  
±24mA INTERNAL R  
NEGATIVE TUE  
SET  
SET  
NEGATIVE TUE  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
–40  
25  
105  
SUPPLY VOLTAGES (AV /AV  
DD  
)
SS  
TEMPERATURE (°C)  
Figure 31. Total Unadjusted Error Current Mode, Internal RSET Sense Resistor  
Figure 34. Total Unadjusted Error vs. Temperature, Internal RSET Sense Resistor  
0.10  
0.010  
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
POSITIVE TUE  
+4mA TO +20mA INTERNAL R  
0mA TO +20mA INTERNAL R  
LINEARITY  
LINEARITY  
LINEARITY  
SET  
SET  
POSITIVE TUE  
0.08  
0.06  
SET  
0.008  
0.006  
0.004  
0.002  
0
SET  
0mA TO +24mA EXTERNAL R  
POSITIVE TUE  
0mA TO +24mA INTERNAL R  
SET  
SET  
±20mA INTERNAL R  
±24mA INTERNAL R  
LINEARITY  
LINEARITY  
±20mA EXTERNAL R  
±24mA EXTERNAL R  
POSITIVE TUE  
SET  
SET  
SET  
SET  
POSITIVE TUE  
0.04  
0.02  
0
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
NEGATIVE TUE  
SET  
NEGATIVE TUE  
SET  
0mA TO +24mA EXTERNAL R  
NEGATIVE TUE  
SET  
AV  
= +24V  
±20mA EXTERNAL R  
±24mA EXTERNAL R  
NEGATIVE TUE  
DD  
SET  
SET  
AV = –24V  
NEGATIVE TUE  
SS  
–40  
25  
105  
–40  
25  
105  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 35. Total Unadjusted Error vs. Temperature, External RSET Sense Resistor  
Figure 32. INL vs. Temperature, Internal RSET Sense Resistor  
Rev. A | Page 18 of 36  
AD5750/AD5750-1  
6
4
2
1
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
AV  
= +24V  
SET  
SET  
DD  
AV = –24V  
SS  
0mA TO +24mA EXTERNAL R  
SET  
0
±20mA, INTERNAL R  
SET  
2
–1  
–2  
–3  
–4  
–5  
–6  
0
±24mA, INTERNAL R  
SET  
–2  
–4  
–6  
AV  
= +24V  
±20mA EXTERNAL R  
±24mA EXTERNAL R  
DD  
SET  
SET  
AV = –24V  
SS  
–40  
25  
105  
–40  
25  
TEMPERATURE (°C)  
105  
TEMPERATURE (°C)  
Figure 36. Zero-Scale Error vs. Temperature, External RSET Sense Resistor  
Figure 39. Bipolar Zero-Scale Error vs. Temperature,  
Internal RSET Sense Resistor  
25  
0.04  
0.03  
0.02  
0.01  
0
+4mA TO +20mA INTERNAL R  
SET  
+4mA TO +20mA EXTERNAL R  
SET  
0mA TO +20mA INTERNAL R  
0mA TO +24mA INTERNAL R  
SET  
SET  
0mA TO +20mA EXTERNAL R  
0mA TO +24mA EXTERNAL R  
SET  
SET  
20  
15  
AV  
= +24V  
DD  
AV = –24V  
10  
AV  
= +24V  
DD  
AV = –24V  
SS  
SS  
5
0
–0.01  
–0.02  
–0.03  
–0.04  
–5  
–10  
–15  
–20  
±20mA INTERNAL R  
±24mA INTERNAL R  
SET  
SET  
±20mA EXTERNAL R  
±24mA EXTERNAL R  
SET  
SET  
–40  
25  
105  
–40  
25  
105  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 37. Zero-Scale Error vs. Temperature, Internal RSET Sense Resistor  
Figure 40. Full-Scale Error vs. Temperature, External RSET Sense Resistor  
3
2
1
0.04  
+4mA TO +20mA INTERNAL R  
SET  
0mA TO +20mA INTERNAL R  
0mA TO +24mA INTERNAL R  
SET  
SET  
0.03  
0.02  
±20mA INTERNAL R  
±24mA INTERNAL R  
SET  
SET  
±24mA, EXTERNAL R  
SET  
0.01  
0
–1  
–2  
0
–0.01  
–0.02  
–0.03  
–0.04  
–0.05  
–0.06  
±20mA, EXTERNAL R  
= +24V  
SET  
–3  
–4  
–5  
AV  
AV  
= +24V  
DD  
DD  
AV = –24V  
AV = –24V  
SS  
SS  
–40  
25  
105  
–40  
25  
TEMPERATURE (°C)  
105  
TEMPERATURE (°C)  
Figure 38. Bipolar Zero-Scale Error vs. Temperature,  
External RSET Sense Resistor  
Figure 41. Full-Scale Error vs. Temperature, Internal RSET Sense Resistor  
Rev. A | Page 19 of 36  
AD5750/AD5750-1  
12  
10  
8
0.000010  
0.000008  
0.000006  
0.000004  
0.000002  
0
0.020  
0.015  
0.010  
0.005  
0
+4mA TO +20mA EXTERNAL R  
SET  
0mA TO +20mA EXTERNAL R  
0mA TO +24mA EXTERNAL R  
SET  
SET  
6
I
OUT  
4
–0.000002  
–0.000004  
–0.000006  
–0.000008  
–0.000010  
2
–0.005  
–0.010  
0
V
DD  
±20mA EXTERNAL R  
±24mA EXTERNAL R  
AV  
= +24V  
SET  
SET  
DD  
–2  
–10  
AV = –24V  
SS  
–0.015  
–8  
–6  
–4  
–2  
0
2
4
6
8
10  
–40  
25  
TEMPERATURE (°C)  
105  
TIME (ms)  
Figure 42. Gain Error vs. Temperature, External RSET Sense Resistor  
Figure 45. Output Current vs. Time on Power-Up  
0.08  
0
–2  
–4  
–6  
–8  
+4mA TO +20mA INTERNAL R  
SET  
0mA TO +20mA INTERNAL R  
0mA TO +24mA INTERNAL R  
SET  
SET  
0.06  
0.04  
±20mA INTERNAL R  
±24mA INTERNAL R  
SET  
SET  
0.02  
0
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–10  
–12  
–14  
–16  
–18  
AV  
= +24V  
DD  
AV = –24V  
SS  
–40  
25  
TEMPERATURE (°C)  
105  
–2  
–1  
0
1
2
3
4
5
6
7
8
TIME (µs)  
Figure 43. Gain Error vs. Temperature, Internal RSET Sense Resistor  
Figure 46. Output Current vs. Time on Output Enable  
1.4  
1.2  
0.025  
0.020  
0.015  
0.010  
0.005  
0
AV  
COMPLIANCE  
DD  
1.0  
0.8  
0.6  
0.4  
0.2  
0
AV COMPLIANCE  
SS  
–40  
25  
105  
–12 –6  
1
8
14 21 28 34 41 48 54 61 68  
TIME (µs)  
TEMPERATURE (°C)  
Figure 44. Output Compliance vs. Temperature  
Figure 47. 4 mA to 20 mA Output Current Step  
Tested When IOUT = 10.8 mA, 24 mA Range Selected  
Rev. A | Page 20 of 36  
AD5750/AD5750-1  
3000  
2500  
2000  
1500  
1000  
500  
6
5
AI  
DD  
4
3
DV  
= 5V  
CC  
2
1
0
–1  
–2  
–3  
DV  
= 3V  
CC  
AI  
SS  
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
LOGIC LEVEL (V)  
±10.8  
±15.0  
±24.0  
±26.4  
AV /AV (V)  
DD SS  
Figure 48. DICC vs. Logic Input Voltage  
Figure 50. AIDD/AISS vs. AVDD/AVSS, IOUT = 0 mA  
6
5
AI  
DD  
4
3
2
1
0
–1  
–2  
–3  
AI  
SS  
±10.8  
±15.0  
±24.0  
±26.4  
AV /AV (V)  
DD SS  
Figure 49. AIDD/AISS vs. AVDD/AVSS, VOUT = 0 V  
Rev. A | Page 21 of 36  
AD5750/AD5750-1  
TERMINOLOGY  
Total Unadjusted Error (TUE)  
Zero-Scale Error  
TUE is a measure of the output error taking all the various  
errors into account: INL error, offset error, gain error, and  
output drift over supplies, temperature, and time. TUE is  
expressed as a percentage of full-scale range (% FSR).  
Zero-scale error is the deviation of the actual zero-scale analog  
output from the ideal zero-scale output. Zero-scale error is  
expressed in millivolts (mV).  
Zero-Scale TC  
Relative Accuracy or Integral Nonlinearity (INL)  
INL is a measure of the maximum deviation, in % FSR, from a  
straight line passing through the endpoints of the output driver  
transfer function. A typical INL vs. input voltage plot can be  
seen in Figure 5.  
Zero-scale TC is a measure of the change in zero-scale error  
with a change in temperature. Zero-scale error TC is expressed  
in ppm FSR/°C.  
Offset Error  
Offset error is a measurement of the difference between the  
actual VOUT and the ideal VOUT, expressed in millivolts (mV)  
in the linear region of the transfer function. It can be negative  
or positive.  
Bipolar Zero Error  
Bipolar zero error is the deviation of the actual vs. ideal half-  
scale output of 0 V/0 mA with a bipolar range selected. A plot of  
bipolar zero error vs. temperature can be seen in Figure 10.  
Output Voltage Settling Time  
Bipolar Zero TC  
Output voltage settling time is the amount of time it takes for  
the output to settle to a specified level for a half-scale input change.  
Bipolar zero TC is a measure of the change in the bipolar  
zero error with a change in temperature. It is expressed in  
ppm FSR/°C.  
Slew Rate  
The slew rate of a device is a limitation in the rate of change of  
the output voltage. The output slewing speed is usually limited  
by the slew rate of the amplifier used at its output. Slew rate is  
measured from 10% to 90% of the output signal and is  
expressed in V/ꢀs.  
Full-Scale Error  
Full-scale error is the deviation of the actual full-scale analog  
output from the ideal full-scale output. Full-scale error is  
expressed as a percentage of full-scale range (% FSR).  
Full-Scale TC  
Current Loop Voltage Compliance  
Full-scale TC is a measure of the change in the full-scale error  
with a change in temperature. It is expressed in ppm FSR/°C.  
Current loop voltage compliance is the maximum voltage at  
the IOUT pin for which the output current is equal to the  
programmed value.  
Gain Error  
Gain error is a measure of the span error of the output. It is the  
deviation in slope of the output transfer characteristic from the  
ideal expressed in % FSR. A plot of gain error vs. temperature  
can be seen in Figure 11.  
Power-On Glitch Energy  
Power-on glitch energy is the impulse injected into the analog  
output when the AD5750/AD5750-1 are powered on. It is  
specified as the area of the glitch in nV-sec.  
Gain Error TC  
Power Supply Rejection Ratio (PSRR)  
PSRR indicates how the output is affected by changes in the  
power supply voltage.  
Gain error TC is a measure of the change in gain error  
with changes in temperature. Gain error TC is expressed in  
ppm FSR/°C.  
Rev. A | Page 22 of 36  
 
AD5750/AD5750-1  
THEORY OF OPERATION  
The AD5750/AD5750-1 are single-channel, precision voltage/  
current output drivers with hardware- or software-programmable  
output ranges. The software ranges are configured via an SPI-/  
MICROWIRE-compatible serial interface. The analog input to  
the AD5750/AD5750-1 is provided from a low voltage, single-  
supply digital-to-analog converter (DAC) and is internally  
conditioned to provide the desired output current/voltage range.  
Analog input ranges available are 0 V to 2.5 V (AD5750-1) or  
0 V to 4.096 V (AD5750).  
selected by programming the R3 to R0 bits in the control  
register (see Table 7 and Table 8).  
Figure 51 and Figure 52 show a typical configuration of the  
AD5750/AD5750-1 in software mode and in hardware mode,  
respectively, in an output module system. The HW SELECT pin  
selects whether the part is configured in software or hardware  
mode. The analog input to the AD5750/AD5750-1 is provided  
from a low voltage, single-supply DAC such as the AD506x or  
AD566x, which provides an output range of 0 V to 4.096 V. The  
supply and reference for the DAC, as well as the reference for the  
AD5750/AD5750-1, can be supplied from a reference such as the  
ADR392. The AD5750/AD5750-1 can operate from supplies up  
to 26.4 V.  
The output current range is programmable across five current  
ranges: 4 mA to 20 mA, 0 mA to 20 mA or 0 mA to 24 mA,  
20 mA, and 24 mA.  
The voltage output is provided from a separate pin that can be  
configured to provide 0 V to 5 V, 0 V to 10 V, 5 V, or 10 V  
output ranges. An overrange of 20% is available on the voltage  
ranges. An overrange of 2% is available on the 4 mA to 20 mA,  
0 mA to 20 mA, and 0 mA to 24 mA current ranges. The  
current and voltage outputs are available on separate pins. Only  
one output can be enabled at one time. The output range is  
SOFTWARE MODE  
In current mode, software-selectable output ranges include  
20 mA, 24 mA, 0 mA to 20 mA, 4 mA to 20 mA, and 0 mA  
to 24 mA.  
In voltage mode, software-selectable output ranges include 0 V  
to 5 V, 0 V to 10 V, 5 V, and 10 V.  
VDD AGND VSS  
ADP1720  
AVDD GND AVSS  
VSENSE+  
AD5750/AD5750-1  
VREF  
VSENSE–  
ADR392  
VDD REFIN  
VOUT  
RANGE  
SCALE  
SCLK  
SDI/DIN  
SDO  
VOUT  
0V TO +5V, 0V TO +10V,  
±5V, ±10V  
VIN  
AD506x  
AD566x  
MCU  
IOUT  
RANGE  
SCALE  
SYNC1  
IOUT  
0mA TO +20mA,  
0mA TO +24mA,  
+4mA TO +20mA,  
±20mA, ±24mA  
SCLK  
SDIN  
SDO  
VOUT SHORT FAULT  
IOUT OPEN FAULT  
OVERTEMP FAULT  
SERIAL  
INTERFACE  
SYNC  
STATUS REGISTER  
HW SELECT  
FAULT  
Figure 51. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs)  
Rev. A | Page 23 of 36  
 
 
AD5750/AD5750-1  
VDD AGND VSS  
AVDD GND AVSS  
ADP1720  
VSENSE+  
VSENSE–  
AD5750/AD5750-1  
VREF  
ADR392  
VDD  
REFIN  
VOUT  
RANGE  
SCALE  
SCLK  
SDI/DIN  
SDO  
VOUT  
0V TO +5V, 0V TO +10V,  
±5V, ±10V  
VIN  
AD506x  
AD566x  
MCU  
SYNC1  
IOUT  
RANGE  
SCALE  
IOUT  
0mA TO +20mA,  
0mA TO +24mA,  
+4mA TO +20mA,  
±20mA, ±24mA  
DVCC  
HW SELECT  
OUTEN  
R3  
R2  
R1  
OUTPUT RANGE  
SELECT PINS  
TEMP  
VFAULT  
IFAULT  
R0  
Figure 52. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs)  
Table 6. Suggested Parts for Use with AD5750 and AD5750-1  
DAC  
Reference  
Internal  
Internal  
Internal  
ADR434  
ADR434  
ADR3922  
ADR3922  
Power  
ADP17201  
N/A  
N/A  
ADP1720  
N/A  
ADR3922  
N/A  
Accuracy  
12-bit INL  
N/A  
N/A  
16-bit INL  
N/A  
Description  
AD5660  
AD5664R  
AD5668  
AD5060  
AD5064  
AD5662  
AD5664  
Mid end system, single channel, internal reference  
Mid end system, quad channel, internal reference  
Mid end system, octal channel, internal reference  
High end system, single channel, external reference  
High end system, quad channel, external reference  
Mid end system, single channel, external reference  
Mid end system, quad channel, external reference  
12-bit INL  
N/A  
1 ADP1720 input range up to 28 V.  
2 ADR392 input range up to 15 V.  
Rev. A | Page 24 of 36  
 
AD5750/AD5750-1  
The current and voltage are output on separate pins and cannot  
be output simultaneously. This allows the user to tie both the  
current and voltage output pins together and configure the end  
system as a single-channel output.  
CURRENT OUTPUT ARCHITECTURE  
The voltage input from the analog input VIN pin (0 V to 4.096 V  
for AD5750; 0 V to 2.5 V for the AD5750-1) is either converted  
to a current (see Figure 53), which is then mirrored to the  
supply rail so that the application simply sees a current source  
output with respect to an internal reference voltage, or it is  
buffered and scaled to output a software-selectable unipolar or  
bipolar voltage range (see Figure 54). The reference is used to  
provide internal offsets for range and gain scaling. The  
selectable output range is programmable through the digital  
interface.  
Driving Large Capacitive Loads  
The voltage output amplifier is capable of driving capacitive loads  
of up to 1 μF with the addition of a nonpolarized compensation  
capacitor between the COMP1 and COMP2 pins.  
Without the compensation capacitor, up to 20 nF capacitive loads  
can be driven. Care should be taken to choose an appropriate  
value for the CCOMP capacitor. This capacitor, while allowing the  
AD5750/AD5750-1 to drive higher capacitive loads and reduce  
overshoot, increases the settling time of the part and therefore  
affects the bandwidth of the system. Considered values of this  
capacitor should be in the range 100 pF to 4 nF, depending on  
the trade-off required between settling time, overshoot, and  
bandwidth.  
RANGE DECODE  
FROM INTERFACE  
R2  
R3  
V
DD  
IOUT  
RANGE  
SCALING  
VIN  
REXT1  
REXT2  
IOUT  
VREF  
R
V
SET  
Vx  
POWER-ON STATE OF AD±7±0/AD±7±0-1  
SS  
On power-up, the AD5750/AD5750-1 sense whether hardware  
or software mode is loaded and set the power-up conditions  
accordingly.  
R1  
R4  
IOUT  
OPEN FAULT  
In software SPI mode, the power-up state of the output is  
dependent on the state of the CLEAR pin. If the CLEAR pin is  
pulled high, then the part powers up, driving an active 0 V on  
the output. If the CLEAR pin is pulled low, then the part powers  
up with the voltage output channel in tristate mode. In both  
cases, the current output channel powers up in the tristate  
condition (0 mA). This allows the voltage and current outputs  
to be connected together if desired.  
Figure 53. Current Output Configuration  
RANGE DECODE  
FROM INTERFACE  
VSENSE+  
VOUT  
VIN  
(0V TO 4.096V)  
VOUT RANGE  
SCALING  
VREF  
VOUT  
SHORT FAULT  
VSENSE–  
Figure 54. Voltage Output  
To put the part into normal operation, the user must set the  
OUTEN bit in the control register to enable the output and, in  
the same write, set the output range configuration using the R3  
to R0 range bits. If the CLEAR pin is still high (active) during  
this write, the part automatically clears to its normal clear state  
as defined by the programmed range and by the CLRSEL pin or  
the CLRSEL bit (see the Asynchronous Clear (CLEAR) section  
for more details). The CLEAR pin must be taken low to operate  
the part in normal mode.  
DRIVING INDUCTIVE LOADS  
When driving inductive or poorly defined loads, connect a 0.01 μF  
capacitor between IOUT and GND. This ensures stability with  
loads beyond 50 mH. There is no maximum capacitance limit.  
The capacitive component of the load may cause slower settling.  
Voltage Output Amplifier  
The voltage output amplifier is capable of generating both  
unipolar and bipolar output voltages. It is capable of driving a  
load of 1 kΩ in parallel with 1.2 μF (with an external compensa-  
tion capacitor on the COMP1 and COMP2 pins). The source  
and sink capabilities of the output amplifier can be seen in  
Figure 16. The slew rate is 2 V/μs.  
The CLEAR pin is typically driven directly from a microcontroller.  
In cases where the power supply for the AD5750/AD5750-1  
supply may be independent of the microcontroller power supply,  
the user can connect a weak pull-up resistor to DVCC or a pull-  
down resistor to ground to ensure that the correct power-up  
condition is achieved independent of the microcontroller. A  
10 kΩ pull-up/pull-down resistor on the CLEAR pin should be  
sufficient for most applications.  
Internal to the device, there is a 2.5 MΩ resistor connected  
between the VOUT and VSENSE+ pins and similarly between  
the VSENSE− pin and the internal device ground. Should a  
fault condition occur, these resistors act to protect the AD5750/  
AD5750-1 by ensuring the amplifier loop is closed so that the  
part does not enter into an open-loop condition.  
If hardware mode is selected, the part powers up to the condi-  
tions defined by the R3 to R0 range bits and the status of the  
OUTEN or CLEAR pin. It is recommended to keep the output  
disabled when powering up the part in hardware mode.  
The VSENSE− pin can work in a common-mode range of 3 V  
with respect to the remote load ground point.  
Rev. A | Page 25 of 36  
 
 
 
 
 
AD5750/AD5750-1  
disabled, both the current and voltage channels go into tristate.  
The user must set the OUTEN bit to enable the output and  
simultaneously set the output range configuration.  
DEFAULT REGISTERS AT POWER-ON  
The AD5750/AD5750-1 power-on reset circuit ensures that all  
registers are loaded with zero code.  
In hardware mode, the output can be enabled or disabled using  
the OUTEN pin. When the output is disabled, both the current  
and voltage channels go into tristate. The user must write to the  
OUTEN pin to enable the output. It is recommended that the  
output be disabled when changing the ranges.  
In software SPI mode, the part powers up with all outputs  
disabled (OUTEN bit = 0). The user must set the OUTEN bit in  
the control register to enable the output and, in the same write,  
set the output range configuration using the R3 to R0 bits.  
If hardware mode is selected, the part powers up to the  
conditions defined by the R3 to R0 bits and the status of the  
OUTEN pin. It is recommended to keep the output disabled  
when powering up the part in hardware mode.  
SOFTWARE CONTROL  
Software control is enabled by connecting the HW SELECT  
pin to ground. In software mode, the AD5750/AD5750-1 are  
controlled over a versatile 3-wire serial interface that operates  
at clock rates up to 50 MHz. It is compatible with SPI, QSPI™,  
MICROWIRE, and DSP standards.  
RESET FUNCTION  
RESET  
In software mode, the part can be reset using the  
pin  
(active low) or the reset bit (reset = 1). A reset disables both the  
current and voltage outputs to their power-on condition. The  
user must write to the OUTEN bit to enable the output and, in  
Input Shift Register  
The input shift register is 16 bits wide. Data is loaded into the  
device MSB first as a 16-bit word under the control of a serial  
clock input, SCLK. Data is clocked in on the falling edge of  
SCLK. The input shift register consists of 16 control bits, as shown  
in Table 7. The timing diagram for this write operation is shown  
in Figure 2. The first three bits of the input shift register are used  
to set the hardware address of the AD5750/AD5750-1 device on  
the printed circuit board (PCB). Up to eight devices can be  
addressed per board.  
RESET  
the same write, set the output range configuration. The  
pin is a level-sensitive input; the part stays in reset mode as long  
RESET  
as the  
pin is low. The reset bit clears to 0 following a  
reset command to the control register.  
In hardware mode, there is no reset. If using the part in hardware  
RESET  
mode, the  
pin should be tied high.  
OUTEN  
Bit D11, Bit D1, and Bit D0 must always be set to 0 during any  
write sequence.  
In software mode, the output can be enabled or disabled using  
the OUTEN bit in the control register. When the output is  
Table 7. Input Shift Register Contents for a Write Operation—Control Register  
MSB  
LSB  
D0  
0
D1±  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D±  
D4  
D3  
D2  
D1  
A2  
A1  
A0  
R/W  
0
R3  
R2  
R1  
R0  
CLRSEL  
OUTEN  
Clear  
RSET  
Reset  
0
Table 8. Input Shift Register Descriptions  
Bit  
Description  
A2, A1, A0  
Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system  
controller.  
A2  
0
0
0
0
1
1
1
1
A1  
0
0
1
1
0
0
1
1
A0  
0
1
0
1
0
1
0
1
Function  
Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0.  
Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1.  
Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0.  
Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1.  
Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0.  
Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1.  
Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0.  
Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1.  
R/W  
Indicates a read from or a write to the addressed register.  
Rev. A | Page 26 of 36  
 
 
 
AD5750/AD5750-1  
Bit  
Description  
R3, R2, R1, R0  
Selects the output configuration in conjunction with RSET.  
RSET R3  
R2  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R1  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output Configuration  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4 mA to 20 mA (external 15 kΩ current sense resistor).  
0 mA to 20 mA (external 15 kΩ current sense resistor).  
0 mA to 24 mA (external 15 kΩ current sense resistor).  
20 mA (external 15 kΩ current sense resistor).  
24 mA (external 15 kΩ current sense resistor).  
0 V to 5 V.  
0 V to 10 V.  
5 V.  
10 V.  
0 V to 6.0 V (20% overrange).  
0 V to 12.0 V (20% overrange).  
6.0 V (20% overrange).  
12.0 V (20% overrange).  
2.5 V.  
N/A; if selected, output drives between 0 V and −1 V.  
N/A; if selected, output drives between 0 V and −1 V.  
4 mA to 20 mA (internal current sense resistor).  
0 mA to 20 mA (internal current sense resistor).  
0 mA to 24 mA (internal current sense resistor).  
20 mA (internal current sense resistor).  
24 mA (internal current sense resistor).  
0 V to 5 V.  
0 V to 10 V.  
5 V.  
10 V.  
0 V to 6.0 V (20% overrange).  
0 V to 12.0 V (20% overrange).  
6.0 V (20% overrange).  
12.0 V (20% overrange).  
3.92 mA to 20.4 mA (internal current sense resistor).  
0 mA to 20.4 mA (internal current sense resistor).  
0 mA to 24.5 mA (internal current sense resistor).  
CLRSEL  
Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section.  
CLRSEL  
Function  
0
1
Clear to 0 V.  
Clear to midscale in unipolar mode; clear to zero scale in bipolar mode.  
OUTEN  
Clear  
Output enable bit. This bit must be set to 1 to enable the outputs.  
Software clear bit, active high.  
RSET  
Select internal/external current sense resistor.  
RSET  
Function  
1
0
Select internal current sense resistor; used with R3 to R0 bits to select range.  
Select external current sense resistor; used with R3 to R0 bits to select range.  
Reset  
Resets the part to its power-on state.  
Rev. A | Page 27 of 36  
AD5750/AD5750-1  
Readback Operation  
In hardware mode, there is no status register. The fault condi-  
tions (open circuit, short circuit, and overtemperature) are  
available on Pin IFAULT, Pin VFAULT, and Pin TEMP. If any  
one of these fault conditions are set, then a low is asserted on  
the specific fault pin. IFAULT, VFAULT, and TEMP are open-  
drain outputs and therefore can be connected together to allow  
the user to generate one interrupt to the system controller to  
communicate a fault. If hardwired in this way, it is not possible  
to isolate which fault occurred in the system.  
Readback mode is activated by selecting the correct device address  
(A2, A1, A0) and then setting the R/ bit to 1. By default, the  
SDO pin is disabled. After having addressed the AD5750/  
W
W
AD5750-1 for a read operation, setting R/ to 1 enables the  
SDO pin and SDO data is clocked out on the 5th rising edge of  
SCLK. After the data has been clocked out on SDO, a rising  
SYNC  
edge on  
disables (tristate) the SDO pin again. Status  
register data (see Table 9) and control register data are both  
available during the same read cycle.  
TRANSFER FUNCTION  
The AD5750/AD5750-1 consist of an internal signal  
The status bits comprise four read-only bits. They are used to  
notify the user of specific fault conditions that occur, such as  
an open circuit or short circuit on the output, overtemperature  
error, or an interface error. If any of these fault conditions occur,  
a hardware FAULT is also asserted low, which can be used as a  
hardware interrupt to the controller.  
conditioning block that maps the analog input voltage to a  
programmed output range. The available analog input ranges  
are 0 V to 4.096 V (AD5750) and 0 V to 2.5 V (AD5750-1).  
For all ranges, both current and voltage, the AD5750 and  
AD5750-1 implement a straight linear mapping function, where  
0 V maps to the lower end of the selected range and 4.096 V (or  
2.5 V for AD5750-1) maps to the upper end of the selected range.  
See the Detailed Description of Features section for a full  
explanation of fault conditions.  
HARDWARE CONTROL  
Hardware control is enabled by connecting the HW SELECT  
pin to DVCC. In this mode, the R3, R2, R1, and R0 pins in  
conjunction with the RSET pin are used to configure the output  
range, as per Table 8.  
Table 9. Input Shift Register Contents for a Read Operation—Status Register  
MSB  
LSB  
D0  
D1±  
D14 D13 D12 D11 D10 D9 D8 D7 D6  
A1 A0 R3 R2 R1 R0  
D±  
D4  
D3  
D2  
D1  
A2  
1
0
CLRSEL OUTEN RSET PEC error OVER TEMP IOUT fault VOUT fault  
Table 10. Status Bit Options  
Bit  
Description  
PEC Error  
OVER TEMP  
IOUT Fault  
VOUT Fault  
This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section.  
This bit is set if the AD5750/AD5750-1 core temperature exceeds approximately 150°C.  
This bit is set if there is an open circuit on the IOUT pin.  
This bit is set if there is a short circuit on the VOUT pin.  
Rev. A | Page 28 of 36  
 
 
AD5750/AD5750-1  
DETAILED DESCRIPTION OF FEATURES  
circuitry that develops the fault output avoids using a  
comparator with window limits because this requires an  
actual output error before the fault output becomes active.  
Instead, the signal is generated when the internal amplifier  
in the output stage has less than approximately 1 V of  
remaining drive capability. Thus, the fault output activates  
slightly before the compliance limit is reached. Because the  
comparison is made within the feedback loop of the output  
amplifier, the output accuracy is maintained by its open-  
loop gain, and an output error does not occur before the  
fault output becomes active. If this fault is detected, the  
IFAULT pin is forced low.  
A short is detected on the voltage output pin (VOUT). The  
short-circuit current is limited to 15 mA. If this fault is  
detected, the VFAULT pin is forced low.  
The core temperature of the AD5750/AD5750-1 exceeds  
approximately 150°C. If this fault is detected, the TEMP  
pin is forced low.  
OUTPUT FAULT ALERT—SOFTWARE MODE  
In software mode, the AD5750/AD5750-1 are equipped with  
one FAULT pin; this is an open-drain output allowing several  
AD5750/AD5750-1 devices to be connected together to one  
pull-up resistor for global fault detection. In software mode, the  
FAULT pin is forced active low by any one of the following fault  
scenarios:  
•
The voltage at IOUT attempts to rise above the compliance  
range due to an open-loop circuit or insufficient power  
supply voltage. The internal circuitry that develops the  
fault output avoids using a comparator with window limits  
because this requires an actual output error before the fault  
output becomes active. Instead, the signal is generated  
when the internal amplifier in the output stage has less  
than approximately 1 V of remaining drive capability.  
Thus, the fault output activates slightly before the com-  
pliance limit is reached. Because the comparison is made  
within the feedback loop of the output amplifier, the output  
accuracy is maintained by its open-loop gain, and an  
output error does not occur before the fault output  
becomes active.  
•
•
VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION  
Under normal operation, the voltage output sinks and sources  
up to 12 mA and maintains specified operation. The maximum  
current that the voltage output delivers is 15 mA; this is the  
short-circuit current.  
•
•
•
A short is detected on the voltage output pin (VOUT). The  
short-circuit current is limited to 15 mA.  
An interface error is detected due to packet error checking  
(PEC) failure. See the Packet Error Checking section.  
If the core temperature of the AD5750/AD5750-1 exceeds  
approximately 150°C.  
ASYNCHRONOUS CLEAR (CLEAR)  
CLEAR is an active high clear that allows the voltage output  
to be cleared to either zero-scale code or midscale code, and is  
user-selectable via the CLRSEL pin or the CLRSEL bit of the input  
shift register, as described in Table 8. (The clear select feature is  
a logical OR function of the CLRSEL pin and the CLRSEL bit).  
The current loop output clears to the bottom of its programmed  
range. When the CLEAR signal is returned low, the output returns  
to its programmed value or to a new programmed value. A clear  
operation can also be performed via the clear command in the  
control register.  
OUTPUT FAULT ALERT—HARDWARE MODE  
In hardware mode, the AD5750/AD5750-1 are equipped with  
three fault pins: VFAULT, IFAULT, and TEMP. These are open-  
drain outputs allowing several AD5750/AD5750-1 devices to  
be connected together to one pull-up resistor for global fault  
detection. In hardware control mode, these fault pins are forced  
active by any one of the following fault scenarios:  
•
An open circuit is detected. The voltage at IOUT attempts  
to rise above the compliance range, due to an open-loop  
circuit or insufficient power supply voltage. The internal  
Table 11. CLRSEL Options  
Output Clear Value  
Unipolar Output  
Voltage Range  
Bipolar Current  
Output Range  
CLRSEL  
Unipolar Current Output Range  
Bipolar Output Range  
0
0 V  
Zero scale; for example,  
Negative full scale  
Zero scale; for example,  
4 mA on the 4 mA to 20 mA range  
0 mA on the 0 mA to 20 mA range  
−24 mA on the 24 mA range  
1
Midscale  
Midscale; for example,  
0 V  
Midscale; for example,  
12 mA on the 4 mA to 20 mA range  
0 mA on the 24 mA range  
10 mA on the 0 mA to 20 mA range  
Rev. A | Page 29 of 36  
 
 
 
AD5750/AD5750-1  
PACKET ERROR CHECKING  
EXTERNAL CURRENT SETTING RESISTOR  
To verify that data has been received correctly in noisy environ-  
ments, the AD5750/AD5750-1 offer the option of error checking  
based on an 8-bit (CRC-8) cyclic redundancy check. The device  
controlling the AD5750/AD5750-1 should generate an 8-bit  
frame check sequence using the following polynomial:  
Referring to Figure 1, RSET is an internal sense resistor and is  
part of the voltage-to-current conversion circuitry. The nominal  
value of the internal current sense resistor is 15 kΩ. To allow for  
overrange capability in current mode, the user can also select  
the internal current sense resistor to be 14.7 kΩ, giving a  
nominal 2% overrange capability. This feature is available in the  
0 mA to 20 mA, 4 mA to 20 mA, and 20 mA current ranges.  
C(x) = x8 + x2 + x1 + 1  
This is added to the end of the data-word, and 24 data bits are  
The stability of the output current value over temperature is  
dependent on the stability of the value of RSET. As a method of  
improving the stability of the output current over temperature,  
an external low drift resistor can be connected to the REXT1  
and REXT2 pins of the AD5750/AD5750-1, which can be used  
instead of the internal resistor. The external resistor is selected  
via the input shift register. If the external resistor option is not  
used, the REXT1 and REXT2 pins should be left floating.  
SYNC  
sent to the AD5750/AD5750-1 before taking  
AD5750/AD5750-1 receive a 24-bit data frame, the parts  
SYNC  
high. If the  
perform the error check when  
goes high. If the check is  
valid, then the data is written to the selected register. If the error  
check fails, the FAULT pin goes low and Bit D3 of the status  
register is set. After reading this register, this error flag is  
cleared automatically and the FAULT pin goes high again.  
UPDATE ON SYNC HIGH  
SYNC  
PROGRAMMABLE OVERRANGE MODES  
The AD5750/AD5750-1 contain an overrange mode for most of  
the available ranges. The overranges are selected by configuring  
the R3, R1, R1, and R0 bits (or pins) accordingly.  
SCLK  
D15  
(MSB)  
D0  
(LSB)  
In voltage mode, the overranges are typically 20%, providing  
programmable output ranges of 0 V to 6 V, 0 V to 12 V, 6 V,  
and 12 V. The analog input remains the same.  
16-BIT DATA  
SDIN  
16-BIT DATA TRANSER—NO ERROR CHECKING  
In current mode, the overranges are typically 2%. In current  
mode, the overrange capability is only available on three ranges,  
0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. For these  
ranges, the analog input also remains the same (0 V to 4.096 V  
for the AD5750, 0 V to 2.5 V for the AD5750-1).  
UPDATE AFTER SYNC HIGH  
ONLY IF ERROR CHECK PASSED  
SYNC  
SCLK  
SDIN  
D23  
(MSB)  
D8  
(LSB)  
D7  
D0  
8-BIT FCS  
16-BIT DATA  
FAULT GOES LOW IF  
ERROR CHECK FAILS  
FAULT  
16-BIT DATA TRANSER WITH ERROR CHECKING  
Figure 55. PEC Error Checking Timing  
Rev. A | Page 30 of 36  
 
 
AD5750/AD5750-1  
APPLICATIONS INFORMATION  
TRANSIENT VOLTAGE PROTECTION  
LAYOUT GUIDELINES  
In any circuit where accuracy is important, careful consideration  
of the power supply and ground return layout helps to ensure the  
rated performance. The PCB on which the AD5750/AD5750-1  
are mounted should be designed so that the AD5750/AD5750-1  
lie on the analog plane.  
The AD5750/AD5750-1 contain ESD protection diodes that  
prevent damage from normal handling. The industrial control  
environment can, however, subject I/O circuits to much higher  
transients. To protect the AD5750/AD5750-1 from excessively  
high voltage transients, external power diodes and a surge  
current limiting resistor may be required, as shown in Figure 56.  
The constraint on the resistor value is that during normal opera-  
tion the output level at IOUT must remain within its voltage  
compliance limit of AVDD − 2.75 V and the two protection  
diodes and resistor must have appropriate power ratings.  
Further protection can be added with transient voltage  
suppressors if needed.  
The AD5750/AD5750-1 should have ample supply bypassing of  
10 μF in parallel with 0.1 μF on each supply located as close to  
the package as possible, ideally right up against the device. The  
10 μF capacitors are the tantalum bead type. The 0.1 μF capaci-  
tor should have low effective series resistance (ESR) and low  
effective series inductance (ESI) such as the common ceramic  
types, which provide a low impedance path to ground at high  
frequencies to handle transient currents due to internal logic  
switching.  
AVDD  
In systems where there are many devices on one board, it is often  
useful to provide some heat sinking capability to allow the power  
to dissipate easily.  
AVDD  
AD5750/AD5750-1  
R
P
IOUT  
R
LOAD  
AD5750/AD5750-1  
AVSS  
Figure 56. Output Transient Voltage Protection  
THERMAL CONSIDERATIONS  
It is important to understand the effects of power dissipation on  
the package and how it affects junction temperature. The internal  
junction temperature should not exceed 125°C. The AD5750/  
AD5750-1 are packaged in a 32-lead, 5 mm × 5 mm LFCSP  
package. The thermal impedance, θJA, is 28°C/W. It is important  
that the devices are not operated under conditions that cause  
the junction temperature to exceed its junction temperature.  
AVSS  
PLANE  
BOARD  
Figure 57. Paddle Connection to Board  
The AD5750/AD5750-1 have an exposed paddle beneath the  
device. Connect this paddle to the AVSS supply for the part. For  
optimum performance, special considerations should be used to  
design the motherboard and to mount the package. For enhanced  
thermal, electrical, and board level performance, the exposed  
paddle on the bottom of the package should be soldered to the  
corresponding thermal land paddle on the PCB. Thermal vias  
should be designed into the PCB land paddle area to further  
improve heat dissipation.  
Worst-case conditions occur when the AD5750/AD5750-1 are  
operated from the maximum AVDD (26.4 V) and driving the  
maximum current (24 mA) directly to ground. The quiescent  
current of the AD5750/AD5750-1 should also be taken into  
account, nominally ~4 mA.  
The following calculations estimate maximum power dissipa-  
tion under these worst-case conditions, and determine  
maximum ambient temperature based on this:  
Power Dissipation = 26.4 V × 28 mA = 0.7392 W  
Temp Increase = 28°C × 0.7392 W = 20.7°C  
The AVSS plane on the device can be increased (as shown in  
Figure 57) to provide a natural heat sinking effect.  
Maximum Ambient Temp = 125°C − 20.7°C = 104.3°C  
These figures assume proper layout and grounding techniques  
are followed to minimize power dissipation, as outlined in the  
Layout Guidelines section.  
Rev. A | Page 31 of 36  
 
 
 
 
AD5750/AD5750-1  
GALVANICALLY ISOLATED INTERFACE  
MICROPROCESSOR INTERFACING  
In many process control applications, it is necessary to provide  
an isolation barrier between the controller and the unit being  
controlled to protect and isolate the controlling circuitry from any  
hazardous common-mode voltages that may occur. The iCoupler®  
family of products from Analog Devices, Inc., provides voltage  
isolation in excess of 5.0 kV. The serial loading structure of the  
AD5750/AD5750-1 makes it ideal for isolated interfaces because  
the number of interface lines is kept to a minimum. Figure 58  
shows a 4-channel isolated interface using an ADuM1400. For  
further information, visit www.analog.com/icouplers.  
Microprocessor interfacing to the AD5750/AD5750-1 is via a  
serial bus that uses a protocol compatible with microcontrollers  
and DSP processors. The communication channel is a 3-wire  
(minimum) interface consisting of a clock signal, a data signal,  
SYNC  
and a  
signal. The AD5750/AD5750-1 require a 16-bit  
data-word with data valid on the falling edge of SCLK.  
CONTROLLER  
ADuM14001  
V
V
V
V
V
V
V
V
OA  
OB  
OC  
OD  
IA  
TO  
SERIAL  
SCLK  
CLOCK OUT  
IB  
IC  
ID  
TO  
SDIN  
SERIAL  
DATA OUT  
TO  
SYNC  
SYNC OUT  
TO  
CLEAR  
CONTROL OUT  
1
ADDITIONAL PINS OMITTED FOR CLARITY.  
Figure 58. Isolated Interface  
Rev. A | Page 32 of 36  
 
 
AD5750/AD5750-1  
OUTLINE DIMENSIONS  
5.00  
BSC SQ  
0.60 MAX  
0.60 MAX  
PIN 1  
INDICATOR  
25  
24  
32  
1
PIN 1  
INDICATOR  
0.50  
BSC  
TOP  
VIEW  
3.25  
3.10 SQ  
2.95  
EXPOSED  
PAD  
(BOTTOM VIEW)  
4.75  
BSC SQ  
0.50  
0.40  
0.30  
17  
16  
8
9
0.25 MIN  
0.80 MAX  
0.65 TYP  
3.50 REF  
12° MAX  
FOR PROPER CONNECTION OF  
THE EXPOSED PAD, REFER TO  
THE PIN CONFIGURATION AND  
FUNCTION DESCRIPTIONS  
0.05 MAX  
0.02 NOM  
1.00  
0.85  
0.80  
0.30  
0.23  
0.18  
COPLANARITY  
0.08  
0.20 REF  
SECTION OF THIS DATA SHEET.  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2  
Figure 59. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
5 mm × 5 mm Body, Very Thin Quad  
(CP-32-2)  
Dimensions shown in millimeters  
ORDERING GUIDE  
TUE  
Accuracy  
Analog Input  
Range  
External  
Reference  
Temperature  
Range  
Package  
Description  
Package  
Option  
Model  
AD5750ACPZ-REEL1  
AD5750ACPZ-REEL71  
AD5750BCPZ-REEL1  
AD5750BCPZ-REEL71  
AD5750-1ACPZ-REEL1  
AD5750-1ACPZ-REEL71  
AD5750-1BCPZ-REEL1  
AD5750-1BCPZ-REEL71  
0.3%  
0.3%  
0.1%  
0.1%  
0.3%  
0.3%  
0.1%  
0.1%  
0 V to 4.096 V  
0 V to 4.096 V  
0 V to 4.096 V  
0 V to 4.096 V  
0 V to 2.5 V  
0 V to 2.5 V  
0 V to 2.5 V  
0 V to 2.5 V  
4.096 V  
4.096 V  
4.096 V  
4.096 V  
1.25 V  
1.25 V  
1.25 V  
1.25 V  
−40°C to +105°C  
−40°C to +105°C  
−40°C to +105°C  
−40°C to +105°C  
−40°C to +105°C  
−40°C to +105°C  
−40°C to +105°C  
−40°C to +105°C  
32-Lead LFCSP_VQ CP-32-2  
32-Lead LFCSP_VQ CP-32-2  
32-Lead LFCSP_VQ CP-32-2  
32-Lead LFCSP_VQ CP-32-2  
32-Lead LFCSP_VQ CP-32-2  
32-Lead LFCSP_VQ CP-32-2  
32-Lead LFCSP_VQ CP-32-2  
32-Lead LFCSP_VQ CP-32-2  
1 Z = RoHS Compliant Part.  
Rev. A | Page 33 of 36  
 
AD5750/AD5750-1  
NOTES  
Rev. A | Page 34 of 36  
AD5750/AD5750-1  
NOTES  
Rev. A | Page 35 of 36  
AD5750/AD5750-1  
NOTES  
©2009 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D07268-0-8/09(A)  
Rev. A | Page 36 of 36  

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VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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