AD5760SDZ [ADI]
Voltage Output DAC;
| 型号： | AD5760SDZ |
| 厂家： | 
ADI |
| 描述： | Voltage Output DAC |
| 文件： | 总27页 (文件大小：595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Stable, 16-Bit 0.5 LSB INL,
Voltage Output DAC
Data Sheet
AD5760
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
V
REFP
CC
DD
True 16-bit voltage output DAC, 0.5 LSB INL
8 nV/√Hz output noise spectral density
0.00625 LSB long-term linearity error stability
0.018 ppm/°C gain error temperature coefficient
2.5 µs output voltage settling time
6.8kΩ 6.8kΩ
R1
A1
R
IOV
CC
FB
R
FB
INV
SDIN
SCLK
SYNC
SDO
INPUT
SHIFT
16
16
16-BIT
DAC
DAC
REG
V
OUT
REGISTER
AND
3.5 nV-sec midscale glitch impulse
CONTROL
LOGIC
Integrated precision reference buffers
Operating temperature range: −40°C to +125°C
4 mm × 5 mm LFCSP package
Wide power supply range of up to 16.5 V
35 MHz Schmitt triggered digital interface
1.8 V-compatible digital interface
6kΩ
LDAC
CLR
POWER-ON RESET
AND CLEAR LOGIC
RESET
AD5760
DGND
V
AGND
V
REFN
SS
Figure 1.
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
Table 1. Related Devices
Part No.
Description
AD5790
AD5791
AD5780
AD5781
20-bit, 2 LSB accurate DAC
20-bit, 1 LSB accurate DAC
18-bit, 1 LSB accurate DAC
18-bit, 0.5 LSB INL
AD5541A/AD5542A
16-bit, 1 LSB accurate 5 V DAC
GENERAL DESCRIPTION
The AD57601 is a true 16-bit, unbuffered voltage output digital-
to-analog converter (DAC) that operates from a bipolar supply
of up to 33 V. The AD5760 accepts a positive reference input
range of 5 V to VDD − 2.5 Vand a negative reference input range
of VSS + 2.5 V to 0 V. The AD5760 offers a relative accuracy
specification of 0.5 LSB maximum range, and operation is
guaranteed monotonic with a 0.5 LSB differential nonlinearity
(DNL) maximum range specification.
PRODUCT HIGHLIGHTS
1. True 16-bit accuracy.
2. Wide power supply range of up to 16.5 V.
3. −40°C to +125°C operating temperature range.
4. Low 8 nV/√Hz noise.
5. Low 0.018 ppm/°C gain error temperature coefficient.
COMPANION PRODUCTS
Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1
External Reference: ADR445
The device uses a versatile 3-wire serial interface that operates
at clock rates of up to 35 MHz and is compatible with standard
serial peripheral interface (SPI), QSPI™, MICROWIRE™, and
DSP interface standards. The device incorporates a power-on
reset circuit that ensures that the DAC output powers up to 0 V
in a known output impedance state and remains in this state
until a valid write to the device takes place. The device provides
an output clamp feature that places the output in a defined load
state.
DC-to-DC Design Tool: ADIsimPower™
Additional companion products on the AD5780 product page.
1 Protected by U.S. Patent No. 7,884,747 and 8,089,380.
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5760
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Architecture....................................................................... 18
Serial Interface............................................................................ 18
Hardware Control Pins.............................................................. 19
On-Chip Registers...................................................................... 19
AD5760 Features ............................................................................ 23
Power-On to 0 V......................................................................... 23
Power-Up Sequence ................................................................... 23
Configuring the AD5760 .......................................................... 23
DAC Output State ...................................................................... 23
Output Amplifier Configuration.............................................. 23
Applications Information.............................................................. 25
Typical Operating Circuit ......................................................... 25
Evaluation Board........................................................................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Companion Products ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
REVISION HISTORY
4/2018—Rev. E to Rev. F
9/2012—Rev. B to Rev. C
Added Power-Up Sequence Section and Figure 50; Renumbered
Sequentially ..................................................................................... 23
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
Changes to Patent Footnote .............................................................1
Changes to Figure 46...................................................................... 17
Changes to Terminology Section ................................................. 19
Changes to Figure 53...................................................................... 25
Changes to Figure 55...................................................................... 27
Updated Outline Dimensions and changes to
10/2016—Rev. D to Rev. E
Changes to Figure 4 and Table 5..................................................... 8
Changes to Figure 42, Figure 43, and Figure 44 ......................... 15
Ordering Guide............................................................................... 29
2/2012—Rev. A to Rev. B
7/2013—Rev. C to Rev. D
Deleted Linearity Compensation Section ......................................3
Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5
Deleted Figure 4................................................................................ 7
Changes to Pin 11 Description ....................................................... 8
Deleted Daisy-Chain Operation Section..................................... 20
12/2011—Rev. 0 to Rev. A
Changes to Table 2.............................................................................3
Changes to Figure 48...................................................................... 18
Changes to DAC Register Section................................................ 22
Changes to Table 10 and Table 11 ................................................ 23
11/2011—Revision 0: Initial Version
Rev. F | Page 2 of 27
Data Sheet
AD5760
SPECIFICATIONS
VDD = +12.5 V to +16.5 V, VSS = −16.5 V to −12.5 V, V REFP = +1 0 V, V REFN = −10 V, VCC = 2.7 V to 5.5 V, IOV CC = 1.71 V to 5.5 V, s
RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted.
Table 2.
A, B Versions1
Parameter
STATIC PERFORMANCE2
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
Integral Nonlinearity Error (Relative
Accuracy)
16
−0.5
Bits
LSB
+0.5
B grade, VREFx
=
10 V, +10 V and +5 V
−2
−0.5
−1
+2
+0.5
+1
LSB
LSB
LSB
A grade, VREFx
B grade, VREFx
A grade, VREFx
=
=
=
10 V, +10 V and +5 V
10 V, +10 V and +5 V
10 V, +10 V and +5 V
Differential Nonlinearity Error
Long-Term Linearity Error Stability3
Full-Scale Error
0.00625
0.2
0.17
LSB
LSB
LSB
LSB
After 750 hours at TA = 135°C
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
−0.75
−1.4
−2.5
+0.75
+1.4
+2.5
0.1
VREFP = 5 V, VREFN = 0 V
Full-Scale Error Temperature
Coefficient
0.026
ppm/°C
VREFP = +10 V, VREFN = −10 V
Zero-Scale Error
−1.2
−2.5
−5.2
0.0812
0.044
0.056
0.025
+1.2
+2.5
+5.2
LSB
LSB
LSB
ppm/°C
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
Zero-Scale Error Temperature
Coefficient
VREFP = +10 V, VREFN = −10 V
Gain Error
−19
−35
−68
2.3
1.9
0.9
0.018
0.015
+19
+35
+68
ppm FSR
ppm FSR
ppm FSR
ppm/°C
%
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
Gain Error Temperature Coefficient
R1, RFB Matching
VREFP = +10 V, VREFN = −10 V
OUTPUT CHARACTERISTICS
Output Voltage Range
VREFN
VREFP
V
Output Voltage Settling Time
2.5
µs
10 V step to 0.02%, using the ADA4898-1
buffer in unity-gain mode
3.5
8
8
µs
125 code step to 1 LSB4
Output Noise Spectral Density
nV/√Hz
nV/√Hz
µV p-p
At 1 kHz, DAC code = midscale
At 10 kHz, DAC code = midscale
DAC code = midscale, 0.1 Hz to 10 Hz
bandwidth
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
Output Voltage Noise
1.1
Midscale Glitch Impulse4
14
3.5
4
14
3.5
4
57
0.27
3.4
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kΩ
VREFP = 5 V, VREFN = 0 V
MSB Segment Glitch Impulse4
VREFP = +10 V, VREFN = −10 V, see Figure 42
VREFP = 10 V, VREFN = 0 V, see Figure 43
VREFP = 5 V, VREFN = 0 V, see Figure 44
On removal of output ground clamp
Output Enabled Glitch Impulse
Digital Feedthrough
DC Output Impedance (Normal
Mode)
DC Output Impedance (Output
Clamped to Ground)
6
kΩ
Rev. F | Page 3 of 27
AD5760
Data Sheet
A, B Versions1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUTS
VREFP Input Range
VREFN Input Range
Input Bias Current
5
VDD − 2.5
0
+20
+4
V
V
nA
VSS + 2.5
−20
−4
−0.63
−0.63
1
TA = 0°C to 105°C
VREFP, VREFN
Input Capacitance
LOGIC INPUTS
Input Current5
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
pF
−1
+1
µA
V
V
0.3 × IOVCC
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V
0.7 × IOVCC
5
3
pF
LOGIC OUTPUT (SDO)
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output
Capacitance
0.4
1
V
V
µA
pF
IOVCC = 1.71 V to 5.5 V, sinking 1 mA
IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
IOVCC − 0.5
POWER REQUIREMENTS
All digital inputs at DGND or IOVCC
VDD
VSS
VCC
7.5
VDD − 33
2.7
VSS + 33
−2.5
5.5
V
V
V
IOVCC
1.71
5.5
V
IOVCC ≤ VCC
IDD
ISS
ICC
IOICC
10.3
−10
600
52
7.5
1.5
90
14
mA
mA
µA
µA
µV/V
µV/V
dB
dB
−14
900
140
SDO disabled
∆VDD 10%, VSS = −15 V
∆VSS 10%, VDD = 15 V
∆VDD 200 mV, 50 Hz/60 Hz, VSS = −15 V
∆VSS 200 mV, 50 Hz/60 Hz, VDD = 15 V
DC Power Supply Rejection Ratio
AC Power Supply Rejection Ratio
90
1 Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
2 Performance characterized with the AD8675ARZ output buffer.
3 Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified.
4 The AD5760 is configured in unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead
capacitance, and so forth).
5 Current flowing in an individual logic pin.
Rev. F | Page 4 of 27
Data Sheet
AD5760
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit1
Parameter
IOVCC = 1.71 V to 3.3 V
40
IOVCC = 3.3 V to 5.5 V Unit
28
Test Conditions/Comments
SCLK cycle time
2
t1
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns min
ns typ
ns min
92
15
9
60
10
5
SCLK cycle time (readback mode)
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge hold time
Minimum SYNC high time
t2
t3
t4
5
5
t5
2
2
t6
48
8
40
6
t7
SYNC rising edge to next SCLK falling edge ignore
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
t8
t9
9
7
7
12
13
20
14
130
130
50
140
0
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
10
16
11
130
130
50
140
0
LDAC falling edge to output response time
SYNC rising edge to output response time (LDAC tied low)
CLR pulse width low
CLR pulse activation time
SYNC falling edge to first SCLK rising edge
65
62
0
60
45
0
ns max SYNC rising edge to SDO tristate (CL = 50 pF)
ns max SCLK rising edge to SDO valid (CL = 50 pF)
ns min
ns typ
ns typ
SYNC rising edge to SCLK rising edge ignore
RESET pulse width low
35
150
35
150
RESET pulse activation time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode.
Rev. F | Page 5 of 27
AD5760
Data Sheet
t1
SCLK
1
2
24
t3
t2
t6
t4
t5
SYNC
SDIN
t9
t8
DB23
DB0
t12
t10
t11
LDAC
t13
V
OUT
OUT
t14
V
t15
CLR
t16
V
OUT
t21
RESET
t22
V
OUT
Figure 2. Write Mode Timing Diagram
t20
t1
t17
t7
SCLK
1
2
24
1
2
24
t3
t2
t6
t17
t5
t5
t4
SYNC
SDIN
t9
t8
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t18
t19
DB23
DB0
SDO
REGISTER CONTENTS CLOCKED OUT
Figure 3. Readback Mode Timing Diagram
Rev. F | Page 6 of 27
Data Sheet
AD5760
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4.
Parameter
VDD to AGND
VSS to AGND
VDD to VSS
VCC to DGND
IOVCC to DGND
Rating
−0.3 V to +34 V
−34 V to +0.3 V
−0.3 V to +34 V
−0.3 V to +7 V
−0.3 V to VCC + 3 V or +7 V
(whichever is less)
This device is a high performance integrated circuit with an
ESD rating of 1.6 kV, and it is ESD sensitive. Proper precautions
must be taken for handling and assembly.
Digital Inputs to DGND
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
ESD CAUTION
VOUT to AGND
VREFP to AGND
VREFN to AGND
DGND to AGND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VSS − 0.3 V to +0.3 V
−0.3 V to +0.3 V
Operating Temperature Range, TA
Industrial
Storage Temperature Range
Maximum Junction Temperature,
TJ max
−40°C to +125°C
−65°C to +150°C
150°C
Power Dissipation
LFCSP Package
(TJ max − TA)/θJA
θJA Thermal Impedance
Lead Temperature
Soldering
31.0°C/W
JEDEC industry standard
J-STD-020
ESD (Human Body Model)
1.6 kV
Rev. F | Page 7 of 27
AD5760
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
AGND
1
2
3
19
18
17
16
15
14
13
OUT
V
V
SS
REFP
V
V
DD
SS
AD5760
TOP VIEW
(Not to Scale)
V
RESET 4
V
REFN
5
6
DGND
SYNC
SCLK
DD
CLR
LDAC 7
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. NEGATIVE ANALOG SUPPLY CONNECTION (V ). A VOLTAGE
SS
IN THE RANGE OF −16.5V TO −2.5V CAN BE CONNECTED TO
THIS PIN. V MUST BE DECOUPLED TO AGND.
SS
3. EXPOSED PAD. THE EXPOSED PAD CAN BE LEFT
ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY
CONNECTION IS MADE AT THE VSS PINS. IT IS RECOMMENDED
THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A
COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3, 5
VOUT
VREFP
VDD
Analog Output Voltage.
Positive Reference Voltage Input. A voltage in the range of 5 V to VDD − 2.5 V can be connected to this pin.
Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected to this pin.
VDD must be decoupled to AGND.
4
6
RESET
CLR
Active Low Reset. Asserting this pin returns the AD5760 to its power-on status.
Active Low Input. Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates
the DAC output. The output value depends on the DAC register coding that is being used, either binary or
twos complement.
7
LDAC
Active Low Load DAC Logic Input. This pin is used to update the DAC register and, consequently, the analog
output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high
during the write cycle, the input register is updated, but the output update is held off until the falling edge
of LDAC. Do not leave the LDAC pin unconnected.
8
9
VCC
IOVCC
Digital Supply. Voltage range is from 2.7 V to 5.5 V. VCC should be decoupled to DGND.
Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage
range is from 1.71 V to 5.5 V.
10, 21, 22, 23
11
12
DNC
SDO
SDIN
Do Not Connect. Do not connect to these pins.
Serial Data Output. Data is clocked out on the rising edge of the serial clock input.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling
edge of the serial clock input.
13
14
SCLK
SYNC
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 35 MHz.
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges
of the following clocks. The DAC is updated on the rising edge of SYNC.
15
16
17, 18
DGND
VREFN
VSS
Ground Reference Pin for Digital Circuitry.
Negative Reference Voltage Input.
Negative Analog Supply Connection. A voltage in the range of −16.5 V to −2.5 V can be connected to this
pin. VSS must be decoupled to AGND.
19
20
24
AGND
RFB
INV
Ground Reference Pin for Analog Circuitry.
Feedback Connection for External Amplifier. See the AD5760 Features section for further details.
Inverting Input Connection for External Amplifier. See the AD5760 Features section for further details.
EPAD (VSS)
Exposed Pad. The exposed pad can be left electrically unconnected provided that a supply connection is
made at the VSS pins. It is recommended that the exposed pad be thermally connected to a copper plane for
enhanced thermal performance.
Rev. F | Page 8 of 27
Data Sheet
AD5760
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0.10
0.05
0
V
V
V
V
= +5V
= 0V
V
V
V
V
= +10V
= –10V
REFP
REFN
DD
SS
REFP
REFN
0.08
0.06
0.04
0.02
0
= +15V
= –15V
= +15V
= –15V
DD
SS
–0.05
–0.10
–0.15
–0.20
–0.02
–0.04
–0.06
–0.08
–0.10
AD8675 OUTPUT BUFFER
= 25°C
AD8675 OUTPUT BUFFER
T = 25°C
A
T
A
0
10000
20000
30000
40000
50000
60000
70000
0
10000
20000
30000
40000
50000
60000
70000
DAC CODE
DAC CODE
Figure 5. Integral Nonlinearity Error vs. DAC Code, 10 V Span
Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode
0.15
0.10
0.05
0
0.10
V
V
V
V
= +10V
= 0V
V
V
V
V
= +10V
= –10V
REFP
REFN
DD
SS
REFP
REFN
DD
SS
0.08
0.06
0.04
0.02
0
= +15V
= +15V
= –15V
= –15V
–0.02
–0.04
–0.06
–0.08
–0.10
–0.05
–0.10
AD8675 OUTPUT BUFFER
= 25°C
AD8675 OUTPUT BUFFER
T = 25°C
A
T
A
0
10000
20000
30000
40000
50000
60000
70000
0
10000
20000
30000
40000
50000
60000
70000
DAC CODE
DAC CODE
Figure 6. Integral Nonlinearity Error vs. DAC Code, 10 V Span
Figure 9. Differential Nonlinearity Error vs. DAC Code, 10 V Span
0.10
0.05
0
0.20
V
V
V
V
= +5V
= 0V
V
V
V
V
= +10V
= 0V
REFP
REFN
DD
SS
REFP
REFN
DD
SS
= +15V
= –15V
= +15V
0.15
0.10
0.05
0
= –15V
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
AD8675 OUTPUT BUFFER
= 25°C
AD8675 OUTPUT BUFFER
= 25°C
T
T
A
A
0
10000
20000
30000
40000
50000
60000
70000
0
10000
20000
30000
40000
50000
60000
70000
DAC CODE
DAC CODE
Figure 7. Integral Nonlinearity Error vs. DAC Code, 5 V Span
Figure 10. Differential Nonlinearity Error vs. DAC Code, 10 V Span
Rev. F | Page 9 of 27
AD5760
Data Sheet
0.10
0.08
0.06
0.04
0.02
0
0.09
0.07
0.05
0.03
0.01
–0.01
V
V
V
V
= +5V
= 0V
V
V
= +15V
= –15V
REFP
REFN
DD
SS
DD
SS
= +15V
= –15V
AD8675 OUTPUT BUFFER
±10V SPAN MAX INL
+10V SPAN MAX INL
+5V SPAN MAX INL
±10V SPAN MIN INL
+10V SPAN MIN INL
+5V SPAN MIN INL
–0.02
–0.04
–0.06
–0.08
–0.10
AD8675 OUTPUT BUFFER
= 25°C
T
A
–40
–20
0
20
40
60
80
100
0
10000
20000
30000
40000
50000
60000
70000
TEMPERATURE (°C)
DAC CODE
Figure 14. Differential Nonlinearity Error vs. Temperature
Figure 11. Differential Nonlinearity Error vs. DAC Code, 5 V Span
0.08
AD8675 OUTPUT BUFFER
0.09
INL MAX
T
= 25°C
A
0.06
0.04
0.07
0.05
0.02
T
V
V
= 25°C
A
0
0.03
= +10V
REFP
REFN
= –10V
–0.02
–0.04
–0.06
–0.08
–0.1.0
AD8675 OUTPUT BUFFER
0.01
–0.01
–0.03
–0.05
INL MIN
14.5
V
V
V
V
= +5V
= 0V
REFP
REFN
DD
SS
= +15V
= –15V
0
10000
20000
30000
40000
50000
60000
70000
12.5
13.0
13.5
14.0
15.0
15.5
16.0
16.5
V
/|V | (V)
DD SS
DAC CODE
Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span,
×2 Gain Mode
Figure 15. Integral Nonlinearity Error vs. Supply Voltage, 10 V Span
0.15
0.20
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
0.15
0.10
0.05
0
0.10
INL MAX
0.05
T
= 25°C
A
V
= 5V
0
–0.05
–0.10
–0.15
REFP
REFN
±10V SPAN MAX INL
+10V SPAN MAX INL
+5V SPAN MAX INL
±10V SPAN MIN INL
+10V SPAN MIN INL
+5V SPAN MIN INL
V
= 0V
AD8675 OUTPUT BUFFER
–0.05
–0.10
–0.15
INL MIN
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
DD SS
Figure 13. Integral Nonlinearity Error vs. Temperature
Figure 16. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span
Rev. F | Page 10 of 27
Data Sheet
AD5760
0.8
0.6
0.4
0.2
0
0.09
0.08
0.07
0.06
T
V
V
= 25°C
A
= 5V
= 0V
REFP
REFN
DNL MAX
AD8675 OUTPUT BUFFER
T
= 25°C
0.05
0.04
0.03
0.02
0.01
0
A
V
V
= +10V
REFP
REFN
= –10V
AD8675 OUTPUT BUFFER
–0.2
DNL MIN
14.5
–0.4
–0.01
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
12.5
13.0
13.5
14.0
15.0
15.5
16.0
16.5
V
DD SS
V
/|V | (V)
DD SS
Figure 17. Differential Nonlinearity Error vs. Supply Voltage, 10 V Span
Figure 20. Zero-Scale Error vs. Supply Voltage, 5 V Span
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
–0.11
–0.12
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
DNL MAX
T
= 25°C
A
V
= 5V
REFP
REFN
V
= 0V
AD8675 OUTPUT BUFFER
T
V
V
= 25°C
A
= +10V
REFP
DNL MIN
= –10V
REFN
AD8675 OUTPUT BUFFER
–0.01
12.5 13.0 13.5 14.0
14.5
15.0
15.5
16.0
16.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
V
/|V | (V)
DD SS
V
DD SS
Figure 18. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span
Figure 21. Midscale Error vs. Supply Voltage, 10 V Span
0.15
0.5
0.4
T
V
V
= 25°C
A
= +10V
REFP
= –10V
REFN
AD8675 OUTPUT BUFFER
0.10
0.05
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.05
T
= 25°C
A
V
V
= 5V
= 0V
REFP
REFN
AD8675 OUTPUT BUFFER
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
–0.10
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
V
/|V | (V)
V
DD SS
DD SS
Figure 19. Zero-Scale Error vs. Supply Voltage, 10 V Span
Figure 22. Midscale Error vs. Supply Voltage, 5 V Span
Rev. F | Page 11 of 27
AD5760
Data Sheet
0.14
0.38
0.36
0.34
0.32
0.30
0.28
0.26
T
A
= 25°C
= +10V
T
V
V
= 25°C
A
V
= 5V
REFP
REFP
= 0V
REFN
V
= –10V
0.12
0.10
0.08
0.06
0.04
0.02
0
REFN
AD8675 OUTPUT BUFFER
AD8675 OUTPUT BUFFER
12.5
13.
0
13.5
14.
0
V
14.5
15.
0
15.5
16.
0
16.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
/|V | (V)
DD SS
V
DD SS
Figure 23. Full-Scale Error vs. Supply Voltage, 10 V Span
Figure 26. Gain Error vs. Supply Voltage, 5 V Span
0.5
0.3
0.08
0.06
0.04
0.02
0
T
V
V
= 25°C
A
INL MAX
= 5V
= 0V
REFP
REFN
AD8675 OUTPUT BUFFER
0.1
T
= 25°C
= +15V
SS
A
DD
V
–0.1
–0.3
–0.5
–0.7
–0.9
V
= –15V
AD8675 OUTPUT BUFFER
–0.02
–0.04
–0.06
–0.08
–0.10
INL MIN
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
V
DD SS
V
| (V)
REFP
REFN
Figure 27. Integral Nonlinearity Error vs. Reference Voltage
Figure 24. Full-Scale Error vs. Supply Voltage, 5 V Span
0.10
0.08
0.06
0.04
0.02
0
0.08
T
= 25°C
A
V
= +10V
REFP
REFN
V
= –10V
INL MAX
AD8675 OUTPUT BUFFER
0.06
0.04
0.02
0
T
= 25°C
= +15V
SS
A
DD
V
V
= –15V
AD8675 OUTPUT BUFFER
–0.02
–0.04
–0.06
INL MIN
–0.02
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
12.5
13.0
13.5
14.0
V
14.5
15.0
15.5
16.0
16.5
/|V | (V)
DD SS
V
| (V)
REFP
REFN
Figure 28. Differential Nonlinearity Error vs. Reference Voltage
Figure 25. Gain Error vs. Supply Voltage, 10 V Span
Rev. F | Page 12 of 27
Data Sheet
AD5760
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
T
= 25°C
DD
SS
A
V
= +15V
= –15V
V
AD8675 OUTPUT BUFFER
5.0
5.5
6.0
6.5
V
7.0
7.5
| (V)
REFN
8.0
8.5
9.0
9.5 10.0
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
V
| (V)
REFP
REFN
/|V
REFP
Figure 32. Gain Error vs. Reference Voltage
Figure 29. Zero-Scale Error vs. Reference Voltage
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
–0.05
–0.07
–0.09
–0.11
–0.13
–0.15
–0.17
–0.19
–0.21
–0.23
–0.25
T
V
V
= 25°C
±10V SPAN
+10V SPAN
+5V SPAN
A
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
40 60 80 100
TEMPERATURE (°C)
–40
–20
0
20
5.0
5.5
6.0
6.5
V
7.0
7.5
| (V)
REFN
8.0
8.5
9.0
9.5 10.0
/|V
REFP
Figure 33. Full-Scale Error vs. Temperature
Figure 30. Midscale Error vs. Reference Voltage
0.15
0.10
0.40
0.38
0.36
0.34
0.32
0.3
±10V SPAN
T
= 25°C
A
V
V
+10V SPAN
+5V SPAN
= +15V
DD
SS
= –15V
AD8675 OUTPUT BUFFER
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
0.28
0.26
0.24
0.22
0.20
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
–40 –20 20
TEMPERATURE (°C)
0
40
60
80
100
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
V
| (V)
REFP
REFN
Figure 34. Midscale Error vs. Temperature
Figure 31. Full-Scale Error vs. Reference Voltage
Rev. F | Page 13 of 27
AD5760
Data Sheet
0.4
0.010
0.008
0.006
0.004
0.002
0
±10V SPAN
+10V SPAN
+5V SPAN
I
DD
0.2
0
–0.2
–0.4
–0.6
–0.002
–0.004
–0.006
–0.008
–0.010
I
SS
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
40 60 80 100
TEMPERATURE (°C)
–0.8
–40
–20
0
20
–20
–15
–10
–5
0
5
10
15
20
V
/V (V)
DD SS
Figure 35. Zero-Scale Error vs. Temperature
Figure 38. Power Supply Currents vs. Power Supply Voltages
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
6
4
2
0
±10V SPAN
+10V SPAN
+5V SPAN
V
V
V
V
= +15V
= –15V
REFP
REFN
DD
SS
= +10V
= –10V
–2
–4
ADA4808-1 BUFFERED
LOAD = 10MΩ | | 20pF
–6
V
V
= +15V
= –15V
DD
SS
–8
AD8675 OUTPUT BUFFER
–1.0
–40
–10
–1
–20
0
20
TEMPERATURE (°C)
40 60 80 100
0
1
2
3
4
5
TIME (µs)
Figure 39. Rising Full-Scale Voltage Step
Figure 36. Gain Error vs. Temperature
6
4
900
IOV = 5V, LOGIC VOLTAGE
CC
INCREASING
V
V
V
V
= +15V
= –15V
T
= 25°C
DD
SS
A
800
700
600
500
400
300
200
100
0
= +10V
IOV = 5V, LOGIC VOLTAGE
REFP
CC
= –10V
REFN
DECREASING
ADA4808-1 BUFFERED
LOAD = 10MΩ | | 20pF
IOV = 3V, LOGIC VOLTAGE
CC
2
INCREASING
IOV = 3V, LOGIC VOLTAGE
CC
0
DECREASING
–2
–4
–6
–8
–10
0
1
2
3
4
5
6
–1
0
1
2
3
4
5
LOGIC INPUT VOLTAGE (V)
TIME (µs)
Figure 40. Falling Full-Scale Voltage Step
Figure 37. IOICC vs. Logic Input Voltage
Rev. F | Page 14 of 27
Data Sheet
AD5760
10
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
V
= 5V
= 0V
NEGATIVE
POSITIVE
REFP
REFN
UNITY-GAIN MODE
ADA4898-1
RC LOW-PASS FILTER
V
V
= +10V
= –10V
REFP
REFN
RC LOW-PASS FILTER
UNITY-GAIN MODE
ADA4898-1
–1
0
1
2
3
4
5
TIME (µs)
CODE
Figure 41. 500 Code Step Settling Time
Figure 44. 6 MSB Segment Glitch Energy for 5 V VREF
55
25
20
15
10
5
±10V REF
10V REF
5V REF
V
V
= +10V
= –10V
NEGATIVE
POSITIVE
REFP
REFN
45
35
UNITY-GAIN MODE
ADA4898-1
RC LOW PASS FILTER
POSITIVE
CODE CHANGE
NEGATIVE
CODE CHANGE
25
15
5
–5
–15
–25
–1
0
0
1
2
3
TIME (µs)
CODE
Figure 45. Midscale Peak-to-Peak Glitch for 10 V
Figure 42. 6 MSB Segment Glitch Energy for 10 V VREF
800
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
= +15V
MIDSCALE CODE LOADED
OUTPUT UNBUFFERED
AD8676 REFERENCE BUFFERS
V
V
= 10V
= 0V
NEGATIVE
POSITIVE
A
REFP
REFN
V
V
V
V
DD
UNITY-GAIN MODE
= –15V
600
400
SS
ADA4898-1
= +10V
= –10V
REFP
REFN
RC LOW-PASS FILTER
200
0
–200
–400
–600
0
1
2
3
4
5
6
7
8
9
10
TIME (Seconds)
CODE
Figure 46. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth
Figure 43. 6 MSB Segment Glitch Energy for 10 V VRE
Rev. F | Page 15 of 27
AD5760
Data Sheet
100
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
V
V
V
V
= +15V
= –15V
REFP
REFN
V
= +15V
= –15V
REFP
DD
SS
DD
SS
V
V
V
= +10V
= –10V
= +10V
= –10V
REFN
UNITY GAIN
ADA4898-1
10
–0.02
1
0
1
2
3
4
5
6
0.1
1
10
100
1k
10k
TIME (µs)
FREQUENCY (Hz)
Figure 47. Noise Spectral Density vs. Frequency
Figure 48. Glitch Impulse on Removal of Output Clamp
Rev. F | Page 16 of 27
Data Sheet
AD5760
TERMINOLOGY
Relative Accuracy
Output Voltage Settling Time
Relative accuracy, or integral nonlinearity (INL), is a measure of
the maximum deviation, in LSB, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL error vs. code plot is shown in Figure 5.
Output voltage settling time is the amount of time it takes for
the output voltage to settle to a specified level for a specified
change in voltage. For fast settling applications, a high speed
buffer amplifier is required to buffer the load from the 3.4 kΩ
output impedance of the AD5760, in which case, it is the
amplifier that determines the settling time.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNL error vs. code plot is shown in Figure 9.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-sec and is
measured when the digital input code is changed by 1 LSB at
the major carry transition (see Figure 48).
Linearity Error Long-Term Stability
Linearity error long-term stability is a measure of the stability of
the linearity of the DAC over a long period of time. It is specified
in LSB for a time period of 500 hours and 1000 hours at an
elevated ambient temperature.
Output Enabled Glitch Impulse
Output enabled glitch impulse is the impulse injected into the
analog output when the clamp to ground on the DAC output is
removed. It is specified as the area of the glitch in nV-sec (see
Figure 48).
Zero-Scale Error
Zero-scale error is a measure of the output error when zero-scale
code (0x00000) is loaded to the DAC register. Ideally, the output
voltage should be VREFN. Zero-scale error is expressed in LSBs.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s, and vice versa.
Zero-Scale Error Temperature Coefficient
Zero-scale error temperature coefficient is a measure of the
change in zero-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Total Harmonic Distortion (THD)
Full-Scale Error
Total harmonic distortion is the ratio of the rms sum of the
harmonics of the DAC output to the fundamental value. Only
the second to fifth harmonics are included.
Full-scale error is a measure of the output error when full-scale
code (0x0FFFF) is loaded to the DAC register. Ideally, the
output voltage should be VREFP − 1 LSB. Full-scale error is
expressed in LSBs.
DC Power Supply Rejection Ratio.
DC power supply rejection ratio is a measure of the rejection of
the output voltage to dc changes in the power supplies applied
to the DAC. It is measured for a given dc change in power
supply voltage and is expressed in µV/V.
Full-Scale Error Temperature Coefficient
Full-scale error temperature coefficient is a measure of the
change in full-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
AC Power Supply Rejection Ratio (AC PSRR)
Gain Error
AC power supply rejection ratio is a measure of the rejection of
the output voltage to ac changes in the power supplies applied
to the DAC. It is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed in ppm of the full-scale range.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with a change in temperature. It is expressed in ppm
FSR/°C.
Midscale Error
Midscale error is a measure of the output error when midscale
code (0x08000) is loaded to the DAC register. Ideally, the output
voltage should be (VREFP – VREFN)/2 +VREFN. Midscale error is
expressed in LSBs.
Rev. F | Page 17 of 27
AD5760
Data Sheet
THEORY OF OPERATION
R
R
R
V
The AD5760 is a high accuracy, fast settling, single, 16-bit,
serial input, voltage output DAC. It operates from a VDD supply
voltage of 7.5 V to 16.5 V and a VSS supply of −16.5 V to −2.5 V.
Data is written to the AD5760 in a 24-bit word format via a 3-wire
serial interface. The AD5760 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
OUT
...
...
...
2R
2R
E0
2R
2R
S0
2R
S1
2R
S9
2R
...
E61
E62
V
REFP
V
REFN
VOUT pin clamped to AGND through a ~6 kΩ internal resistor.
10-BIT R-2R LADDER
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
DAC ARCHITECTURE
Figure 49. DAC Ladder Structure Serial Interface
The architecture of the AD5760 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 49.
The six MSBs of the 16-bit data-word are decoded to drive
63 switches, E0 to E62. Each of these switches connects one of
63 matched resistors to either the buffered VREFP or buffered
VREFN voltage. The remaining 10 bits of the data-word drive the
S0 to S9 switches of a 10-bit voltage mode R-2R ladder network.
SERIAL INTERFACE
The AD5760 has a 3-wire serial interface (
, SCLK, and
SYNC
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see Figure 2 for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
W
input register consists of a R/ bit, three address bits, and
20 data bits as shown in Table 6. The timing diagram for this
operation is shown in Figure 2.
Table 6. Input Shift Register Format
MSB
LSB
DB23
DB22
DB21
Register address
DB20
DB19 to DB0
R/W
Register data
Table 7. Decoding the Input Shift Register
R/W
X1
0
0
0
0
1
1
Register Address
Description
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No operation (NOP). Used in readback operations.
Write to the DAC register.
Write to the control register.
Write to the clearcode register.
Write to the software control register.
Read from the DAC register.
Read from the control register.
Read from the clearcode register.
1
1 X is don’t care.
Rev. F | Page 18 of 27
Data Sheet
AD5760
Standalone Operation
Synchronous DAC Update
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
LDAC
In this mode,
is held low while data is being clocked into
the input shift register. The DAC output is updated on the rising
SYNC
SYNC
only if
In gated clock mode, a burst clock containing the exact number
SYNC
is held low for the correct number of clock cycles.
edge of
Asynchronous DAC Update
LDAC
.
of clock cycles must be used, and
the final clock to latch the data. The first falling edge of
starts the write cycle. Exactly 24 falling clock edges must be applied
SYNC SYNC
is brought
must be taken high after
In this mode,
into the input shift register. The DAC output is asynchronously
LDAC SYNC
is held high while data is being clocked
SYNC
updated by taking
The update now occurs on the falling edge of
RESET
low after
has been taken high.
to SCLK before
is brought high again. If
LDAC
.
high before the 24th falling SCLK edge, the data written is invalid.
Reset Function (
The AD5760 can be reset to its power-on state by two means:
RESET
)
SYNC
If more than 24 falling SCLK edges are applied before
brought high, the input data is also invalid.
is
either by asserting the
in the software control register (see Table 13). If the
is not used, hardwire it to IOVCC
Asynchronous Clear Function (
pin or by using the reset function
SYNC
The input shift register is updated on the rising edge of
.
RESET
pin
SYNC
For another serial transfer to take place,
must be brought
.
low again. After the end of the serial data transfer, data is
automatically transferred from the input shift register to the
addressed register. When the write cycle is complete, the output
)
CLR
CLR
The
pin is an active low clear that allows the output to be
LDAC
SYNC
can be updated by taking
low while
is high.
cleared to a user defined value. The 16-bit clearcode value is
programmed to the clearcode register (see Table 12). It is
CLR
Readback
The contents of all the on-chip registers can be read back via the
SDO pin. Table 7 outlines how the registers are decoded. After a
register has been addressed for a read, the next 24 clock cycles
clock the data out on the SDO pin. The clocks must be applied
necessary to maintain
low for a minimum amount of time
CLR
to complete the operation (see Figure 2). When the
is returned high, the output remains at the clear value (if
signal
LDAC
is high) until a new value is loaded to the DAC register. The
CLR
SYNC
SYNC
while
is low. When
is returned high, the SDO pin
output cannot be updated with a new value while the
pin is
is placed in tristate. For a read of a single register, the NOP
function can be used to clock out the data. Alternatively, if more
than one register is to be read, the data of the first register to be
addressed can be clocked out at the same time that the second
register to be read is being addressed. The SDO pin must be
enabled to complete a readback operation. The SDO pin is
enabled by default.
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see Table 13).
ON-CHIP REGISTERS
DAC Register
Table 9 outlines how data is written to and read from the DAC
register.
HARDWARE CONTROL PINS
The following equation describes the ideal transfer function of
the DAC:
LDAC
Load DAC Function (
)
(
VREFP −VREFN × D
)
After data has been transferred into the input register of the
DAC, there are two ways to update the DAC register and DAC
VOUT
=
+VREFN
216
SYNC
LDAC
output. Depending on the status of both
and
, one
where:
of two update modes is selected: synchronous DAC update or
asynchronous DAC update.
V
REFN is the negative voltage applied at the VREFN input pin.
V
REFP is the positive voltage applied at the VREFP input pin.
D is the 16-bit code programmed to the DAC.
Rev. F | Page 19 of 27
AD5760
Data Sheet
Table 8. Hardware Control Pins Truth Table
LDAC
CLR
RESET
Function
X1
X1
0
0
1
X1
X1
0
1
0
1
0
1
0
0
The AD5760 is in reset mode. The device cannot be programmed.
The AD5760 is returned to its power-on state. All registers are set to their default values.
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The output remains at the clearcode register value.
The output remains set according to the DAC register value.
The output remains at the clearcode register value.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output remains at the clearcode register value.
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
The output is set according to the DAC register value.
1 X is don’t care.
Table 9. DAC Register
MSB
LSB
DB23
R/W
DB22
DB21
DB20
DB19 to DB4
DB3
DB2
DB1
DB0
Register address
0
DAC register data
16 bits of data
R/W
0
1
X1
X1
X1
X1
1 X is don’t care.
Rev. F | Page 20 of 27
Data Sheet
AD5760
Control Register
Clearcode Register
The clearcode register sets the value to which the DAC output is
set when the pin or CLR bit in the software control register
The control register controls the mode of operation of the
AD5760.
CLR
is asserted. The output value depends on the DAC coding that is
being used, either binary or twos complement. The default
register value is 0.
Table 10. Control Register
MSB
LSB
DB23 DB22 DB21 DB20 DB19 to DB11 DB10
DB9 DB8 DB7 DB6 DB5
Control register data
SDODIS BIN/2sC DACTRI OPGND RBUF Reserved
DB4
DB3
DB2
DB1
DB0
Register address
R/W
R/W
0
1
0
Reserved
Reserved
0000
Table 11. Control Register Functions
Bit Name
Reserved
RBUF
Description
These bits are reserved and should be programmed to zero.
Output amplifier configuration control.
0: the internal amplifier, A1, is powered up and Resistors RFB and R1 are connected in series, as shown in Figure 53. This allows
an external amplifier to be connected in a gain of two configuration. See the AD5760 Features section for further details.
1: (default) the internal amplifier, A1, is powered down and Resistors RFB and R1 are connected in parallel, as shown in
Figure 52, so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB
and INV pins to be used for input bias current compensation for an external unity-gain amplifier. See the AD5760 Features
section for further details.
OPGND
Output ground clamp control.
0: the DAC output clamp to ground is removed, and the DAC is placed in normal mode.
1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode.
Resetting the device puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated.
Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit.
DACTRI
BIN/2sC
SDODIS
DAC tristate control.
0: the DAC is in normal operating mode.
1: (default) the DAC is in tristate mode.
DAC register coding selection.
0: (default) the DAC register uses twos complement coding.
1: the DAC register uses offset binary coding.
SDO pin enable/disable control.
0: (default) the SDO pin is enabled.
1: the SDO pin is disabled (tristate).
Read/write select bit.
W
R/
0: AD5760 is addressed for a write operation.
1: AD5760 is addressed for a read operation.
Table 12. Clearcode Register
MSB
LSB
DB23
R/W
DB22
DB21
DB20
DB19 to DB4
DB3
DB2
DB1
DB0
Register address
1
Clearcode register data
16 bits of data
R/W
0
1
X1
X1
X1
X1
1 X is don’t care.
Rev. F | Page 21 of 27
AD5760
Data Sheet
Software Control Register
This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low.
Table 13. Software Control Register
MSB
LSB
DB23
R/W
0
DB22
DB21
DB20
DB19 to DB3
DB2
Software control register data
Reset
CLR1
DB1
DB0
Register address
0
1
0
Reserved
LDAC2
1
LDAC
CLR
The CLR function has no effect when the
The LDAC function has no effect when the
pin is low.
pin is low.
2
Table 14. Software Control Register Functions
Bit Name
Description
LDAC
Setting this bit to 1 updates the DAC register and, consequently, the DAC output.
CLR
Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output
value depends on the DAC register coding that is being used, either binary or twos complement.
Reset
Setting this bit to 1 returns the AD5760 to its power-on state.
Rev. F | Page 22 of 27
Data Sheet
AD5760
AD5760 FEATURES
POWER-ON TO 0 V
OUTPUT AMPLIFIER CONFIGURATION
The AD5760 contains a power-on reset circuit that, as well as
resetting all registers to their default values, controls the output
voltage during power-up. Upon power-on, the DAC is placed in
tristate (its reference inputs are disconnected), and its output is
clamped to AGND through a ~6 kΩ resistor. The DAC remains
in this state until programmed otherwise via the control register.
This is a useful feature in applications where it is important to
know the state of the DAC output while it is in the process of
powering up.
There are a number of different ways that an output amplifier
can be connected to the AD5760, depending on the voltage
references applied and the desired output voltage span.
Unity-Gain Configuration
Figure 51 shows an output amplifier configured for unity gain.
In this configuration, the output spans from VREFN to VREFP
.
V
REFP
6.8kΩ 6.8kΩ
R1
R
FB
A1
POWER-UP SEQUENCE
AD8675
ADA4898-1
ADA4004-1
R
FB
INV
OUT
To power up the device in a known safe state, power up the VDD
supply before powering up the VCC supply. This step ensures
that VCC does not come up while VDD is unpowered during
power-on. If the device cannot be powered-up in a safe state,
connect an external Schottky diode across the VDD and VCC
supplies as shown in Figure 50.
V
16-BIT
DAC
V
OUT
AD5760
V
REFN
V
V
CC
DD
Figure 51. Output Amplifier in Unity-Gain Configuration
A second unity-gain configuration for the output amplifier is
one that removes an offset from the input bias currents of the
amplifier. It does this by inserting a resistance in the feedback
path of the amplifier that is equal to the output resistance of the
DAC. The DAC output resistance is 3.4 kΩ. By connecting R1
and RFB in parallel, a resistance equal to the DAC resistance is
available on chip. Because the resistors are all on one piece of
silicon, they are temperature coefficient matched. To enable this
mode of operation, the RBUF bit of the control register must be
set to Logic 1. Figure 52 shows how the output amplifier is
connected to the AD5760. In this configuration, the output
amplifier is in unity gain, and the output spans from VREFN to
V
V
CC
DD
AD5760
Figure 50. Schottky Diode Connection
CONFIGURING THE AD5760
After power-on, the AD5760 must be configured to put it into
normal operating mode before programming the output. To
do this, the control register must be programmed. The DAC
is removed from tristate by clearing the DACTRI bit, and the
output clamp is removed by clearing the OPGND bit. At this
point, the output goes to VREFN unless an alternative value is
first programmed to the DAC register.
VREFP. This unity-gain configuration allows a capacitor to be
placed in the amplifier feedback path to improve dynamic
performance.
V
REFP
DAC OUTPUT STATE
R
FB
R
6.8kΩ
R1
6.8kΩ
The DAC output can be placed in one of three states, controlled
by the DACTRI and OPGND bits of the control register, as
shown in Table 15.
FB
10pF
INV
OUT
V
OUT
V
16-BIT
DAC
AD8675
ADA4898-1
ADA4004-1
Table 15. Output State Truth Table
DACTRI OPGND Output State
AD5760
0
0
1
1
0
1
0
1
Normal operating mode.
Output is clamped via ~6 kΩ to AGND.
Output is in tristate.
V
REFN
Figure 52. Output Amplifier in Unity-Gain with Amplifier Input Bias Current
Compensation
Output is clamped via ~6 kΩ to AGND.
Rev. F | Page 23 of 27
AD5760
Data Sheet
V
REFP
Gain of Two Configuration (×2 Gain Mode)
Figure 53 shows an output amplifier configured for a gain of
two. The gain is set by the internal matched 6.8 kΩ resistors,
which are exactly twice the DAC resistance, having the effect
of removing an offset from the input bias current of the external
6.8kΩ 6.8kΩ
R1
R
FB
A1
R
10pF
FB
INV
OUT
V
OUT
V
16-BIT
DAC
amplifier. In this configuration, the output spans from 2 × VREFN
−
AD8675
ADA4898-1
ADA4004-1
VREFP to VREFP. This configuration is used to generate a bipolar
output span from a single-ended reference input, with VREFN
0 V. For this mode of operation, the RBUF bit of the control
register must be cleared to Logic 0.
=
AD5760
V
REFN
Figure 53. Output Amplifier in Gain of Two Configuration
Rev. F | Page 24 of 27
Data Sheet
AD5760
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
Figure 54. Typical Operating Circuit
Rev. F | Page 25 of 27
AD5760
Data Sheet
Figure 54 shows a typical operating circuit for the AD5760
using an AD8675 as an output buffer. Because the output
impedance of the AD5760 is 3.4 kΩ, an output buffer is
required for driving low resistive, high capacitive loads.
to aid designers in evaluating the high performance of the device
with minimum effort. The evaluation kit includes a populated
and tested AD5780 printed circuit board (PCB). The evaluation
board interfaces to the USB port of a PC. Software is available
with the evaluation board to allow the user to easily program
the AD5780. The software runs on any PC that has Microsoft®
Windows® XP (SP2), Vista (32-bit or 64-bit), or Windows 7
installed. The UG-256 is available, which gives full details on
the operation of the evaluation board
EVALUATION BOARD
Refer to the evaluation board available for the AD5780 or
AD5790 to evaluate a 18-bit version or 20-bit version of the
AD5760. An evaluation board is available for the AD5780
Rev. F | Page 26 of 27
Data Sheet
AD5760
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
2.75
2.65
2.50
4.10
4.00
3.90
PIN 1
INDICATOR
PIN 1
INDIC
(SEE DETAIL A)
ATOR AREA OPTIONS
24
20
1
19
0.50
BSC
5.10
5.00
4.90
3.75
3.65
3.50
EXPOSED
PAD
13
7
12
8
0.50
0.40
0.30
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1.00
0.90
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.30
0.25
0.20
SECTION OF THIS DATA SHEET.
0.20 REF
Figure 55. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 5 mm Body and 0.90 mm Package Height
(CP-24-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
INL
0.5 LSB
0.5 LSB
2 LSB
Package Description
Package Option
CP-24-5
CP-24-5
CP-24-5
CP-24-5
AD5760BCPZ
AD5760BCPZ-REEL7
AD5760ACPZ
AD5760ACPZ-REEL7
EVAL-AD5760SDZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
2 LSB
1 Z = RoHS Compliant Part.
©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09650-0-4/18(F)
Rev. F | Page 27 of 27
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