AD5770RBCBZ-RL7 [ADI]
6-Channel, 14-Bit, Current Output DAC;
| 型号： | AD5770RBCBZ-RL7 |
| 厂家： | 
ADI |
| 描述： | 6-Channel, 14-Bit, Current Output DAC |
| 文件： | 总59页 (文件大小：2053K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6-Channel, 14-Bit, Current Output DAC
with On-Chip Reference, SPI Interface
Data Sheet
AD5770R
FEATURES
APPLICATIONS
6-channel, current output DAC
14-bit resolution
Programmable output current ranges
Photonics control
LED driver programmable current source
Current mode biasing
Channel 0: 0 mA to 300 mA, −60 mA to +300 mA, −60 mA
to 0 mA
Channel 1: 0 mA to 140 mA, 0 mA to 250 mA
Channel 2: 0 mA to 55 mA, 0 mA to 150 mA
Channel 3, Channel 4, Channel 5: 0 mA to 45 mA, 0 mA to
100 mA
All current sourcing output ranges scale back by up to 0.5×
1.25 V, on-chip voltage reference
Integrated precision reference resistor
SPI interface
GENERAL DESCRIPTION
The AD5770R is a 6-channel, 14-bit resolution, low noise,
programmable current output, digital-to-analog converter (DAC)
for photonics control applications. The device incorporates a
1.25 V, on-chip voltage reference, a 2.5 kΩ precision resistor for
reference current generation, die temperature, output monitoring
functions, fault alarm, and reset functions.
The AD5770R contains five 14-bit resolution current sourcing
DAC channels and one 14-bit resolution current sourcing and
sinking DAC channel.
Reset function
Output current monitor
Compliance voltage monitor
Die temperature monitor
Channel 0 can be configured to sink up to 60 mA and source up
to 300 mA. Channel 1 to Channel 5 have multiple programmable
output current sourcing ranges set by register access.
Integrated thermal shutdown
Each DAC operates with a wide power supply rail from 0.8 V to
AVDD − 0.4 V for optimizing power efficiency and thermal
power dissipation.
49-ball, 4 mm × 4 mm WLCSP package
Operating temperature: −40°C to +105°C
The AD5770R operates from a 2.9 V to 5.5 V AVDD supply and
is specified over the −40°C to +105°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
IOVDD
DVDD
AVDD
CREG
CDAMP_IDACx
PVDDx
AD5770R
CS
INPUT
DAC
REGISTER
DAC
DAC
IDAC0
IDAC1
REGISTER
SCLK
SDI
SDO
INPUT
REGISTER
DAC
REGISTER
INTERFACE
LOGIC
ALARM
LDAC
INPUT
REGISTER
DAC
REGISTER
DAC
IDAC5
RESET
1.25V
REFERENCE
VREF_IO
CREF
IREF
MUX_OUT
TEMPERATURE
SENSOR
2.5kΩ INTERNAL
RESISTOR
REFGND
AVEE
DGND
AGND
PVEE0
Figure 1.
Rev. 0
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Technical Support
©2019 Analog Devices, Inc. All rights reserved.
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AD5770R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Load DAC.................................................................................... 28
Input Page Mask Register.......................................................... 28
DAC Page Mask Register........................................................... 28
Output Stages.............................................................................. 28
Output Filter ............................................................................... 30
Output Current Scaling ............................................................. 30
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Performance Characteristics ................................................ 6
Timing Specifications .................................................................. 7
Timing Diagrams.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 24
Theory of Operation ...................................................................... 25
Digital to Analog Converter ..................................................... 25
Precision Reference Current Generation ................................ 25
Diagnostic Monitoring .............................................................. 25
Serial Interface ............................................................................ 26
Reset Function ............................................................................ 28
....................................................................................... 30
ALARM
Applications Information .............................................................. 33
Microprocessor Interfacing....................................................... 33
AD5770R to SPI interface ......................................................... 33
Thermal Considerations............................................................ 33
Combining Channels to Increase Current Range.................. 33
Layout Guidelines....................................................................... 33
Register Summary .......................................................................... 35
SPI Configuration Registers...................................................... 35
AD5770R Configuration Registers.......................................... 35
Register Details ............................................................................... 38
Outline Dimensions....................................................................... 59
Ordering Guide .......................................................................... 59
REVISION HISTORY
2/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 59
Data Sheet
AD5770R
SPECIFICATIONS
AVDD = DVDD = 2.9 V to 5.5 V, PVDD = 0.8 V to AVDD − 0.4 V, AVEE = −3.0 V to 0 V, 2.5 V ≤ PVDD − AVEE ≤ 5.5 V,
IOVDD = 1.65 V to 5.5 V, AVEE ≤ PVEE0 ≤ 0 V, AVDD − PVEE0 ≤ 5.5 V, VREF = 1.25 V external voltage reference, ambient
temperature (TA) = −40°C to +105°C, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
2
STATIC PERFORMANCE, EXTERNAL RSET
VREF = 1.25 V external voltage reference,
assumes ideal 2.5 kΩ external RSET resistor,
all channels and all output current ranges
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
14
−6.5
−1
Bits
LSB
LSB
+6.5
+1
TA = −20°C to +105°C, guaranteed
monotonic
−1
−1.3
+1.2
+1.3
LSB
% full-scale
range (FSR)
Guaranteed monotonic
Total Unadjusted Error
Zero-Scale Error
Zero-Scale Error Drift
+600
μA
All 0s loaded into the DAC register
Channel 0, Channel 1
Channel 2
500
300
170
nA/°C
nA/°C
nA/°C
μA
μA/°C
μA/°C
% FSR
ppm/°C
ppm/°C
% FSR
ppm/°C
ppm/°C
LSB
Channel 3, Channel 4, Channel 5
Offset Error
Offset Error Drift
−600
−1.3
−1.3
+600
+1.3
+1.3
1
0.5
Channel 0, Channel 1
Channel 2, Channel 3, Channel 4, Channel 5
All 1s loaded into the DAC register
Channel 0, Channel 1
Full-Scale Error
Full-Scale Error Drift
20
50
Channel 2, Channel 3, Channel 4, Channel 5
Gain Error
Gain Temperature Coefficient
30
80
2
Channel 0, Channel 1
Channel 2, Channel 3, Channel 4, Channel 5
TA = 25°C, due to full-scale change in output
current on a single adjacent channel
DC Crosstalk
DC Power Supply Rejection Ratio (PSRR)
STATIC PERFORMANCE, INTERNAL RSET
17
μA/V
TA = 25°C, DAC register loaded to full scale
VREF = 1.25 V internal voltage reference,
all channels and all output current ranges
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
14
−6.5
−1
Bits
LSB
LSB
+6.5
+1
TA = −20°C to +105°C, guaranteed
monotonic
−1
−1.3
+1.2
+1.3
+600
LSB
% FSR
μA
Guaranteed monotonic
Total Unadjusted Error (TUE)
Zero-Scale Error
Zero-Scale Error Drift
All 0s loaded into the DAC register
Channel 0, Channel 1
Channel 2
500
300
170
nA/°C
nA/°C
nA/°C
μA
μA/°C
μA/°C
% FSR
ppm/°C
ppm/°C
% FSR
ppm/°C
ppm/°C
Channel 3, Channel 4, Channel 5
Offset Error
Offset Error Drift
−600
−1.3
−1.3
+600
+1.3
+1.3
1
0.5
Channel 0, Channel 1
Channel 2, Channel 3, Channel 4, Channel 5
All 1s loaded into the DAC register
Channel 0, Channel 1
Full-Scale Error
Full-Scale Error Drift
20
50
Channel 2, Channel 3, Channel 4, Channel 5
Gain Error
Gain Temperature Coefficient
30
80
Channel 0, Channel 1
Channel 2, Channel 3, Channel 4, Channel 5
Rev. 0 | Page 3 of 59
AD5770R
Data Sheet
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DC Crosstalk
2
LSB
TA = 25°C, due to 200 mW change in
output power on a single channel
DC PSRR
17
μA/V
TA = 25°C, DAC register loaded to midscale
OUTPUT CHARACTERISTICS
Output Current Ranges
Channel 0
−60
−60
0
0
0
0
0
0
0
0
mA
mA
mA
mA
mA
mA
mA
mA
mA
+300
300
140
250
55
150
45
100
Channel 1
Channel 2
Channel 3, Channel 4, Channel 5
Output Compliance Voltage3
Channel 0
0
PVDD0 −
0.45
V
When sourcing in the 0 mA to 300 mA
range, DAC register is loaded to full scale
PVEE0 + 0.5
When sinking current on the −60 mA to
0 mA and the −60 mA to +300 mA ranges,
DAC register is loaded to zero scale
Channel 1
0
0
0
PVDD1 −
0.275
V
V
When configured to the 140 mA range
with low headroom, DAC register is
loaded to full scale
When configured to the 250 mA range or
to the 140 mA range with low noise, DAC
register is loaded to full scale
PVDD1 −
0.45
Channel 2, Channel 3, Channel 4,
Channel 5
PVDDx −
0.275
V
All output ranges, DAC register loaded to
full scale
DC Output Impedance
VOLTAGE REFERENCE INPUT
Reference Input Impedance
600
kΩ
TA = 25°C
60
115
1.25
GΩ
kΩ
V
TA = 25°C, external 1.25 V reference option
TA = 25°C, external 2.5 V reference option
For specified performance, external
1.25 V reference option
Reference Input Range
2.5
V
External 2.5 V reference option
VOLTAGE REFERENCE OUTPUT
Output Voltage
Reference Temperature Coefficient
Output Impedance
Output Current Load Capability
Maximum Capacitive Load
Load Regulation Sourcing
Load Regulation Sinking
Output Voltage Noise
1.245
1.25
15
0.01
5
1.255
V
TA = 25°C, reference output on
Internal RSET resistor
ppm/°C
Ω
mA
10
µF
250
250
920
70
70
35
µV/mA
µV/mA
nV rms
nV/√Hz
nV/√Hz
µV/V
TA = 25°C, 0.1 Hz to 10 Hz
TA = 25°C , 1 kHz
TA = 25°C, 10 kHz
Output Voltage Noise Spectral Density
Line Regulation
TA = 25°C, due to change in AVDD
INTEGRATED MULTIPLEXER
Buffer Output Current
Buffer Output Impedance
Buffer Offset
8
mA
Ω
mV
pF
0.5
0.3
100
Buffer Maximum Capacitive Load
Rev. 0 | Page 4 of 59
Data Sheet
AD5770R
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS
Input Current
CS, SCLK, SDI, LDAC, RESET
Per pin
−3.5
+3.5
μA
Input Voltage
Input Low Voltage (VINL
)
0.3 ×
V
IOVDD
Input High Voltage (VINH
)
0.7 ×
V
IOVDD
Pin Capacitance
LOGIC OUTPUTS
SDO Pin
4.5
pF
Per pin
Output Low Voltage (VOL)
Output High Voltage (VOH)
0.4
0.4
V
V
IOVDD −
0.4
Floating State Output Capacitance
ALARM Pin
Output Low Voltage (VOL)
4
pF
V
V
Open-drain enabled4, 10 kΩ pull-up
resistor to IOVDD
Open-drain enabled4, 10 kΩ pull-up
resistor to IOVDD
Output High Voltage (VOH)
IOVDD –
0.4
TEMPERATURE MEASUREMENT DIODE
Diode Output Voltage
700
880
1.04
−1.8
−1.3
−0.9
mV
mV
V
mV/°C
mV/°C
mV/°C
µA
TA = 25°C, internal bias current
TA = 25°C, 100 µA external bias current
TA = 25°C, 200 µA external bias current
Internal bias current
100 µA external bias current
200 µA external bias current
Temperature Coefficient
External Bias Current5
100
200
Temperature diode bias current is
supplied externally
THERMAL ALARMS
Overheat Warning Temperature
125
°C
Junction temperature, warning flag
activated
Overheat Shutdown Temperature
Overheat Warning Hysteresis
Overheat Shutdown Hysteresis
POWER REQUIREMENTS
Analog Power Supply Voltage
AVDD
150
4
20
°C
°C
°C
Junction temperature, thermal shutdown
2.9
−3.0
0.8
5.5
0
AVDD − 0.4
0
V
V
V
V
AVDD must be equal to DVDD
AVEE
PVDD0 to PVDD5
PVEE0
2.5 V ≤ PVDD − AVEE ≤ 5.5 V
AVDD − PVEE0 ≤ 5.5 V
AVEE
Analog Power Supply Current
AVDD Supply Current
AVEE Supply Current
PVDD0 to PVDD5 Supply Current
Digital Power Supply Voltage
DVDD
32
30
125
mA
µA
µA
Internal voltage reference option selected
All IDACx outputs disabled
2.9
1.65
5.5
5.5
V
V
AVDD must be equal to DVDD
IOVDD
Rev. 0 | Page 5 of 59
AD5770R
Data Sheet
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
Digital Power Supply Current
DVDD Supply Current
IODVDD Supply Current
Power Consumption
1.1
200
110
mA
nA
mW
All outputs at 0 A, nominal supplies
1 See the Terminology section.
2 See the Precision RSET Resistor section for more information about the internal and external RSET resistors
3 When sourcing current, the output compliance voltage is the maximum voltage at the IDACx pin, for which the output current is within 0.1% of the measured full-
scale range. When sinking current on Channel 0, the output compliance voltage is the minimum voltage at the IDAC0 pin, for which the output current is within 0.1%
of the measured zero-scale current.
4
ALARM
ALARM
section.
The active low
pin can be configured as an open drain. Refer to the
5 The internal temperature sensing diode can be biased with an internal or external current. Refer to the Internal Die Temperature Monitoring section.
AC PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 2.9 V to 5.5 V, PVDD = 0.8 V to AVDD − 0.4 V, AVEE = −3.0 V to 0 V, 2.5 V ≤ PVDD − AVEE ≤ 5.5 V,
IOVDD = 1.65 V to 5.5 V, AVEE ≤ PVEE0 ≤ 0 V, AVDD − PVEE0 ≤ 5.5 V, VREF = 1.25 V external voltage reference, TA = 25°C, unless
otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments2
DYNAMIC PERFORMANCE
Output Current Settling Time
13
10
µs
µs
Zero-scale to full-scale step settling to 4 LSB,
0 mA to 300 mA range
Zero-scale to full-scale step settling to 4 LSB,
0 mA to 45 mA range, Channel 3, Channel 4, and
Channel 5
Slew Rate
50
10
mA/µs
mA/µs
Channel 0 , 0 mA to 300 mA range
Channel 3, Channel 4, Channel 5, 0 mA to
45 mA range
Digital-to-Analog Glitch Impulse
Multiplexer Switching Glitch
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
0.057
14
0.03
0.03
0.8
nA-sec
pA-sec
nA-sec
nA-sec
nA-sec
1 LSB change around major carry
Switching monitored channel
Victim Channel 4, due to a 300 mA step change
on Channel 0
Output Noise Spectral Density (NSD)
35
18
19
13
nA/√Hz
nA/√Hz
nA/√Hz
nA/√Hz
Channel 0, 0 mA to 300 mA range, at 1 kHz, DAC
register loaded to midscale
Channel 1, 0 mA to 140 mA low noise range, at
1 kHz, DAC register loaded to midscale
Channel 2, 0 mA to 150 mA range, at 1 kHz, DAC
register loaded to midscale
Channel 3, Channel 4, Channel 5, 0 mA to
100 mA range, at 1 kHz, DAC register loaded to
midscale
16
9
nA/√Hz
nA/√Hz
nA/√Hz
nA/√Hz
Channel 0, 0 mA to 300 mA range, at 10 kHz,
DAC register loaded to midscale
Channel 1, 0 mA to 140 mA low noise range, at
10 kHz, DAC register loaded to midscale
Channel 2, 0 mA to 150 mA range, at 10 kHz,
DAC register loaded to midscale
Channel 3, Channel 4, Channel 5, 0 mA to
100 mA range, at 10 kHz, DAC register loaded to
midscale
9
6
Rev. 0 | Page 6 of 59
Data Sheet
AD5770R
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments2
Output Noise
900
nA rms
0.1 Hz to 10 Hz, Channel 0, 0 mA to 300 mA
range, DAC register loaded to full scale
180
400
300
nA rms
nA rms
nA rms
0.1 Hz to 10 Hz, Channel 1, 0 mA to 140 mA low
noise range, DAC register loaded to full scale
0.1 Hz to 10 Hz, Channel 2, 0 mA to 150 mA
range, DAC register loaded to full scale
0.1 Hz to 10 Hz, Channel 3, Channel 4, Channel 5,
0 mA to 100 mA range, DAC register loaded to
full scale
PVDDx AC PSRR
−98
−87
−67
−23
−8
dB
dB
dB
dB
dB
100 Hz
1 kHz
10 kHz
1000 kHz
3000 kHz
1 See the Terminology section.
2 Temperature range is −40°C to +105°C, typically at 25°C.
TIMING SPECIFICATIONS
Table 3.
Parameter
1.65 V ≤ IOVDD ≤ 5.5 V
Unit
Test Conditions/Comments
SCLK cycle time, write operation.
SCLK cycle time, read operation.
SCLK high time.
SCLK low time.
CS to SCLK rising edge setup time.
Data setup time.
t1
50
100
20
20
25
10
10
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
t2
t3
t4
t5
t6
t7
Data hold time.
SCLK rising edge to CS rising edge. LDAC idle high mode.
SCLK rising edge to CS rising edge. LDAC idle low mode.
CS high time.
1
t7
250
30
40
5
t8
t9
CS rising edge to SCLK rising edge.
SCLK rising edge to CS falling edge.
SDO data valid from SCLK falling edge.
CS rising edge to SDO disabled.
LDAC pulse width low.
t10
t11
t12
t13
t14
t15
t16
t17
90
40
100
10
100
10
100
LDAC falling edge to CS rising edge.
SCLK rising edge to LDAC falling edge.
RESET minimum pulse width low.
RESET pulse activation time.
1
CS
LDAC
CS
t7 ≥ 250 ns only applies to the first SCLK rising edge to rising edge after
Refer to Figure 3.
(IDLEL LOW) falling edge. t7 ≥ 0 ns applies for all other SCLK rising edge to rising edge.
Table 4. LDAC Idle Low Timing
Parameter 1.65 V ≤ IOVDD ≤ 5.5 V Unit
Test Conditions/Comments
t1
250
ns min
SCLK rising edge to CS rising edge. The first SCLK rising edge to CS rising edge after
LDAC idle low falling edge.
t2
t3
0
ns min
ns min
SCLK rising edge to CS rising edge.
LDAC falling edge to CS rising edge.
10
Rev. 0 | Page 7 of 59
AD5770R
TIMING DIAGRAMS
SCLK
Data Sheet
t1
t4
t2
t7
t10
t3
t9
t8
CS
t5
t6
A
A
A
A
D
D
D
D
D
D
D
0
SDI
R/W
7
6
1
0
n
n – 1
n – 1
1
t11
t12
SDO
D0
n
1
t15
t13
LDAC (IDLE HIGH)
t14
LDAC (IDLE LOW)
RESET
IDACx
t16
t17
Figure 2. Timing Diagram (Not to Scale)
SCLK
t1
t2
CS
t3
LDAC (IDLE LOW)
LDAC
Figure 3.
Idle Low Timing Diagram
Rev. 0 | Page 8 of 59
Data Sheet
AD5770R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 5.
Parameter
Rating
AVDD to DVDD
AVDD to AGND
AVDD to PVDDx
AVDD to AVEE
AVEE to AGND
PVEE0 to AGND
AVEE to PVEE0
PVDDx to AGND
PVDDx to AVEE
AVDD to PVEE0
VREF_IO to AGND
IDAC0 to PVEE0
IDAC1 through IDAC5 to AGND
DVDD to DGND
IOVDD to DGND
REFGND to AGND
AGND to DGND
Digital Inputs to DGND1
Digital Outputs to DGND2
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature, TJMAX
Power Dissipation
Lead Temperature, Soldering Reflow
−0.3 V to +0.3 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +10 V
+0.3 V to −3.5 V
+0.3 V to −3.5 V
−3 .0 V to +0.3 V
−0.3 V to +6.5 V
−0.3 V to +8.5 V
−0.3 V to +6.5 V
−0.3 V to AVDD + 0.3 V
−0.3 V to +6.5 V
−0.3 V to PVDDx + 0.3 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
θ
JA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
Table 6. Thermal Resistance
Package Type
θJA
301
Unit
CB-49-5
°C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with 16 thermal vias. See JEDEC JESD51.
ESD CAUTION
(TJMAX – TA)/θJA
260°C, as per JEDEC
J-STD-020
1
RESET
, and
LDAC
.
Digital inputs include SCLK, SDI,
Digital outputs include SDO and
2
ALARM
.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 9 of 59
AD5770R
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
AD5770R
1
2
3
4
5
6
7
CDAMP_
IDAC1
A
PVDD1
IDAC1
PVDD0
IDAC2
IDAC0
PVDD2
CDAMP_
IDAC2
B
C
D
E
F
IDAC0
PVEE0
DNC
PVDD0
PVDD5
IDAC5
PVDD4
IDAC4
PVDD1
PVDD3
DNC
IDAC1
IDAC3
CDAMP_
IDAC0
AGND
AVEE
AGND
DGND
CDAMP_
IDAC5
CDAMP_
IDAC4
CDAMP_
IDAC3
AVEE
IREF
REFGND
DNC
AVDD
DVDD
DNC
CS
VREF_IO ALARM
DGND
LDAC
SDI
G
CREF
RESET MUX_OUT CREG
SDO
IOVDD
SCLK
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type1
F
Description
A1, B1
IDAC0
AO
Current Output of Channel 0 is Available on this Pin. Channel 0 sinks up to 60 mA and sources up to
300 mA.
A2, B2
A3
A4
PVDD0
IDAC2
PVDD2
S
AO
S
Power Supply for IDAC0.
Current Output of Channel 2 is Available on this Pin. Channel 2 sources up to 150 mA.
Power Supply for IDAC2.
A5
CDAMP_IDAC1 AI
Damping Capacitor for IDAC1. Connect a 10 nF capacitor between this pin and the PVDD1
supply.
A6, B6
A7, B7
B3
PVDD1
IDAC1
PVDD5
S
AO
S
Power Supply for IDAC1.
Current Output of Channel 1 is Available on this Pin. Channel 1 sources up to 250 mA.
Power Supply for IDAC5.
B4
CDAMP_IDAC2 AI
Damping Capacitor for IDAC2. Connect a 10 nF capacitor between this pin and the PVDD2
supply.
B5
C1
PVDD4
PVEE0
S
S
Power Supply for IDAC4.
Power Supply Return for IDAC0 Sink. When sinking this current on Channel 0, up to 60 mA
flows out of PVEE0.
C2
CDAMP_IDAC0 AI
Damping Capacitor for IDAC0. Connect a 10 nF capacitor between this pin and the PVDD0
supply.
C3
C4, E4
C5
C6
C7
IDAC5
AGND
IDAC4
PVDD3
IDAC3
AO
S
Current Output of Channel 5 is Available on this Pin. Channel 5 sources up to 100 mA.
Analog Supply Ground Pin.
Current Output of Channel 4 is Available on this Pin. Channel 4 sources up to 100 mA.
Power Supply for IDAC3.
Current Output of Channel 3 is Available on this Pin. Channel 3 sources up to 100 mA.
Do Not Connect. Do not connect to this pin.
Negative Power Supply. AVEE must be between −3 V and 0 V. This pin supplies the low side
voltage for biasing some analog circuit blocks.
AO
S
AO
DNC
S
D1, D6, E3, E6 DNC
D2, D4
AVEE
D3
CDAMP_IDAC5 AI
Damping Capacitor for IDAC5. Connect a 10 nF capacitor between this pin and the PVDD5
supply.
Rev. 0 | Page 10 of 59
Data Sheet
AD5770R
Pin No.
Mnemonic
CDAMP_IDAC4 AI
Type1
F
Description
D5
Damping Capacitor for IDAC4. Connect a 10 nF capacitor between this pin and the PVDD4
supply.
D7
E1
E2
CDAMP_IDAC3 AI
Damping Capacitor for IDAC3. Connect a 10 nF capacitor between this pin and the PVDD3
supply.
External Resistor Pin for Reference Current Generation (Optional). When using an external RSET
resistor, connect this pin directly to REFGND via a low drift, 2.5 kΩ external resistor.
Reference Supply Ground Pin. Connect this pin with a low impedance path to AGND. If using
an external resistor, the low side of the RSET resistor must be connected to REFGND before the
connection to AGND.
IREF
AI/O
REFGND
S
E5
E7
F1
AVDD
CS
S
Analog Power Supply. AVDD must be between 2.9 V and 5.5 V. This pin supplies power to the
analog circuit blocks on the device. This pin must be at the same potential as DVDD.
Active Low Control Input. CS is used to frame data during a SPI transaction. When CS is low,
data is transferred on the rising edges of SCLK.
Voltage Reference Input/Output. When the internal reference is enabled, the buffered 1.25 V
reference voltage can be made available on this pin. When the internal reference is disabled, an
external reference must be applied to this pin. The external reference voltage must be 1.25 V or
2.5 V.
DI
VREF_IO
AI/O
F2
ALARM
DO
Active Low Output. When ALARM goes low, this alerts the user of a change in the status
register. User must read the status register to deassert this pin.
Digital Power Supply Ground.
Digital Power Supply. DVDD must be between 2.9 V and 5.5 V. This pin supplies power to the
digital core and internal oscillator blocks on the device. This pin must be at the same potential
as AVDD.
F3, F4
F5
DGND
DVDD
S
S
F6
LDAC
DI
Logic Input. Pulsing this pin low allows any or all DAC registers to be updated if the input
registers have new data, allowing any or all DAC outputs to update synchronously.
Alternatively, this pin can be tied low.
F7
SDI
DI
Serial Data Input. Data to be written to the device is provided on this input and is clocked into
the register on the rising edge of SCLK.
G1
G2
G3
CREF
AI/O
DI
Filter Capacitor for Voltage Reference. A 0.1 µF capacitor connected from the CREF pin to AGND
is recommended to achieve the specified performance from the AD5770R.
Active Low Reset Input. Tie this pin high for normal operation. Asserting this pin low resets the
AD5770R to the default configuration.
Analog Output. An external analog-to-digital converter (ADC) reads voltages on this pin for
diagnostic purposes. Use external excitation current for the temperature sensing diode and
force the current on this pin.
RESET
MUX_OUT
AI/O
G4
G5
G6
G7
CREG
SDO
AI/O
DO
S
Filter Capacitor for Internal Regulator. A 1 µF capacitor connected from the CREG pin to AGND
is recommended to achieve the specified performance from the AD5770R.
Serial Data Output. A read back operation provides data on this output pin as a serial data
stream. Data is clocked out on the falling edge of SCLK and is valid on the rising edge of SCLK.
Logic Power Supply. IOVDD must be between 1.65 V and 5.5 V. This pin supplies power to the
serial interface circuit blocks on the device.
Serial Clock Input. Data is clocked into the input shift register on the rising edge of the serial
clock input. Data can be transferred at rates up to 20 MHz when writing to the AD5770R. This
pin has a maximum speed of 10 MHz when performing a read operation from the AD5770R.
IOVDD
SCLK
DI
1 AO is analog output, S is power, AI is analog input, DNC is do not connect, AI/O is analog input and output, DI is digital input, and DO is digital output.
Rev. 0 | Page 11 of 59
AD5770R
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
1.0
0.8
0.4
0.6
0.2
0.4
0
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 5. INL Error vs. DAC Code (Channel 0, 0 mA to 300 mA Range)
Figure 8. INL Error vs. DAC Code (Channel 3, 0 mA to 100 mA Range)
0.6
0.4
0.6
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 6. INL Error vs. DAC Code (Channel 1, 0 mA to 250 mA Range)
Figure 9. INL Error vs. DAC Code (Channel 4, 0 mA to 100 mA Range)
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–0.2
–0.4
–0.6
–0.8
–1.0
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 7. INL Error vs. DAC Code (Channel 2, 0 mA to 150 mA Range)
Figure 10. INL Error vs. DAC Code (Channel 5, 0 mA to 100 mA Range)
Rev. 0 | Page 12 of 59
Data Sheet
AD5770R
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 11. DNL Error vs. DAC Code (Channel 0, 0 mA to 300 mA Range)
Figure 14. DNL Error vs. DAC Code (Channel 3, 0 mA to 100 mA Range)
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 12. DNL Error vs. DAC Code (Channel 1, 0 mA to 250 mA Range)
Figure 15. DNL Error vs. DAC Code (Channel 4, 0 mA to 100 mA Range)
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 13. DNL Error vs. DAC Code (Channel 2, 0 mA to 150 mA Range)
Figure 16. DNL Error vs. DAC Code (Channel 5, 0 mA to 100 mA Range)
Rev. 0 | Page 13 of 59
AD5770R
Data Sheet
1.0
1.0
1.5
+105°C
+85°C
+25°C
–40°C
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
+105°C
+85°C
+25°C
–40°C
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 17. INL Error vs. DAC Code for Various Temperatures (Channel 0, 0 mA
to 300 mA Range)
Figure 20. INL Error vs. DAC Code for Various Temperatures (Channel 3, 0 mA
to 100 mA Range)
1.0
2.0
1.5
1.0
0.5
0
+105°C
+85°C
1.5
+25°C
–40°C
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
+105°C
+85°C
+25°C
–40°C
–1.5
–2.0
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 18. INL Error vs. DAC Code for Various Temperatures (Channel 1, 0 mA
to 250 mA Range)
Figure 21. INL Error vs. DAC Code for Various Temperatures (Channel 4, 0 mA
to 100 mA Range)
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–0.5
–1.5
+105°C
+85°C
+25°C
–40°C
–1.0
–1.5
+105°C
+85°C
–2.0
+25°C
–40°C
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
–2.5
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 19. INL Error vs. DAC Code for Various Temperatures (Channel 2, 0 mA
to 150 mA Range)
Figure 22. INL Error vs. DAC Code for Various Temperatures (Channel 5, 0 mA
to 100 mA Range)
Rev. 0 | Page 14 of 59
Data Sheet
AD5770R
1.0
1.0
0.8
+105°C
+85°C
+25°C
–40°C
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
+105°C
+85°C
+25°C
–40°C
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 23. DNL Error vs. DAC Code for Various Temperatures (Channel 0,
0 mA to 300 mA Range)
Figure 26. DNL Error vs. DAC Code for Various Temperatures (Channel 3,
0 mA to 100 mA Range)
1.0
1.0
0.8
0.6
0.4
0.2
0
+105°C
+85°C
+25°C
–40°C
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
+105°C
+85°C
–0.8
–1.0
+25°C
–40°C
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 24. DNL Error vs. DAC Code for Various Temperatures (Channel 1,
0 mA to 250 mA Range)
Figure 27. DNL Error vs. DAC Code for Various Temperatures (Channel 4,
0 mA to 100 mA Range)
1.0
1.0
0.8
0.6
0.4
0.2
0
+105°C
+85°C
+25°C
–40°C
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
+105°C
+85°C
–0.8
–1.0
+25°C
–40°C
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
CODE
Figure 25. DNL Error vs. DAC Code for Various Temperatures (Channel 2,
0 mA to 150 mA Range)
Figure 28. DNL Error vs. DAC Code for Various Temperatures (Channel 5,
0 mA to 100 mA Range)
Rev. 0 | Page 15 of 59
AD5770R
Data Sheet
70
60
50
40
30
20
10
0.50
0.45
0.40
0.35
0.30
0.25
0.20
CH0
CH1
CH2
CH3
CH4
CH5
CH0
CH1
CH2
CH3
CH4
CH5
0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29. Zero-Scale Error vs. Temperature
Figure 32. Gain Error vs. Temperature
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
CH0
CH1
CH2
CH3
CH4
CH5
+105°C
+85°C
+25°C
–40°C
–0.005
–0.010
–0.015
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 30. Full-Scale Error vs. Temperature
Figure 33. Total Unadjusted Error vs. DAC Code for Various Temperatures
(Channel 0, 0 mA to 300 mA Range)
0.05
CH0
CH1
CH2
CH3
CH4
CH5
+105°C
+85°C
+25°C
110
0.03
0.01
60
10
–0.01
–0.03
–0.05
–40
–90
–40
–20
0
20
40
60
80
100
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
TEMPERATURE (°C)
Figure 34. Total Unadjusted Error vs. DAC Code for Various Temperatures
(Channel 1, 0 mA to 250 mA Range)
Figure 31. Offset Error vs. Temperature
Rev. 0 | Page 16 of 59
Data Sheet
AD5770R
0.005
0.03
0.02
0.01
0
0
–0.005
–0.010
–0.015
–0.020
–0.025
–0.01
–0.02
–0.03
+105°C
+85°C
+25°C
–40°C
+105°C
+85°C
+25°C
–40°C
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
Figure 35. Total Unadjusted Error vs. DAC Code for Various Temperatures
(Channel 2, 0 mA to 150 mA Range)
Figure 38. Total Unadjusted Error vs. DAC Code for Various Temperatures
(Channel 5, 0 mA to 100 mA Range)
0.03
0.02
0.01
0
1.6
1.4
1.2
1.0
0.8
0.6
–0.01
–0.02
CH1 (0mA TO 250mA)
CH0 (0mA TO 300mA)
CH0 (–60mA TO +300mA)
0.4
0.2
0
+105°C
+85°C
+25°C
–40°C
–0.03
–0.04
WITH 5Ω LOAD
–10
0
10
20
30
40
50
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
TIME (µs)
Figure 36. Total Unadjusted Error vs. DAC Code for Various Temperatures
(Channel 3, 0 mA to 100 mA Range)
Figure 39. Full-Scale Settling Time (Rising Step)
0.010
0.005
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
CH1 (0mA TO 250mA)
CH0 (0mA TO 300mA)
CH0 (–60mA TO +300mA)
WITH 5Ω LOAD
–0.005
–0.010
–0.015
–0.020
–0.025
+105°C
+85°C
+25°C
–40°C
–0.030
–10
0
10
20
30
40
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
TIME (µs)
Figure 37. Total Unadjusted Error vs. DAC Code for Various Temperatures
(Channel 4, 0 mA to 100 mA Range)
Figure 40. Full-Scale Settling Time (Falling Step)
Rev. 0 | Page 17 of 59
AD5770R
Data Sheet
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
+105°C
+85°C
+25°C
–40°C
+105°C
+85°C
+25°C
–40°C
0
0
0.05
0.10
0.15
0.20
0.25
PVDD3 HEADROOM (V)
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
PVDD0 HEADROOM (V)
Figure 41. CH0 Output Current for Various Temperatures vs. PVDD0 Headroom
Figure 44. CH3 Output Current for Various Temperatures vs. PVDD3 Headroom
0.16
0.14
0.12
0.10
0.08
0.06
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.04
0.010
+105°C
+105°C
+85°C
+85°C
+25°C
–40°C
0.02
0
0.005
0
+25°C
–40°C
0
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
PVDD1 HEADROOM (V)
0
0.05
0.10
0.15
0.20
0.25
PVDD4 HEADROOM (V)
Figure 42. CH1 Output Current for Various Temperatures vs. PVDD1 Headroom
Figure 45. CH4 Output Current for Various Temperatures vs. PVDD4 Headroom
0.06
0.05
0.04
0.03
0.02
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
+105°C
+105°C
+85°C
+25°C
–40°C
0.01
0
+85°C
0.005
0
+25°C
–40°C
0
0.05
0.10
0.15
0.20
0.25
0
0.05
0.10
0.15
0.20
0.25
PVDD2 HEADROOM (V)
PVDD5 HEADROOM (V)
Figure 43. CH2 Output Current for Various Temperatures vs. PVDD2 Headroom
Figure 46. CH5 Output Current for Various Temperatures vs. PVDD5 Footroom
Rev. 0 | Page 18 of 59
Data Sheet
AD5770R
900k
800k
700k
600k
500k
400k
300k
200k
100k
0
0.35
DC OUTPUT IMPEDANCE
FULL-SCALE OUTPUT CURRENT
0.30
0.25
0.20
0.15
0.10
0.05
0
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
+105°C
+85°C
+25°C
–40°C
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
PVEE0 HEADROOM (V)
Figure 47. CH0 Output Current for Various Temperatures vs. PVEE0 Footroom
Figure 49. DC Output Impedance vs. Full-Scale Output Current (All Ranges)
20
4
3
CH0 (0mA TO 300mA)
CH0 (–60mA TO +300mA)
CH1 (0mA TO 140mA, LOW HEADROOM)
CH1 (0mA TO 140mA, LOW NOISE)
CH1 (0mA TO 250mA)
CH2 (0mA TO 55mA)
CH2 (0mA TO 150mA)
0
–20
2
1
–40
0
–60
–1
–2
–3
–4
–5
–80
CH3 (0mA TO 45mA)
CH3 (0mA TO 100mA)
CH4 (0mA TO 45mA)
CH4 (0mA TO 100mA)
CH5 (0mA TO 45mA)
CH5 (0mA TO 100mA)
–100
–120
–140
0dB = 1A/V
1
10
100
1k
10k
100k
1M
10M
0
20
40
60
80
100
FREQUENCY (Hz)
TIME (Seconds)
Figure 50. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth,
(CH0 0 mA to 300 mA Range)
Figure 48. AC PSRR vs. Frequency (All Ranges)
Rev. 0 | Page 19 of 59
AD5770R
Data Sheet
10µ
400
300
4.0
3.5
3.0
2.5
2.0
1.5
CH0 (0mA TO 300mA)
CH0 (–60mA TO +300mA)
CH1 (0mA TO 140mA, LOW HEADROOM)
CH1 (0mA TO 140mA, LOW NOISE)
CH1 (0mA TO 250mA)
1µ
CH2 (0mA TO 55mA)
CH2 (0mA TO 150mA)
200
100
100n
10n
1n
0
CS
–100
–200
–300
–400
20MHz SCLK
0x0000 TO
0x3FFF
1.0
0.5
0
CH3 (0mA TO 45mA)
CH3 (0mA TO 100mA)
CH4 (0mA TO 45mA)
CH4 (0mA TO 100mA)
CH5 (0mA TO 45mA)
CH5 (0mA TO 100mA)
20MHz SCLK
0x3FFF TO
0x0000
20MHz SCLK
0x0000 TO
0x2AAA
100p
1
–0.5
4.5
10
100
1k
10k
100k
1.5
2.0
2.5
3.0
3.5
4.0
FREQUENCY (Hz)
TIME (µs)
Figure 51. Output NSD vs. Frequency (All Ranges)
Figure 54. Digital Feedthrough
10µ
1µ
450
ATTACK CH1 ZS TO FS
ATTACK CH1 FS TO ZS
ATTACK CH2 ZS TO FS
ATTACK CH2 FS TO ZS
ATTACK CH3 ZS TO FS
ATTACK CH3 FS TO ZS
ATTACK CH4 ZS TO FS
ATTACK CH4 FS TO ZS
ATTACK CH5 ZS TO FS
ATTACK CH5 FS TO ZS
350
250
150
50
100n
10n
–50
–150
–250
0.1
1
10
100
1k
10k
100k
186.2
191.2
196.2
201.2
206.2
211.2
FREQUENCY (Hz)
TIME (µs)
Figure 55. DAC to DAC Crosstalk (Victim Channel Zero)
Figure 52. VREF_IO Output NSD vs. Frequency
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.2530
1.2525
1.2520
1.2515
1.2510
1.2505
1.2500
0.007
0.005
0.003
RLOAD IDAC0 = 5Ω
RLOAD IDAC1 = 5Ω
RLOAD IDAC2 = 5Ω
RLOAD IDAC3 = 5Ω
0.001
–0.001
V
V
V
= 5.5V
= 3.3V
= 2.9V
DD
DD
DD
RLOAD IDAC4 = 5Ω
RLOAD IDAC5 = 5Ω
CS
–0.003
–0.5
227
–0.005
–0.003
–0.001
0.001
0.003
0.005
220
221
222
223
224
225
226
LOAD CURRENT (I)
TIME (µs)
Figure 53. VREF_IO Voltage vs. Load Current
Figure 56. Analog Crosstalk
Rev. 0 | Page 20 of 59
Data Sheet
AD5770R
600
500
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
400
ATTACK CH0 ZS TO FS
ATTACK CH0 FS TO ZS
ATTACK CH1 ZS TO FS
ATTACK CH1 FS TO ZS
ATTACK CH2 ZS TO FS
ATTACK CH2 FS TO ZS
300
200
100
0
–100
–200
–300
–400
–500
ATTACK CH4 ZS TO FS
ATTACK CH4 FS TO ZS
ATTACK CH5 ZS TO FS
ATTACK CH5 FS TO ZS
CS
EXTERNAL BIAS (100µA)
EXTERNAL BIAS (200µA)
INTERNAL BIAS (10µA)
–0.5
5.0
2.0
2.5
3.0
3.5
4.0
4.5
–50
–30
–10
10
30
50
70
90
110
TIME (µs)
TEMPERATURE (°C)
Figure 60. Diode Voltage vs. Temperature
Figure 57. Digital Crosstalk
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1
COOLING DOWN
HEATING UP
–0.5
RESET
RLOAD IOUT3 = 10Ω
0
110
–1.0
–200
120
130
140
150
160
170
0
200
400
600
800
1000
DIE TEMPERATURE (°C)
TIME (ns)
Figure 58. Reset Glitch
Figure 61. Overheat Warning
1.2535
1.2530
1.2525
1.2520
1.2515
1.2510
COOLING DOWN
HEATING UP
1
0
110
115
120
125
130
135
140
145
150
155
–50
–30
–10
10
30
50
70
90
110
DIE TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 59. VREF vs. Temperature for Devices for Five
AD5770R Devices
Figure 62. Overheat Shutdown
Rev. 0 | Page 21 of 59
AD5770R
Data Sheet
33.6
33.4
33.2
33.0
32.8
32.6
32.4
32.2
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
32.0
2.0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 63. AVDD Supply Current (IAVDD) vs. Supply Voltage for Five AD5770R
Devices
Figure 66. IOVDD Supply Current vs. IOVDD Supply Voltage for
Five AD5770R Devices
33.5
33.0
32.5
32.0
31.5
31.0
1.16
1.15
1.14
1.13
1.12
1.11
30.5
–50
1.10
–30
–10
10
30
50
70
90
110
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 67. IAVDD vs. Temperature for Ten AD5770R Devices
Figure 64. DVDD Supply Current (IDVDD) vs. Supply Voltage for Five AD5770R
Devices
4.0
3.5
3.0
2.5
2.0
1.5
1.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Figure 65. IOVDD Supply Current vs. IOVDD Supply Voltage for Five
AD5770R Devices
Rev. 0 | Page 22 of 59
Data Sheet
AD5770R
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.75
1.73
1.71
1.69
1.67
1.65
1.04
–50
–30
–10
10
30
50
70
90
110
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 69. IDVDD vs. Temperature
Figure 68. IDVDD vs. Temperature for Ten AD5770R Devices
Rev. 0 | Page 23 of 59
AD5770R
Data Sheet
TERMINOLOGY
TUE
Output Settling Time
Total unadjusted error is a measure of the output error taking
all the various errors into account, namely INL error, offset
error, gain error, and output drift over supplies, temperature,
and time. TUE is expressed in % FSR.
Output settling time is the amount of time it takes for the output of
a DAC to settle to a specified level for a zero-scale to full-scale
LDAC
input change and is measured from the falling edge of
.
Digital-to-Analog Glitch Impulse
Relative Accuracy or Integral Nonlinearity (INL)
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nA-sec,
and is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x1FFF to 0x2000 for the AD5770R).
Relative accuracy or integral nonlinearity is a measurement of the
maximum deviation, in LSBs, from a straight line passing through
the endpoints of the DAC transfer function. Typical INL error vs.
DAC code plots are shown in Figure 5 to Figure 10.
Differential Nonlinearity (DNL)
Digital Feedthrough
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. Typical DNL error vs. DAC code plots are shown in
Figure 11 to Figure 16.
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nA-sec and measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice versa.
DC Crosstalk
Zero-Scale Error
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC when monitoring
another DAC maintained at midscale. It is expressed in nA-sec.
Zero-scale error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Zero code
error is expressed in µA.
Zero-Scale Error Temperature Coefficient
Digital Crosstalk
Zero code error drift is a measure of the change in zero code
error with a change in temperature. It is expressed in nA/°C.
Digital crosstalk is the glitch impulse transferred to the output of
one DAC at midscale in response to a full-scale code change (all 0s
to all 1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nA-sec.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % FSR.
DAC to DAC Crosstalk
DAC to DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by loading
the attack channel with a full-scale code change (all 0s to all 1s
and vice versa), using the write to and update commands when
monitoring the output of the victim channel that is at midscale. The
energy of the glitch is expressed in nA-sec.
Gain Error Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Offset Error
Offset error is a measurement of the difference between IOUTx
(actual) and IOUTx (ideal), expressed in µA, in the linear region
of the transfer function. Offset error can be negative or positive.
Output Noise Spectral Density
Output noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nA/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. It is measured
in nA/√Hz.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µA/°C.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
IOUTx to a change in AVDD for a full-scale output of the DAC. It
is measured in µA/V.
Multiplexer Switching Glitch
The multiplexer switching glitch is a measure of the impulse
injected into the analog output of the DAC when the monitor
mux is changed to monitor a different channel.
AC Power Supply Rejection Ratio (AC PSRR)
AC power supply rejection ratio is a measure of the rejection of the
output current to ac changes in the power supplies applied to the
DAC. AC PSRR is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
Rev. 0 | Page 24 of 59
Data Sheet
AD5770R
THEORY OF OPERATION
When the external 1.25 V reference option is selected, switch
SWA1 is closed, switch SWA2 is open, and switch SWA3 is
connected to switch SWA2.
DIGITAL TO ANALOG CONVERTER
The AD5770R is a 6-channel, 14-bit, serial input, current output
DAC capable of multiple low noise output current ranges with
high power efficiency. Each of the six DACs has a segmented
current steering architecture, chosen to achieve low glitch
performance when changing codes.
When the external 2.5 V option is selected, switch SWA1 and
switch SWA2 are open and switch SWA3 is connected to the
resistor divider shown in Figure 70.
Precision RSET Resistor
PRECISION REFERENCE CURRENT GENERATION
The AD5770R integrates an on-chip 2.5 kΩ (10 ppm/°C, 0.1%)
precision RSET resistor that can be used for the reference current
generation. If required, an external precision RSET resistor can be
used for reference current generation. The user selects an internal
or an external reference resistor by writing to the REFERENCE_
RESISTOR_SEL bit in the reference register. The AD5770R
powers up with the internal precision RSET resistor selected.
The AD5770R requires a 500 μA precision reference current for
all four DAC cores, which is generated using a 1.25 V voltage
reference and a 2.5 kΩ precision RSET resistor. The AD5770R
integrates an internal 1.25 V voltage reference and 2.5 kΩ internal
precision RSET resistor for this function. The AD5770R can also
use an external voltage reference and external precision RSET resistor
for the reference current generation. Ensure that the voltage
reference and the precision RSET resistor have low noise, high
accuracy, and low temperature drift to help minimize the
overall IDACx gain error and gain error drift. Table 1 outlines the
performance specifications of the AD5770R with both the internal
reference and internal RSET resistor, and an external 1.25 V reference
and external precision RSET resistor.
The AD5770R integrates fault protection circuitry when using
an external resistor. The AD5770R automatically switches from
an external to an internal resistor if the external resistor option
is selected, and if the external resistance is below the minimum
specification. A simplified diagram of the how the reference resistor
is configured by changing switch SWB1 is shown in Figure 70.
SWA1
Voltage Reference
VREF_IO
The AD5770R can use an external voltage reference for the
precision reference current generation. The external reference
voltage can be either 1.25 V or 2.5 V, configured by writing to
the REFERENCE_VOLTAGE_SEL bits in the reference register.
When the user selects the 2.5 V external voltage reference option,
an internal voltage divider attenuates to achieve the 1.25 V
required.
1.25V
SWA2
INTERNAL
REFERENCE
SWA3
PRECISION
REFERENCE
CURRENT
The device powers up with the external 2.5 V reference voltage
option selected.
CREF
100nF
IREF
The AD5770R integrates a low noise, on-chip, 15 ppm/°C, 1.25 V
voltage reference that can be used as the voltage reference. The
on-chip reference is powered down by default and is enabled when
the REFERENCE_VOLTAGE_SEL bits in the reference register
select the internal reference.
SWB1
R
SET_EXT
2.5kΩ
R
SET_INT
2.5kΩ
The buffered 1.25 V internal reference voltage can be made
available at the VREF_IO pin for use as a system reference.
Figure 70. AD5770R Reference Options
DIAGNOSTIC MONITORING
Regardless of the voltage reference scheme used, it is recommended
that a 100 nF capacitor is placed between the CREF pin and AGND
to achieve specified performance. A simplified diagram of the
voltage reference configuration is shown in Figure 70.
The AD5770R diagnostic feature allows the user to monitor
output compliance voltages, output currents, and the internal
die temperature of the device. The output compliance voltages,
which are voltages representative of output current and internal
die temperature, are multiplexed on-chip and are available on
the MUX_OUT pin and can be measured using an external ADC.
When the internal 1.25 V reference is selected and made
available on the VREF_IO pin, switch SWA1 and switch SWA2
are closed, and switch SWA3 is connected to switch SWA2.
Diagnostics monitoring is disabled on power up and can be
enabled by writing to the MON_FUNCTION bits in the
MONITOR_SETUP register.
When the internal 1.25 V reference is selected but not made
available on the VREF_IO pin, switch SWA1 is open, switch
SWA2 is closed, and switch SWA3 is connected to switch SWA2.
The AD5770R integrates a voltage buffer on the multiplexer
output to ease system design. The multiplexer buffer is disabled
Rev. 0 | Page 25 of 59
AD5770R
Data Sheet
and bypassed on power up. The multiplexer buffer is enabled by
setting the MUX_BUFFER bit in the MONITOR_SETUP register.
where:
T is the die temperature (°C).
VD is the diode voltage.
Compliance Voltage Monitoring
Using an external bias current of 100 µA, with the IB_EXT_EN
bit set high, the internal die temperature can be calculated as
follows:
When the MON_FUNCTION bits in the MONITOR_
SETUP register are set to select output voltage monitoring, the
output compliance voltage of the selected DAC channel is
multiplexed onto the MUX_OUT pin. The IDACx channel to
be monitored is selected using the MON_CH bits in the
MONITOR_SETUP register.
880 mV −VD
T =
+ 25
(3)
1.3 mV
When using an external bias current of 200 µA, with the
IB_EXT_EN bit set high, the die temperature can be calculated
as follows:
Output Current Monitoring
When the MON_FUNCTION bits in the MONITOR_SETUP
register select output current monitoring, a voltage representation
of the output current of the selected DAC channel is multiplexed
onto the MUX_OUT pin. The output current can only be
monitored in current sourcing mode. The IDACx channel to be
monitored is selected using the MON_CH bits in the MONITOR_
SETUP register.
1.04 V −VD
0.9 mV
T =
+ 25
(4)
SERIAL INTERFACE
The AD5770R has a 4-wire ( , SCLK, SDI, and SDO) interface
CS
that is compatible with SPI, QSPI, and MICROWIRE interface
standards as well as most digital signal processors (DSPs).
The output current is calculated by
For both read and write SPI transactions, data must be valid on
the rising edge of SCLK (SCLK clock polarity = 0, SCLK clock
phase = 0). For all SPI transactions, data is shifted MSB first.
Communication with the device is separated into two distinct
phases of operation. The first phase is the instruction phase and
is used to initiate some action of the device. The second phase is
the data phase where data is either passed to the device to operate
on or received from the device in response to the instruction
phase. Figure 71 illustrates the SPI transaction phases.
IFULLSCALE × V
−VOS
(
)
MUX
ISOURCE
=
(1)
400 mV
where:
I
I
V
V
SOURCE is the output current being sourced.
FULLSCALE is the full-scale output current.
MUX is the measured voltage at the MUX_OUT pin.
OS is the monitor offset voltage, nominally 28 mV.
Uncalibrated, the current monitoring feature is accurate to
within 10% of the full-scale output range. To improve the
accuracy of the current monitor feature, calibrate VOS by
measuring the voltage at the MUX_OUT pin at zero scale. To
calibrate the 400 mV term, measure the voltage at the
MUX_OUT pin at full scale.
CS
SDI
7-BIT ADDRESS
Z
R/W
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
SDO
DATA PHASE
INSTRUCTION PHASE
Figure 71. SPI Transaction Phases
For 0 mA to 140 mA low headroom mode on Channel 1, use a
value of 250 mA for IFULLSCALE
.
Instruction Phase
Internal Die Temperature Monitoring
The instruction phase immediately follows the falling edge of
When temperature monitoring is selected in the MONITOR_
SETUP register, a voltage representation of the internal die
temperature is multiplexed onto the MUX_OUT pin. To monitor
the internal die temperature, a precision current is forced through a
diode on the chip, and the voltage across the diode is multiplexed
onto the MUX_OUT pin. Choose to use an external bias current
for the temperature monitoring function by setting the
IB_EXT_EN bit high in the MONITOR_SETUP register. The
external bias current must be forced into the MUX_OUT pin.
The multiplexer buffer must be bypassed when using an
external bias current for temperature monitoring.
CS
that initiates the SPI transaction. The instruction phase
W
consists of a read/write bit (R/ ) followed by a register address
word. Setting R/ high selects a read instruction. Setting R/
low selects a write instruction. The address word is 7 bits long.
The register address sent in the instruction phase is used as the
starting address to start writing or reading from. Refer to Table
12 and Table 13 for a full list of registers and the associated
addresses.
W
W
Data Phase
The data phase immediately follows the instruction phase.
When a write instruction is sent to the device, data is written to
the register location selected. When a read instruction is sent to
the device, data stored in the register location selected is shifted
out on the SDO pin.
Using the internal bias current with the IB_EXT_EN bit set low,
calculate the internal die temperature as follows:
700 mV −VD
T =
+ 25
(2)
1.8 mV
Rev. 0 | Page 26 of 59
Data Sheet
AD5770R
SPI Frame Synchronization
mode, the internal SPI state machine resets after the data phase as if
CS
was deasserted, and awaits the next instruction. Single
instruction mode forces each data phase to be preceded with a
CS
CS
The
falling edge on
during a SPI transaction terminates part or all of the data transfer.
CS
pin is used to frame data during an SPI transaction. A
CS CS
initiates a SPI transaction. Deasserting
new instruction phase even though the
deasserted by the SPI master. Single instruction mode allows the
user to access one or more registers in a single synchronization
frame without having to deassert the
The default for this bit is cleared, resulting in streaming mode
being enabled.
line has not been
If
is complete, the transaction aborts and the AD5770R returns to
CS
is deasserted (returned high) before the instruction phase
CS
line after each data bye.
the ready state. If
written, the transaction aborts and the AD5770R returns to the
CS
is deasserted before the first data word is
ready state. If
is deasserted after one or more data words have
Figure 74 illustrates an SPI transaction in single instruction mode
in which the following sequence of events occur:
been written, those completed data words are written or read, but
any partial written data words are aborted.
1. Sets the output range of Channel 1.
2. Enables the output of Channel 1.
3. Writes to the Channel 1 DAC register.
4. Reads the status register.
Streaming Mode
CS
The
pin can be held low, and multiple data bytes can be
shifted during the data phase, which reduces the amount of
overhead associated with data transfer. This mode of operation
is known as streaming mode. When in streaming mode, the
register address sent in the instruction phase is automatically
incremented or decremented after each byte of data is processed.
The ADDR_ASCENSION_MSB bit and ADDR_ASCENSION_
LSB bit in the INTERFACE_CONFIG_A register selects the
address increment or decrement. The default operation is to
decrement addresses when streaming data. Figure 72 illustrates
a streaming mode SPI write transaction in which the six input
registers are accessed using only a single instruction byte. The
register address is automatically decremented after each data
byte is processed. Figure 73 illustrates a streaming mode SPI
read transaction in which the six DAC registers are accessed
using a decrementing address.
Multibyte Registers
CS
If writing to a multibyte register,
must be held low for the
whole transaction for the write to be valid. The address used
must be the address of the most significant byte. The ADDR_
ASCENSION_MSB bit and the ADDR_ASCENSION_LSB bit in
the INTERFACE_CONFIG_A register must be cleared. This
applies when reading or writing to any multibyte register in
both single instruction mode and streaming mode. Figure 75
illustrates a multibyte register access. The AD5770R contains 14
multibyte registers, as follows:
•
•
•
•
Six input registers.
Six DAC registers.
One input page mask register.
One DAC page mask register.
Single Instruction Mode
When the single instruction bit is set in the INTERFACE_
CONFIG_B register, streaming mode is disabled, and the
AD5770R is placed in single instruction mode. In single instruction
CS
CH5_INPUT_MSB ADDRESS
INSTRUCTION PHASE
CH5_INPUT_MSB
CH5_INPUT_LSB
CH0_INPUT_MSB
CH0_INPUT_LSB
SDI
W
DATA PHASE
Figure 72. Streaming Mode SPI Write Transaction with Decrementing Address
CS
CH5_DAC_LSB ADDRESS
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
SDI
R
SDO
CH5_DAC_MSB
CH5_DAC_LSB
CH0_DAC_MSB
CH0_DAC_MSB
INSTRUCTION PHASE
DATA PHASE
Figure 73. Streaming Mode SPI Read Transaction with Decrementing Address
CS
OUTPUT_RANGE_CH1 CH1_MODE
CH_CONFIG CH1 OUTPUT EN
CH1_DAC_MSB MSB BYTE LSB BYTE
R
STATUS DON’T CARE
STATUS
SDI
W
W
W
SDO
INSTRUCTION PHASE
DATA PHASE
Figure 74. SPI Transaction in Single Instruction Mode
Rev. 0 | Page 27 of 59
AD5770R
Data Sheet
CS
SDI
CH3_DAC_MSB ADDRESS CH3_DAC_MSB
CH3_DAC_LSB
W
DATA PHASE
INSTRUCTION PHASE
Figure 75. Multibyte Register Write
Setting the SW_LDAC register for any channel updates the selected
channels DAC register with the input register contents. The
contents of the SW_LDAC register clear to 0x00 after a software
RESET FUNCTION
RESET
The AD5770R has an asynchronous
pin. For normal
RESET
pin to logic
RESET
operation,
is tied high. Asserting the
LDAC
operation.
low for at least 10 ns resets all registers to their default values.
The reset function takes 100 ns, maximum. Data must not be
written to the device during this time.
INPUT PAGE MASK REGISTER
Following a write to the input page mask register, the code
loaded into this register is copied into the input register of any
channels selected in the CH_SELECT register.
The AD5770R has a software reset function that performs the
RESET
same function as the
pin, with the exception of not
resetting the INTERFACE_CONFIG_A register. The reset
function is activated by setting the SW_RESET_MSB and
SW_RESET_LSB bits in the INTERFACE_CONFIG_A register.
The SW_RESET_MSB and SW_RESET_LSB bits clear
automatically during a software reset.
DAC PAGE MASK REGISTER
Following a write to the DAC page mask register, the DAC code
loaded into this register is copied into the DAC register of any
channels selected in the CH_SELECT register.
OUTPUT STAGES
A reset function must not be performed when the TEMP_
WARNING bit in the status register is high. Ensure that the device
reads the correct trim values from the internal memory.
Each of the six AD5770R channels has a programmable current
output stage that sets the required output current.
Channel 0 Sink Current Generator
LOAD DAC
To sink current on Channel 0, the sink current generator must
be enabled by setting the CH0_SINK_EN bit in the CHANNEL_
CONFIG register to one. On power-up, the sink current generator
is enabled.
The AD5770R DAC consists of double buffered registers for the
DAC code. Data for one or many channels can be written to the
input register without changing the DAC outputs. A load DAC
command issued to the device transfers input register content into
the DAC register, updating the DAC output.
Output Shutdown
Hardware
Pin
LDAC
The AD5770R has an active low
updates to the outputs of the DACs. When
DAC codes can be written to the input registers of the DAC
LDAC
On power-up, the outputs of each channel are in shutdown mode.
When a DAC output is in shutdown mode, the output current is
set to 0 mA. However, the bias circuitry for each IDACx channel
remains powered up, and only the output is shut down. The
shutdown bits for each register are located in the CHANNEL_
CONFIG register. When changing between output modes on a
DAC channel, the output stage of the channel must be shut down
to prevent glitches on the output.
LDAC
pin that can synchronize
LDAC
is held high,
without affecting the output. When
contents of the input register are transferred to the DAC register
of the corresponding channel, and the output updates. The
is taken low, the
LDAC
idle high behavior is shown in Figure 2.
Channel 0
LDAC
CS
pin is held low before the last rising edge of
When the
Channel 0 of the AD5770R sinks up to 60 mA and sources up to
300 mA of current. This channel has three different modes of
operation. The CH0_MODE bits in the OUTPUT_RANGE_CH0
register configure the different modes. The configuration options
for Channel 0 are listed in Table 8.
prior to the beginning of a new SPI transaction and the input
registers contents are modified, the update to the DAC output
happens when the LSB of the DAC input register is written. The
LDAC
idle low behavior is shown in Figure 2 and Figure 3.
LDAC
The
pin functionality can be masked for any or all
On power-up, Channel 0 defaults to the 0 mA to 300 mA range.
channels by configuring the corresponding HW_LDAC_
MASK_CHx bits high in the HW_LDAC register, which is
useful in cases where only a selection of channels are required to
update synchronously.
Channel 0 has a sinking only mode of −60 mA to 0 mA. In
this mode, the DAC has a zero-scale output of −60 mA and a
full-scale output of 0 mA. To enter this mode safely without
output glitches, the output must be shut down first by setting
CH0_SHUTDOWN_B high in the CHANNEL_CONFIG register.
LDAC
Software
It is possible to transfer data from any or all input registers to
the corresponding DAC registers with a write to the SW_LDAC
register, which is useful in cases where only a selection of channels
are required to update synchronously.
Channel 0 has a sourcing and sinking mode where the DAC has
a zero-scale output of −60 mA and a full-scale output of +300 mA.
To reduce glitches on the output of Channel 0, CH0_MODE
must be configured before taking the output out of shutdown.
Rev. 0 | Page 28 of 59
Data Sheet
AD5770R
Channel 1
Channel 3 to Channel 5
Channel 1 can be set up to source 0 mA to 140 mA or 0 mA to
250 mA. The full-scale output range for Channel 1 must be set
by writing to the CH1_MODE bits of the OUTPUT_RANGE_
CH1 register. In addition to the 0 mA to 250 mA range, Channel 1
has two 0 mA to 140 mA ranges; the channel can be set up to
optimize for better noise and PSRR or for reduced headroom.
The configuration options for Channel 1 are listed in Table 8.
Channel 3, Channel 4, and Channel 5 of the AD5770R can be set
up to source 0 mA to 45 mA or 0 mA to 100 mA. The full-scale
output rages for Channel 3, Channel 4, and Channel 5 must be
set by writing to the CH3_MODE, CH4_MODE, and
CH5_MODE bits of the OUTPUT_RANGE_CH3, OUTPUT_
RANGE_CH4, and OUTPUT_RANGE_CH5 registers. The
configuration options for Channel 3, Channel 4, and Channel 5
are listed in Table 8.
Channel 2
Channel 2 can be set up to source 0 mA to 55 mA or 0 mA to
150 mA. The full-scale output range for Channel 2 must be set
by writing to the CH2_MODE bits of the OUTPUT_RANGE_
CH2 register. Table 8 lists configuration options for Channel 2.
Table 8. Output Range Mode Register Setup
Minimum
Channel
Mode Bit Name Mode Zero-Scale Output (mA) Full-Scale Output (mA)1 Headroom (mV) Comments
Channel 0 CH0_MODE
0x0
0x1
0x2
0x1
0x2
0x3
0x0
0x1
0x0
0x1
0x0
0x1
0x0
0x1
0
300
0
450
02
−60
−60
0
0
0
0
0
0
0
0
0
0
0
300
140
140
250
55
150
45
100
45
4502
275
450
450
275
275
275
275
275
275
275
275
Channel 1 CH1_MODE
Low headroom
Low noise and PSRR
Channel 2 CH2_MODE
Channel 3 CH3_MODE
Channel 4 CH4_MODE
Channel 5 CH5_MODE
100
45
100
1 Output current scaling feature disabled. See the Output Current Scaling section for more information.
2 500 mV footroom from PVEE0 supply required when sinking current.
Rev. 0 | Page 29 of 59
AD5770R
Data Sheet
Background CRC Failure
OUTPUT FILTER
The AD5770R periodically performs a background cyclic
redundancy check (CRC) on the status of the on-chip registers to
ensure that the memory bits are not corrupted. In the unlikely
Each channel of the AD5770R has a user programmable variable
resistor in the output stage used for filtering. The output filter
resistor creates a low-pass RC filter with the 10 nF external
capacitor connected to the CDAMP_IDACx pin. The value loaded
into the OUTPUT_FILTER_CH0x register configures the value of
the variable resistor. Table 9 shows the cutoff frequency of each
resistor setting.
ALARM
event that the background CRC fails, the
pin activates
and the BACKGROUND_CRC_STATUS bit in the status
register is set high. Reading the status register deasserts the
ALARM
pin. A hardware or software reset is required to clear the
ALARM
BACKGROUND_CRC_STATUS bit. The
pin can be set
Table 9. IDACx Filter Bandwidth Control Settings
to ignore background CRC failures by setting the BACKGROUND
_CRC_ALARM_MASK bit of the ALARM_CONFIG register.
OUTPUT_FIILTER_CHx
Setting
Cutoff
Frequency
Resistor Value
60 Ω
5.6 kΩ
11.2 kΩ
22.2 kΩ
44.4 kΩ
104 kΩ
Overtemperature Warning and Shutdown
0x0
0x5
0x6
0x7
0x8
0x9
262 kHz
2.8 kHz
1.4 kHz
715 Hz
357 Hz
153 Hz
To protect the device from damage from overtemperature
occurrences during operation, the AD5770R has an
overtemperature warning alert and an overtemperature
shutdown alert.
When the internal die temperature reaches approximately
OUTPUT CURRENT SCALING
ALARM
125°C, the
bit in the status register is set high. The user must read the
ALARM
pin activates, and the TEMP_WARNING
When in current sourcing mode only, the full-scale output current
of each channel of the AD5770R can be scaled by up to ½ of the
nominal full-scale current and maintain 14-bit monotonicity.
status register to deassert the
When the internal die temperature reaches approximately 145°C,
ALARM
pin.
The full-scale output current of any channel can be scaled by
writing to the CHx_OUTPUT_SCALING bits of the OUTPUT_
RANGE_CHx register. The value loaded into the CHx_OUTPUT_
SCALING bits determines the multiplier, which scales the full-
scale current. The adjusted full-scale current of an IDACx channel
is calculated by,
the
OVER_TEMP bit in the status register is set. The user must
ALARM
pin activates (if not already activated) and the
read the status register to deassert the
pin.
If the THERMAL_SHUTDOWN_EN bit in the ALARM_
CONFIG register is set to high, the device shuts down the
output stages to protect from over temperature, and the outputs
remain shut down until the user initiates a software or hardware
reset to the device.
x
128
IADJ = INOM × 1−
(5)
The TEMP_WARNING and OVER_TEMP flags in the status
register clear when the device temperature returns below
approximately 120°C. To guarantee proper data downloads
from the internal memory, a reset function must not be
performed when the TEMP_WARNING bit in the status
register is high.
where:
I
I
ADJ is the adjusted full-scale output current.
NOM is the nominal full-scale output current.
x is the code loaded into output scaling register, 0 ≤ x ≤ 63.
Refer to Table 10 for a list of output current ranges achievable
using the scaling feature.
ALARM
The
pin can be set to ignore over temperature faults
ALARM
and over temperature warnings by setting the OVER_TEMP_
ALARM_MASK and TEMP_WARNING_ALARM_MASK bits
of the ALARM_CONFIG register.
The AD5770R provides a number of fault alerts that are signaled
via the
ALARM
ALARM
pin and the status register. The active low
pin can be configured as an open-drain output by setting the
OPEN_DRAIN_EN bit in the ALARM_CONFIG register,
allowing several devices to be connected together to one pull-up
resistor for global fault detection. Open drain mode on the
Negative Compliance Voltage
The compliance voltage on IDAC0 pin of the AD5770R can be a
negative value when sinking current. The AD5770R has a
negative compliance voltage alert feature to protect an external
unipolar ADC connected to the MUX_OUT pin.
ALARM
pin is disabled on power up.
The following sequence of events occurs if the user enables voltage
monitoring of Channel 0 when the voltage on IDAC0 is negative:
ALARM
1. The
pin activates.
2. The MUX_OUT pin is disabled.
3. The NEGATIVE_CHANNEL0 bit in the status register
is set.
Rev. 0 | Page 30 of 59
Data Sheet
AD5770R
ALARM
current that is too high and can damage the device. The AD5770R
incorporates an internal protection circuit that protects the device
if the reference current is too high.
The status register must be read to dessert the
pin.
The following sequence of events occurs if the voltage on IDAC0
goes negative after the user enables voltage monitoring of
Channel 0:
When the protection circuit detects a reference current that is
too high, the following events occur:
ALARM
1. The
pin activates.
1. This circuit switches to the internal RSET resistor.
2. The MUX_OUT pin is set to the same voltage as PVDD0.
3. The NEGATIVE_CHANNEL0 bit in the status register is set.
ALARM
2. The
pin activates.
3. The IREF_FAULT bit in the status register is set.
ALARM
The status register must be read to dessert the
pin.
ALARM
The user must then read the status register to deassert the
ALARM
The
pin can be set to ignore the negative compliance
voltage warning by setting the NEGATIVE_CHANNEL0_
ALARM_MASK bit of the ALARM_CONFIG register.
ALARM
pin. The
pin can be set to ignore IREF faults by setting
the IREF_FAULT_ALARM_MASK bit of the ALARM_CONFIG
register.
IREF Fault
When the external RSET resistor option is selected, it is important
that the value of this external RSET resistor cannot create a reference
Table 10. Full-Scale Output Current for All Scaling Code Values
Channel 0,
0 mA to
Channel 1,
0 mA to
Channel 1,
0 mA to
Channel 2,
0 mA to
Channel 2,
0 mA to
150 mA Range to 45 mA Range
Channel 3 to
Channel 5, 0 mA
Channel 3 to
Channel 5, 0 mA
to 100 mA Range
Scaling
Code
300 mA Range 140 mA Range 250 mA Range 55 mA Range
0
300
140
250
55
150
45
100
(Default)
1
2
3
4
5
6
7
8
298
295
293
291
288
286
284
281
279
277
274
272
270
267
265
263
260
258
255
253
251
248
246
244
241
239
237
234
232
230
227
225
139
138
137
136
135
133
132
131
130
129
128
127
126
125
124
123
121
120
119
118
117
116
115
114
113
112
110
109
108
107
106
105
248
246
244
242
240
238
236
234
232
230
229
227
225
223
221
219
217
215
213
211
209
207
205
203
201
199
197
195
193
191
189
188
55
54
54
53
53
52
52
52
51
51
50
50
49
49
49
48
48
47
47
46
46
46
45
45
44
44
43
43
43
42
42
41
149
148
146
145
144
143
142
141
139
138
137
136
135
134
132
131
130
129
128
127
125
124
123
122
121
120
118
117
116
115
114
113
45
44
44
44
43
43
43
42
42
41
41
41
40
40
40
39
39
39
38
38
38
37
37
37
36
36
36
35
35
34
34
34
99
98
98
97
96
95
95
94
93
92
91
91
90
89
88
88
87
86
85
84
84
83
82
81
80
80
79
78
77
77
76
75
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Rev. 0 | Page 31 of 59
AD5770R
Data Sheet
Channel 0,
0 mA to
Channel 1,
0 mA to
Channel 1,
0 mA to
Channel 2,
0 mA to
Channel 2,
0 mA to
150 mA Range to 45 mA Range
Channel 3 to
Channel 5, 0 mA
Channel 3 to
Channel 5, 0 mA
to 100 mA Range
Scaling
Code
300 mA Range 140 mA Range 250 mA Range 55 mA Range
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
223
220
218
216
213
211
209
206
204
202
199
197
195
192
190
188
185
183
180
178
176
173
171
169
166
164
162
159
157
155
152
104
103
102
101
100
98
97
96
95
94
93
92
91
90
89
88
86
85
84
83
82
81
80
79
78
77
75
74
73
72
71
186
184
182
180
178
176
174
172
170
168
166
164
162
160
158
156
154
152
150
148
146
145
143
141
139
137
135
133
131
129
127
41
40
40
40
39
39
38
38
37
37
37
36
36
35
35
34
34
34
33
33
32
32
31
31
31
30
30
29
29
28
28
111
110
109
108
107
105
104
103
102
101
100
98
97
96
95
94
93
91
90
89
33
33
33
32
32
32
31
31
31
30
30
30
29
29
28
28
28
27
27
27
26
26
26
25
25
25
24
24
24
23
23
74
73
73
72
71
70
70
69
68
67
66
66
65
64
63
63
62
61
60
59
59
58
57
56
55
55
54
53
52
52
51
88
87
86
84
83
82
81
80
79
77
76
Rev. 0 | Page 32 of 59
Data Sheet
AD5770R
APPLICATIONS INFORMATION
COMBINING CHANNELS TO INCREASE CURRENT
RANGE
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5770R is via a serial
bus that uses a standard protocol compatible with DSPs and
microcontrollers. The communications channel requires a
4-wire serial interface consisting of a clock signal, a data input
signal, a data output signal, and a synchronization signal.
The maximum current that can be sourced from IDAC0 is 300 mA.
It is possible to increase the current source capability by connecting
two channels directly together. Figure 77 shows IDAC1 combined
with IDAC2 to create a full-scale output current of 400 mA. When
channels are combined, care must be taken to ensure the following:
AD5770R TO SPI INTERFACE
•
The output compliance voltage stays within the range
specified in Table 1.
The SPI interface of the AD5770R is designed to be easily
connected to industry-standard DSPs and microcontrollers.
Figure 76 shows the AD5770R connected to the ADuCM320.
The ADuCM320 has an integrated SPI port that can be
connected directly to the SPI pins of the AD5770R.
•
The output voltage stays within the absolute maximum
ratings specified in Table 5.
PVDDx
250mA
IDAC1
ADuCM320
AD5770R
AD5770R
P0.3/IRQ0/CS0/PLACLK0/PLAI[3]
P0.0/SCLK0/PLAI[0]
CS
150mA
IDAC2
SCLK
SDI
400mA
P0.2/MOSI0/PLAI[2]
P0.1/MISO0/PLAI[1]
SDO
R
LOAD
P1.4/PWM2/SCLK1/PLAO[10]
P1.5/PWM3/MISO1/PLAO[11]
P1.6/PWM4/MOSI1/PLAO[12]
RESET
LDAC
ALARM
Figure 77. Increasing the Current Range by Summing Channels
Figure 76. ADuCM320 SPI Interface
LAYOUT GUIDELINES
Take careful consideration of the power supply and ground return
layout in order to ensure the rated performance. Design the PCB
on which the AD5770R is mounted so that the AD5770R lies on
the analog plane.
THERMAL CONSIDERATIONS
The AD5770R has a maximum junction temperature of 150°C (see
Table 5). To ensure reliable and specified operation over the lifetime
of the device, it is important that the AD5770R is not operated
under conditions that cause the junction temperature to exceed
150°C. The junction temperature is directly affected by the power
dissipated across the AD5770R and the ambient temperature.
The AD5770R must have an ample supply bypassing of 10 μF in
parallel with 0.1 μF on each supply, located as close to the package
as possible (ideally directly against the device). The 10 μF capacitors
are the tantalum bead type. The 0.1 μF capacitor must have low
effective series resistance (ESR) and low effective series inductance
(ESI). Common ceramic capacitors provide a low impedance
path to ground at high frequencies to handle transient currents,
due to internal logic switching.
Table 1 specifies the output current ranges for each AD5770R
channel and the maximum power supply voltages. Therefore, it
is important to understand the effects of power dissipation on
the package and the effects the package has on the junction
temperature. The AD5770R is packaged in a 49-ball, 4 mm ×
4 mm, wafer level chip scale packaging (WLCSP) package. The
thermal impedance, θJA, is specified in Table 6.
Ensure that the power supply line has as large a trace as possible
to provide a low impedance path and reduce glitch effects on the
supply line. Shield clocks and other fast switching digital signals
from other parts of the board by using a digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the ground
plane only, and the signal traces are placed on the solder side.
However, this technique is not always possible with a 2-layer board.
Table 11 provides examples of the maximum allowed power
dissipation and the maximum allowed ambient temperature
under certain conditions.
Rev. 0 | Page 33 of 59
AD5770R
Data Sheet
Because the AD5770R can dissipate a large amount of power, it is
recommended to provide some heat sinking capability to allow
power to dissipate easily.
If using an external RSET resistor, the low side of the RSET resistor
must be connected to REFGND before the connection to
AGND. Ensure that the width of the trace connecting RSET to
the IREF pin is as wide as possible to reduce the resistance and
the temperature coefficient of the trace.
For the WLCSP package, heat is transferred through the solder
balls to the PCB board. θJA thermal impedance is dependent on
board construction. More copper layers enable heat to be
removed more effectively.
Table 11. Thermal Considerations for 49-Ball WLCSP Package
Parameter
Description
Maximum Power Dissipation
Maximum allowed AD5770R power dissipation (PDISS) when operating at an ambient temperature of 105°C,
TJMAX −TA
150 −105
=
=1.5 W
θJA
30
Maximum Ambient
Temperature
Maximum allowed ambient temperature, when dissipating 1.985 W across the AD5770R:
JMAX – PDISS × θJA = 150 – (1.985 × 30) = 90.45°C
T
Power dissipation calculation example:
AVDD = DVDD = IOVDD = 3.3 V, PVDDx = 2.9 V
AVEE = PVEE0 = 0 V, RLOAD = 5 Ω per channel, AD5770R quiescent power dissipation = 110 mW
IDAC0 = 300 mA, power dissipation = 420 mW
IDAC1 = 250 mA, power dissipation = 412.5 mW
IDAC2 = 150 mA, power dissipation = 322.5 mW
IDAC3, IDAC4, IDAC5 = 100 mA, power dissipation = 720 mW
Total power dissipation = 110 mW + 1.875 W = 1.985 W
Rev. 0 | Page 34 of 59
Data Sheet
AD5770R
REGISTER SUMMARY
SPI CONFIGURATION REGISTERS
Table 12. AD5770R SPI Configuration Register Summary
Reg
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x00
INTERFACE_
CONFIG_A
[7:0]
SW_RESET_
MSB
Reserved
ADDR_
ASCENSION_
SDO_
ACTIVE_MSB
SDO_
ACTIVE_LSB
ADDR_
ASCENSION_
Reserved
SW_
RESET_
0x18
R/W
MSB
LSB
LSB
0x01
INTERFACE_
CONFIG_B
[7:0]
SINGLE_INST
Reserved
SHORT_
INSTRUCTION
Reserved
0x08
R/W
0x03
0x04
0x05
0x06
0x0A
0x0B
0x0C
0x0D
0x0E
0x10
CHIP_TYPE
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Reserved
CHIP_TYPE
0x08
0x04
0x40
0x00
0x00
0x82
0x56
0x04
0x00
0x20
R
PRODUCT_ID_L
PRODUCT_ID_H
CHIP_GRADE
SCRATCH_PAD
SPI_REVISION
VENDOR_L
PRODUCT_ID[7:0]
R
PRODUCT_ID[15:8]
R
GRADE
DEVICE_REVISION
R
VALUE
VERSION
VID[7:0]
VID[15:8]
LENGTH
R/W
R
R
VENDOR_H
R
STREAM_MODE
R/W
R
INTERFACE_
CONFIG_C
Reserved
STRICT_
REGISTER_
Reserved
ACCESS
0x11
INTERFACE_
STATUS_A
[7:0]
INTERFACE_
NOT_READY
Reserved
0x00
R
AD5770R CONFIGURATION REGISTERS
Table 13. AD5770R Configuration Register Summary
Reg Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset R/W
0x14 CHANNEL_ [7:0]
CONFIG
CH0_SINK_EN
Reserved CH5_
CH4_
CH3_
CH2_
CH1_
SHUTDOWN_B
CH0_
SHUTDOWN_B
0x80 R/W
SHUTDOWN_B SHUTDOWN_B SHUTDOWN_B SHUTDOWN_B
0x15 OUTPUT_
RANGE_
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
CH0_OUTPUT_SCALING
CH0_MODE
0x00 R/W
0x02 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x06 R/W
CH0
0x16 OUTPUT_
RANGE_
CH1_OUTPUT_SCALING
CH2_OUTPUT_SCALING
CH3_OUTPUT_SCALING
CH4_OUTPUT_SCALING
CH5_OUTPUT_SCALING
CH1_MODE
CH1
0x17 OUTPUT_
RANGE_
Reserved
Reserved
Reserved
Reserved
CH2_
MODE
CH2
0x18 OUTPUT_
RANGE_
CH3_
MODE
CH3
0x19 OUTPUT_
RANGE_
CH4_
MODE
CH4
0x1A OUTPUT_
RANGE_
CH5_
MODE
CH5
0x1B REFERENCE [7:0]
Reserved
REFERENCE_
RESISTOR_
SEL
REFERENCE_VOLTAGE_SEL
0x1C ALARM_
CONFIG
[7:0]
BACKGROUND_ IREF_
NEGATIVE_
CHANNEL0_
ALARM_
OVER_TEMP_ TEMP_
ALARM_MASK WARNING_
ALARM_
BACKGROUND_ THERMAL_
OPEN_
DRAIN_
EN
CRC_ALARM_
FAULT_
CRC_EN
SHUTDOWN_
MASK
ALARM_
EN
MASK
MASK
MASK
0x1D OUTPUT_
FILTER_
[7:0]
[7:0]
[7:0]
[7:0]
Reserved
OUTPUT_FILTER_RESISTOR0
OUTPUT_FILTER_RESISTOR1
OUTPUT_FILTER_RESISTOR2
OUTPUT_FILTER_RESISTOR3
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
CH0
0x1E OUTPUT_
FILTER_
Reserved
Reserved
Reserved
CH1
0x1F OUTPUT_
FILTER_
CH2
0x20 OUTPUT_
FILTER_
CH3
Rev. 0 | Page 35 of 59
AD5770R
Data Sheet
Reg Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset R/W
0x21 OUTPUT_
FILTER_
[7:0]
Reserved
OUTPUT_FILTER_RESISTOR4
OUTPUT_FILTER_RESISTOR5
MON_CH
0x00 R/W
CH4
0x22 OUTPUT_
FILTER_
[7:0]
Reserved
0x00 R/W
0x00 R/W
CH5
0x23 MONITOR_ [7:0]
SETUP
MON_FUNCTION
MUX_
BUFFER
IB_EXT_EN
0x24 STATUS
[7:0]
BACKGROUND_
CRC_STATUS
Reserved
IREF_FAULT
NEGATIVE_
CHANNEL0
OVER_TEMP
TEMP_
WARNING
0x00
R
0x25 HW_LDAC [7:0]
Reserved
HW_LDAC_
MASK_CH5
HW_LDAC_
MASK_CH4
HW_LDAC_
MASK_CH3
HW_LDAC_
MASK_CH2
HW_LDAC_
MASK_CH1
HW_LDAC_
MASK_CH0
0x00 R/W
0x26 CH0_DAC_ [7:0]
LSB
DAC_DATA0[5:0]
DAC_DATA1[5:0]
DAC_DATA2[5:0]
DAC_DATA3[5:0]
DAC_DATA4[5:0]
DAC_DATA5[5:0]
Reserved
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x27 CH0_DAC_ [7:0]
MSB
DAC_DATA0[13:6]
DAC_DATA1[13:6]
DAC_DATA2[13:6]
DAC_DATA3[13:6]
DAC_DATA4[13:6]
DAC_DATA5[13:6]
0x28 CH1_DAC_ [7:0]
LSB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x29 CH1_DAC_ [7:0]
MSB
0x2A CH2_DAC_ [7:0]
LSB
0x2B CH2_DAC_ [7:0]
MSB
0x2C CH3_DAC_ [7:0]
LSB
0x2D CH3_DAC_ [7:0]
MSB
0x2E CH4_DAC_ [7:0]
LSB
0x2F CH4_DAC_ [7:0]
MSB
0x30 CH5_DAC_ [7:0]
LSB
0x31 CH5_DAC_ [7:0]
MSB
0x32 DAC_PAGE [7:0]
DAC_PAGE_MASK[5:0]
_
MASK_LSB
0x33 DAC_PAGE [7:0]
DAC_PAGE_MASK[13:6]
0x00 R/W
_
MASK_MSB
0x34 CH_SELECT [7:0]
Reserved
Reserved
SEL_CH5
SEL_CH4
SEL_CH3
SEL_CH2
SEL_CH1
SEL_CH0
Reserved
0x00 R/W
0x00 R/W
0x35 INPUT_
PAGE_
[7:0]
[7:0]
[7:0]
INPUT_PAGE_MASK[5:0]
MASK_LSB
0x36 INPUT_
PAGE_
INPUT_PAGE_MASK[13:6]
0x00 R/W
MASK_MSB
0x37 SW_LDAC
SW_LDAC_
CH5
SW_LDAC_
CH4
SW_LDAC_
CH3
SW_LDAC_
CH2
SW_LDAC_
CH1
SW_LDAC_
CH0
0x00
W
0x38 CH0_INPUT [7:0]
_LSB
INPUT_DATA0[5:0]
INPUT_DATA1[5:0]
INPUT_DATA2[5:0]
INPUT_DATA3[5:0]
INPUT_DATA4[5:0]
Reserved
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x00 R/W
0x39 CH0_INPUT [7:0]
_MSB
INPUT_DATA0[13:6]
INPUT_DATA1[13:6]
INPUT_DATA2[13:6]
INPUT_DATA3[13:6]
0x3A CH1_INPUT [7:0]
_LSB
Reserved
Reserved
Reserved
Reserved
0x3B CH1_INPUT [7:0]
_MSB
0x3C CH2_INPUT [7:0]
_LSB
0x3D CH2_INPUT [7:0]
_MSB
0x3E CH3_INPUT [7:0]
_LSB
0x3F CH3_INPUT [7:0]
_MSB
0x40 CH4_INPUT [7:0]
_LSB
Rev. 0 | Page 36 of 59
Data Sheet
AD5770R
Reg Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset R/W
0x41 CH4_INPUT [7:0]
_MSB
INPUT_DATA4[13:6]
0x00 R/W
0x42 CH5_INPUT [7:0]
_LSB
INPUT_DATA5[5:0]
Reserved
0x00 R/W
0x00 R/W
0x43 CH5_INPUT [7:0]
_MSB
INPUT_DATA5[13:6]
0x44 RESERVED
[7:0]
RESERVED0
RESERVED1
0x3F
R
Rev. 0 | Page 37 of 59
AD5770R
Data Sheet
REGISTER DETAILS
Address: 0x00, Reset: 0x18, Name: INTERFACE_CONFIG_A
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
[7] SW_RESET_MSB (R/W)
Software Reset
[0] SW_RESET_LSB (R/W)
Software Reset
0: Do Nothing.
0: Do Nothing.
1: Initiates a Software Reset.
1: Initiates a Software Reset.
[6] RESERVED
[1] RESERVED
[5] ADDR_ASCENSION_MSB (R/W)
Address Ascension
[2] ADDR_ASCENSION_LSB (R/W)
Address Ascension
0: Address Decrement.
1: Address Increment.
0: Address Decrement.
1: Address Increment.
[4] SDO_ACTIVE_MSB (R)
[3] SDO_ACTIVE_LSB (R)
SDO Pin Active
SDO Pin Active
Table 14. Bit Descriptions for INTERFACE_CONFIG_A
Bits Bit Name
Description
Reset Access
7
SW_RESET_MSB
Software reset. Setting both software reset bits in a single SPI write performs a
software reset on the device, returning all registers except INTERFACE_CONFIG_A to
the default power-up state.
0x0
R/W
0: do nothing.
1: initiates a software reset.
Reserved.
6
5
Reserved
0x0
0x0
R
R/W
ADDR_ASCENSION_MSB Address Ascension. When set, this bit causes incrementing streaming addresses;
otherwise, decrementing addresses are generated. This must be a mirror of ADDR_
ASCENSION_LSB.
0: address decrement.
1: address increment.
4
3
2
SDO_ACTIVE_MSB
SDO_ACTIVE_LSB
SDO pin active. SDO pin enabled. This bit is always set.
SDO pin active. SDO pin enabled. This bit is always set.
0x1
0x1
0x0
R
R
ADDR_ASCENSION_LSB
Address ascension. When set, this bit causes incrementing streaming addresses;
otherwise, decrementing addresses are generated. This must be a mirror of ADDR_
ASCENSION_MSB.
R/W
0: address decrement.
1: address increment.
Reserved.
Software reset. Setting both software reset bits in a single SPI write performs a
software reset on the device, returning all registers except INTERFACE_CONFIG_A to
the default power up state.
1
0
Reserved
SW_RESET_LSB
0x0
0x0
R
R/W
0: do nothing.
1: initiates a software reset.
Address: 0x01, Reset: 0x08, Name: INTERFACE_CONFIG_B
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
[7] SINGLE_INST (R/W)
[2:0] RESERVED
Single Instruction
[3] SHORT_INSTRUCTION (R)
[6:4] RESERVED
Short Instruction
Table 15. Bit Descriptions for INTERFACE_CONFIG_B
Bits Bit Name Description
SINGLE_INST
Reset Access
7
Single instruction. When this bit is set, streaming mode is disable, and each SPI
transaction must specify the register address to access.
0x0
R/W
0: streaming mode enabled.
1: streaming mode disabled.
Reserved.
[6:4] Reserved
3
0x0
0x01
R
R
SHORT_INSTRUCTION Short instruction. When this bit is set, the address word must be 7 bits long.
Rev. 0 | Page 38 of 59
Data Sheet
AD5770R
Bits Bit Name
Description
Reset Access
[2:0] Reserved
Reserved.
0x0
R
Address: 0x03, Reset: 0x08, Name: CHIP_TYPE
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
[7:4] RESERVED
[3:0] CHIP_TYPE (R)
Chip Type
Table 16. Bit Descriptions for CHIP_TYPE
Bits
[7:4]
[3:0]
Bit Name
Reserved
CHIP_TYPE
Description
Reserved.
Reset
0x0
Access
R
R
Chip type. Precision DAC chip type = 0x08.
0x8
Address: 0x04, Reset: 0x04, Name: PRODUCT_ID_L
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[7:0] PRODUCT_ID[7:0] (R)
Product ID
Table 17. Bit Descriptions for PRODUCT_ID_L
Bits
Bit Name
Description
Reset
Access
[7:0]
PRODUCT_ID[7:0]
Product ID. AD5770R product ID = 0x4004.
0x4
R
Address: 0x05, Reset: 0x40, Name: PRODUCT_ID_H
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
[7:0] PRODUCT_ID[15:8] (R)
Product ID
Table 18. Bit Descriptions for PRODUCT_ID_H
Bits
Bit Name
Description
Reset
Access
[7:0]
PRODUCT_ID[15:8]
Product ID. AD5770R product ID = 0x4004.
0x40
R
Address: 0x06, Reset: 0x00, Name: CHIP_GRADE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] GRADE (R)
[3:0] DEVICE_REVISION (R)
Device Grade
Device Revision
Table 19. Bit Descriptions for CHIP_GRADE
Bits
[7:4]
[3:0]
Bit Name
Grade
DEVICE_REVISION
Description
Device grade
Device revision
Reset
0x0
0x0
Access
R
R
Address: 0x0A, Reset: 0x00, Name: SCRATCH_PAD
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VALUE (R/W)
Scratch Pad
Table 20. Bit Descriptions for SCRATCH_PAD
Bits
Bit Name
Description
Reset
Access
[7:0]
Value
Scratch pad. Use this is register to test communication with the device.
0x0
R/W
Rev. 0 | Page 39 of 59
AD5770R
Data Sheet
Address: 0x0B, Reset: 0x82, Name: SPI_REVISION
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
0
[7:0] VERSION (R)
SPI Standard Version
Table 21. Bit Descriptions for SPI_REVISION
Bits
Bit Name
Description
Reset
Access
[7:0]
Version
SPI standard version. Analog Devices SPI standard used.
0x82
R
Address: 0x0C, Reset: 0x56, Name: VENDOR_L
7
6
5
4
3
2
1
0
0
1
0
1
0
1
1
0
[7:0] VID[7:0] (R)
Manufacturer ID
Table 22. Bit Descriptions for VENDOR_L
Bits
[7:0]
Bit Name
VID[7:0]
Description
Manufacturer ID. Analog Devices ID = 0x0456.
Reset
0x56
Access
R
Address: 0x0D, Reset: 0x04, Name: VENDOR_H
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[7:0] VID[15:8] (R)
Manufacturer ID
Table 23. Bit Descriptions for VENDOR_H
Bits
[7:0]
Bit Name
VID[15:8]
Description
Manufacturer ID. Analog Devices ID = 0x0456.
Reset
0x4
Access
R
Address: 0x0E, Reset: 0x00, Name: STREAM_MODE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] LENGTH (R/W)
Stream Length
Table 24. Bit Descriptions for STREAM_MODE
Bits
Bit Name
Description
Reset
Access
[7:0]
LENGTH
Stream length. These bits set the length of registers addresses to increment/decrement when streaming
multiple bytes of data before looping back to the first register address. When the contents of this register
are cleared, register addresses increment/decrement when in streaming mode until the end of the
address space before looping to the last/first address and continuing to increment/decrement.
0x0
R/W
Address: 0x10, Reset: 0x20, Name: INTERFACE_CONFIG_C
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
[7:6] RESERVED
[4:0] RESERVED
[5] STRICT_REGISTER_ACCESS (R)
Strict Entity Access
Table 25. Bit Descriptions for INTERFACE_CONFIG_C
Bits
[7:6]
5
Bit Name
Reserved
Description
Reserved.
Reset
0x0
Access
R
R
STRICT_REGISTER_ACCESS
Strict register access. When this bit is set, all multibyte registers must be written to in a
single SPI transaction. The address used must be the address of the most significant
byte when address ascension is off or the address of the least significant byte when
address accession is on.
0x1
[4:0]
Reserved
Reserved.
0x0
R
Rev. 0 | Page 40 of 59
Data Sheet
AD5770R
Address: 0x11, Reset: 0x00, Name: INTERFACE_STATUS_A
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] INTERFACE_NOT_READY (R)
[6:0] RESERVED
Interface Not Ready
Table 26. Bit Descriptions for INTERFACE_STATUS_A
Bits Bit Name
Description
Reset Access
7
INTERFACE_NOT_READY Interface not ready. When this bit is set, the device is not ready to receive data on the
SPI bus.
0x0
R
[6:0] Reserved
Reserved.
0x0
R
Address: 0x14, Reset: 0x80, Name: CHANNEL_CONFIG
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7] CH0_SINK_EN (R/W)
Channel 0 Sink Current Generator
Enable
[0] CH0_SHUTDOWN_B (R/W)
Channel 0 Output Enable
0: Output Shutdown.
0: Disable.
1: Enable.
1: Normal Operation.
[1] CH1_SHUTDOWN_B (R/W)
Channel 1 Output Enable
0: Output Shutdown.
[6] RESERVED
[5] CH5_SHUTDOWN_B (R/W)
Channel 5 Output Enable
0: Output Shutdown.
1: Normal Operation.
[2] CH2_SHUTDOWN_B (R/W)
Channel 2 Output Enable
0: Output Shutdown.
1: Normal Operation.
[4] CH4_SHUTDOWN_B (R/W)
Channel 4 Output Enable
0: Output Shutdown.
1: Normal Operation.
[3] CH3_SHUTDOWN_B (R/W)
Channel 3 Output Enable
0: Output Shutdown.
1: Normal Operation.
1: Normal Operation.
Table 27. Bit Descriptions for CHANNEL_CONFIG
Bits Bit Name Description
Reset Access
7
CH0_SINK_EN
Channel 0 sink current generator enable. When this bit is set, Channel 0 sink current is
enabled.
0x1
R/W
0: disable.
1: enable.
Reserved.
6
5
Reserved
0x0
0x0
R
R/W
CH5_SHUTDOWN_B Channel 5 output enable. This active low enable bit shuts down the output of IDAC5
when asserted.
0: output shutdown.
1: normal operation.
4
3
2
1
0
CH4_SHUTDOWN_B Channel 4 output enable. This active low enable bit shuts down the output of IDAC4 when
asserted.
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
0: output shutdown.
1: normal operation.
CH3_SHUTDOWN_B Channel 3 output enable. This active low enable bit shuts down the output of IDAC3 when
asserted.
0: output shutdown.
1: normal operation.
CH2_SHUTDOWN_B Channel 2 output enable. This active low enable bit shuts down the output of IDAC2 when
asserted.
0: output shutdown.
1: normal operation.
CH1_SHUTDOWN_B Channel 1 output enable. This active low enable bit shuts down the output of IDAC1 when
asserted.
0: output shutdown.
1: normal operation.
CH0_SHUTDOWN_B Channel 0 output enable. This active low enable bit shuts down the output of IDAC0 when
asserted.
Rev. 0 | Page 41 of 59
AD5770R
Data Sheet
Bits Bit Name
Description
Reset Access
0: output shutdown.
1: normal operation.
Address: 0x15, Reset: 0x00, Name: OUTPUT_RANGE_CH0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] CH0_OUTPUT_SCALING (R/W)
Channel 0 Output Range Scaling
[1:0] CH0_MODE (R/W)
Channel 0 Output Range Mode
00: 0mA to 300mA.
01: -60mA to 0mA.
10: -60mA to 300mA.
Table 28. Bit Descriptions for OUTPUT_RANGE_CH0
Bits Bit Name
Description
Reset Access
[7:2] CH0_OUTPUT_SCALING Channel 0 output range scaling. These bits set the output range scaling factor for
Channel 0. Output scaling must only be used when in a sourcing current mode.
0x0
R/W
[1:0] CH0_MODE
Channel 0 output range mode. These bits select the output range mode for Channel 0.
0x0
R/W
00: 0 mA to 300 mA.
01: −60 mA to 0 mA.
10: −60 mA to +300 mA.
Address: 0x16, Reset: 0x02, Name: OUTPUT_RANGE_CH1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[7:2] CH1_OUTPUT_SCALING (R/W)
[1:0] CH1_MODE (R/W)
Channel 1 Output Range Scaling
Channel 1 Output Range Mode
01: 0mA to 140mA - Low Headroom.
10: 0mA to 140mA - Low Noise.
11: 0mA to 250mA.
Table 29. Bit Descriptions for OUTPUT_RANGE_CH1
Bits Bit Name
Description
Reset Access
[7:2] CH1_OUTPUT_SCALING Channel 1 output range scaling. These bits set the output range scaling factor for
Channel 1.
0x0
R/W
[1:0] CH1_MODE
Channel 1 output range mode. These bits select the output range mode for Channel 1.
01: 0 mA to 140 mA low headroom.
0x2
R/W
10: 0 mA to 140 mA low noise.
11: 0 mA to 250 mA.
Address: 0x17, Reset: 0x00, Name: OUTPUT_RANGE_CH2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] CH2_OUTPUT_SCALING (R/W)
Channel 2 Output Range Scaling
[0] CH2_MODE (R/W)
Channel 2 Output Range Mode
0: 0mA to 55mA.
[1] RESERVED
1: 0mA to 150mA.
Table 30. Bit Descriptions for OUTPUT_RANGE_CH2
Bits Bit Name
Description
Reset Access
[7:2] CH2_OUTPUT_SCALING Channel 2 output range scaling. These bits set the output range scaling factor for
Channel 2.
0x0
R/W
1
0
Reserved
CH2_MODE
Reserved.
0x0
0x0
R
R/W
Channel 2 output range mode. This bit selects the output range mode for Channel 2.
0: 0 mA to 55 mA.
1: 0 mA to 150 mA.
Rev. 0 | Page 42 of 59
Data Sheet
AD5770R
Address: 0x18, Reset: 0x00, Name: OUTPUT_RANGE_CH3
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] CH3_OUTPUT_SCALING (R/W)
Channel 3 Output Range Scaling
[0] CH3_MODE (R/W)
Channel 3 Output Range Mode
0: 0mA to 45mA.
[1] RESERVED
1: 0mA to 100mA.
Table 31. Bit Descriptions for OUTPUT_RANGE_CH3
Bits Bit Name
Description
Reset Access
[7:2] CH3_OUTPUT_SCALING Channel 3 output range scaling. These bits set the output range scaling factor for
Channel 3.
0x0
R/W
1
0
Reserved
CH3_MODE
Reserved.
0x0
0x0
R
R/W
Channel 3 output range mode. This bit selects the output range mode for Channel 3.
0: 0 mA to 45 mA.
1: 0 mA to 100 mA.
Address: 0x19, Reset: 0x00, Name: OUTPUT_RANGE_CH4
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] CH4_OUTPUT_SCALING (R/W)
Channel 4 Output Range Scaling
[0] CH4_MODE (R/W)
Channel 4 Output Range Mode
0: 0mA to 45mA.
[1] RESERVED
1: 0mA to 100mA.
Table 32. Bit Descriptions for OUTPUT_RANGE_CH4
Bits Bit Name
Description
Reset Access
[7:2] CH4_OUTPUT_SCALING Channel 4 output range scaling. These bits set the output range scaling factor for
Channel 4.
0x0
R/W
1
0
Reserved
CH4_MODE
Reserved.
0x0
0x0
R
R/W
Channel 4 output range mode. This bit selects the output range mode for Channel 4.
0: 0 mA to 45 mA.
1: 0 mA to 100 mA.
Address: 0x1A, Reset: 0x00, Name: OUTPUT_RANGE_CH5
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] CH5_OUTPUT_SCALING (R/W)
Channel 5 Output Range Scaling
[0] CH5_MODE (R/W)
Channel 5 Output Range Mode
0: 0mA to 45mA.
[1] RESERVED
1: 0mA to 100mA.
Table 33. Bit Descriptions for OUTPUT_RANGE_CH5
Bits Bit Name
Description
Reset Access
[7:2] CH5_OUTPUT_SCALING Channel 5 output range scaling. These bits set the output range scaling factor for
Channel 5.
0x0
R/W
1
0
Reserved
CH5_MODE
Reserved.
0x0
0x0
R
R/W
Channel 5 output range mode. This bit selects the output range mode for Channel 5.
0: 0 mA to 45 mA.
1: 0 mA to 100 mA.
Rev. 0 | Page 43 of 59
AD5770R
Data Sheet
Address: 0x1B, Reset: 0x00, Name: REFERENCE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:3] RESERVED
[1:0] REFERENCE_VOLTAGE_SEL (R/W)
Voltage Reference Setup
00: External 2.5V.
01: Internal 1.25V (Reference Output
On)
[2] REFERENCE_RESISTOR_SEL (R/W)
IREF Resistor Setup
0: Internal Resistor.
1: External Resistor.
10: External 1.25V.
11: Internal 1.25V (Reference Output
Off)
Table 34. Bit Descriptions for REFERENCE
Bits Bit Name
Description
Reset Access
[7:3] Reserved
Reserved.
0x0
0x0
R
R/W
2
REFERENCE_RESISTOR_SEL IREF resistor setup. This bit selects whether an internal or external resistor is used
for reference current generation.
0: internal resistor.
1: external resistor.
[1:0] REFERENCE_VOLTAGE_SEL
Voltage reference setup. These bits select the voltage reference scheme used for
reference current generation.
0x0
R/W
00: external 2.5 V.
01: internal 1.25 V (reference output on).
10: external 1.25 V.
11: internal 1.25 V (reference output off).
Address: 0x1C, Reset: 0x06, Name: ALARM_CONFIG
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
0
[7] BACKGROUND_CRC_ALARM_MASK (R/W)
Background CRC Alarm Mask
0: Normal Operation.
[0] OPEN_DRAIN_EN (R/W)
Open Drain ALARM Enable
0: ALARM Open Drain Disable.
1: ALARM Open Drain Enable.
1: Mask Background CRC ALARM Activation.
[6] IREF_FAULT_ALARM_MASK (R/W)
External IREF Resistor Fault Alarm
Mask
[1] THERMAL_SHUTDOWN_EN (R/W)
Thermal Shutdown Enable
0: Disable Thermal Shutdown - Not
Recommended.
0: Normal Operation.
1: Mask IREF Fault ALARM Activation.
1: Enable Thermal Shutdown.
[5] NEGATIVE_CHANNEL0_ALARM_MASK (R/W)
Negative Voltage Channel 0 Fault
Alarm Mask
[2] BACKGROUND_CRC_EN (R/W)
Background CRC Enable
0: Disable Background CRC.
1: Enable Background CRC.
0: Normal Operation.
1: Mask Negative Channel 0 ALARM
Activation.
[3] TEMP_WARNING_ALARM_MASK (R/W)
Over-Temperature Warning Alarm
Mask
0: Normal Operation.
1: Mask Temperature Warning ALARM
Activation.
[4] OVER_TEMP_ALARM_MASK (R/W)
Over-Temperature Fault Alarm Mask
0: Normal Operation.
1: Mask Over Temperature ALARM Activation.
Table 35. Bit Descriptions for ALARM_CONFIG
Bits Bit Name
Description
Reset Access
7
BACKGROUND_CRC_ALARM_MASK
Background CRC alarm mask. When this bit is set, the ALARM pin does
not activate for background CRC errors.
0x0
R/W
0: normal operation.
1: mask background CRC ALARM activation.
6
IREF_FAULT_ALARM_MASK
External IREF resistor fault alarm mask. When this bit is set, the ALARM pin
does not activate for external reference current generation resistor faults.
0: normal operation.
0x0
R/W
1: mask IREF fault ALARM activation.
Rev. 0 | Page 44 of 59
Data Sheet
AD5770R
Bits Bit Name
Description
Reset Access
5
NEGATIVE_CHANNEL0_ALARM_MASK Negative Voltage Channel 0 fault alarm mask. When this bit is set, the
ALARM pin does not activate when a negative voltage is multiplexed to
the MUX_OUT pin due to monitoring Channel 0.
0x0
R/W
0: normal operation.
1: mask negative Channel 0 ALARM activation.
4
3
OVER_TEMP_ALARM_MASK
Overtemperature fault alarm mask. When this bit is set, the ALARM pin
does not activate for an overtemperature fault occurrence.
0: normal operation.
0x0
0x0
R/W
R/W
1: mask overtemperature ALARM activation.
TEMP_WARNING_ALARM_MASK
Overtemperature warning alarm mask. When this bit is set, the ALARM
pin does not activate for an overtemperature warning occurrence.
0: normal operation.
1: mask temperature warning ALARM activation.
2
1
0
BACKGROUND_CRC_EN
THERMAL_SHUTDOWN_EN
OPEN_DRAIN_EN
Background CRC enable. When this bit is set, a CRC of the memory map
contents is periodically computed by the device.
0: disable background CRC.
1: enable background CRC.
Thermal shutdown enable. When this bit is set, the AD5770R goes into
thermal shutdown in the event of an overtemperature fault.
0: disable thermal shutdown (not recommended).
1: enable thermal shutdown.
0x1
0x1
0x0
R/W
R/W
R/W
Open-drain ALARM enable. When this bit is set, the ALARM pin is
configured as an open-drain output.
0: ALARM open-drain disable.
1: ALARM open-drain enable.
Address: 0x1D, Reset: 0x00, Name: OUTPUT_FILTER_CH0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] OUTPUT_FILTER_RESISTOR0 (R/W)
Output Filter Resistor Setup Channel 0
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 KΩ.
1001: 104 KΩ.
Table 36. Bit Descriptions for OUTPUT_FILTER_CH0
Bits Bit Name
Description
Reset Access
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] OUTPUT_FILTER_RESISTOR0 Output Filter Resistor Setup Channel 0. These bits select the internal variable
resistor to be used for the output filter on Channel 0. The output filter resistor
creates a resistor capacitor filter with the external capacitor connected to the
CDAMP_IDAC0 pin.
R/W
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Rev. 0 | Page 45 of 59
AD5770R
Data Sheet
Address: 0x1E, Reset: 0x00, Name: OUTPUT_FILTER_CH1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] OUTPUT_FILTER_RESISTOR1 (R/W)
Output Filter Resistor Setup Channel 1
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Table 37. Bit Descriptions for OUTPUT_FILTER_CH1
Bits Bit Name
Description
Reset Access
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] OUTPUT_FILTER_RESISTOR1 Output Filter Resistor Setup Channel 1. These bits select the internal variable
resistor to be used for the output filter on Channel 1. The output filter resistor
creates a resistor capacitor filter with the external capacitor connected to the
CDAMP_IDAC1 pin.
R/W
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Address: 0x1F, Reset: 0x00, Name: OUTPUT_FILTER_CH2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] OUTPUT_FILTER_RESISTOR2 (R/W)
Output Filter Resistor Setup Channel 2
0000: 60 Ω.
0101: 5.6 KΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Table 38. Bit Descriptions for OUTPUT_FILTER_CH2
Bits Bit Name
Description
Reset Access
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] OUTPUT_FILTER_RESISTOR2 Output Filter Resistor Setup Channel 2. These bits select the internal variable
resistor to be used for the output filter on Channel 2. The output filter resistor
creates a resistor capacitor filter with the external capacitor connected to the
CDAMP_IDAC2 pin.
R/W
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Rev. 0 | Page 46 of 59
Data Sheet
AD5770R
Address: 0x20, Reset: 0x00, Name: OUTPUT_FILTER_CH3
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] OUTPUT_FILTER_RESISTOR3 (R/W)
Output Filter Resistor Setup Channel 3
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Table 39. Bit Descriptions for OUTPUT_FILTER_CH3
Bits Bit Name
Description
Reset Access
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] OUTPUT_FILTER_RESISTOR3 Output Filter Resistor Setup Channel 3. These bits select the internal variable
resistor to be used for the output filter on Channel 3. The output filter resistor
creates a resistor capacitor filter with the external capacitor connected to the
CDAMP_IDAC3 pin.
R/W
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Address: 0x21, Reset: 0x00, Name: OUTPUT_FILTER_CH4
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] OUTPUT_FILTER_RESISTOR4 (R/W)
Output Filter Resistor Setup Channel 4
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Table 40. Bit Descriptions for OUTPUT_FILTER_CH4
Bits Bit Name
Description
Reset Access
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] OUTPUT_FILTER_RESISTOR4 Output Filter Resistor Setup Channel 4. These bits select the internal variable
resistor to be used for the output filter on Channel 4. The output filter resistor
creates a resistor capacitor filter with the external capacitor connected to the
CDAMP_IDAC4 pin.
R/W
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Rev. 0 | Page 47 of 59
AD5770R
Data Sheet
Address: 0x22, Reset: 0x00, Name: OUTPUT_FILTER_CH5
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] OUTPUT_FILTER_RESISTOR5 (R/W)
Output Filter Resistor Setup Channel 5
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Table 41. Bit Descriptions for OUTPUT_FILTER_CH5
Bits Bit Name
Description
Reset Access
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] OUTPUT_FILTER_RESISTOR5 Output Filter Resistor Setup Channel 5. These bits select the internal variable
resistor to be used for the output filter on Channel 5. The output filter resistor
creates a resistor capacitor filter with the external capacitor connected to the
CDAMP_IDAC5 pin.
R/W
0000: 60 Ω.
0101: 5.6 kΩ.
0110: 11.2 kΩ.
0111: 22.2 kΩ.
1000: 44.4 kΩ.
1001: 104 kΩ.
Address: 0x23, Reset: 0x00, Name: MONITOR_SETUP
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] MON_FUNCTION (R/W)
Monitor Function Setup
0: Disable.
[3:0] MON_CH (R/W)
Monitor Channel Setup
0: Channel 0.
1: Voltage Monitoring.
10: Current Monitoring.
11: Temperature Monitoring.
1: Channel 1.
10: Channel 2.
11: Channel 3.
100: Channel 4.
101: Channel 5.
[5] MUX_BUFFER (R/W)
Multiplexer Buffer Setup
0: Bypass.
[4] IB_EXT_EN (R/W)
1: Enable.
Temperature Diode External Bias
Current Enable
0: Internal Bias Current.
1: External Bias Current.
Table 42. Bit Descriptions for MONITOR_SETUP
Bits Bit Name
Description
Reset Access
[7:6] MON_FUNCTION Monitor function setup. These bits configure which on-chip diagnostic function is selected.
0x0
R/W
0: disable.
1: voltage monitoring.
10: current monitoring.
11: temperature monitoring.
5
4
MUX_BUFFER
IB_EXT_EN
Multiplexer buffer setup. When this bit is set, the multiplexer buffer is enabled and used to
buffer the multiplexer output. Clearing this bit disables the buffer and bypasses it.
0: bypass.
1: enable.
0x0
0x0
R/W
R/W
Temperature diode external bias current enable. When this bit is set, an internal bias current
for the temperature monitoring diode is shut off. This bias current must then be supplied
externally.
0: internal bias current.
1: external bias current.
Rev. 0 | Page 48 of 59
Data Sheet
AD5770R
Bits Bit Name
Description
Reset Access
[3:0] MON_CH
Monitor channel setup. These bits select the channel to be monitored when output voltage
or output current diagnostics are enabled.
0x0
R/W
0: Channel 0.
1: Channel 1.
10: Channel 2.
11: Channel 3.
100: Channel 4.
101: Channel 5.
Address: 0x24, Reset: 0x00, Name: STATUS
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] BACKGROUND_CRC_STATUS (R)
[0] TEMP_WARNING (R)
Background CRC Status
Overtemperature Warning Status
[6:4] RESERVED
[1] OVER_TEMP (R)
Overtemperature Fault Status
[3] IREF_FAULT (R)
External IREF Resistor Fault Status
[2] NEGATIVE_CHANNEL0 (R)
Negative Voltage Channel 0 Status
Table 43. Bit Descriptions for STATUS
Bits Bit Name Description
Reset Access
7
BACKGROUND_CRC_STATUS Background CRC status. Read only status bit. When this bit is high, this signifies
that a background CRC of the memory map has failed and a memory bit may
have inadvertently flipped.
0x0
R
0: normal.
1: background CRC error activated.
[6:4] Reserved
Reserved.
0x0
0x0
R
R
3
2
1
IREF_FAULT
External IREF resistor fault status. Read only status bit. When this bit is set, a fault
has been detected with the external reference current generation resistor, and
the internal resistor has been switched to avoid damage to the device.
0: normal.
1: IREF fault activated.
NEGATIVE_CHANNEL0
OVER_TEMP
Negative Voltage Channel 0 status. Read only status bit. When this bit is set, a
fault has been detected due to a negative voltage being multiplexed to the
MUX_OUT pin when monitoring Channel 0.
0: normal.
1: negative Channel 0 activated.
0x0
0x0
R
R
Overtemperature fault status. Read only status bit. When this bit is set, an
overtemperature fault occurrence has been detected. An overtemperature fault
occurs when the internal die temperature reaches approximately 145°C. A reset
command must be issued to the device to clear this bit.
0: normal.
1: overtemperature activated.
0
TEMP_WARNING
Overtemperature warning status. Read only status bit. When this bit is set, an
overtemperature warning occurrence has been detected. An overtemperature
warning occurs when the internal die temperature reaches approximately 125°C. This
bit is automatically cleared when the internal die temperature returns below 120°C.
0x0
R
0: normal.
1: temperature warning activated.
Rev. 0 | Page 49 of 59
AD5770R
Data Sheet
Address: 0x25, Reset: 0x00, Name: HW_LDAC
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[0] HW_LDAC_MASK_CH0 (R/W)
Hardware LDAC Mask Channel 0
0: No Operation.
[5] HW_LDAC_MASK_CH5 (R/W)
Hardware LDAC Mask Channel 5
0: No Operation.
1: Mask LDAC on Channel 0.
1: Mask LDAC on Channel 5.
[1] HW_LDAC_MASK_CH1 (R/W)
Hardware LDAC Mask Channel 1
0: No Operation.
[4] HW_LDAC_MASK_CH4 (R/W)
Hardware LDAC Mask Channel 4
0: No Operation.
1: Mask LDAC on Channel 1.
1: Mask LDAC on Channel 4.
[2] HW_LDAC_MASK_CH2 (R/W)
Hardware LDAC Mask Channel 2
0: No Operation.
[3] HW_LDAC_MASK_CH3 (R/W)
Hardware LDAC Mask Channel 3
0: No Operation.
1: Mask LDAC on Channel 2.
1: Mask LDAC on Channel 3.
Table 44. Bit Descriptions for HW_LDAC
Bits Bit Name
Description
Reset Access
[7:6] RESERVED
Reserved.
0x0
R
5
4
3
2
1
0
HW_LDAC_MASK_CH5 Hardware LDAC Mask Channel 5. When this bit is set, activity on the LDAC pin is ignored for 0x0
R/W
Channel 5.
0: no operation.
1: mask LDAC on Channel 5.
HW_LDAC_MASK_CH4 Hardware LDAC Mask Channel 4. When this bit is set, activity on the LDAC pin is ignored for 0x0
R/W
R/W
R/W
R/W
R/W
Channel 4.
0: no operation.
1: mask LDAC on Channel 4.
HW_LDAC_MASK_CH3 Hardware LDAC Mask Channel 3. When this bit is set, activity on the LDAC pin is ignored for 0x0
Channel 3.
0: no operation.
1: mask LDAC on Channel 3.
HW_LDAC_MASK_CH2 Hardware LDAC Mask Channel 2. When this bit is set, activity on the LDAC pin is ignored for 0x0
Channel 2.
0: no operation.
1: mask LDAC on Channel 2.
HW_LDAC_MASK_CH1 Hardware LDAC Mask Channel 1. When this bit is set, activity on the LDAC pin is ignored for 0x0
Channel 1.
0: no operation.
1: mask LDAC on Channel 1.
HW_LDAC_MASK_CH0 Hardware LDAC Mask Channel 0. When this bit is set, activity on the LDAC pin is ignored for 0x0
Channel 0.
0: no operation.
1: mask LDAC on Channel 0.
Address: 0x26, Reset: 0x00, Name: CH0_DAC_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] DAC_DATA0[5:0] (R/W)
Channel 0 DAC Data
[1:0] RESERVED
Table 45. Bit Descriptions for CH0_DAC_LSB
Bits
[7:2]
[1:0]
Bit Name
DAC_DATA0[5:0]
RESERVED
Description
Reset
0x0
Access
R/W
R
Channel 0 DAC data. These bits are the DAC code loaded into the DAC register for IDAC0.
Reserved.
0x0
Rev. 0 | Page 50 of 59
Data Sheet
AD5770R
Address: 0x27, Reset: 0x00, Name: CH0_DAC_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] DAC_DATA0[13:6] (R/W)
Channel 0 DAC Data
Table 46. Bit Descriptions for CH0_DAC_MSB
Bits
Bit Name
Description
Reset
Access
[7:0]
DAC_DATA0[13:6]
Channel 0 DAC data. These bits are the DAC code loaded into the DAC register for IDAC0.
0x0
R/W
Address: 0x28, Reset: 0x00, Name: CH1_DAC_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] DAC_DATA1[5:0] (R/W)
Channel 1 DAC Data
[1:0] RESERVED
Table 47. Bit Descriptions for CH1_DAC_LSB
Bits
[7:2]
[1:0]
Bit Name
DAC_DATA1[5:0]
Reserved
Description
Reset
0x0
0x0
Access
R/W
R
Channel 1 DAC data. These bits are the DAC code loaded into the DAC register for IDAC1.
Reserved.
Address: 0x29, Reset: 0x00, Name: CH1_DAC_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] DAC_DATA1[13:6] (R/W)
Channel 1 DAC Data
Table 48. Bit Descriptions for CH1_DAC_MSB
Bits
Bit Name
Description
Reset
Access
[7:0]
DAC_DATA1[13:6]
Channel 1 DAC data. These bits are the DAC code loaded into the DAC register for IDAC1.
0x0
R/W
Address: 0x2A, Reset: 0x00, Name: CH2_DAC_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] DAC_DATA2[5:0] (R/W)
Channel 2 DAC Data
[1:0] RESERVED
Table 49. Bit Descriptions for CH2_DAC_LSB
Bits
[7:2]
[1:0]
Bit Name
DAC_DATA2[5:0]
Reserved
Description
Reset
0x0
Access
R/W
R
Channel 2 DAC Data. These bits are the DAC code loaded into the DAC register for IDAC2.
Reserved.
0x0
Address: 0x2B, Reset: 0x00, Name: CH2_DAC_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] DAC_DATA2[13:6] (R/W)
Channel 2 DAC Data
Table 50. Bit Descriptions for CH2_DAC_MSB
Bits
Bit Name
Description
Reset
Access
[7:0]
DAC_DATA2[13:6]
Channel 2 DAC data. These bits are the DAC code loaded into the DAC register for IDAC2.
0x0
R/W
Rev. 0 | Page 51 of 59
AD5770R
Data Sheet
Address: 0x2C, Reset: 0x00, Name: CH3_DAC_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] DAC_DATA3[5:0] (R/W)
Channel 3 DAC Data
[1:0] RESERVED
Table 51. Bit Descriptions for CH3_DAC_LSB
Bits
[7:2]
[1:0]
Bit Name
DAC_DATA3[5:0]
Reserved
Description
Reset
0x0
Access
R/W
R
Channel 3 DAC data. These bits are the DAC code loaded into the DAC register for IDAC3.
Reserved.
0x0
Address: 0x2D, Reset: 0x00, Name: CH3_DAC_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] DAC_DATA3[13:6] (R/W)
Channel 3 DAC Data
Table 52. Bit Descriptions for CH3_DAC_MSB
Bits
Bit Name
Description
Reset
Access
[7:0]
DAC_DATA3[13:6]
Channel 3 DAC data. These bits are the DAC code loaded into the DAC register for IDAC3.
0x0
R/W
Address: 0x2E, Reset: 0x00, Name: CH4_DAC_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] DAC_DATA4[5:0] (R/W)
Channel 4 DAC Data
[1:0] RESERVED
Table 53. Bit Descriptions for CH4_DAC_LSB
Bits
[7:2]
[1:0]
Bit Name
DAC_DATA4[5:0]
Reserved
Description
Reset
0x0
0x0
Access
R/W
R
Channel 4 DAC data. These bits are the DAC code loaded into the DAC register for IDAC4.
Reserved.
Address: 0x2F, Reset: 0x00, Name: CH4_DAC_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] DAC_DATA4[13:6] (R/W)
Channel 4 DAC Data
Table 54. Bit Descriptions for CH4_DAC_MSB
Bits
Bit Name
Description
Reset
Access
[7:0]
DAC_DATA4[13:6]
Channel 4 DAC data. These bits are the DAC code loaded into the DAC register for
IDAC4.
0x0
R/W
Address: 0x30, Reset: 0x00, Name: CH5_DAC_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] DAC_DATA5[5:0] (R/W)
Channel 5 DAC Data
[1:0] RESERVED
Table 55. Bit Descriptions for CH5_DAC_LSB
Bits
[7:2]
[1:0]
Bit Name
DAC_DATA5[5:0]
Reserved
Description
Reset
0x0
Access
R/W
R
Channel 5 DAC data. These bits are the DAC code loaded into the DAC register for IDAC5.
Reserved.
0x0
Rev. 0 | Page 52 of 59
Data Sheet
AD5770R
Address: 0x31, Reset: 0x00, Name: CH5_DAC_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] DAC_DATA5[13:6] (R/W)
Channel 5 DAC Data
Table 56. Bit Descriptions for CH5_DAC_MSB
Bits
[7:0]
Bit Name
DAC_DATA5[13:6]
Description
Reset
0x0
Access
R/W
Channel 5 DAC data. These bits are the DAC code loaded into the DAC register for IDAC5.
Address: 0x32, Reset: 0x00, Name: DAC_PAGE_MASK_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] DAC_PAGE_MASK[5:0] (R/W)
[1:0] RESERVED
Page Mask DAC Data
Table 57. Bit Descriptions for DAC_PAGE_MASK_LSB
Bits Bit Name
Description
Reset Access
[7:2] DAC_PAGE_MASK[5:0] Page mask DAC data. Following a write to this register, the DAC code loaded into this
register is copied into the DAC register of any channels selected in the CH_SELECT register.
0x0
R/W
[1:0] Reserved
Reserved.
0x0
R
Address: 0x33, Reset: 0x00, Name: DAC_PAGE_MASK_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] DAC_PAGE_MASK[13:6] (R/W)
Page Mask DAC Data
Table 58. Bit Descriptions for DAC_PAGE_MASK_MSB
Bits Bit Name
Description
Reset Access
0x0 R/W
[7:0] DAC_PAGE_MASK[13:6] Page mask DAC data. Following a write to this register, the DAC code loaded into this
register is copied into the DAC register of any channels selected in the CH_SELECT register.
Address: 0x34, Reset: 0x00, Name: CH_SELECT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[0] SEL_CH0 (R/W)
Select Channel 0
0: No Operation.
1: Copy to Channel 0.
[5] SEL_CH5 (R/W)
Select Channel 5
0: No Operation.
1: Copy to Channel 5.
[1] SEL_CH1 (R/W)
Select Channel 1
0: No Operation.
1: Copy to Channel 1.
[4] SEL_CH4 (R/W)
Select Channel 4
0: No Operation.
1: Copy to Channel 4.
[2] SEL_CH2 (R/W)
Select Channel 2
0: No Operation.
1: Copy to Channel 2.
[3] SEL_CH3 (R/W)
Select Channel 3
0: No Operation.
1: Copy to Channel 3.
Table 59. Bit Descriptions for CH_SELECT
Bits Bit Name
Description
Reset Access
[7:6] Reserved
Reserved.
0x0
0x0
R
5
SEL_CH5
Select Channel 5. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to
the INPUT_DATA5 bits and data written to the DAC_PAGE_MASK register is copied to the
DAC_DATA5 bits.
R/W
0: no operation.
1: copy to Channel 5.
Rev. 0 | Page 53 of 59
AD5770R
Data Sheet
Bits Bit Name
Description
Reset Access
4
3
2
1
0
SEL_CH4
SEL_CH3
SEL_CH2
SEL_CH1
SEL_CH0
Select Channel 4. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to
the INPUT_DATA4 bits and data written to the DAC_PAGE_MASK register is copied to the
DAC_DATA4 bits.
0: no operation.
1: copy to Channel 4.
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
Select Channel 3. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to
the INPUT_DATA3 bits and data written to the DAC_PAGE_MASK register is copied to the
DAC_DATA3 bits.
0: no operation.
1: copy to Channel 3.
Select Channel 2. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to
the INPUT_DATA2 bits and data written to the DAC_PAGE_MASK register is copied to the
DAC_DATA2 bits.
0: no operation.
1: copy to Channel 2.
Select Channel 1. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to
the INPUT_DATA1 bits and data written to the DAC_PAGE_MASK register is copied to the
DAC_DATA1 bits.
0: no operation.
1: copy to Channel 1.
Select Channel 0. When this bit is set, data written to the INPUT_PAGE_MASK register is copied to
the INPUT_DATA0 bits and data written to the DAC_PAGE_MASK register is copied to the
DAC_DATA0 bits.
0: no operation.
1: copy to Channel 0.
Address: 0x35, Reset: 0x00, Name: INPUT_PAGE_MASK_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] INPUT_PAGE_MASK[5:0] (R/W)
[1:0] RESERVED
Input Data Page Mask
Table 60. Bit Descriptions for INPUT_PAGE_MASK_LSB
Bits Bit Name
Description
Reset Access
[7:2] INPUT_PAGE_MASK[5:0] Input data page mask. Following a write to this register, the DAC code loaded into this
0x0
R/W
register is copied into the input register of any channels selected in the CH_SELECT
register.
[1:0] Reserved
Reserved.
0x0
R
Address: 0x36, Reset: 0x00, Name: INPUT_PAGE_MASK_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] INPUT_PAGE_MASK[13:6] (R/W)
Input Data Page Mask
Table 61. Bit Descriptions for INPUT_PAGE_MASK_MSB
Bits Bit Name
Description
Reset Access
0x0 R/W
[7:0] INPUT_PAGE_MASK[13:6] Input data page mask. Following a write to this register, the DAC code loaded into
this register is copied into the input register of any channels selected in the CH_SELECT
register.
Rev. 0 | Page 54 of 59
Data Sheet
AD5770R
Address: 0x37, Reset: 0x00, Name: SW_LDAC
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5] SW_LDAC_CH5 (W)
Software LDAC Channel 5
0: No Operation.
[0] SW_LDAC_CH0 (W)
Software LDAC Channel 0
0: No Operation.
1: Load DAC 0.
1: Load DAC 5.
[1] SW_LDAC_CH1 (W)
Software LDAC Channel 1
0: No Operation.
[4] SW_LDAC_CH4 (W)
Software LDAC Channel 4
0: No Operation.
1: Load DAC 1.
1: Load DAC 4.
[2] SW_LDAC_CH2 (W)
Software LDAC Channel 2
0: No Operation.
[3] SW_LDAC_CH3 (W)
Software LDAC Channel 3
0: No Operation.
1: Load DAC 2.
1: Load DAC 3.
Table 62. Bit Descriptions for SW_LDAC
Bits Bit Name
Description
Reset Access
[7:6] Reserved
Reserved.
0x0
0x0
R
5
4
3
2
1
0
SW_LDAC_CH5 Software LDAC Channel 5. Setting this bit transfers content from the INPUT_DATA5 bits to the
W
DAC_DATA5 bits. This bit automatically resets after a write to the SW_LDAC register.
0: no operation.
1: load DAC_DATA5.
SW_LDAC_CH4 Software LDACChannel 4. Setting this bit transfers content from the INPUT_DATA4 bits to the
0x0
0x0
0x0
0x0
0x0
W
W
W
W
W
DAC_DATA4 bits. This bit automatically resets after a write to the SW_LDAC register.
0: no operation.
1: load DAC_DATA4.
SW_LDAC_CH3 Software LDAC Channel 3. Setting this bit transfers content from the INPUT_DATA3 bits to the
DAC_DATA3 bits. This bit automatically resets after a write to the SW_LDAC register.
0: no operation.
1: load DAC_DATA3.
SW_LDAC_CH2 Software LDAC Channel 2. Setting this bit transfers content from the INPUT_DATA2 bits to the
DAC_DATA2 bits. This bit automatically resets after a write to the SW_LDAC register.
0: no operation.
1: load DAC_DATA2.
SW_LDAC_CH1 Software LDACChannel 1. Setting this bit transfers content from the INPUT_DATA1 bits to the
DAC_DATA1 bits. This bit automatically resets after a write to the SW_LDAC register.
0: no operation.
1: load DAC_DATA1.
SW_LDAC_CH0 Software LDAC Channel 0. Setting this bit transfers content from the INPUT_DATA0 bits to the
DAC_DATA0 bits. This bit automatically resets after a write to the SW_LDAC register.
0: no operation.
1: load DAC_DATA0.
Address: 0x38, Reset: 0x00, Name: CH0_INPUT_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] INPUT_DATA0[5:0] (R/W)
Input Data Channel 0
[1:0] RESERVED
Table 63. Bit Descriptions for CH0_INPUT_LSB
Bits Bit Name Description
Reset
0x0
Access
R/W
R
[7:2] INPUT_DATA0[5:0]
[1:0] Reserved
Input Data Channel 0. These bits are the DAC code loaded into the input register for IDAC0.
Reserved.
0x0
Rev. 0 | Page 55 of 59
AD5770R
Data Sheet
Address: 0x39, Reset: 0x00, Name: CH0_INPUT_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] INPUT_DATA0[13:6] (R/W)
Input Data Channel 0
Table 64. Bit Descriptions for CH0_INPUT_MSB
Bits Bit Name Description
[7:0] INPUT_DATA0[13:6] Input Data Channel 0. These bits are the DAC code loaded into the input register for IDAC0.
Reset Access
0x0
R/W
Address: 0x3A, Reset: 0x00, Name: CH1_INPUT_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] INPUT_DATA1[5:0] (R/W)
Input Data Channel 1
[1:0] RESERVED
Table 65. Bit Descriptions for CH1_INPUT_LSB
Bits Bit Name Description
Reset
0x0
0x0
Access
R/W
R
[7:2] INPUT_DATA1[5:0]
[1:0] Reserved
Input Data Channel 1. These bits are the DAC code loaded into the input register for IDAC1.
Reserved.
Address: 0x3B, Reset: 0x00, Name: CH1_INPUT_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] INPUT_DATA1[13:6] (R/W)
Input Data Channel 1
Table 66. Bit Descriptions for CH1_INPUT_MSB
Bits Bit Name Description
[7:0] INPUT_DATA1[13:6] Input Data Channel 1. These bits are the DAC code loaded into the input register for IDAC1.
Reset Access
0x0
R/W
Address: 0x3C, Reset: 0x00, Name: CH2_INPUT_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] INPUT_DATA2[5:0] (R/W)
Input Data Channel 2
[1:0] RESERVED
Table 67. Bit Descriptions for CH2_INPUT_LSB
Bits Bit Name Description
Reset
0x0
Access
R/W
R
[7:2] INPUT_DATA2[5:0]
[1:0] Reserved
Input Data Channel 2. These bits are the DAC code loaded into the input register for IDAC2.
Reserved.
0x0
Address: 0x3D, Reset: 0x00, Name: CH2_INPUT_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] INPUT_DATA2[13:6] (R/W)
Input Data Channel 2
Table 68. Bit Descriptions for CH2_INPUT_MSB
Bits Bit Name Description
[7:0] INPUT_DATA2[13:6] Input Data Channel 2. These bits are the DAC code loaded into the input register for IDAC2.
Reset Access
0x0 R/W
Rev. 0 | Page 56 of 59
Data Sheet
AD5770R
Address: 0x3E, Reset: 0x00, Name: CH3_INPUT_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] INPUT_DATA3[5:0] (R/W)
Input Data Channel 3 MSB
[1:0] RESERVED
Table 69. Bit Descriptions for CH3_INPUT_LSB
Bits Bit Name
Description
Reset Access
[7:2] INPUT_DATA3[5:0]
[1:0] Reserved
Input Data Channel 3. These bits are the DAC code loaded into the input register for IDAC3.
Reserved.
0x0
0x0
R/W
R
Address: 0x3F, Reset: 0x00, Name: CH3_INPUT_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] INPUT_DATA3[13:6] (R/W)
Input Data Channel 3 MSB
Table 70. Bit Descriptions for CH3_INPUT_MSB
Bits Bit Name Description
Reset Access
[7:0] INPUT_DATA3[13:6] Input Data Channel 3. These bits are the DAC code loaded into the input register for
IDAC3.
0x0
R/W
Address: 0x40, Reset: 0x00, Name: CH4_INPUT_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] INPUT_DATA4[5:0] (R/W)
[1:0] RESERVED
Input Data Channel 4
Table 71. Bit Descriptions for CH4_INPUT_LSB
Bits Bit Name Description
Reset
0x0
0x0
Access
R/W
R
[7:2] INPUT_DATA4[5:0]
[1:0] Reserved
Input Data Channel 4. These bits are the DAC code loaded into the input register for IDAC4.
Reserved.
Address: 0x41, Reset: 0x00, Name: CH4_INPUT_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] INPUT_DATA4[13:6] (R/W)
Input Data Channel 4
Table 72. Bit Descriptions for CH4_INPUT_MSB
Bits Bit Name Description
[7:0] INPUT_DATA4[13:6] Input Data Channel 4. These bits are the DAC code loaded into the input register for IDAC4.
Reset Access
0x0
R/W
Address: 0x42, Reset: 0x00, Name: CH5_INPUT_LSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] INPUT_DATA5[5:0] (R/W)
Input Data Channel 5
[1:0] RESERVED
Table 73. Bit Descriptions for CH5_INPUT_LSB
Bits Bit Name Description
Reset
0x0
Access
R/W
R
[7:2] INPUT_DATA5[5:0]
[1:0] Reserved
Input Data Channel 5. These bits are the DAC code loaded into the input register for IDAC5.
Reserved.
0x0
Rev. 0 | Page 57 of 59
AD5770R
Data Sheet
Address: 0x43, Reset: 0x00, Name: CH5_INPUT_MSB
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] INPUT_DATA5[13:6] (R/W)
Input Data Channel 5
Table 74. Bit Descriptions for CH5_INPUT_MSB
Bits Bit Name Description
[7:0] INPUT_DATA5[13:6] Input Data Channel 5. These bits are the DAC code loaded into the input register for IDAC5.
Reset Access
0x0
R/W
Address: 0x44, Reset: 0x3F, Name: RESERVED
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:6] RESERVED0[7:6] (R)
RESERVED
[5:0] RESERVED1 (R)
RESERVED
Table 75. Bit Descriptions for RESERVED
Bits
[7:6]
[0:5]
Bit Name
RESERVED0
RESERVED1
Description
Reserved
Reserved
Reset
0x0
0x1
Access
R
R
Rev. 0 | Page 58 of 59
Data Sheet
AD5770R
OUTLINE DIMENSIONS
4.080
4.040 SQ
4.000
7
6
5
4
3
2
1
A
BALL A1
IDENTIFIER
B
C
D
E
F
3.00 REF
SQ
G
0.50
BSC
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.390
0.360
0.330
0.660
0.600
0.540
END VIEW
COPLANARITY
0.05
0.360
0.320
0.280
SEATING
PLANE
0.270
0.240
0.210
Figure 78. 49-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-49-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
Package Description
Package Option
CB-49-5
AD5770RBCBZ-RL7
EVAL-AD5770RSDZ
49-Ball Wafer Level Chip Scale Packaging [WLCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16128-0-2/19(0)
Rev. 0 | Page 59 of 59
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