AD5781SRUZ-EP [ADI]
True 18-Bit, Voltage Output DAC ±0.5 LSB INL, ±0.5 LSB DNL;
| 型号： | AD5781SRUZ-EP |
| 厂家： | 
ADI |
| 描述： | True 18-Bit, Voltage Output DAC ±0.5 LSB INL, ±0.5 LSB DNL |
| 文件： | 总28页 (文件大小：873K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
System Ready, 20-Bit, 2ꢀSB ꢁIꢀ,
Voltage Output DAC
Data Sheet
AD5790
FEATURES
FUNCTIONAꢀ BꢀOCK DIAGRAM
V
V
V
REFP
CC
DD
Single 20-bit voltage output DAC, 2 ꢀSB INꢀ
8 nV/√Hz output noise spectral density
0.1 ꢀSB long-term linearity error stability
0.018 ppm/°C gain error temperature coefficient
2.5 μs output voltage settling time
6.8kΩ 6.8kΩ
R1
A1
R
IOV
CC
FB
R
FB
INV
SDIN
SCLK
SYNC
SDO
INPUT
SHIFT
20
20
20-BIT
DAC
DAC
REG
V
OUT
REGISTER
AND
3.5 nV-sec midscale glitch impulse
CONTROL
LOGIC
Integrated precision reference buffers
Operating temperature range: −40°C to +125°C
4 mm × 5 mm ꢀFCSP package
Wide power supply range of up to 16.5 V
35 MHz Schmitt-triggered digital interface
1.8 V compatible digital interface
6kΩ
LDAC
CLR
POWER-ON-RESET
AND CLEAR LOGIC
RESET
AD5790
DGND
V
AGND
V
REFN
SS
Figure 1.
APPꢀICATIONS
Table 1. Related Devices
Part No.
AD5791
AD5780
Description
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
20-bit, 1 LSB accurate DAC
18-bit, 1 LSB ꢀIL, voltage output DAC ,
buffered reference inputs
18-bit, 1 LSB ꢀIL, voltage Output DAC ,
unbuffered reference inputs
16-bit, 0ꢁ5 LSB ꢀIL, voltage Output DAC
AD5781
AD5760
AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC
GENERAꢀ DESCRIPTION
The AD57901 is a single 20-bit, unbuffered voltage-output DAC
that operates from a bipolar supply of up to 33 V. The AD5790
PRODUCT HIGHꢀIGHTS
1. 20-bit resolution.
accepts a positive reference input in the range of 5 V to VDD
−
2. Wide power supply range of up to 1ꢁ.5 V.
3. −40°C to +125°C operating temperature range.
4. ꢀow 8 nV/√Hz noise.
2.5 V and a negative reference input in the range of VSS + 2.5 V
to 0 V. The AD5790 offers a relative accuracy specification of
2 ꢀSB maximum range, and operation is guaranteed mono-
tonic with a −1 ꢀSB to +3 ꢀSB DNꢀ specification.
5. ꢀow 0.018 ppm/°C gain error temperature coefficient.
COMPANION PRODUCTS
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 35 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, and DSP interface standards.
Reference buffers are also provided on chip. The part incorpo-
rates a power-on reset circuit that ensures the DAC output
powers up to 0 V in a known output impedance state and
remains in this state until a valid write to the device takes place.
The part provides a disable feature that places the output in a
defined load state. The part provides an output clamp feature
that places the output in a defined load state.
Output Amplifier Buffer: AD8ꢁ75, ADA4898-1, ADA4004-1
External Reference: ADR445
DC-to-DC Design Tool: ADIsimPower™
Additional companion products on the AD5790 product page
1 Protected by UꢁSꢁ Patent Ioꢁ 7,884,747ꢁ
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.
AD5790
Data Sheet
TABꢀE OF COITEITS
Features .............................................................................................. 1
DAC Architecture....................................................................... 19
Serial Interface............................................................................ 19
Standalone Operation................................................................ 20
Hardware Control Pins.............................................................. 20
On-Chip Registers...................................................................... 21
AD5790 Features ............................................................................ 24
Power-On to 0 V......................................................................... 24
Configuring the AD5790 .......................................................... 24
DAC Output State ...................................................................... 24
Output Amplifier Configuration.............................................. 24
Applications Information.............................................................. 2ꢁ
Typical Operating Circuit ......................................................... 2ꢁ
Evaluation Board........................................................................ 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Companion Products....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
REVISION HISTORY
2/12—Rev. A to Rev. B
Deleted ꢀinearity Compensation Section ................................... 24
12/11—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 1
Changes to Table 2............................................................................ 4
Changes to Figure 48...................................................................... 17
Changes to DAC Register Section................................................ 21
Changes to Table 11........................................................................ 22
Updated Outline Dimensions....................................................... 28
11/11—Revision 0: Initial Version
Revꢁ B | Page 2 of 28
Data Sheet
AD5790
SPECꢁFꢁCATꢁOIS
VDD = 12.5 V to 1ꢁ.5 V, VSS = −1ꢁ.5 V to −12.5 V, VREFP = 10 V, VREFN = −10 V, VCC = 2.7 V to +5.5 V, IOVCC = 1.71 V to 5.5 V,
Rꢀ = unloaded, Cꢀ = unloaded, TMIN to TMAX, unless otherwise noted.
Table 2.
B Version1
Parameter
STATꢀC PERFORMAICE2
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
ꢀntegral Ionlinearity Error (Relative
Accuracy)
20
−2
Bits
LSB
1ꢁ2
+2
VREFP = +10 V, VREFI = −10 V, TA = 0°C to 105°C
VREFP = +10 V, VREFI = −10 V, TA =−40°C to +105°C
−3
−4
−1
−1
1ꢁ2
1ꢁ2
+3
+4
+2
+3
LSB
LSB
LSB
LSB
VREFx
VREFP = +10 V, VREFI = −10 V, TA = 0°C to 105°C
VREFx 10 V, +10 V, and +5 V
= 10 V, +10 V, and +5 V
Differential Ionlinearity Error
=
Long-Term Linearity Error Stability3
Full-Scale Error
0ꢁ1
3ꢁ8
2ꢁ7
1ꢁ8
3ꢁ8
2ꢁ7
1ꢁ8
0ꢁ026
1ꢁ3
0ꢁ7
0ꢁ9
1ꢁ3
0ꢁ7
0ꢁ9
0ꢁ025
2ꢁ3
1ꢁ9
0ꢁ9
2ꢁ3
2ꢁ9
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
LSB
LSB
LSB
After 750 hours at TA = 135°C
VREFP = +10 V, VREFI = −10 V
VREFP = 10 V, VREFI = 0 V
−12
−22
−40
−9
−12
−22
+12
+22
+40
+9
+12
+22
VREFP = 5 V, VREFI = 0 V
VREFP = +10 V, VREFI = −10 V, TA = 0°C to 105°C
VREFP = 10 V, VREFI = 0 V, TA = 0°C to 105°C
VREFP = 5 V, VREFI = 0 V, TA = 0°C to 105°C
VREFP = +10 V, VREFI = −10 V
VREFP = +10 V, VREFI = −10 V
VREFP = 10 V, VREFI = 0 V
Full-Scale Error Temperature Coefficient
Zero-Scale Error
−19
−40
−82
−8
−13
−22
+19
+40
+82
+8
+13
+22
VREFP = 5 V, VREFI = 0 V
VREFP = +10 V, VREFI = −10 V, TA = 0°C to 105°C
VREFP = 10 V, VREFI = 0 V, TA = 0°C to 105°C
VREFP = 5 V, VREFI = 0 V, TA = 0°C to 105°C
VREFP = +10 V, VREFI = −10 V
VREFP = +10 V, VREFI = −10 V
VREFP = 10 V, VREFI = 0 V
LSB
Zero-Scale Error Temperature Coefficient
Gain Error
ppm/°C
ppm FSR
ppm FSR
ppm FSR
ppm FSR
ppm FSR
ppm FSR
ppm/°C
%
−19
−35
−68
−9
−15
−22
+19
+35
+68
+9
+15
+22
VREFP = 5 V, VREFI = 0 V
VREFP = +10 V, VREFI = −10 V, TA = 0°C to 105°C
VREFP = 10 V, VREFI = 0 V, TA = 0°C to 105°C
VREFP = 5 V, VREFI = 0 V, TA = 0°C to 105°C
VREFP = +10 V, VREFI = −10 V
0ꢁ9
0ꢁ018
0ꢁ015
Gain Error Temperature Coefficient
R1, RFB Matching
OUTPUT CHARACTERꢀSTꢀCS
Output Voltage Range
VREFI
VREFP
V
Output Voltage Settling Time
2ꢁ5
μs
10 V step to 0ꢁ02%, using the ADA4898-1 buffer
in unity-gain mode
3ꢁ5
8
8
1ꢁ1
14
3ꢁ5
4
14
3ꢁ5
4
μs
500 code step to 1 LSB4
Output Ioise Spectral Density
nV/√Hz
nV/√Hz
μV p-p
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
At 1 kHz, DAC code = midscale
At 10 kHz, DAC code = midscale
DAC code = midscale, 0ꢁ1 Hz to 10 Hz bandwidth
VREFP = +10 V, VREFI = −10 V
Output Voltage Ioise
Midscale Glitch ꢀmpulse4
VREFP = 10 V, VREFI = 0 V
VREFP = 5 V, VREFI = 0 V
MSB Segment Glitch ꢀmpulse4
VREFP = +10 V, VREFI = −10 V, see Figure 43
V
REFP = 10 V, VREFI = 0 V, see Figure 44
REFP = 5 V, VREFI = 0 V, see Figure 45
V
Revꢁ B | Page 3 of 28
AD5790
Data Sheet
B Version1
Parameter
Min
Typ
57
0ꢁ27
3ꢁ4
6
Max
Unit
nV-sec
nV-sec
kΩ
Test Conditions/Comments
Output Enabled Glitch ꢀmpulse
Digital Feedthrough
DC Output ꢀmpedance (Iormal Mode)
DC Output ꢀmpedance (Output
Clamped to Ground)
On removal of output ground clamp
kΩ
REFEREICE ꢀIPUTS
VREFP ꢀnput Range
VREFI ꢀnput Range
ꢀnput Bias Current
5
VDD − 2ꢁ5
0
+20
+4
V
V
nA
VSS + 2ꢁ5
−20
−4
−0ꢁ63
−0ꢁ63
1
TA = 0°C to 105°C
VREFP, VREFI
ꢀnput Capacitance
pF
LOGꢀC ꢀIPUTS
ꢀnput Current5
ꢀnput Low Voltage, VꢀL
−1
+1
0ꢁ3 × ꢀOVCC
μA
V
ꢀOVCC = 1ꢁ71 V to 5ꢁ5 V
ꢀOVCC = 1ꢁ71 V to 5ꢁ5 V
ꢀnput High Voltage, VꢀH
0ꢁ7 × ꢀOVCC
V
Pin Capacitance
5
3
pF
LOGꢀC OUTPUT (SDO)
Output Low Voltage, VOL
Output High Voltage, VOH
High ꢀmpedance Leakage Current
0ꢁ4
1
V
V
μA
pF
ꢀOVCC = 1ꢁ71 V to 5ꢁ5 V, sinking 1 mA
ꢀOVCC = 1ꢁ71 V to 5ꢁ5 V, sourcing 1 mA
ꢀOVCC − 0ꢁ5
High ꢀmpedance Output Capacitance
POWER REQUꢀREMEITS
All digital inputs at DGID or ꢀOVCC
VDD
VSS
VCC
7ꢁ5
VDD − 33
2ꢁ7
VSS + 33
−2ꢁ5
5ꢁ5
V
V
V
ꢀOVCC
1ꢁ71
5ꢁ5
V
ꢀOVCC ≤ VCC
ꢀDD
ꢀSS
ꢀCC
ꢀOꢀCC
10ꢁ3
−10
600
52
7ꢁ5
1ꢁ5
90
14
mA
mA
μA
μA
μV/V
μV/V
dB
dB
−14
900
140
SDO disabled
∆VDD 10%, VSS = −15 V
∆VSS 10%, VDD = 15 V
∆VDD 200 mV, 50 Hz/60 Hz, VSS = −15 V
∆VSS 200 mV, 50 Hz/60 Hz, VDD = 15 V
DC Power Supply Rejection Ratio
AC Power Supply Rejection Ratio
90
1 Temperature range: −40°C to +125°C, typical conditions: TA = +25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFI = −10 Vꢁ
2 Performance characterized with the AD8675ARZ output bufferꢁ
3 Linearity error refers to both ꢀIL error and DIL error, either parameter can be expected to drift by the amount specified after the length of time specifiedꢁ
4 The AD5790 is configured in unity-gain mode with a low-pass RC filter on the outputꢁ R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead
capacitance, and so forth)ꢁ
5 Current flowing in an individual logic pinꢁ
Revꢁ B | Page 4 of 28
Data Sheet
AD5790
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
ꢀimit1
Parameter
Unit
Test Conditions/Comments
IOVCC = 1.71 V to 3.3 V
IOVCC = 3.3 V to 5.5 V
2
t1
40
92
15
9
28
60
10
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns min
ns typ
ns min
SCLK cycle time
SCLK cycle time (readback and daisy-chain modes)
SCLK high time
t2
t3
t4
SCLK low time
5
5
SYIC to SCLK falling edge setup time
SCLK falling edge to SYIC rising edge hold time
Minimum SYIC high time
t5
2
2
t6
48
8
40
6
t7
SYIC rising edge to next SCLK falling edge ignore
Data setup time
Data hold time
LDAC falling edge to SYIC falling edge
SYIC rising edge to LDAC falling edge
LDAC pulse width low
t8
t9
9
7
7
12
13
20
14
130
130
50
140
0
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
10
16
11
130
130
50
140
0
LDAC falling edge to output response time
SYIC rising edge to output response time (LDAC tied low)
CLR pulse width low
CLR pulse activation time
SYIC falling edge to first SCLK rising edge
65
62
0
60
45
0
ns max SYIC rising edge to SDO tristate (CL = 50 pF)
ns max SCLK rising edge to SDO valid (CL = 50 pF)
ns min
ns typ
ns typ
SYIC rising edge to SCLK rising edge ignore
RESET pulse width low
35
150
35
150
RESET pulse activation time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of ꢀOVCC) and timed from a voltage level of (VꢀL + VꢀH)/2ꢁ
2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modesꢁ
Revꢁ B | Page 5 of 28
AD5790
Data Sheet
t1
t7
SCLK
1
2
24
t3
t2
t6
t4
t5
SYNC
SDIN
t9
t8
DB23
DB0
t12
t10
t11
LDAC
t13
V
V
OUT
OUT
t14
t15
CLR
t16
V
OUT
t21
RESET
t22
V
OUT
Figure 2. Write Mode Timing Diagram
t20
t1
t17
t7
SCLK
1
2
24
1
2
24
t3
t2
t6
t17
t5
t5
t4
SYNC
SDIN
t9
t8
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t18
t19
DB23
DB0
SDO
REGISTER CONTENTS CLOCKED OUT
Figure 3. Readback Mode Timing Diagram
Revꢁ B | Page 6 of 28
Data Sheet
AD5790
t20
t1
t17
SCLK
26
1
2
24
25
48
t3
t2
t6
t5
t4
SYNC
SDIN
t9
t8
DB23
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N – 1
t19
INPUT WORD FOR DAC N
t18
DB0
DB0
DB23
SDO
INPUT WORD FOR DAC N
UNDEFINED
Figure 4. Daisy-Chain Mode Timing Diagram
Revꢁ B | Page 7 of 28
AD5790
Data Sheet
ABSOꢀUTE MAXꢁMUM RATꢁIGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
VDD to AGID
VSS to AGID
VDD to VSS
VCC to DGID
ꢀOVCC to DGID
Rating
−0ꢁ3 V to +34 V
−34 V to +0ꢁ3 V
−0ꢁ3 V to +34 V
−0ꢁ3 V to +7 V
−0ꢁ3 V to VCC + 3 V or +7 V
(whichever is less)
−0ꢁ3 V to ꢀOVCC + 0ꢁ3 V or
+7 V (whichever is less)
−0ꢁ3 V to VDD + 0ꢁ3 V
−0ꢁ3 V to VDD + 0ꢁ3 V
VSS − 0ꢁ3 V to + 0ꢁ3 V
−0ꢁ3 V to +0ꢁ3 V
This device is a high performance integrated circuit with an
ESD rating of <1.ꢁ kV, and it is ESD sensitive. Proper
precautions must be taken for handling and assembly.
Digital ꢀnputs to DGID
VOUT to AGID
VREFP to AGID
VREFI to AGID
DGID to AGID
ESD CAUTION
Operating Temperature Range, TA
ꢀndustrial
Storage Temperature Range
Maximum Junction Temperature,
TJ max
−40°C to +125°C
−65°C to +150°C
150°C
Power Dissipation
LFCSP Package
(TJ max − TA)/θJA
θJA Thermal ꢀmpedance
Lead Temperature
Soldering
31ꢁ0°C/W
JEDEC industry standard
J-STD-020
ESD (Human Body Model)
1ꢁ6 kV
Revꢁ B | Page 8 of 28
Data Sheet
AD5790
PꢁI COIFꢁGURATꢁOI AID FUICTꢁOI DESCRꢁPTꢁOIS
V
AGND
1
2
3
19
18
17
16
15
OUT
V
V
SS
REFP
V
V
DD
SS
AD5790
TOP VIEW
(Not to Scale)
V
RESET 4
V
REFN
5
DGND
DD
CLR 6
LDAC 7
14 SYNC
13
SCLK
NOTES
THIS PIN.
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO
2. NEGATIVE ANALOG SUPPLY CONNECTION (V ).
SS
A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V
CAN BE CONNECTED. V SHOULD BE DECOUPLED
SS
CTRICALLY
TO AGND. THE PADDLE CAN BE LEFT ELE
UNCONNECTED PROVIDED THAT A SUPPLY
CONNECTION IS MADE AT THE VSS PINS. IT IS
RECOMMENDED THAT THE PADDLE BE THER
CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
MALLY
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VOUT
Analog Output Voltageꢁ
2
VREFP
Positive Reference Voltage ꢀnputꢁ A voltage in the range of 5 V to VDD − 2ꢁ5 V can be connectedꢁ
3, 5
VDD
Positive Analog Supply Connectionꢁ A voltage in the range of 7ꢁ5 V to 16ꢁ5 V can be connectedꢁ VDD must be
decoupled to AGIDꢁ
4
6
RESET
CLR
Active Low Resetꢁ Asserting this pin returns the AD5790 to its power-on statusꢁ
Active Low ꢀnputꢁ Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates the
DAC outputꢁ The output value depends on the DAC register coding that is being used, either binary or twos
complementꢁ
7
LDAC
Active Low Load DAC Logic ꢀnputꢁ This is used to update the DAC register and, consequently, the analog outputꢁ
SYIC LDAC
When tied permanently low, the output is updated on the rising edge of
ꢁ ꢀf
is held high during the
LDAC
write cycle, the input register is updated, but the output update is held off until the falling edge of
LDAC
ꢁ The
pin should not be left unconnectedꢁ
Digital Supplyꢁ Voltage range is from 2ꢁ7 V to 5ꢁ5 Vꢁ VCC should be decoupled to DGIDꢁ
8
9
VCC
ꢀOVCC
Digital ꢀnterface Supplyꢁ Digital threshold levels are referenced to the voltage applied to this pinꢁ Voltage range is
from 1ꢁ71 V to 5ꢁ5 V
10, 21, 22, 23
11
12
DIC
SDO
SDꢀI
Do Iot Connectꢁ Do not connect to these pinsꢁ
Serial Data Outputꢁ
Serial Data ꢀnputꢁ This device has a 24-bit input shift registerꢁ Data is clocked into the register on the falling edge
of the serial clock inputꢁ
13
14
SCLK
SYIC
Serial Clock ꢀnputꢁ Data is clocked into the input shift register on the falling edge of the serial clock inputꢁ Data
can be transferred at rates of up to 35 MHzꢁ
Level-Triggered Control ꢀnput (Active Low)ꢁ This is the frame synchronization signal for the input dataꢁ When
SYIC
goes low, it enables the input shift register, and data is then transferred in on the falling edges of the
SYIC
following clocksꢁ The DAC is updated on the rising edge of
ꢁ
15
16
17, 18
DGID
VREFI
VSS
Ground Reference Pin for Digital Circuitryꢁ
Iegative Reference Voltage ꢀnputꢁ
Iegative Analog Supply Connectionꢁ A voltage in the range of −16ꢁ5 V to −2ꢁ5 V can be connectedꢁ VSS must be
decoupled to AGIDꢁ
19
20
AGID
RFB
Ground Reference Pin for Analog Circuitryꢁ
Feedback Connection for External Amplifierꢁ See the AD5790 Features section for further detailsꢁ
ꢀnverting ꢀnput Connection for External Amplifierꢁ See the AD5790 Features section for further detailsꢁ
Iegative Analog Supply Connection (VSS)ꢁ A voltage in the range of −16ꢁ5 V to −2ꢁ5 V can be connectedꢁ VSS must
be decoupled to AGIDꢁ The paddle can be left electrically unconnected provided that a supply connection is
made at the VSS pinsꢁ ꢀt is recommended that the paddle be thermally connected to a copper plane for enhanced
thermal performanceꢁ
24
ꢀIV
VSS
EPAD
Revꢁ B | Page 9 of 28
AD5790
Data Sheet
TYPꢁCAꢀ PERFORMAICE CHARACTERꢁSTꢁCS
AD8675 OUTPUT BUFFER
2.0
1.5
AD8675 OUTPUT BUFFER
= 25°C
T
= 25°C
1.25
A
T
A
0.75
1.0
0.5
0.25
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.25
–0.75
–1.25
–1.75
V
V
V
V
= +10V
= –10V
REFP
REFN
DD
SS
V
= +5V
= 0V
REFP
REFN
DD
SS
V
V
V
= +15V
= +15V
= –15V
= –15V
0
200000
400000
600000
DAC CODE
800000 1000000 1200000
0
200000
400000
600000
800000 1000000 1200000
DAC CODE
Figure 6. Integral Nonlinearity Error vs. DAC Code, 1ꢀ V Span
Figure 9. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode
2.5
2.0
AD8675 OUTPUT BUFFER
= 25°C
AD8675 OUTPUT BUFFER
A
T
A
T
= 25°C
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
V
V
V
V
= +10V
= 0V
REFP
REFN
DD
SS
V
V
V
V
= +10V
= –10V
REFP
REFN
DD
SS
= +15V
= +15V
= –15V
= –15V
0
200000
400000
600000
DAC CODE
800000 1000000 1200000
0
200000
400000
600000
800000 1000000 1200000
DAC CODE
Figure 1ꢀ. Differential Nonlinearity Error vs. DAC Code, 1ꢀ V Span
Figure 7. Integral Nonlinearity Error vs. DAC Code, 1ꢀ V Span
2.0
2.0
AD8675 OUTPUT BUFFER
A
AD8675 OUTPUT BUFFER
= 25°C
T
= 25°C
T
A
1.5
1.0
1.5
1.0
0.5
0
0.5
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
–0.5
–1.0
–1.5
V
V
V
V
= +10V
= 0V
REFP
REFN
DD
SS
V
V
V
V
= +5V
= 0V
REFP
REFN
DD
SS
= +15V
= +15V
= –15V
= –15V
0
200000
400000
600000
800000 1000000 1200000
0
200000
400000
600000
800000 1000000 1200000
DAC CODE
DAC CODE
Figure 11. Differential Nonlinearity Error vs. DAC Code, 1ꢀ V Span
Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span
Revꢁ B | Page 10 of 28
Data Sheet
AD5790
3.0
±10V SPAN MAX DNL
+10V SPAN MAX DNL
+5V SPAN MAX DNL
±10V SPAN MIN DNL
+10V SPAN MIN DNL
+5V SPAN MIN DNL
AD8675 OUTPUT BUFFER
= 25°C
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
V
V
= +5V
= 0V
REFP
REFN
DD
SS
T
A
= +15V
= –15V
2.5
2.0
1.5
1.0
0.5
0
V
V
= +15V
= –15V
DD
SS
AD8675 OUTPUT BUFFER
–0.5
–1.0
–0.2
–40
–20
0
20
40
60
80
100
0
200000
400000
600000
800000 1000000 1200000
TEMPERATURE (°C)
DAC CODE
Figure 15. Differential Nonlinearity Error vs. Temperature
Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span
1.5
2.5
AD8675 OUTPUT BUFFER
= 25°C
V
V
V
V
= +5V
= 0V
REFP
REFN
DD
SS
T
A
INL MAX
= +15V
= –15V
2.0
1.5
1.0
0.5
0
1.0
0.5
T
= 25°C
A
V
V
= +10V
0
REFP
REFN
= –10V
AD8675 OUTPUT BUFFER
–0.5
–1.0
–1.5
INL MIN
15.5
–0.5
–1.0
12.5
13.0
13.5
14.0
14.5
15.0
16.0
16.5
0
200000
400000
600000
800000 1000000 1200000
V
/|V | (V)
DD
SS
DAC CODE
Figure 16. Integral Nonlinearity Error vs. Supply Voltage, 1ꢀ V Span
Figure 13. Differential Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain
Mode
1.8
2.5
±10V SPAN MAX INL
+10V SPAN MAX INL
+5V SPAN MAX INL
±10V SPAN MIN INL
+10V SPAN MIN INL
+5V SPAN MIN INL
INL MAX
1.3
2.0
1.5
0.8
0.3
–0.2
–0.7
–1.2
–1.7
–2.2
T
= 25°C
1.0
A
V
= 5V
REFP
REFN
V
= 0V
0.5
AD8675 OUTPUT BUFFER
V
V
= +15V
= –15V
DD
SS
0
AD8675 OUTPUT BUFFER
INL MIN
–0.5
–1.0
–1.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
DD SS
Figure 17. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span
Figure 14. Integral Nonlinearity Error vs. Temperature
Revꢁ B | Page 11 of 28
AD5790
Data Sheet
1.4
1.2
1.0
11
9
T
V
V
= 25°C
A
= 5V
REFP
REFN
DNL MAX
= 0V
AD8675 OUTPUT BUFFER
7
T
= 25°C
0.8
0.6
0.4
0.2
0
5
A
V
= +10V
REFP
REFN
V
= –10V
AD8675 OUTPUT BUFFER
3
1
–1
–3
–5
DNL MIN
15.0
–0.2
12.5
13.0
13.5
14.0
14.5
15.5
16.0
16.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
V
/|V | (V)
V
DD SS
DD SS
Figure 18. Differential Nonlinearity Error vs. Supply Voltage, 1ꢀ V Span
Figure 21. Zero-Scale Error vs. Supply Voltage, 5 V Span
1.4
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
T
= 25°C
DNL MAX
A
V
V
= +10V
= –10V
REFP
REFN
1.2
AD8675 OUTPUT BUFFER
1.0
0.8
T
= 25°C
A
0.6
0.4
0.2
0
V
V
= 5V
REFP
REFN
= 0V
AD8675 OUTPUT BUFFER
DNL MIN
–0.2
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
V
DD SS
V
/|V | (V)
DD SS
Figure 19. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span
Figure 22. Midscale Error vs. Supply Voltage, 1ꢀ V Span
10
8
T
V
V
= 25°C
A
T
V
V
= 25°C
A
= +10V
REFP
REFN
= 5V
1.0
0.5
REFP
REFN
= –10V
= 0V
AD8675 OUTPUT BUFFER
AD8675 OUTPUT BUFFER
6
4
0
2
0
–0.5
–1.0
–1.5
–2.0
–2
–4
–6
–8
–10
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
/|V | (V)
DD SS
V
/|V | (V)
DD SS
Figure 2ꢀ. Zero-Scale Error vs. Supply Voltage, 1ꢀ V Span
Figure 23. Midscale Error vs. Supply Voltage, 5 V Span
Revꢁ B | Page 12 of 28
Data Sheet
AD5790
2.0
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
T
= 25°C
A
V
V
= +10V
REFP
REFN
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
= –10V
AD8675 OUTPUT BUFFER
T
= 25°C
A
V
V
= 5V
REFP
= 0V
REFN
AD8675 OUTPUT BUFFER
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
V
V
/|V | (V)
DD SS
DD SS
Figure 27. Gain Error vs. Supply Voltage, 5 V Span
Figure 24. Full-Scale Error vs. Supply Voltage, 1ꢀ V Span
1.25
0.75
8
T
= 25°C
A
V
V
= 5V
INL MAX
REFP
6
4
= 0V
REFN
AD8675 OUTPUT BUFFER
2
0.25
T
= 25°C
A
V
V
= +15V
DD
0
= –15V
SS
AD8675 OUTPUT BUFFER
–0.25
–0.75
–1.25
–1.75
–2
–4
–6
–8
–10
–12
INL MIN
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
/|V | (V)
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
V
V
| (V)
DD SS
REFP
REFN
Figure 28. Integral Nonlinearity Error vs. Reference Voltage
Figure 25. Full-Scale Error vs. Supply Voltage, 5 V Span
1.5
1.0
0.5
0
1.15
T
= 25°C
A
V
V
= +10V
REFP
INL MAX
= –10V
REFN
0.95
0.75
AD8675 OUTPUT BUFFER
T
= 25°C
A
DD
SS
0.55
V
V
= +15V
= –15V
AD8675 OUTPUT BUFFER
0.35
0.15
INL MIN
–0.5
–0.05
–0.25
–1.0
12.5
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
V
| (V)
REFP
REFN
V
/|V | (V)
DD SS
Figure 26. Gain Error vs. Supply Voltage, 1ꢀ V Span
Figure 29. Differential Nonlinearity Error vs. Reference Voltage
Revꢁ B | Page 13 of 28
AD5790
Data Sheet
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
T
V
V
= 25°C
A
T
= 25°C
DD
SS
–0.1
–0.3
–0.5
–0.7
–0.9
–1.1
–1.3
–1.5
A
V
V
= +15V
= –15V
DD
SS
= +15V
= –15V
AD8675 OUTPUT BUFFER
AD8675 OUTPUT BUFFER
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
V
| (V)
REFP
REFN
V
| (V)
REFP
REFN
Figure 3ꢀ. Zero-Scale Error vs. Reference Voltage
Figure 33. Gain Error vs. Reference Voltage
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
T
V
V
= 25°C
= +15V
REFN
A
V
V
= +15V
= –15V
DD
SS
REFP
= –15V
AD8675 OUTPUT BUFFER
AD8675 OUTPUT BUFFER
±10V SPAN
+10V SPAN
+5V SPAN
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
V
| (V)
REFP
REFN
Figure 31. Midscale Error vs. Reference Voltage
Figure 34. Full-Scale Error vs. Temperature
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3
2
V
V
= +15V
T
= 25°C
= +15V
SS
±10V SPAN
+10V SPAN
+5V SPAN
DD
SS
A
DD
= –15V
V
V
= –15V
AD8675 OUTPUT BUFFER
AD8675 OUTPUT BUFFER
1
0
–1
–2
–3
–4
–5
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
–40
–20
0
20
40
60
80
100
V
| (V)
REFP
REFN
TEMPERATURE (°C)
Figure 32. Full-Scale Error vs. Reference Voltage
Figure 35. Midscale Error vs. Temperature
Revꢁ B | Page 14 of 28
Data Sheet
AD5790
0.010
0.008
0.006
0.004
0.002
0
5
V
V
= +15V
±10V SPAN
+10V SPAN
+5V SPAN
DD
SS
= –15V
3
1
AD8675 OUTPUT BUFFER
I
DD
–1
–3
–5
–7
–9
–11
–0.002
–0.004
–0.006
–0.008
–0.010
I
SS
–40
–20
0
20
40
60
80
100
–20
–15
–10
–5
0
5
10
15
20
V
/V (V)
TEMPERATURE (°C)
DD SS
Figure 39. Power Supply Currents vs. Power Supply Voltages
Figure 36. Zero-Scale Error vs. Temperature
0
–2
6
4
V
V
= +15V
= –15V
±10V SPAN
+10V SPAN
+5V SPAN
DD
SS
AD8675 OUTPUT BUFFER
2
–4
0
–6
–2
–4
–6
–8
–8
–10
–12
–14
–16
–10
–1
0
1
2
3
4
5
–40
–20
0
20
40
60
80
100
TIME (µs)
TEMPERATURE (°C)
Figure 37. Gain Error vs. Temperature
Figure 4ꢀ. Rising Full-Scale Voltage Step
6
4
900
800
700
600
500
400
300
200
100
0
IOV = 5V, LOGIC VOLTAGE
CC
INCREASING
T
= 25°C
A
IOV = 5V, LOGIC VOLTAGE
CC
DECREASING
IOV = 3V, LOGIC VOLTAGE
CC
2
INCREASING
IOV = 3V, LOGIC VOLTAGE
CC
0
DECREASING
–2
–4
–6
–8
–10
–1
0
1
2
3
4
5
0
1
2
3
4
5
6
TIME (µs)
LOGIC INPUT VOLTAGE (V)
Figure 41. Falling Full-Scale Voltage Step
Figure 38. IOICC vs. Logic Input Voltage
Revꢁ B | Page 15 of 28
AD5790
Data Sheet
10
9
8
7
6
5
4
3
2
1
6
5
4
3
2
1
0
V
V
= 5V
= 0V
NEGATIVE
POSITIVE
REFP
REFN
UNITY GAIN MODE
ADA4898-1
RC LOW-PASS FILTER
V
V
= +10V
= –10V
REFP
REFN
RC LOW-PASS FILTER
UNITY GAIN MODE
ADA4898-1
0
–1
0
1
2
3
4
5
TIME (µs)
CODE
Figure 42. 5ꢀꢀ Code Step Settling Time
Figure 45. 6 MSB Segment Glitch Energy for 5 V VREF
55
25
±10V SPAN
+10V SPAN
+5V SPAN
NEGATIVE
POSITIVE
V
V
= +10V
= –10V
V
V
= +10V
= –10V
REFP
REFN
REFP
REFN
45
35
UNITY GAIN MODE
RC LOW-PASS FILTER
UNITY GAIN MODE
ADA4898-1
ADA4898-1
20
15
10
5
RC LOW-PASS FILTER
NEGATIVE CODE
CHANGE
POSITIVE CODE
CHANGE
25
15
5
–5
–15
–25
0
1
0
1
2
3
TIME (µs)
CODE
Figure 43. 6 MSB Segment Glitch Energy for 1ꢀ V VREF
Figure 46. Midscale Peak-to-Peak Glitch for 1ꢀ V
800
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
= 10V
= 0V
T
V
V
V
V
= 25°C
REFP
REFN
A
MIDSCALE CODE LOADED
OUTPUT UNBUFFERED
AD8676 REFERENCE BUFFERS
= +15V
= –15V
DD
SS
UNITY GAIN MODE
600
400
ADA4898-1
= +10V
= –10V
REFP
REFN
RC LOW-PASS FILTER
NEGATIVE
POSITIVE
200
0
–200
–400
–600
0
1
2
3
4
5
6
7
8
9
10
TIME (Seconds)
CODE
Figure 44. 6 MSB Segment Glitch Energy for 1ꢀ V VREF
Figure 47. Voltage Output Noise, ꢀ.1 Hz to 1ꢀ Hz Bandwidth
Revꢁ B | Page 16 of 28
Data Sheet
AD5790
200
180
160
140
120
100
80
100
V
V
V
V
= +15V
= –15V
REFP
REFN
V
V
V
V
= +15V
DD
SS
DD
SS
= –15V
= +10V
= –10V
= +10V
REFP
REFN
= –10V
UNITY GAIN
ADA4898-1
10
60
40
20
0
1
–20
0.1
1
10
100
1k
10k
0
1
2
3
4
5
6
FREQUENCY (Hz)
TIME (µs)
Figure 48. Noise Spectral Density vs. Frequency
Figure 49. Glitch Impulse on Removal of Output Clamp
Revꢁ B | Page 17 of 28
AD5790
Data Sheet
TERMꢁIOꢀOGY
Output Voltage Settling Time
Relative Accuracy
Output voltage settling time is the amount of time it takes for
the output voltage to settle to a specified level for a specified
change in voltage. For fast settling applications, a high speed
buffer amplifier is required to buffer the load from the 3.4 kΩ
output impedance of the AD5790, in which case, it is the
amplifier that determines the settling time.
Relative accuracy, or integral nonlinearity (INꢀ), is a measure of
the maximum deviation, in ꢀSB, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INꢀ error vs. code plot is shown in Figure ꢁ.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 ꢀSB change between any two adjacent
codes. A specified differential nonlinearity of 1 ꢀSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNꢀ error vs. code plot is shown in Figure 10.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-s and is
measured when the digital input code is changed by 1 ꢀSB at
the major carry transition. See Figure 49.
Long-Term Linearity Error Stability
ꢀinearity error long-term stability is a measure of the stability of
the linearity of the DAC over a long period of time. It is speci-
fied in ꢀSB for a time period of 500 hours and 1000 hours at an
elevated ambient temperature.
Output Enabled Glitch Impulse
Output enabled glitch impulse is the impulse injected into the
analog output when the clamp to ground on the DAC output is
removed. It is specified as the area of the glitch in nV-sec (see
Figure 49).
Zero-Scale Error
Zero-scale error is a measure of the output error when zero-scale
code (0x00000) is loaded to the DAC register. Ideally, the output
voltage should be VREFN. Zero-scale error is expressed in ꢀSBs.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s, and vice versa.
Zero-Scale Error Temperature Coefficient
Zero-scale error temperature coefficient is a measure of the
change in zero-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Total Harmonic Distortion (THD)
Full-Scale Error
Total harmonic distortion is the ratio of the rms sum of the
harmonics of the DAC output to the fundamental value. Only
the second to fifth harmonics are included.
Full-scale error is a measure of the output error when full-scale
code (0x3FFFF) is loaded to the DAC register. Ideally, the
output voltage should be VREFP − 1 ꢀSB. Full-scale error is
expressed in ꢀSBs.
DC Power Supply Rejection Ratio
DC power supply rejection ratio is a measure of the rejection of
the output voltage to dc changes in the power supplies applied
to the DAC. It is measured for a given dc change in power
supply voltage and is expressed in μV/V.
Full-Scale Error Temperature Coefficient
Full-scale error temperature coefficient is a measure of the
change in full-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
AC Power Supply Rejection Ratio (AC PSRR)
Gain Error
AC power supply rejection ratio is a measure of the rejection of
the output voltage to ac changes in the power supplies applied
to the DAC. It is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed in ppm of the full-scale range.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change
in gain error with a change in temperature. It is expressed in
ppm FSR/°C.
Midscale Error
Midscale error is a measure of the output error when midscale
code (0x20000) is loaded to the DAC register. Ideally, the output
voltage should be (VREFP − VREFN)/2 + VREFN. Midscale error is
expressed in ꢀSBs.
Revꢁ B | Page 18 of 28
Data Sheet
AD5790
THEORY OF OPERATꢁOI
R
R
R
The AD5790 is a high accuracy, fast settling, single, 20-bit,
serial input, voltage-output DAC. It operates from a VDD supply
voltage of 7 V to 1ꢁ.5 V and a VSS supply of −1ꢁ.5 V to -2.5 V.
Data is written to the AD5790 in a 24-bit word format via a 3-wire
serial interface. The AD5790 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
V
OUT
..........
.........
.....................
.....................
2R
S13
2R
2R
E0
2R
S0
2R
S1
2R
E62
E61
V
REFP
V
REFN
VOUT pin clamped to AGND through a ~ꢁ kΩ internal resistor.
14-BIT R-2R LADDER
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
DAC ARCHITECTURE
Figure 5ꢀ. DAC Ladder Structure
The architecture of the AD5790 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 50.
The six MSBs of the 20-bit data-word are decoded to drive
ꢁ3 switches, E0 to Eꢁ2. Each of these switches connects one of
ꢁ3 matched resistors to either the buffered VREFP or buffered
VREFN voltage. The remaining 14 bits of the data-word drive
Switches S0 to S13 of a 14-bit voltage mode R-2R ladder
network.
SERIAꢀ INTERFACE
The AD5790 has a 3-wire serial interface (
, SCꢀK, and
SYNC
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see Figure 2 for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCꢀK, which can operate at up to 35 MHz. The
W
input register consists of a R/ bit, three address bits and
20 data bits as shown in Table ꢁ. The timing diagram for this
operation is shown in Figure 2.
Table 6. Input Shift Register Format
MSB
ꢀSB
DB23
DB22
DB21
Register address
DB20
DB19 to DB0
R/W
Register data
Table 7. Decoding the Input Shift Register
R/W
X1
0
0
0
0
1
1
Register Address
Description
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Io operation (IOP)ꢁ Used in readback operationsꢁ
Write to the DAC registerꢁ
Write to the control registerꢁ
Write to the clearcode registerꢁ
Write to the software control registerꢁ
Read from the DAC registerꢁ
Read from the control registerꢁ
Read from the clearcode registerꢁ
1
1 X is don’t careꢁ
Revꢁ B | Page 19 of 28
AD5790
Data Sheet
STANDAꢀONE OPERATION
AD5790*
CONTROLLER
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCꢀK source can be used
DATA OUT
SERIAL CLOCK
CONTROL OUT
SDIN
SCLK
SYNC
SYNC
only if
In gated clock mode, a burst clock containing the exact number
SYNC
is held low for the correct number of clock cycles.
DATA IN
SDO
of clock cycles must be used, and
must be taken high
after the final clock to latch the data. The first falling edge of
SDIN
SYNC
starts the write cycle. Exactly 24 falling clock edges must
AD5790*
SYNC
be applied to SCꢀK before
SYNC
is brought high again. If
th
is brought high before the 24 falling SCꢀK edge, the
SCLK
SYNC
data written is invalid. If more than 24 falling SCꢀK edges are
SYNC
applied before
invalid.
is brought high, the input data is also
SDO
SYNC
must be brought
The input shift register is updated on the rising edge of
SYNC
.
For another serial transfer to take place,
SDIN
low again. After the end of the serial data transfer, data is
automatically transferred from the input shift register to the
addressed register. When the write cycle is complete, the output
AD5790*
SCLK
SYNC
ꢀDAC
SYNC
can be updated by taking
low while
is high.
Daisy-Chain Operation
SDO
For systems that contain several devices, the SDO pin can be
used to daisy chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 51. Daisy-Chain Block Diagram
SYNC
of serial interface lines. The first falling edge of
write cycle. SCꢀK is continuously applied to the input shift
SYNC
starts the
Readback
The contents of all the on-chip registers can be read back via
the SDO pin. Table 7 outlines how the registers are decoded.
After a register has been addressed for a read, the next 24 clock
cycles clock the data out on the SDO pin. The clocks must be
register when
is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCꢀK and is valid on the falling edge. By connecting the SDO
of the first device to the SDIN input of the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24 × N, where N is the total number of
AD5790 devices in the chain. When the serial transfer to all
SYNC
SYNC
applied while
is low. When
is returned high, the
SDO pin is placed in tristate. For a read of a single register, the
NOP function can be used to clock out the data. Alternatively,
if more than one register is to be read, the data of the first
register to be addressed can be clocked out at the same time
the second register to be read is being addressed. The SDO pin
must be enabled to complete a readback operation. The SDO
pin is enabled by default.
SYNC
devices is complete,
is taken high. This latches the input
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
HARDWARE CONTROꢀ PINS
SYNC
A continuous SCꢀK source can be used only if
is held
LDAC
Load DAC Function (
)
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
After data has been transferred into the input register of the
DAC, there are two ways to update the DAC register and DAC
SYNC
be used, and
latch the data.
must be taken high after the final clock to
SYNC
ꢀDAC
output. Depending on the status of both
and
, one
of two update modes is selected: synchronous DAC update or
asynchronous DAC update.
In any one daisy-chain sequence, do not mix writes to the DAC
register with writes to any of the other registers. All writes to the
daisy-chained parts must be either writes to the DAC registers
or writes to the control, clearcode, or software control register.
Synchronous DAC Update
ꢀDAC
In this mode,
the input shift register. The DAC output is updated on the rising
SYNC
is held low while data is being clocked into
edge of
.
Revꢁ B | Page 20 of 28
Data Sheet
AD5790
CꢀR
pin is
Asynchronous DAC Update
output cannot be updated with a new value while the
low. A clear operation can also be performed by setting the CꢀR
bit in the software control register (see Table 13).
ꢀDAC
In this mode,
into the input shift register. The DAC output is asynchronously
ꢀDAC SYNC
is held high while data is being clocked
updated by taking
The update now occurs on the falling edge of
RESET
low after
has been taken high.
ON-CHIP REGISTERS
DAC Register
ꢀDAC
.
Table 9 outlines how data is written to and read from the DAC
register.
Reset Function (
The AD5790 can be reset to its power-on state by two means:
RESET
)
The following equation describes the ideal transfer function of
the DAC:
either by asserting the
control function (see Table 13). If the
hardwire it to IOVCC
Asynchronous Clear Function (CLR)
pin or by using the software reset
RESET
pin is not used,
.
VREFP −VREFN × D
)
VOUT
where:
=
+VREFN
220
CꢀR
The
pin is an active low clear that allows the output to
be cleared to a user defined value. The 20-bit clear code value
is programmed to the clearcode register (see Table 12). It is
V
V
REFN is the negative voltage applied at the VREFN input pin.
REFP is the positive voltage applied at the VREFP input pin.
CꢀR
D is the 20-bit code programmed to the DAC.
necessary to maintain
to complete the operation (see Figure 2).When the
is returned high the output remains at the clear value (if
low for a minimum amount of time
CꢀR
signal
ꢀDAC
is high) until a new value is loaded to the DAC register. The
Table 8. Hardware Control Pins Truth Table
ꢀDAC
CꢀR
RESET
Function
X1
X1
0
0
1
X1
X1
0
1
0
1
0
1
0
0
The AD5790 is in reset modeꢁ The device cannot be programmedꢁ
The AD5790 is returned to its power-on stateꢁ All registers are set to their default valuesꢁ
The DAC register is loaded with the clearcode register value and the output is set accordinglyꢁ
The output is set according to the DAC register valueꢁ
The DAC register is loaded with the clearcode register value and the output is set accordinglyꢁ
The output is set according to the DAC register valueꢁ
The output remains at the clearcode register valueꢁ
The output remains set according to the DAC register valueꢁ
The output remains at the clearcode register valueꢁ
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
The DAC register is loaded with the clearcode register value and the output is set accordinglyꢁ
The DAC register is loaded with the clearcode register value and the output is set accordinglyꢁ
The output remains at the clearcode register valueꢁ
The output is set according to the DAC register valueꢁ
1 X is don’t careꢁ
Table 9. DAC Register
MSB
ꢀSB
DB23
R/W
DB22
DB21
DB20
DB19 to DB0
Register address
0
DAC register data
20 bits of data
R/W
0
1
Revꢁ B | Page 21 of 28
AD5790
Data Sheet
Clearcode Register
The clearcode register sets the value to which the DAC output is
set when the pin or CꢀR bit in the software control register
Control Register
The control register controls the mode of operation of the
AD5790.
CꢀR
is asserted. The output value depends on the DAC coding that is
being used, either binary or twos complement. The default
register value is 0.
Table 10. Control Register
MSB
ꢀSB
DB23 DB22 DB21 DB20 DB19 to DB11 DB10
DB9 DB8 DB7 DB6 DB5
Control register data
SDODꢀS BꢀI/2sC DACTRꢀ OPGID RBUF Reserved
DB4
DB3
DB2
DB1
DB0
W
Register address
R/
R/
W
0
1
0
Reserved
Reserved
0000
Table 11. Control Register Functions
Bit Name
Reserved
RBUF
Description
These bits are reserved and should be programmed to zeroꢁ
Output amplifier configuration controlꢁ
0: the internal amplifier, A1, is powered up and Resistors RFB and R1 are connected in series, as shown in Figure 54ꢁ This
allows an external amplifier to be connected in a gain of two configurationꢁ See the AD5790 Features section for further
detailsꢁ
1: (default) the internal amplifier, A1, is powered down and Resistors RFB and R1 are connected in parallel, as shown in Figure 53,
so that the resistance between the RFB and ꢀIV pins is 3ꢁ4 kΩ, equal to the resistance of the DACꢁ This allows the RFB and ꢀIV
pins to be used for input bias current compensation for an external unity-gain amplifierꢁ See the AD5790 Features section
for further detailsꢁ
OPGID
Output ground clamp controlꢁ
0: the DAC output clamp to ground is removed and the DAC is placed in normal modeꢁ
1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate modeꢁ
Resetting the part puts the DAC in OPGID mode, where the output ground clamp is enabled and the DAC is tristatedꢁ
Setting the OPGID bit to 1 in the control register overrules any write to the DACTRꢀ bitꢁ
DACTRꢀ
BꢀI/2sC
SDODꢀS
R/W
DAC tristate controlꢁ
0: the DAC is in normal operating modeꢁ
1: (default) DAC is in tristate modeꢁ
DAC register coding selectionꢁ
0: (default) the DAC register uses twos complement codingꢁ
1: the DAC register uses offset binary codingꢁ
SDO pin enable/disable controlꢁ
0: (default) the SDO pin is enabledꢁ
1: the SDO pin is disabled (tristate)ꢁ
Read/write select bitꢁ
0: AD5790 is addressed for a write operationꢁ
1: AD5790 is addressed for a read operationꢁ
Table 12. Clearcode Register
MSB
ꢀSB
DB23
R/W
DB22
DB21
DB20
DB19 to DB0
Register address
1
Clearcode register data
20 bits of data
R/W
0
1
Revꢁ B | Page 22 of 28
Data Sheet
AD5790
Software Control Register
This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low.
Table 13. Software Control Register
MSB
ꢀSB
DB23
R/W
0
DB22
DB21
DB20
DB19 to DB3
DB2
Software control register data
Reset
CLR1
DB1
DB0
LDAC2
Register address
0
1
0
Reserved
1
LDAC
CLR
The CLR function has no effect when the
The LDAC function has no effect when the
pin is lowꢁ
pin is lowꢁ
2
Table 14. Software Control Register Functions
Bit Name
Description
LDAC
Setting this bit to 1 updates the DAC register and consequently the DAC outputꢁ
CLR
Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC outputꢁ The output
value depends on the DAC register coding that is being used, either binary or twos complementꢁ
Reset
Setting this bit to 1 returns the AD5790 to its power-on stateꢁ
Revꢁ B | Page 23 of 28
AD5790
Data Sheet
AD5790 FEATURES
A second unity-gain configuration for the output amplifier is
one that removes an offset from the input bias currents of the
amplifier. It does this by inserting a resistance in the feedback
path of the amplifier that is equal to the output resistance of the
DAC. The DAC output resistance is 3.4 kΩ. By connecting R1
and RFB in parallel, a resistance equal to the DAC resistance is
available on chip. Because the resistors are all on one piece of
silicon, they are temperature coefficient matched. To enable this
mode of operation the RBUF bit of the control register must be
set to ꢀogic 1. Figure 53 shows how the output amplifier is
connected to the AD5790. In this configuration, the output
amplifier is in unity gain and the output spans from VREFN to
POWER-ON TO 0 V
The AD5790 contains a power-on reset circuit that, as well as
resetting all registers to their default values, controls the output
voltage during power-up. Upon power-on, the DAC is placed in
tristate (its reference inputs are disconnected), and its output is
clamped to AGND through a ~ꢁ kΩ resistor. The DAC remains
in this state until programmed otherwise via the control register.
This is a useful feature in applications where it is important to
know the state of the DAC output while it is in the process of
powering up.
CONFIGURING THE AD5790
VREFP. This unity-gain configuration allows a capacitor to be placed
After power-on, the AD5790 must be configured to put it into
normal operating mode before programming the output. To do
this, the control register must be programmed. The DAC is
removed from tristate by clearing the DACTRI bit, and the
output clamp is removed by clearing the OPGND bit. At this
point, the output goes to VREFN, unless an alternative value is
first programmed to the DAC register.
in the amplifier feedback path to improve dynamic performance.
V
REFP
R
FB
R
6.8kΩ
R1
6.8kΩ
FB
10pF
INV
OUT
V
OUT
V
20-BIT
DAC
DAC OUTPUT STATE
AD8675
ADA4898-1
ADA4004-1
The DAC output can be placed in one of three states, controlled
by the DACTRI and OPGND bits of the control register, as
shown in Table 15.
AD5790
V
= 0V
REFN
Figure 53. Output Amplifier in Unity Gain with Amplifier Input Bias Current
Compensation
Table 15. Output State Truth Table
DACTRI OPGND Output State
0
0
1
1
0
1
0
1
Iormal operating mode
Output is clamped via ~6 kΩ to AGID
Output is in tristate
Output is clamped via ~6 kΩ to AGID
OUTPUT AMPꢀIFIER CONFIGURATION
There are a number of different ways that an output amplifier
can be connected to the AD5790, depending on the voltage
references applied and the desired output voltage span.
Unity-Gain Configuration
Figure 52 shows an output amplifier configured for unity gain.
In this configuration, the output spans from VREFN to VREFP
.
V
REFP
6.8kΩ 6.8kΩ
R1
R
FB
A1
AD8675
ADA4898-1
ADA4004-1
R
FB
INV
OUT
V
20-BIT
DAC
V
OUT
AD5790
V
REFN
Figure 52. Output Amplifier in Unity-Gain Configuration
Revꢁ B | Page 24 of 28
Data Sheet
AD5790
V
REFP
Gain of Two Configuration (×2 Gain Mode)
Figure 54 shows an output amplifier configured for a gain of
two. The gain is set by the internal matched ꢁ.8 kΩ resistors,
which are exactly twice the DAC resistance, having the effect of
removing an offset from the input bias current of the external
amplifier. In this configuration, the output spans from 2 ×
6.8kΩ 6.8kΩ
R1
R
FB
A1
R
10pF
FB
INV
OUT
V
OUT
V
20-BIT
DAC
AD8675
ADA4898-1
ADA4004-1
V
REFN − VREFP to VREFP. This configuration is used to generate a
bipolar output span from a single ended reference input with
REFN = 0 V. For this mode of operation, the RBUF bit of the
control register must be cleared to ꢀogic 0.
AD5790
V
V
REFN
Figure 54. Output Amplifier in Gain of Two Configuration
Revꢁ B | Page 25 of 28
AD5790
Data Sheet
APPꢀꢁCATꢁOIS ꢁIFORMATꢁOI
TYPICAꢀ OPERATING CIRCUIT
5 5 0 9 - 0 2 1 3
Figure 55. Typical Operating Circuit
Revꢁ B | Page 26 of 28
Data Sheet
AD5790
Figure 55 shows a typical operating circuit for the AD5790
using an AD8ꢁ75 as an output buffer. Because the output
impedance of the AD5790 is 3.4 kΩ, an output buffer is
required for driving low resistive, high capacitive loads.
The evaluation board interfaces to the USB port of a PC. Soft-
ware is available with the evaluation board to allow the user to
easily program the AD5790. The software runs on any PC that
has Microsoft® Windows® XP (SP2), or Vista (32-bit or ꢁ4-bit),
or Windows 7 installed. The AD5790 user guide, UG-342, is
available, which gives full details on the operation of the
evaluation board.
EVAꢀUATION BOARD
An evaluation board is available for the AD5790 to aid
designers in evaluating the high performance of the part
with minimum effort. The AD5790 evaluation kit includes
a populated and tested AD5790 printed circuit board (PCB).
Revꢁ B | Page 27 of 28
AD5790
Data Sheet
OUTꢀꢁIE DꢁMEISꢁOIS
2.75
2.65
2.50
4.00 BSC
PIN 1
PIN 1
INDICATOR
(Chamfer 0.225)
INDICATOR
20
24
19
1
0.50
BSC
5.00 BSC
3.75
3.65
3.50
EXPOSED
PAD
13
7
12
8
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
1.00
0.90
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.25
0.20
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 5 mm Body, Very Thin Quad
(CP-24-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5790BCPZ
AD5790BCPZ-RL7
EVAL-AD5790SDZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
INꢀ
4 LSB
4 LSB
Package Description
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Evaluation Board
Package Option
CP-24-5
CP-24-5
1 Z = RoHS Compliant Partꢁ
©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10239-0-2/12(B)
Revꢁ B | Page 28 of 28
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