AD5930YRUZ [ADI]
Programmable Frequency Sweep and Output Burst Waveform Generator; 可编程频率扫描和输出脉冲波形发生器
| 型号： | AD5930YRUZ |
| 厂家： | 
ADI |
| 描述： | Programmable Frequency Sweep and Output Burst Waveform Generator |
| 文件： | 总28页 (文件大小：856K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Programmable Frequency Sweep and
Output Burst Waveform Generator
AD5930
FEATURES
GENERAL DESCRIPTION
Programmable frequency profile
No external components necessary
Output frequency up to 25 MHz
Burst and listen capability
Preprogrammable frequency profile minimizes number of
DSP/µcontroller writes
Sinusoidal/triangular/square wave outputs
Automatic or single pin control of frequency stepping
Waveform starts at known phase
Increments at 0° phase or phase continuously
Power-down mode: 20 µA
1
The AD5930 is a waveform generator with programmable
frequency sweep and output burst capability. Utilizing
embedded digital processing that allows enhanced frequency
control, the device generates synthesized analog or digital
frequency-stepped waveforms. Because frequency profiles
are preprogrammed, continuous write cycles are eliminated
and thereby free up valuable DSP/µcontroller resources.
Waveforms start from a known phase and are incremented
phase continuously, which allows phase shifts to be easily
determined. Consuming only 8 mA, the AD5930 provides a
convenient low power solution to waveform generation.
Power supply: 2.3 V to 5.5 V
The AD5930 can be operated in a variety of modes. In
continuous output mode, the device outputs the required
frequency for a defined length of time and then steps to the
next frequency. The length of time the device outputs a
particular frequency is either preprogrammed and the device
increments the frequency automatically, or, alternatively, is
incremented externally via the CTRL pin. In burst mode, the
device outputs its frequency for a length of time and then
returns to midscale for a further predefined length of time
before stepping to the next frequency. When the MSBOUT pin
is enabled, a digital output is generated.
Automotive temperature range: −40°C to +125°C
20-lead pb-free TSSOP
APPLICATIONS
Frequency sweeping/radar
Network/impedance measurements
Incremental frequency stimulus
Sensory applications
Proximity and motion
BFSK
Frequency bursting/pulse trains
(continued on Page 3)
FUNCTIONAL BLOCK DIAGRAM
INTERRUPT STANDBY
DVDD CAP/2.5V
DGND
AGND AVDD
AD5930
REGULATOR
VCC
2.5V
SYNC
SYNCOUT
MCLK
CTRL
BUFFER
BUFFER
OUTPUT BURST
CONTROLLER
DGND O/P
MSBOUT
DATA
SYNC
INCREMENT
CONTROLLER
24-BIT
PIPELINED
DDS CORE
IOUTB
IOUT
DATA
INCR
10-BIT
DAC
FREQUENCY
CONTROLLER
24
DATA
AND CONTROL
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
COMP
CONTROL
REGISTER
SERIAL INTERFACE
REF
FSADJUST
FSYNC SCLK SDATA
Figure 1.
1 Protected by US Patent Number 6747583, other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.Trademarks and registered trademarks are theproperty of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD5930
TABLE OF CONTENTS
Features .............................................................................................. 1
Powering up the AD5930.......................................................... 17
Programming the AD5930........................................................ 17
Setting up the Frequency Sweep............................................... 19
Activating and Controlling the Sweep..................................... 20
Outputs from the AD5930 ........................................................ 21
Applications..................................................................................... 22
Grounding and Layout .............................................................. 22
AD5930 to ADSP-21xx Interface ............................................. 22
AD5930 to 68HC11/68L11 Interface....................................... 23
AD5930 to 80C51/80L51 Interface.......................................... 23
AD5930 to DSP56002 Interface ............................................... 23
Evaluation Board........................................................................ 24
Schematic..................................................................................... 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Timing Characteristics..................................................................... 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
The Frequency Profile................................................................ 16
Output Modes............................................................................. 16
Serial Interface ............................................................................ 17
REVISION HISTORY
11/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5930
GENERAL DESCRIPTION
(continued from Page 1)
sweep again. In addition, a single frequency or burst can be
generated without any sweep.
To program the device, the user enters the start frequency, the
increment step size, the number of increments to be made, and
the time interval that the part outputs each frequency. The
frequency sweep profile is initiated, started, and executed by
toggling the CTRL pin.
The AD5930 is written to via a 3-wire serial interface, which
operates at clock rates up to 40 MHz. The device operates with
a power supply from 2.3 V to 5.5 V. Note that AVDD and DVDD
are independent of each other and can be operated from
different voltages. The AD5930 also has a standby function,
which allows sections of the device that are not being used
to be powered down.
A number of different sweep profiles are offered. Frequencies can
be stepped in triangular-sweep mode, which continuously sweeps
up and down through the frequency range. Alternatively, in saw-
sweep mode, the frequency is swept up through the frequency
range, but returns to the initial frequency before executing the
The AD5930 is available in a 20-lead pb-free TSSOP package.
Rev. 0 | Page 3 of 28
AD5930
SPECIFICATIONS
AVDD = DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ, RLOAD = 200 Ω for IOUT and IOUTB,
unless otherwise noted.
Table 1.
Y Grade1
Parameter
Min
Typ
Max Unit
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10
Bits
Update Rate
50
4.0
MSPS
mA
V
mV
V
IOUT Full-Scale2
3
0.56
45
VOUT Peak-to-Peak
VOUT Offset
VMIDSCALE
From 0 V to the trough of the waveform
Voltage at midscale output
0.325
Output Compliance
DC Accuracy
0.8
V
AVDD = 2.3 V, internal reference used3
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio
Total Harmonic Distortion
1.5
0.75
LSB
LSB
53
60
−60
dB
dBc
fMCLK = 50 MHz, fOUT = fMCLK/4096
fMCLK = 50 MHz, fOUT = fMCLK/4096
−53
Spurious-Free Dynamic Range
(SFDR)
Wideband (0 to Nyquist)
Narrowband ( 200 kHz)
Clock Feedthrough
−62
−76
−50
1.7
−52
−73
dBc
dBc
dBc
ms
fMCLK = 50 MHz, fOUT = fMCLK/50
fMCLK = 50 MHz, fOUT = fMCLK/50
Up to 16 MHz out
Wake-Up Time
From standby
OUTPUT BUFFER
VOUT Peak-to-Peak
0
DVDD
V
Typically, square wave on MSBOUT and SYNCOUT
Output Rise/Fall Time2
VOLTAGE REFERENCE
Internal Reference
External Reference Range
REFOUT Input Impedance
12
ns
1.15
1.18
1.26
1.3
V
V
kΩ
1
VIN @ REF pin < Internal VREF
VIN @ REF pin > Internal VREF
25
90
kΩ
ppm/°C
Reference TC2
LOGIC INPUTS
Input Current
VINH, Input High Voltage
0.1
1
µA
V
V
1.7
2.0
2.8
DVDD = 2.3 V to 2.7 V
DVDD = 2.7 V to 3.6 V
DVDD = 4.5 V to 5.5 V
DVDD = 2.3 V to 2.7 V
DVDD = 2.7 V to 3.6 V
DVDD = 4.5 V to 5.5 V
V
VINL, Input Low Voltage
0.6
0.7
0.8
V
V
V
pF
CIN, Input Capacitance2
LOGIC OUTPUTS2
VOH, Output High Voltage
VOL, Output Low Voltage
Floating-State O/P Capacitance
3
5
DVDD − 0.4 V
V
V
pF
ISINK = 1 mA
ISINK = 1 mA
0.4
Rev. 0 | Page 4 of 28
AD5930
Y Grade1
Typ
Parameter
Min
Max Unit
Test Conditions/Comments
POWER REQUIREMENTS
fMCLK = 50 MHz, fOUT = fMCLK/7
AVDD/DVDD
IAA
IDD
IAA + IDD
2.3
5.5
4
2.7
6.7
V
3.8
2.4
6.2
mA
mA
mA
Low Power Sleep Mode
Device is reset before putting into standby
20
140
85
240
µA
µA
All outputs powered down, MCLK = 0 V, serial interface active
All outputs powered down, MCLK active, serial interface active
1 Operating temperature range is as follows: Y Version: −40°C to +125°C; typical specifications are at 25°C.
2 Guaranteed by design.
3 Minimum RSET = 3.9 kΩ.
R
SET
6.8V
100nF
10nF
AVDD
10nF
CAP/2.5V
REFOUT
FSADJUST
COMP
ON-BOARD
FULL-SCALE
REGULATOR
REFERENCE
CONTROL
12
IOUT
SIN
ROM
10-BIT
DAC
AD5930
R
LOAD
200V
20pF
Figure 2. Test Circuit Used to Test the Specifications
Rev. 0 | Page 5 of 28
AD5930
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 4 to Figure 7. DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.1
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
20
8
8
25
10
10
5
10
5
3
2 x t1
0
10 x t1
8 x t1
2 x t1
2 x t1
2 x t1
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
ns typ
ns max
MCLK period
MCLK high duration
MCLK low duration
SCLK period
SCLK high time
SCLK low time
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
t9
t10
t11
t12
t13
Data hold time
Minimum CTRL pulse width
CTRL rising edge to MCLK falling edge setup time
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
Frequency change to SYNC output, saw sweep, each frequency increment
Frequency change to SYNC output, saw sweep, end of sweep
Frequency change to SYNC output, triangle sweep, end of sweep
MCLK falling edge after 16th clock edge to MSB out
t14
t15
t16
t17
1 Guaranteed by design, not production tested.
t1
MCLK
t2
t3
Figure 3. Master Clock
t5
t4
SCLK
t7
t6
t8
FSYNC
SDATA
t10
t9
D15
D14
D2
D1
D0
D15
D14
Figure 4. Serial Timing
Rev. 0 | Page 6 of 28
AD5930
t12
MCLK
CTRL
t11
IOUT/IOUTB
t13
Figure 5. CTRL Timing
CTRL
t13
IOUT
SYNC O/P
(Each Frequency
Increment)
t14
SYNC O/P
(End of Sweep)
t15
Figure 6. CTRL Timing, Saw-Sweep Mode
CTRL
IOUT
t13
SYNC O/P
(Each Frequency
Increment)
t14
SYNC O/P
(End of Sweep)
t16
Figure 7. CTRL Timing, Triangular-Sweep Mode
Rev. 0 | Page 7 of 28
AD5930
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVDD to AGND
DVDD to DGND
AGND to DGND
CAP/2.5V to DGND
−0.3 V to +6.0 V
−0.3 V to +6.0 V
−0.3 V to +0.3 V
−0.3 V to 2.75 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
Digital I/O Voltage to DGND
Analog I/O Voltage to AGND
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering (Pb-Free)
PeakTemperature
−40°C to +125°C
−65°C to +150°C
+150°C
112°C/W
27.6°C/W
300°C
260(+0/−5)°C
10 sec to 40 sec
Time at PeakTemperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 28
AD5930
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
20
19
18
17
16
15
14
13
12
11
FSADJUST
IOUTB
2
REF
IOUT
3
COMP
AGND
AD5930
TOP VIEW
(Not to Scale)
4
AVDD
STANDBY
FSYNC
SCLK
5
DVDD
6
CAP/2.5V
DGND
7
SDATA
CTRL
8
MCLK
9
SYNCOUT
MSBOUT
INTERRUPT
DGND O/P
10
Figure 8. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
FSADJUST
Full-Scale Adjust Control. A resistor (RSET) must be connected externally between this pin and AGND.
This determines the magnitude of the full-scale DAC current. The relationship between RSET and the
full-scale current is:
IOUTFULL-SCALE = 18 × VREFOUT/RSET
where VREFOUT = 1.20 V nominal and RSET = 6.8 kΩ typical.
2
REF
Voltage Reference. This pin can be an input or an output. The AD5930 has an internal 1.18 V reference, which
is made available at this pin. Alternatively, this reference can be overdriven by an external reference, with a
voltage range as given in the Specifications section. A 10 nF decoupling capacitor should be connected
between REF and AGND.
3
4
COMP
AVDD
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage to AVDD.
Positive Power Supply for the Analog Section. AVDD can have a value from +2.3 V to +5.5 V. A 0.1 µF decoupling
capacitor should be connected between AVDD and AGND.
5
6
DVDD
Positive Power Supply for the Digital Section. DVDD can have a value from +2.3 V to +5.5 V. A 0.1 µF decoupling
capacitor should be connected between DVDD and DGND.
Digital Circuitry. Operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board
regulator. The regulator requires a decoupling capacitor of typically 100 nF, which is connected from CAP/2.5V
to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5V can be shorted to DVDD.
CAP/2.5V
7
8
DGND
MCLK
Ground for all Digital Circuitry. This excludes digital output buffers.
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK.
The output frequency accuracy and phase noise are determined by this clock.
9
SYNCOUT
MSBOUT
Digital Output for Sweep Status Information. User selectable for end of sweep (EOS) or frequency increments
through the control register (SYNCOP bit). This pin must be enabled by setting Control Register Bit SYNCOPEN to 1.
Digital Output. The inverted MSB of the DAC data is available at this pin. This output pin must be enabled by
setting bit MSBOUTEN in the control register to 1.
10
11
12
DGND O/P
Separate DGND Connection for Digital Output Buffers. Connect to DGND.
INTERRUPT Digital Input. This pins acts as an interrupt during a frequency sweep. A low to high transition is sampled by the
internal MCLK, which resets internal state machines. This results in the DAC output going to midscale.
13
CTRL
Digital Input. Triple function pin for initialization, start, and external frequency increments. A low-to-high transition,
sampled by the internal MCLK, is used to initialize and start internal state machines, which then execute the pre-
programmed frequency sweep sequence. When in auto-increment mode, a single pulse executes the entire sweep
sequence. When in external increment mode, each frequency increment is triggered by low-to-high transitions.
14
SDATA
Serial Data Input. The 16-bit serial data-word is applied to this input with the register address first followed by the
MSB to LSB of the data.
15
16
SCLK
FSYNC
Serial Clock Input. Data is clocked into the AD5930 on each falling SCLK edge.
Active Low Control Input. This is the frame synchronization signal for the serial data. When FSYNC is taken low,
the internal logic is informed that a new word is being loaded into the device.
17
STANDBY
Active High Digital Input. When this pin is high, the internal MCLK is disabled, and the reference DAC and regulator
are powered down. For optimum power saving, it is recommended to reset the AD5930 before putting it into
standby, as this results in a shutdown current of typically 20 µA.
Rev. 0 | Page 9 of 28
AD5930
Pin No. Mnemonic Description
18
19
AGND
IOUT
Ground for all Analog Circuitry.
Current Output. This is a high impedance current source output. A load resistor of nominally 200 Ω should be
connected between IOUT and AGND. A 20 pF capacitor to AGND is also recommended to act as a low-pass filter
and to reduce clock feedthrough. In conjunction with IOUTB, a differential signal is available.
20
IOUTB
Current Output. IOUTB is the compliment of IOUT. This pin should preferably be tied through an external load
resistor of 200 Ω to AGND, but can be tied directly to AGND. A 20 pF capacitor to AGND is also recommended as a
low-pass filter to reduce clock feedthrough. In conjunction with IOUT, a differential signal is available.
Rev. 0 | Page 10 of 28
AD5930
TYPICAL PERFORMANCE CHARACTERISTICS
9
–40
T
= 25°C
AVDD = DVDD = 3V/5V
–45 MCLK = 50MHz
= 0111 1111 1111
A
AVDD = 5V
MSBOUT, SYNCOUT ENABLED
8
7
6
5
4
3
2
1
0
C
REG
T = 25°C
A
–50
–55
–60
–65
–70
DVDD = 5V
F
F
= MCLK/7
OUT
= MCLK/50
OUT
DVDD = 3V
DVDD = 5V, F
OUT
= MCLK/7
–75
–80
–85
–90
F
= MCLK/3
OUT
DVDD = 3V, F
OUT
= MCLK/7
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
MCLK FREQUENCY (MHz)
MCLK FREQUENCY (MHz)
Figure 9. Current Consumption (IDD) vs. MCLK Frequency
Figure 12. Wideband SFDR vs. MCLK Frequency
7
–60
–65
T
= 25°C
A
AVDD = DVDD = 3V/5V
MCLK = 50MHz
MSBOUT ON,
SYNCOUT ON
MCLK = 50MHz
6
C
= 0111 1111 1111
REG
= 25°C
T
A
5
4
3
MSBOUT OFF,
SYNCOUT ON
F
= MCLK/50
–70
–75
–80
–85
–90
OUT
MSBOUT ON,
SYNCOUT OFF
F
= MCLK/3
OUT
MSBOUT OFF,
SYNCOUT OFF
2
1
0
F
= MCLK/7
OUT
1kHz
500kHz 10kHz
100kHz
1MHz
5MHz
15MHz
25MHz
0
5
10
15
20
25
30
35
40
45
50
500kHz
2MHz 10MHz
20MHz
MCLK FREQUENCY (MHz)
F
(Hz)
OUT
Figure 10. IDD vs. FOUT for Various Digital Output Conditions
Figure 13. Narrowband SFDR vs. MCLK Frequency
–30
–40
3.5
AVDD = DVDD = 3V/5V
C
= 0111 1111 1111
REG
AIDD
3.0
T
= 25°C
A
MCLK = 50MHz
2.5
–50
–60
–70
–80
–90
DIDD
2.0
1.5
1.0
MCLK = 10MHz
MCLK = 1MHz
LEGEND
MCLK = 30MHz
1. SINEWAVE OUTPUT, INTERNALLY CONTROLLED SWEEP
0.5
0
2. TRIANGULAR OUTPUT, INTERNALLY CONTROLLED SWEEP
3. SINEWAVE OUTPUT, EXTERNALLY CONTROLLED SWEEP
4. TRIANGULAR OUTPUT, EXTERNALLY CONTROLLED SWEEP
0.001
0.01
0.1
1
10
100
1
2
3
4
F
(MHz)
CONTROL OPTION (See Legend)
OUT
Figure 11. IDD vs. Output Waveform Type and Control
Figure 14. Wideband SFDR vs. FOUT for Various MCLK Frequencies
Rev. 0 | Page 11 of 28
AD5930
70
65
60
55
50
12
10
8
T
= 25°C
A
AVDD = DVDD = 5V
fOUT = FMCLK/4096
6
4
45
2
0
40
0
552 554 556 558 560 562 564 566 568 570 572
PEAK-TO-PEAK (mV)
10M
20M
30M
40M
50M
MCLK FREQUENCY (MHz)
V
OUT
Figure 15. SNR vs. MCLK Frequency
Figure 18. Histogram of VOUT Peak-to-Peak
1.25
1.23
12
10
8
AVDD = DVDD = 5V
1.21
1.19
1.17
6
4
2
0
1.15
–40
–20
0
20
40
60
80
100
120
44.4 44.6 44.8 45.0 45.2 45.4 45.6 45.8 46.0 46.2
OFFSET (mV)
TEMPERATURE (°C)
V
OUT
Figure 16. VREF vs. Temperature
Figure 19. Histogram of VOUT Offset
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
0
–10
–20
–30
T
= 25°C
A
100mV p-p RIPPLE
NO DECOUPLING ON SUPPLIES
AVDD = DVDD = 5V
AVDD = DVDD = 2.3V
AVDD = DVDD = 5V
DVDD (on CAP/2.5V)
–40
–50
–60
–70
–80
AVDD (on IOUT)
1.2
–40
–20
0
20
40
60
80
100
120
10
100
1k
10k
100k
1M
TEMPERATURE (°C)
MODULATING FREQUENCY (Hz)
Figure 17. Wake-up Time vs. Temperature
Figure 20. PSSR
Rev. 0 | Page 12 of 28
AD5930
0
–10
–20
0
–10
–20
–30
–30
–40
–50
–60
–40
–50
–60
–70
–80
–90
–100
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
0
5M
100
1k
10k
100k
RWB 1K
VWB 300
ST 50 SEC
f
(Hz)
FREQUENCY (Hz)
Figure 21. Output Phase Noise
Figure 24. fMCLK = 10 MHz; fOUT = 3.33 MHz = fMCLK/3,
Frequency Word = 5555555
0
–10
–20
–30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
0
RWB 100
100k
ST 100 SEC
0
160k
ST 200 SEC
VWB 30
RWB 100
VWB 30
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. fMCLK = 10 MHz;
OUT = 2.4 kHz, Frequency Word = 000FBA9
Figure 25. fMCLK = 50 MHz;
OUT = 12 kHz, Frequency Word = 000FBA9
f
f
0
–10
–20
–30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
0
1.6M
ST 200 SEC
0
RWB 1K
5M
ST 50 SEC
RWB 100
VWB 300
VWB 300
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26. fMCLK = 50 MHz;
OUT = 120 kHz, Frequency Word = 009D496
Figure 23. fMCLK = 10 MHz;
OUT = 1.43 MHz = fMCLK/7, Frequency Word = 2492492
f
f
Rev. 0 | Page 13 of 28
AD5930
0
–10
–20
–30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
–100
–100
0
25M
ST 200 SEC
0
25M
ST 200 SEC
RWB 1K
VWB 300
RWB 1K
VWB 300
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27. fMCLK = 50 MHz;
OUT = 1.2 MHz, Frequency Word = 0624DD3
Figure 29. fMCLK = 50 MHz; fOUT = 7.143 MHz = fMCLK/7,
Frequency Word = 2492492
f
0
0
–10
–20
–30
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
0
25M
ST 200 SEC
0
25M
ST 200 SEC
RWB 1K
VWB 300
RWB 1K
VWB 300
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. fMCLK = 50 MHz; fOUT = 16.667 MHz = fMCLK/3,
Frequency Word = 5555555
Figure 28. fMCLK = 50 MHz;
OUT = 4.8 MHz, Frequency Word = 189374C
f
Rev. 0 | Page 14 of 28
AD5930
TERMINOLOGY
Integral Nonlinearity (INL)
Total Harmonic Distortion (THD)
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale and full scale.
The error is expressed in LSBs.
THD is the ratio of the rms sum of harmonics to the rms value
of the fundamental. For the AD5930, THD is defined as
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD(dB) = 20 log
V1
Differential Nonlinearity (DNL)
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC. A specified
differential nonlinearity of 1 LSB maximum ensures
monotonicity.
through the sixth harmonic.
Signal-to-Noise Ratio (SNR)
Output Compliance
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency. The value for SNR is expressed in decibels.
The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifica-
tions. When voltages greater than that specified for the output
compliance are generated, the AD5930 may not meet the
specifications listed in the data sheet.
Clock Feedthrough
There is feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD5930’s output spectrum.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the
fundamental frequency and images of these frequencies are
present at the output of a DDS device. The SFDR refers to the
largest spur or harmonic that is present in the band of interest.
The wide band SFDR gives the magnitude of the largest
harmonic or spur relative to the magnitude of the fundamental
frequency in the 0 to Nyquist bandwidth. The narrow band
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of 200 kHz about the fundamental frequency.
Rev. 0 | Page 15 of 28
AD5930
THEORY OF OPERATION
Triangular-Sweep Mode
The AD5930 is a general-purpose synthesized waveform
generator capable of providing digitally programmable
waveform sequences in both the frequency and time domain.
The device contains embedded digital processing to provide a
repetitive sweep of a user programmable frequency profile
allowing enhanced frequency control. Because the device is pre-
programmable, it eliminates continuous write cycles from a
DSP/μcontroller in generating a particular waveform.
In the case of a triangular sweep, the AD5930 repeatedly
sweeps between sweep start to sweep end, that is, from FSTART
incrementally to
F
START + NINCR × Δf
and then returns to FSTART in a decremented manner (see Figure 32).
The triangular-sweep cycle time is given by
(1 + (2 × NINCR)) × tINT
THE FREQUENCY PROFILE
The frequency profile is defined by the start frequency (FSTART),
the frequency increment (Δf) and the number of increments
per sweep (NINCR). The increment interval between frequency
increments, tINT, is either user programmable with the interval
automatically determined by the device (auto-increment mode),
or externally controlled via a hardware pin (external increment
mode). For automatic update, the interval profile can either be
for a fixed number of clock periods or for a fixed number of
output waveform cycles.
F
START
MIDSCALE
F
F
+ N
INCR
× ∆F
F
START
START
START
F
+ ∆F
F
+ ∆F
START
START
Figure 32. Triangular-Sweep Profile
OUTPUT MODES
In the auto-increment mode, a single pulse at the CTRL pin starts
and executes the frequency sweep. In the external increment
mode, the CTRL pin also starts the sweep, but the frequency
increment interval is determined by the time interval between
sequential 0/1 transitions on the CTRL pin. Furthermore, the
CTRL pin can be used to directly control the burst profile, where
during the input high time, the output waveform is present, and
during the input low time, the output is reset to midscale.
The AD5930 offers two possible output modes: continuous
output mode and burst output mode. Both of these modes are
illustrated in Figure 33.
tINT
CONTINUOUS
MODE
T
BURST
The frequency profile can be swept in two different modes: saw
sweep or triangular (up/down) sweep.
BURST
MODE
Saw-Sweep Mode
1
2
In the case of a saw sweep, the AD5930 repeatedly
sweeps between sweep start to sweep end, that is, from
FSTART incrementally to
NUMBER STEP CHANGES
Figure 33. Continuous Mode and Burst Mode of the AD5930
Continuous Output Mode
F
START + NINCR × Δf
In this mode, each frequency of the sweep is available for the
length of time programmed into the time interval (tINT) register.
This means the frequency swept output signal is continuously
available, and is therefore phase continuous at all frequency
increments.
and then returns directly to FSTART to begin again (see Figure 31).
This gives a saw-sweep cycle time of
(NINCR + 1) × tINT
To set up the AD5930 in continuous mode, the CW/BURST bit
(D7) in the control register must be set to 0. See the Activating
and Controlling the Sweep section for more details.
Burst Output Mode
In this mode, the AD5930 provides a programmable burst
F
START
of the waveform output for a fixed length of time (TBURST
)
MIDSCALE
within the programmed increment interval (tINT). Then for
the remainder of the tINT interval, the output is reset to mid-
scale and remains there until the next frequency increment.
F
F
+ ∆F
F
START
+ N × ∆F
INCR
START
START
Figure 31. Saw-Sweep Profile
Rev. 0 | Page 16 of 28
AD5930
This is beneficial for applications where the user needs to burst
a frequency for a set period, and then “listen” for a response
before increasing to the next frequency. Note also that the
beginning of each frequency increment is at midscale (Phase 0
Rad). Therefore, the phase of the signal is always known.
PROGRAMMING THE AD5930
The AD5930 is designed to provide automatic frequency sweeps
when the CTRL pin is triggered. The automatic sweep is
controlled by a set of registers, the addresses of which are given
in Table 5. The function of each register is described in more
detail in the following section.
To set up the AD5930 in burst mode, the CW/BURST bit (D7)
in the control register must be set to 1. See the Activating and
Controlling the Sweep section for more details about the burst
output mode.
Table 5. Register Addresses
Register Address
D15 D14 D13 D12 Mnemonic Name
0
0
0
0
0
0
0
1
CREG
NINCR
Control bits
Number of
increments
Lower 12 bits of delta
frequency
Higher 12 bits of
delta frequency
Increment interval
Burst interval
Lower 12 bits of start
frequency
Higher 12 bits of start
frequency
Reserved
Reserved
SERIAL INTERFACE
The AD5930 has a standard 3-wire serial interface, which is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP
interface standards.
0
0
0
0
1
1
0
1
∆f
∆f
Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing diagram for
this operation is given in Figure 4.
0
1
1
1
0
1
tINT
TBURST
FSTART
0
0
0
1
The FSYNC input is a level-triggered input that acts as a frame
synchronization and chip enable. Data can only be transferred
into the device when FSYNC is low. To start the serial data
transfer, FSYNC should be taken low, observing the minimum
FSYNC to SCLK falling edge setup time, t7. After FSYNC goes
low, serial data is shifted into the device's input shift register on
the falling edges of SCLK for 16 clock pulses. FSYNC can be
taken high after the 16th falling edge of SCLK, observing the
minimum SCLK falling edge to FSYNC rising edge time, t8.
Alternatively, FSYNC can be kept low for a multiple of 16 SCLK
pulses, and then brought high at the end of the data transfer. In
this way, a continuous stream of 16-bit words can be loaded while
FSYNC is held low. FSYNC should only go high after the 16th
SCLK falling edge of the last word is loaded.
1
1
FSTART
1
1
1
1
1
1
0
1
The Control Register
The AD5930 contains a 12-bit control register (see Table 6) that
sets up the operating modes of the AD5930. The different
functions and the various output options from the AD5930 are
controlled by this register.
Table 7 describes the individual bits of the control register.
To address the control register, D15 to D12 of the 16-bit serial
word must be set to 0.
The SCLK can be continuous, or, alternatively, the SCLK can
idle high or low between write operations.
Table 6. Control Register
POWERING UP THE AD5930
D15
D14
D13
D12
D11 to D0
0
0
0
0
Control Bits
When the AD5930 is powered up, the part is in an undefined
state, and therefore, must be reset before use. The eight registers
(control and frequency) contain invalid data and need to be set
to a known value by the user. The control register should be the
first register to be programmed, as this sets up the part. Note
that a write to the control register automatically resets the
internal state machines and provides an analog output of
midscale as it provides the same function as the INTERRUPT
pin. Typically, this is followed by a serial loading of all the
required sweep parameters. The DAC output remains at
midscale until a sweep is started using the CTRL pin.
Rev. 0 | Page 17 of 28
AD5930
Table 7. Description of Bits in the Control Register
Bit
Name
Function
D15
to
ADDR
Register address bits.
D12
D11
B24
Two write operations are required to load a complete word into the FSTART register and the ∆f register.
When B24 = 1, a complete word is loaded into a frequency register in two consecutive writes. The first write
contains the 12 LSBs of the frequency word and the next write contains the 12 MSBs. Refer to Table 5 for the
appropriate addresses. The write to the destination register occurs after both words have been loaded, so the
register never holds an intermediate value.
When B24 = 0, the 24-bit FSTART /∆f register operates as two 12-bit registers, one containing the 12 MSBs and the
other containing the 12 LSBs. This means that the 12 MSBs of the frequency word can be altered independent of
the 12 LSBs and vice versa. This is useful if the complete 24-bit update is not required. To alter the 12 MSBs or the
12 LSBs, a single write is made to the appropriate register address. Refer to Table 5 for the appropriate addresses.
D10
D9
DAC ENABLE When DAC ENABLE = 1, the DAC is enabled.
When DAC ENABLE = 0, the DAC is powered down. This saves power and is beneficial when only using the MSB of
the DAC input data (available at the MSBOUT pin).
SINE/TRI
The function of this bit is to control what is available at the IOUT/IOUTB pins.
When SINE/TRI = 1, the SIN ROM is used to convert the phase information into amplitude information resulting in a
sinusoidal signal at the output.
When SINE/TRI = 0, the SIN ROM is bypassed, resulting in a triangular (up-down) output from the DAC.
When MSBOUTEN = 1, the MSBOUT pin is enabled.
When MSBOUTEN = 0, the MSBOUT is disabled (tri-state).
D8
D7
MSBOUTEN
CW/BURST
When CW/BURST = 1, the AD5930 outputs each frequency continuously for the length of time or number of output
waveform cycles specified in the appropriate register, TBURST
.
When CW/BURST = 0, the AD5930 bursts each frequency for the length of time/number of cycles specified in the
burst register, TBURST. For the remainder of the time within each increment window (TBURST − tINT), the AD5930
outputs a DC value of midscale. In external increment mode, it is defined by the pulse widths on the CTRL pin.
D6
INT/EXT
BURST
This bit is active when D7 = 0 and is also used in conjunction with D5. When the user is incrementing the frequency
externally (D5 = 1), D6 dictates whether the user is controlling the burst internally or externally.
When INT/EXT BURST = 1, the output burst is controlled externally through the CTRL pin. This is useful if the user is
using an external source to both trigger the frequency increments and determine the burst interval.
When INT/EXT BURST = 0, the output burst is controlled internally. The burst is pre-programmed by the user into
the TBURST register (the burst interval can either be clock-based or for a specified number of output cycles).
When D5 = 0, this bit is ignored.
D5
D4
INT/EXT
INCR
When INT/EXT INCR = 1, the frequency increments are triggered externally through the CTRL pin.
When INT/EXT INCR = 0, the frequency increments are triggered automatically.
The function of this bit is to control what type of frequency sweep is carried out.
When MODE = 1, the frequency profile is a saw sweep.
MODE
When MODE = 0, the frequency profile is a triangular (up-down) sweep.
D3
SYNCSEL
This bit is active when D2 = 1. It is user-selectable to pulse at the end of sweep (EOS) or at each frequency
increment.
When SYNCSEL = 1, the SYNCOP pin outputs a high level at the end of the sweep and returns to zero at the start of
the subsequent sweep.
When SYNCSEL= 0, the SYNCOP outputs a pulse of 4 × TCLOCK only at each frequency increment.
D2
SYNCOUTEN When SYNCOUTEN= 1, the SYNC output is available at the SYNCOP pin.
When SYNCOUTEN= 0, the SYNCOP pin is disabled (tri-state).
D1
D0
Reserved
Reserved
This bit must always be set to 1.
This bit must always be set to 1.
Rev. 0 | Page 18 of 28
AD5930
Number of Increments (NINCR
)
SETTING UP THE FREQUENCY SWEEP
An end frequency, or a maximum/minimum frequency before
the sweep changes direction is not required on the AD5930.
Instead, this end frequency is calculated by multiplying the
frequency increment value (Δf) by the number of frequency
steps (NINCR), and adding it to/subtracting it from the start
frequency (FSTART), that is, FSTART + NINCR × Δ f. The NINCR register
is a 12-bit register, with the address shown in Table 10.
As stated previously in The Frequency Profile section, the
AD5930 requires certain registers to be programmed to enable a
frequency sweep. The following sections discuss these registers
in more detail.
Start Frequency (FSTART
)
To start a frequency sweep, the user needs to tell the AD5930
what frequency to start sweeping from. This frequency is stored
in a 24-bit register called FSTART. If the user wishes to alter the
entire contents of the FSTART register, two consecutive writes
must be preformed, one to the LSBs and the other to the MSBs.
Note that for an entire write to this register, the Control Bit B24
(D11) should be set to 1 with the LSBs programmed first.
Table 10. NINCR Register Bits
D15
D14
D13
D12
D11 to D0
0
0
0
1
12 bits of NINCR <11…0>
The number of increments is programmed in binary fashion,
with 000000000010 representing the minimum number of
frequency increments (2 increments), and 111111111111
representing the maximum number of increments (4095).
In some applications, the user does not need to alter all 24 bits
of the FSTART register. By setting the Control Bit B24 (D11) to 0,
the 24-bit register operates as two 12-bit registers, one
containing the 12 MSBs and the other containing the 12 LSBs.
This means that the 12 MSBs of the FSTART word can be altered
independently of the 12 LSBs, and vice versa. The addresses of
both the LSBs and the MSBs of this register is given in Table 8.
Table 11. NINCR Data Bits
D11
D0
Number of Increments
0000 0000 0010 2 frequency increments. This is the
minimum number of frequency
increments.
0000 0000 0011 3 frequency increments.
0000 0000 0100 4 frequency increments.
Table 8. FSTART Register Bits
…
…
…
…
D15
D14
D13
D12
D11 to D0
1111 1111 1110 4094 frequency increments.
1111 1111 1111 4095 frequency increments.
1
1
1
1
0
0
0
1
12 LSBs of FSTART <11…0>
12 MSBs of FSTART <23…12>
Increment Interval (tINT)
Frequency Increments (∆f)
The increment interval dictates the duration of the DAC output
signal for each individual frequency of the frequency sweep.
The AD5930 offers the user two choices:
The value in the Δf register sets the increment frequency for the
sweep and is added incrementally to the current output frequency.
Note that the increment frequency can be positive or negative,
thereby giving an increasing or decreasing frequency sweep.
•
•
The duration is a multiple of cycles of the output frequency.
The duration is a multiple of MCLK periods.
At the start of a sweep, the frequency contained in the FSTART
register is output. Next, the frequency (FSTART + Δf ) is output.
This is followed by (FSTART + Δf + Δf) and so on. Multiplying the
Δf value by the number of increments (NINCR), and adding it to
the start frequency (FSTART), gives the final frequency in the
sweep. Mathematically this final frequency/stop frequency is
represented by
This is selected by Bit D13 in the tINT register as shown in Table 12.
Table 12. tINT Register Bits
D15 D14 D13 D12 D11 D10 to D0
0
1
0
x
x
11 bits <10…0>
Fixed number of output
waveform cycles.
FSTART + (NINCR × Δf).
0
1
1
x
x
11 bits <10…0>
Fixed number of clock
periods.
The Δf register is a 23-bit register, and requires two 16-bit
writes to be programmed. Table 9 gives the addresses associated
with both the MSB and LSB registers of the Δf word.
Programming of this register is in binary form with the
minimum number being decimal 2. Note in Table 12 that 11
bits, Bit D10 to Bit D0, of the register are available to program
the time interval. As an example, if MCLK = 50 MHz, then each
clock period/base interval is (1/50 MHz) = 20 ns. If each
frequency needs to be output for 100 ns, then <00000000101>
or decimal 5 needs to be programmed to this register. Note that
the AD5930 can output each frequency for a maximum
duration of 211 −1 (or 2047) times the increment interval.
Table 9. ∆f Register Bits
Sweep
Direction
D15 D14 D13 D12 D11 D10 to D0
0
0
0
0
0
0
1
1
1
0
1
1
N/A
12 LSBs of ∆f
<11…0>
0
11 MSBs of
Positive Δf
(FSTART + Δf)
Δf <22…12>
1
11 MSBs of
Negative ∆f
(FSTART − Δf)
Δf <22…12>
Rev. 0 | Page 19 of 28
AD5930
Therefore, in this example, a time interval of 20 ns × 2047 = 40 µs
is the maximum, with the minimum being 40 ns. For some
applications, this maximum time of 40 µs may be insufficient.
Therefore, to cater for sweeps that need a longer increment
interval, time-base multipliers are provided. Bit D12 and Bit D11
are dedicated to the time-base multipliers (see Table 12). A more
detailed table of the multiplier options is given in Table 13.
Table 14. TBURST Register Bits
D15 D14 D13 D12 D11 D10 to D0
1
0
0
x
x
11 bits of <0…10>
Fixed number of output
waveform cycles.
11 bits of <0…10>
Fixed number of clock
periods.
1
0
1
x
x
Table 13. Time-Base Multiplier Values
However, note that when using both the increment interval
(tINT) and burst time register (TBURST), the settings for Bit D13
should be the same. In instances where they differ, the AD5930
defaults to the value programmed into the tINT register.
Similarly, Bit 12 and Bit 11, the time-base multiplier bits, always
default to the value programmed into the tINT register.
D12
D11
Multiplier Value
0
0
1
1
0
1
0
1
Multiply (1/MCLK) by 1
Multiply (1/MCLK) by 5
Multiply (1/MCLK) by 100
Multiply (1/MCLK) by 500
If MCLK is 50 MHz and a multiplier of 500 is used, then the
base interval (TBASE) is now (1/(50 MHz) x 500)) = 10 µs. Using
a multiplier of 500, the maximum increment interval is 10 µs ×
211 − 1 = 20.5 ms. Therefore, the option of time-base multipliers
gives the user enhanced flexibility when programming the
length of the frequency window, because any frequency can be
output for a minimum of 40 ns up to a maximum of 20.5 ms.
ACTIVATING AND CONTROLLING THE SWEEP
After the registers have been programmed, a 0 ≥ 1 transition on
the CTRL pin starts the sweep. The sweep always starts from
the frequency programmed into the FSTART register. It changes by
the value in the ∆F register and increases by the number of
steps in the NINCR register. However, both the time interval and
burst duration of each frequency can be internally controlled
using the tINT and TBURST registers, or externally using the CTRL
pin. The options available are:
Length of Sweep Time
The length of time to complete a user-programmed frequency
sweep is given by the following equation:
1. auto-increment, auto-burst control
2. external increment, auto-burst control
3. external increment, external burst control
1. Auto-Increment, Auto-Burst Control
TSWEEP = (1 + NINCR) × TBASE
Burst Time Resister (TBURST
)
As previously described in the Burst Output Mode section, the
AD5930 offers the user the ability to output each frequency in
the sweep for a length of time within the increment interval
(tINT), and then return to midscale for the remainder of the time
(tINT – TBURST) before stepping to the next frequency. The burst
option must be enabled. This is done by setting Bit D7 in the
control register to 0.
The values in the tINT and TBURST registers are used to control the
sweep. The AD5930 bursts each frequency for the length of
time programmed in the TBURST register, and outputs midscale
for the remainder of the interval time (tINT – TBURST).
To set up the AD5930 to this mode, CW/BURST (Bit D7) in the
control register must be set to 0, INT/EXT BURST (Bit D6)
must be set to 0, and INT/EXT INCR (Bit D5) must be set to 0.
Note that if the part is only operating in continuous mode, then
(Bit D7) in the control register should be set to 1.
Similar to the time interval register, the burst register can have
its duration as:
•
•
A multiple of cycles of the output frequency
A multiple of MCLK periods
2. External Increment, Auto-Burst Control
The address for this register is given in Table 14.
The time interval, tINT, is set by the pulse rate on the CTRL pin.
The first 0 ≥1 transition on the pin starts the sweep. Each
subsequent 0 ≥1 transition on the CTRL pin increments the
output frequency by the value programmed into the ∆F register.
For each increment interval, the AD5930 outputs each
frequency for the length of time programmed into the TBURST
register, and outputs midscale until the CTRL pin is pulsed
again. Note that for this mode, the values programmed into Bit
D13, Bit D12, and bit D11 of the TBURST register are used.
Rev. 0 | Page 20 of 28
AD5930
To setup the AD5930 to this mode, CW/BURST (Bit D7) in the
control register must be set to 0, INT/EXT BURST (Bit D6)
must be set to 0, and INT/EXT INCR (Bit D5) must be set to 1.
Note that if the part is only operating in continuous mode, then
Bit D7 in the control register should be set to 1.
OUTPUTS FROM THE AD5930
The AD5930 offers a variety of outputs from the chip. The analog
outputs are available from the IOUT/IOUTB pins, and include a
sine wave and a triangle output. The digital outputs are available
from the MSBOUT pin and the SYNCOUT pin.
3. External Increment, External Burst Control:
Analog Outputs
Both the increment interval (tINT) and the burst interval (TBURST
)
Sinusoidal Output
are controlled by the CTRL pin. A 0 ≥ 1 transition on the CTRL
pin starts the sweep. The duration of CTRL high then dictates
the length of time the AD5930 bursts that frequency. The low
time of CTRL is the “listen” time, that is, how long the part
remains at midscale. Bringing the CTRL pin high again initiates a
frequency increment, and the pattern continues. For this mode,
the settings for Bit D13, Bit D12, and Bit D11 are ignored.
The SIN ROM is used to convert the phase information from
the frequency register into amplitude information, which results
in a sinusoidal signal at the output. To have a sinusoidal output
from the IOUT/IOUTB pins, set Bit SINE/TRI (Bit D9) to 1.
Triangle Output
The SIN ROM can be bypassed so that the truncated digital
output from the NCO is sent to the DAC. In this case, the
output is no longer sinusoidal. The DAC produces a 10-bit
linear triangular function. To have a triangle output from the
IOUT/IOUTB pins, set Bit SINE/TRI (D9) to 0. Note that the
DAC ENABLE bit (D10) must be 1 (that is, the DAC is enabled)
when using these pins.
To setup the AD5930 to this mode, CW/BURST (Bit D7) in the
control register must be set to 0, INT/EXT BURST (Bit D6)
must be set to 1, and INT/EXT INCR (Bit D5) must be set to 1.
Note that if the part is only operating in continuous mode, then
Bit D7 in the control register should be set to 1.
Interrupt Pin
p/2
5p/2
9p/2
V
OUT MAX
This function is used as an interrupt during a frequency sweep.
A low-to-high transition on this pin is sampled by the internal
MCLK, thereby resetting internal state machines, which results
in the output going to midscale.
V
OUT MIN
3p/2
7p/2
11p/2
Figure 34. Triangle Output
Standby Pin
Digital Outputs
Square Wave Output from MSBOUT
Sections of the AD5930 that are not in use can be powered
down to minimize power consumption. This is done by using
the STANDBY pin. For the optimum power savings, it is
recommended to reset the AD5930 before entering standby,
because doing so reduces the power-down current to 20 µA.
The inverse of the MSB from the NCO can be output from the
AD5930. By setting the MSBOUTEN (D8) control bit to 1, the
inverted MSB of the DAC data is available at the MSBOUT pin.
This is useful as a digital clock source.
When this pin is high, the internal MCLK is disabled, and the
reference, DAC, and regulator are powered down. When in this
state, the DAC output of the AD5930 remains at its present
value as the NCO is no longer accumulating. When the device
is taken back out of standby mode, the MCLK is re-activated
and the sweep continues. To ensure correct operation for new
data, it is recommended that the device be internally reset using
a control register write or using the INTERRUPT pin, and then
restarted.
DVDD
DGND
Figure 35. MSB Output
SYNCOUT Pin
The SYNCOUT pin can be used to give the status of the sweep.
It is user selectable for the end of the sweep, or to output a 4 ×
TCLOCK pulse at frequency increments. The timing information
for both of these modes is shown in Figure 6 and Figure 7.
The SYNCOUT pin must be enabled before use. This is done
using Bit D2 in the control register. The output available from
this pin is then controlled by Bit D3 in the control register. See
Table 5 for more information.
Rev. 0 | Page 21 of 28
AD5930
APPLICATIONS
Proper operation of the comparator requires good layout
strategy. The strategy must minimize the parasitic capacitance
between VIN and the SIGN BIT OUT pin by adding isolation
using a ground plane. For example, in a multilayered board, the
VIN signal could be connected to the top layer and the SIGN
BIT OUT connected to the bottom layer, so that isolation is
provided between the power and ground planes.
GROUNDING AND LAYOUT
The printed circuit board that houses the AD5930 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes because it
gives the best shielding. Digital and analog ground planes
should only be joined in one place. If the AD5930 is the only
device requiring an AGND to DGND connection, then the
ground planes should be connected at the AGND and DGND
pins of the AD5930. If the AD5930 is in a system where
multiple devices require AGND to DGND connections, the
connection should be made at one point only, a star ground
point that should be established as close as possible to the
AD5930.
Interfacing to Microprocessors
The AD5930 has a standard serial interface that allows the part
to interface directly with several microprocessors. The device
uses an external serial clock to write the data/control
information into the device. The serial clock can have a
frequency of 40 MHz maximum. The serial clock can be
continuous, or it can idle high or low between write operations.
When data/control information is being written to the AD5930,
FSYNC is taken low and is held low while the 16 bits of data are
being written into the AD5930. The FSYNC signal frames the
16 bits of information being loaded into the AD5930.
Avoid running digital lines under the device as these couple
noise onto the die. The analog ground plane should be allowed
to run under the AD5930 to avoid noise coupling. The power
supply lines to the AD5930 should use as large a track as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals, such
as clocks, should be shielded with digital ground to avoid
radiating noise to other sections of the board. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces the
effects of feedthrough through the board. A microstrip
technique is by far the best, but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes, while signals are placed
on the other side.
AD5930 TO ADSP-21xx INTERFACE
Figure 36 shows the serial interface between the AD5930 and
the ADSP-21xx. The ADSP-21xx should be set up to operate in
the SPORT transmit alternate framing mode (TFSW = 1). The
ADSP-21xx are programmed through the SPORT control
register and should be configured as follows:
1. Internal clock operation (ISCLK = 1)
2. Active low framing (INVTFS = 1)
3. 16-bit word length (SLEN = 15)
4. Internal frame sync signal (ITFS = 1)
5. Generate a frame sync for each write (TFSR = 1)
Good decoupling is important. The analog and digital supplies
to the AD5930 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to
AGND and DGND, respectively, with 0.1 µF ceramic capacitors
in parallel with 10 µF tantalum capacitors. To achieve the best
from the decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the
AVDD and DVDD of the AD5930, it is recommended that the
system’s AVDD supply be used. This supply should have the
recommended analog supply decoupling between the AVDD
pins of the AD5930 and AGND, and the recommended digital
supply decoupling capacitors between the DVDD pins and
DGND.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. The data is clocked out on
each rising edge of the serial clock and clocked into the AD5930
on the SCLK falling edge.
ADSP-2101/
ADSP-21031
AD59301
TFS
FSYNC
DT
SDATA
SCLK
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 36. ADSP-2101/ADSP-2103 to AD5930 Interface
Rev. 0 | Page 22 of 28
AD5930
a second write operation is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of the
second write operation. SCLK should idle high between the two
write operations. The 80C51/80L51 outputs the serial data in an
LSB first format. The AD5930 accepts the MSB first (the 4
MSBs being the control information, the next 4 bits being the
address while the 8 LSBs contain the data when writing to a
destination register). Therefore, the transmit routine of the
80C51/80L51 must take this into account and rearrange the bits
so that the MSB is output first.
AD5930 TO 68HC11/68L11 INTERFACE
Figure 37 shows the serial interface between the AD5930 and
the 68HC11/68L11 µcontroller. The µcontroller is configured as
the master by setting bit MSTR in the SPCR to 1, which
provides a serial clock on SCK while the MOSI output drives
the serial data line SDATA. Since the µcontroller does not have
a dedicated frame sync pin, the FSYNC signal is derived from a
port line (PC7). The setup conditions for correct operation of
the interface are as follows:
1. SCK idles high between write operations (CPOL = 0)
2. Data is valid on the SCK falling edge (CPHA = 1)
80C51/80L511
AD59301
P3.3
FSYNC
When data is being transmitted to the AD5930, the FSYNC line
is taken low (PC7). Serial data from the 68HC11/68L11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
In order to load data into the AD5930, PC7 is held low after the
first 8 bits are transferred and a second serial write operation is
performed to the AD5930. Only after the second 8 bits have
been transferred should FSYNC be taken high again.
RXD
TXD
SDATA
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 38. 80C51/80L51 to AD5930 Interface
AD5930 TO DSP56002 INTERFACE
Figure 39 shows the interface between the AD5930 and the
DSP56002. The DSP56002 is configured for normal mode,
asynchronous operation with a gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated internally
(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and
the frame sync signal frames the 16 bits (FSL = 0). The frame
sync signal is available on Pin SC2, but needs to be inverted
before being applied to the AD5930. The interface to the
DSP56000/DSP56001 is similar to that of the DSP56002.
68HC11/68L111
AD59301
PC7
FSYNC
MOSI
SDATA
SCLK
SCK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 37. 68HC11/68L11 to AD5930 Interface
AD5930 TO 80C51/80L51 INTERFACE
DSP560021
AD59301
Figure 38 shows the serial interface between the AD5930 and
the 80C51/80L51 µcontroller. The µcontroller is operated in
mode 0 so that TXD of the 80C51/80L51 drives SCLK of the
AD5930, while RXD drives the serial data line SDATA. The
FSYNC signal is again derived from a bit programmable pin on
the port (P3.3 being used in the diagram). When data is to be
transmitted to the AD5930, P3.3 is taken low. The 80C51/80L51
transmits data in 8-bit bytes, thus, only eight falling SCLK edges
occur in each cycle. To load the remaining 8 bits to the AD5930,
P3.3 is held low after the first 8 bits have been transmitted, and
SC2
FSYNC
STD
SCK
SDATA
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. DSP56002 to AD5930 Interface
Rev. 0 | Page 23 of 28
AD5930
Using the AD5930 Evaluation Board
EVALUATION BOARD
The AD5930 evaluation kit is a test system designed to simplify
the evaluation of the AD5930. An application note is also
available with the evaluation board and gives full information
on operating the evaluation board.
The AD5930 evaluation board allows designers to evaluate the high
performance AD5930 DDS modulator with minimum effort.
The evaluation board interfaces to the USB port of a PC. It is
possible to power the entire board off the USB port. All that is
needed to complete the evaluation of the chip is either a
spectrum analyzer or a scope.
Prototyping Area
An area is available on the evaluation board for the user to add
additional circuits to the evaluation test set. Users may want to
build custom analog filters for the output or add buffers and
operational amplifiers to be used in the final application.
The DDS evaluation kit includes a populated and tested
AD5930 printed circuit board. The EVAL-AD5930EB kit is
shipped with a CD-ROM that includes self-installing software.
The PC is connected to the evaluation board using the supplied
cable. The software is compatible with Microsoft® Windows®
2000 and Windows XP.
XO vs. External Clock
The AD5930 can operate with master clocks up to 50 MHz. A
50 MHz oscillator is included on the evaluation board.
However, this oscillator can be removed and, if required, an
external CMOS clock can be connected to the part.
A schematic of the evaluation board is shown in Figure 40 and
Figure 41.
Rev. 0 | Page 24 of 28
AD5930
SCHEMATIC
D
D
D
D
D
D
D
G N
G N
G N
G N
G N
G N
G N
5 6
5 3
4 1
2 8
2 6
1 2
1 0
V C C
V C C
V C C
V C C
V C C
V C C
V C C
5 5
4 3
3 2
2 7
1 7
1 1
7
N D A G
6
C C A V
3
Figure 40. Page 1 of EVAL-AD5930EB Schematic
Rev. 0 | Page 25 of 28
AD5930
4
5
1 8
7
6
1 1
B S 4
B S 3
B S 2
B S 1
8
1
1 3
1 0
6
1 5
3
Figure 41. Page 2 of EVAL-AD5930EB Schematic
Rev. 0 | Page 26 of 28
AD5930
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 42. 20-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD5930YRUZ1
AD5930YRUZ-REEL71
EVAL-AD5930EB
−40°C to +105°C
−40°C to +105°C
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
RU-20
RU-20
1 Z = Pb-free part.
Rev. 0 | Page 27 of 28
AD5930
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05333-0-11/05(0)
Rev. 0 | Page 28 of 28
相关型号：
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IC SPECIALTY ANALOG CIRCUIT, PDSO16, LEAD FREE, MO-150AC, SSOP-16, Analog IC:Other
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IC SPECIALTY ANALOG CIRCUIT, PDSO16, LEAD FREE, MO-150AC, SSOP-16, Analog IC:Other
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