AD600ARZ [ADI]
Dual, Low Noise, Wideband Variable Gain Amplifier, 0 dB To +40 dB Gain;
| 型号： | AD600ARZ |
| 厂家： | 
ADI |
| 描述： | Dual, Low Noise, Wideband Variable Gain Amplifier, 0 dB To +40 dB Gain 光电二极管 |
| 文件： | 总24页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, Low Noise, Wideband
Variable Gain Amplifiers
a
AD600/AD602*
FUNCTIONAL BLOCK DIAGRAM
FEATURES
2 Channels with Independent Gain Control
"Linear in dB" Gain Response
2 Gain Ranges:
GAT1
PRECISION PASSIVE
INPUT ATTENUATOR
SCALING
REFERENCE
GATING
INTERFACE
AD600: 0 dB to 40 dB
AD602: –10 dB to +30 dB
C1HI
V
A1OP
A1CM
G
Accurate Absolute Gain: ꢀ0.3 dB
Low Input Noise: 1.4 nV/√Hz
Low Distortion: –60 dBc THD at ꢀ1 V Output
High Bandwidth: DC to 35 MHz (–3 dB)
Stable Group Delay: ꢀ2 ns
Low Power: 125 mW (Max) per Amplifier
Signal Gating Function for Each Amplifier
Drives High Speed A/D Converters
MIL-STD-883-Compliant and DESC Versions Available
C1LO
GAIN CONTROL
INTERFACE
RF2
2.24kꢁ(AD600)
694ꢁ(AD602)
0dB
–12.04dB
–18.06dB
–22.08dB
–36.12dB
–42.14dB
–6.02dB
–30.1dB
RF1
20ꢁ
A1HI
FIXED-GAIN
AMPLIFIER
41.07dB(AD600)
31.07(AD602)
A1LO
500ꢁ
62.5ꢁ
R-2R LADDER NETWORK
APPLICATIONS
The gain-control interfaces are fully differential, providing an
input resistance of ~15 MΩ and a scale factor of 32 dB/V (that
is, 31.25 mV/dB) defined by an internal voltage reference. The
response time of this interface is less than 1 µs. Each channel
also has an independent gating facility that optionally blocks
signal transmission and sets the dc output level to within a few
millivolts of the output ground. The gating control input is TTL
and CMOS compatible.
Ultrasound and Sonar Time-Gain Control
High Performance Audio and RF AGC Systems
Signal Measurement
GENERAL DESCRIPTION
The AD600 and AD602 dual channel, low noise, variable gain
amplifiers are optimized for use in ultrasound imaging systems,
but are applicable to any application requiring very precise gain,
low noise and distortion, and wide bandwidth. Each indepen-
dent channel provides a gain of 0 dB to +40 dB in the AD600
and –10 dB to +30 dB in the AD602. The lower gain of the
AD602 results in an improved signal-to-noise ratio at the out-
put. However, both products have the same 1.4 nV/√Hz input
noise spectral density. The decibel gain is directly proportional
to the control voltage, is accurately calibrated, and is supply-
and temperature-stable.
The maximum gain of the AD600 is 41.07 dB, and that of the
AD602 is 31.07 dB; the –3 dB bandwidth of both models is
nominally 35 MHz, essentially independent of the gain. The
signal-to-noise ratio (SNR) for a 1 V rms output and a 1 MHz
noise bandwidth is typically 76 dB for the AD600 and 86 dB for
the AD602. The amplitude response is flat within 0.5 dB from
100 kHz to 10 MHz; over this frequency range the group delay
varies by less than 2 ns at all gain settings.
Each amplifier channel can drive 100 Ω load impedances with
low distortion. For example, the peak specified output is 2.5 V
minimum into a 500 Ω load, or 1 V into a 100 Ω load. For a
200 Ω load in shunt with 5 pF, the total harmonic distortion for
To achieve the difficult performance objectives, a proprietary
circuit form—the X-AMP®—has been developed. Each chan-
nel of the X-AMP comprises a variable attenuator of 0 dB to
–42.14 dB followed by a high speed fixed gain amplifier. In this
way, the amplifier never has to cope with large inputs, and can
benefit from the use of negative feedback to precisely define the
gain and dynamics. The attenuator is realized as a seven-stage
R-2R ladder network having an input resistance of 100 Ω, laser-
trimmed to 2%. The attenuation between tap points is 6.02 dB;
the gain-control circuit provides continuous interpolation between
these taps. The resulting control function is linear in dB.
a
1 V sinusoidal output at 10 MHz is typically –60 dBc.
The AD600J and AD602J are specified for operation from 0°C
to 70°C, and are available in both 16-lead plastic DIP (N) and
16-lead SOIC (R) packages. The AD600A and AD602A are
specified for operation from –40°C to +85°C and are available in
both 16-lead Cerdip (Q) and 16-lead SOIC (R) packages.
The AD600S and AD602S are specified for operation from
–55°C to +125°C, are available in a 16-lead Cerdip (Q) package,
and are MIL-STD-883 compliant. The AD600S and AD602S
are also available under DESC SMD 5962-94572.
*Patented.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD600/AD602–SPECIFICATIONS (Each amplifier section, at T = 25ꢂC, V = ꢀ5 V, –625 mV ≤ V ≤
A
S
G
+625 mV, RL = 500 ꢁ, and CL = 5 pF, unless otherwise noted. Specifications for the AD600 and AD602 are identical unless otherwise noted.)
AD600J/AD602J
AD600A/AD602A
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Resistance
Pins 2 to 3; Pins 6 to 7
98
100
2
1.4
5.3
2
102
95
100
2
1.4
5.3
2
105
Ω
pF
nV/√Hz
dB
dB
Input Capacitance
Input Noise Spectral Density1
Noise Figure
RS = 50 Ω, Maximum Gain
RS = 200 Ω, Maximum Gain
f = 100 kHz
Common-Mode Rejection Ratio
30
30
dB
OUTPUT CHARACTERISTICS
–3 dB Bandwidth
V
OUT = 100 mV rms
35
275
3
35
275
3
MHz
V/µs
V
Slew Rate
Peak Output2
RL ≥ 500 Ω
f ≤ 10 MHz
2.5
2.5
Output Impedance
2
2
Ω
Output Short-Circuit Current
Group Delay Change vs. Gain
Group Delay Change vs. Frequency
Total Harmonic Distortion
50
2
2
50
2
2
mA
ns
ns
f = 3 MHz; Full Gain Range
VG = 0 V, f = 1 MHz to 10 MHz
RL= 200 Ω, VOUT
=
1 V Peak, Rpd = 1 kΩ
–60
–60
dBc
ACCURACY
AD600
Gain Error
0 dB to 3 dB Gain
3 dB to 37 dB Gain
37 dB to 40 dB Gain
VG = –625 mV to +625 mV
VG = –625 mV to +625 mV
0
–0.5
–1
+0.5
0.2
–0.5
10
+1
+0.5
0
50
50
–0.5
–1.0
–1.5
+0.5
0.2
–0.5
10
+1.5
+1.0
+0.5
65
dB
dB
dB
mV
mV
Maximum Output Offset Voltage3
Output Offset Variation
AD602
10
10
65
Gain Error
–10 dB to –7 dB Gain
–7 dB to +27 dB Gain
27 dB to 30 dB Gain
VG = –625 mV to +625 mV
VG = –625 mV to +625 mV
0
–0.5
–1
+0.5
0.2
–0.5
5
+1
+0.5
0
30
30
–0.5
–1.0
–1.5
+0.5
0.2
–0.5
10
+1.5
+1.0
+0.5
45
dB
dB
dB
mV
mV
Maximum Output Offset Voltage3
Output Offset Variation
5
10
45
GAIN CONTROL INTERFACE
Gain Scaling Factor
Common-Mode Range
Input Bias Current
Input Offset Current
Differential Input Resistance
Response Rate
3 dB to 37 dB (AD600); –7 dB to +27 dB (AD602) 31.7
32
32.3
+2.5
1
30.5
–0.75
32
33.5
+2.5
1
dB/V
V
µA
nA
MΩ
dB/µs
–0.75
0.35
10
15
0.35
10
15
50
50
Pins 1 to 16; Pins 8 to 9
Full 40 dB Gain Change
40
40
SIGNAL GATING INTERFACE
Logic Input “LO” (Output ON)
Logic Input “HI” (Output OFF)
Response Time
0.8
0.8
V
V
µs
kΩ
2.4
ON to OFF, OFF to ON
Pins 4 to 3; Pins 5 to 6
2.4
0.3
30
0.3
30
Input Resistance
Output Gated OFF
Output Offset Voltage
Output Noise Spectral Density
Signal Feedthrough @ 1 MHz
AD600
10
65
ꢀ100
10
65
ꢀ400
mV
nV/√Hz
–80
–70
–80
–70
dB
dB
AD602
POWER SUPPLY
Specified Operating Range
Quiescent Current
4.75
5.25
12.5
4.75
5.25
14
V
mA
11
11
NOTES
1Typical open or short-circuited input; noise is lower when the system is set to maximum gain and the input is short-circuited. This figure includes the effects of both
voltage and current noise sources.
2Using resistive loads of 500 Ω or greater, or with the addition of a 1 kΩ pull-down resistor when driving lower loads.
3The dc gain of the main amplifier in the AD600 is ϫ113; thus an input offset of only 100 µV becomes an 11.3 mV output offset. In the AD602, the amplifier’s gain is
ϫ35.7; thus, an input offset of 100 µV becomes a 3.57 mV output offset.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
–2–
REV. D
AD600/AD602
PIN FUNCTION DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltages
7.5 V
Pin Mnemonic Description
Pins 1, 8, 9, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Pins 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . . 2 V Continuous
. . . . . . . . . . . . . . . . . . . . . . . . . VS for 10 ms
Pins 4, 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW
Operating Temperature Range (J) . . . . . . . . . . . . 0°C to 70°C
Operating Temperature Range (A) . . . . . . . . –40°C to +85°C
Operating Temperature Range (S) . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
1
C1LO
A1HI
CH1 Gain-Control Input “LO” (Positive
Voltage Reduces CH1 Gain)
CH1 Signal Input “HI” (Positive Voltage
Increases CH1 Output)
CH1 Signal Input “LO” (Usually Taken to
CH1 Input Ground)
CH1 Gating Input (A Logic “HI” Shuts Off
CH1 Signal Path)
CH2 Gating Input (A Logic “HI” Shuts Off
CH2 Signal Path)
CH2 Signal Input “LO” (Usually Taken to
CH2 Input Ground)
CH2 Signal Input “HI” (Positive Voltage
Increases CH2 Output)
CH2 Gain-Control Input “LO” (Positive
Voltage Reduces CH2 Gain)
2
3
A1LO
GAT1
GAT2
A2LO
A2HI
4
5
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Thermal characteristics:
6
7
8
C2LO
C2HI
A2CM
16-lead plastic package: θJA = 85°C/W
16-lead SOIC package: θJA = 100°C/W
9
CH2 Gain-Control Input “HI” (Positive
Voltage Increases CH2 Gain)
CH2 Common (Usually Taken to CH2
Output Ground)
16-lead Cerdip package: θJA = 120°C/W
ORDERING GUIDE
10
Temperature
Range
Package
Option1
11
12
13
14
15
A2OP
VNEG
VPOS
A1OP
A1CM
CH2 Output
Model
Gain Range
Negative Supply for Both Amplifiers
Positive Supply for Both Amplifiers
CH1 Output
CH1 Common (Usually Taken to CH1
Output Ground)
AD600AQ
AD600AR
0 dB to 40 dB
0 dB to 40 dB
–40°C to +85°C Q-16
–40°C to +85°C R-16
–40°C to +85°C R-16
–40°C to +85°C R-16
–40°C to +85°C R-16
–40°C to +85°C R-16
–40°C to +85°C R-16
DIE
AD600AR-REEL 0 dB to 40 dB
AD600AR-REEL7 0 dB to 40 dB
AD600ARZ2
AD600ARZ-R72
AD600ARZ-RL2
AD600JCHIPS
AD600JN
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
16
C1HI
CH1 Gain-Control Input “HI” (Positive
Voltage Increases CH1 Gain)
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
N-16
R-16
R-16
R-16
R-16
R-16
R-16
AD600JR
AD600JR-REEL
CONNECTION DIAGRAM
16-Lead Plastic DIP (N) Package
16-Lead Plastic SOIC (R) Package
16-Lead Cerdip (Q) Package
AD600JR-REEL7 0 dB to 40 dB
AD600JRZ2
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
–10 dB to +30 dB –40°C to +85°C Q-16
–10 dB to +30 dB –40°C to +85°C R-16
AD600JRZ-R72
AD600JRZ-RL2
AD600SQ/883B3
AD602AQ
–55°C to +125°C Q-16
C1HI
1
2
3
4
5
6
7
8
C1LO
A1HI
16
15
14
AD602AR
A1CM
A1OP
+
–
A1
AD602AR-REEL –10 dB to +30 dB –40°C to +85°C R-16
AD602AR-REEL7 –10 dB to +30 dB –40°C to +85°C R-16
AD602JCHIPS
AD602JN
AD602JR
A1LO
GAT1
GAT2
A2LO
A2HI
DIE
13 VPOS
12 VNEG
11 A2OP
REF
–10 dB to +30 dB 0°C to 70°C
–10 dB to +30 dB 0°C to 70°C
–10 dB to +30 dB 0°C to 70°C
N-16
R-16
R-16
R-16
–
+
AD602JR-REEL
A2
AD602JR-REEL7 –10 dB to +30 dB 0°C to 70°C
10
9
A2CM
C2HI
AD602SQ/883B4
NOTES
–10 dB to +30 dB –55°C to +150°C Q-16
C2LO
AD600/AD602
1N = plastic DIP; Q = Cerdip; R = small outline IC (SOIC).
2Z = Pb-free part.
3Refer to AD600/AD602 Military data sheet. Also available as 5962-9457201MEA.
4Refer to AD600/AD602 Military data sheet. Also available as 5962-9457202MEA.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD600/AD602 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
AD600/AD602–Typical Performance Characteristics
0.45
0.35
20dB
17dB
10dB
7dB
0.25
0.15
0.05
0ꢂ
0ꢂ
–45ꢂ
–90ꢂ
–0.05
–45ꢂ
–0.15
–90ꢂ
–0.25
–0.35
–0.45
100k
1M
10M
100M
100k
1M
10M
100M
–0.7 –0.5 –0.3 –0.1 0.1
0.3
0.5
0.7
FREQUENCY – Hz
FREQUENCY – Hz
GAIN CONTROL VOLTAGE – V
TPC 2. AD600 Frequency and Phase
Response vs. Gain
TPC 3. AD602 Frequency and Phase
Response vs. Gain
TPC 1. Gain Error vs. Gain Control
Voltage
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–2.2
–2.4
–2.6
–2.8
–3.0
–3.2
–3.4
10.0
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
V
= 0V
G
10dB/DIV
CENTER
FREQ 1MHz
10kHz/DIV
0
50
100 200 500 1000 2000
–0.7 –0.5 –0.3 –0.1 0.1
0.3
0.5
0.7
LOAD RESISTANCE – ꢁ
GAIN CONTROL VOLTAGE – V
TPC 5. Third Order Intermodula-
tion Distortion, VOUT = 2 V p-p,
RL = 500 Ω
TPC 6. Typical Output Voltage vs.
Load Resistance (Negative Output
Swing Limits First)
TPC 4. AD600 and AD602 Typical
Group Delay vs. VC
6
5
102
GAIN = 40dB
1µs
1V VOUT
101
4
3
AD600
100
90
100
99
GAIN = 20dB
2
98
AD602
1
97
96
95
94
GAIN = 0dB
0
10
–1
–2
0%
1V VC
–3
–4
93
92
–0.7 –0.5 –0.3 –0.1 0.1
0.3
0.5
0.7
100k
1M
10M
100M
GAIN CONTROL VOLTAGE – V
FREQUENCY – Hz
TPC 8. Output Offset vs. Gain
Control Voltage (Control Channel
Feedthrough)
TPC 9. Gain Control Channel
Response Time. Top: Output Volt-
age, 2 V max, Bottom: Gain Con-
trol Voltage VC = 625 mV
TPC 7. Input Impedance vs.
Frequency
–4–
REV. D
AD600/AD602
50mV
50mV
1V
100
90
100
90
100
90
10
10
10
0%
0%
0%
5V
100ns
5V
100ns
100mV
500ns
TPC 10. Gating Feedthrough to
Output, Gating Off to On
TPC 11. Gating Feedthrough to
Output, Gating On to Off
TPC 12. Transient Response,
Medium and High Gain
500mV
1V
500mV
100
90
100
90
100
90
10
10
10
0%
0%
0%
1V
200ns
200mV
500ns
1V
500ns
TPC 13. Input Stage Overload
Recovery Time
TPC 14. Output Stage Overload
Recovery Time
TPC 15. Transient Response
Minimum Gain
20
10
0
10
10
AD600: CH1 G = 40dB, V = 0
AD600: G = 20dB
IN
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
5
CH2 G = 20dB, V = 100mV
IN
AD602: G = 10dB
AD602: CH1 G = 30dB, V = 0
IN
BOTH:
V
V
= 100mV RMS
5V
CM
0
–5
CH2 G = 0dB, V = 316mV
IN
=
S
AD600
–10
BOTH:
V
= 1V RMS1, R = 50ꢁ,
OUT S
L
R
T
= 500ꢁ
= 25ꢂC
L
R
= 500ꢁ
CH1 V
A
OUT
–20
–30
CROSSTALK = 20log
–10
–15
–20
–25
–30
{
}
CH2 V
IN
AD602
AD600
–40
AD600
AD600: G = 40dB
–50
AD602: G = 30dB
BOTH:
R
V
R
= 500ꢁ
= 0V
= 50ꢁ
–60
L
AD602
AD602
IN
–70
–80
–35
–40
S
100k
1M
10M
100M
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 17. PSRR vs. Frequency
TPC 18. Crosstalk between A1
and A2 vs. Frequency
TPC 16. CMRR vs. Frequency
REV. D
–5–
AD600/AD602
THEORY OF OPERATION
To understand the AD600, it helps to think in terms of a
mechanical means for moving this slider from left to right; in
fact, it is voltage controlled. The details of the control interface
are discussed later. Note that the gain is exactly determined
at all times, and a linear decibel relationship is automatically
guaranteed between the gain and the control parameter that
determines the position of the slider. In practice, the gain
deviates from the ideal law by about 0.2 dB peak (see Figure 6).
The AD600 and AD602 have the same general design and
features. They comprise two fixed gain amplifiers, each pre-
ceded by a voltage-controlled attenuator of 0 dB to 42.14 dB
with independent control interfaces, each having a scaling factor
of 32 dB per volt. The gain of each amplifier in the AD600 is
laser trimmed to 41.07 dB (ϫ113), providing a control range
of –1.07 dB to +41.07 dB (0 dB to +40 dB with overlap). The
AD602 amplifiers have a gain of 31.07 dB (ϫ35.8) and pro-
vide an overall gain of –11.07 dB to +31.07 dB (–10 dB to
+30 dB with overlap).
Note that the signal inputs are not fully differential. A1LO,
A1CM (for CH1), A2LO, and A2CM (for CH2) provide
separate access to the input and output grounds. This recog-
nizes that even when using a ground plane, small differences
arise in the voltages at these nodes. It is important that A1LO
and A2LO be connected directly to the input ground(s).
Significant impedance in these connections reduces the gain
accuracy. A1CM and A2CM should be connected to the load
ground(s).
The advantage of this topology is that the amplifier can use
negative feedback to increase the accuracy of its gain. Also, since
the amplifier never has to handle large signals at its input, the
distortion can be very low. Another feature of this approach is
that the small-signal gain and phase response, and thus the
pulse response, are essentially independent of gain.
The following describes the AD600. Figure 1 is a simplified
schematic of one channel. The input attenuator is a seven-section
R-2R ladder network, using untrimmed resistors of nominally
R = 62.5 Ω, which results in a characteristic resistance of
125 Ω 20%. A shunt resistor is included at the input and laser
trimmed to establish a more exact input resistance of 100 Ω 2%,
which ensures accurate operation (gain and HP corner frequency)
when used in conjunction with external resistors or capacitors.
Noise Performance
An important reason for using this approach is the superior
noise performance that can be achieved. The nominal resistance
seen at the inner tap points of the attenuator is 41.7 Ω (one third
of 125 Ω), which, at 27°C, exhibits a Johnson noise spectral den-
sity (NSD) of 0.84 nV/√Hz (that is, √4kTR), a large fraction of
the total input noise. The first stage of the amplifier contributes
another 1.12 nV/√Hz, for a total input noise of 1.4 nV/√Hz.
The noise at the 0 dB tap depends on whether the input is
short-circuited or open-circuited. When shorted, the minimum
NSD of 1.12 nV/√Hz is achieved. When open, the resistance
of 100 Ω at the first tap generates 1.29 nV/√Hz, so the noise
increases to a total of 1.71 nV/√Hz. This last calculation would
be important if the AD600 were preceded, for example, by a
900 Ω resistor to allow operation from inputs up to 10 V rms.
However, in most cases the low impedance of the source
limits the maximum noise resistance.
GAT1
PRECISION PASSIVE
SCALING
GATING
INTERFACE
INPUT ATTENUATOR
REFERENCE
C1HI
V
A1OP
A1CM
G
C1LO
GAIN CONTROL
INTERFACE
RF2
2.24kꢁ(AD600)
694ꢁ(AD602)
0dB
–12.04dB
–18.06dB
–22.08dB
–36.12dB
–42.14dB
–6.02dB
–30.1dB
It is apparent from the foregoing that it is essential to use a low
resistance in the design of the ladder network to achieve low
noise. In some applications this may be inconvenient, requiring
the use of an external buffer or preamplifier. However, very few
amplifiers combine the needed low noise with low distortion at
maximum input levels, and the power consumption required to
achieve this performance is quite high (due to the need to maintain
very low resistance values while also coping with large inputs).
On the other hand, there is little value in providing a buffer
with high input impedance since the usual reason for this—
the minimization of loading of a high resistance source—is not
compatible with low noise.
RF1
20ꢁ
A1HI
FIXED-GAIN
AMPLIFIER
41.07dB(AD600)
31.07(AD602)
A1LO
500ꢁ
62.5ꢁ
R-2R LADDER NETWORK
Figure 1. Simplified Block Diagram of Single Channel of
the AD600 and AD602
The nominal maximum signal at input A1HI is 1 V rms ( 1.4 V
peak) when using the recommended 5 V supplies, although
operation to 2 V peak is permissible with some increase in HF
distortion and feedthrough. Each attenuator is provided with a
separate signal “LO” connection for use in rejecting common
mode, the voltage between input and output grounds. Circuitry
is included to provide rejection of up to 100 mV.
Apart from the small variations just mentioned, the signal-to-
noise (S/N) ratio at the output is essentially independent of the
attenuator setting, since the maximum undistorted output is
1 V rms and the NSD at the output of the AD600 is fixed at
113 ϫ 1.4 nV/√Hz, or 158 nV/√Hz. Thus, in a 1 MHz band-
width, the output S/N ratio would be 76 dB. The input NSD
of the AD600 and AD602 are the same, but because of the
10 dB lower gain in the AD602’s fixed amplifier, its output S/N
ratio is 10 dB better, or 86 dB in a 1 MHz bandwidth.
The signal applied at the input of the ladder network is attenu-
ated by 6.02 dB by each section; thus, the attenuation to each of
the taps is progressively 0, 6.02, 12.04, 18.06, 24.08, 30.1, 36.12,
and 42.14 dB. A unique circuit technique is employed to interpo-
late between these tap points, indicated by the “slider” in
Figure 1, providing continuous attenuation from 0 dB to 42.14 dB.
–6–
REV. D
AD600/AD602
The Gain-Control Interface
Common-Mode Rejection
The attenuation is controlled through a differential, high imped-
ance (15 MΩ) input, with a scaling factor that is laser trimmed to
32 dB per volt, that is, 31.25 mV/dB. Each of the two amplifiers
has its own control interface. An internal band gap reference
ensures stability of the scaling with respect to supply and tempera-
ture variations, and is the only circuitry common to both channels.
A special circuit technique provides rejection of voltages appear-
ing between input grounds (A1LO and A2LO) and output
grounds (A1CM and A2CM). This is necessary because of the
op amp form of the amplifier, as shown in Figure 1. The
feedback voltage is developed across the resistor RF1 (which, to
achieve low noise, has a value of only 20 Ω). The voltage
developed across this resistor is referenced to the input common,
so the output voltage is also referred to that node.
When the differential input voltage VG = 0 V, the attenuator
slider is centered, providing an attenuation of 21.07 dB,
resulting in an overall gain of 20 dB (= –21.07 dB + 41.07 dB).
When the control input is –625 mV, the gain is lowered by
20 dB (= 0.625 × 32) to 0 dB; when set to 625 mV, the gain is
increased by 20 dB to 40 dB. When this interface is over-
driven in either direction, the gain approaches either –1.07 dB
(= –42.14 dB + 41.07 dB) or 41.07 dB (= 0 + 41.07 dB),
respectively.
For zero differential signal input between A1HI and A1LO,
the output A1OP simply follows the voltage at A1CM. Note that
the range of voltage differences that can exist between A1LO
and A1CM (or A2LO and A2CM) is limited to about 100 mV.
TPC 16 shows typical common-mode rejection ratio versus
frequency.
ACHIEVING 80 dB GAIN RANGE
The gain of the AD600 can be calculated using the following
simple expression:
The two amplifier sections of the X-AMP can be connected
in series to achieve higher gain. In this mode, the output of
A1 (A1OP and A1CM) drives the input of A2 via a high-pass
network (usually just a capacitor) that rejects the dc offset. The
nominal gain range is now –2 dB to +82 dB for the AD600 or
–22 dB to +62 dB for the AD602.
Gain (dB) = 32 VG + 20
(1)
(2)
where VG is in volts. For the AD602, the expression is:
Gain (dB) = 32 VG + 10
Operation is specified for VG in the range from –625 mV dc
to +625 mV dc. The high impedance gain-control input ensures
minimal loading when driving many amplifiers in multiple-channel
applications. The differential input configuration provides flexibil-
ity in choosing the appropriate signal levels and polarities for
various control schemes.
There are several options in connecting the gain-control inputs.
The choice depends on the desired signal-to-noise ratio (SNR)
and gain error (output ripple). The following examples feature
the AD600; the arguments generally apply to the AD602, with
appropriate changes to the gain values.
Sequential Mode (Maximum S/N Ratio)
For example, the gain-control input can be fed differentially to
the inputs, or single-ended by simply grounding the unused
input. In another example, if the gain is to be controlled by
a DAC providing a positive only ground referenced output,
the Gain Control LO pin (either C1LO or C2LO) should be
biased to a fixed offset of 625 mV to set the gain to 0 dB when
Gain Control HI (C1HI or C2HI) is at zero, and to set the
gain to 40 dB when at 1.25 V.
In the sequential mode of operation, the SNR is maintained at
its highest level for as much of the gain control range possible,
as shown in Figure 2. Note here that the gain range is 0 dB to
80 dB. Figure 3 shows the general connections to accomplish
this. Both gain-control inputs, C1HI and C2HI, are driven in
parallel by a positive only, ground referenced source with a
range of 0 V to 2.5 V.
85
80
75
It is a simple matter to include a voltage divider to achieve other
scaling factors. When using an 8-bit DAC with an FS output of
2.55 V (10 mV/bit), a 1.6 divider ratio (generating 6.25 mV/bit)
results in a gain setting resolution of 0.2 dB/bit. Later in this data
sheet, cascading the two sections of an AD600 or AD602
when various options exist for gain control is explained.
70
65
60
55
50
45
40
Signal-Gating Inputs
Each amplifier section of the AD600 and AD602 is equipped
with a signal gating function, controlled by a TTL or CMOS
logic input (GAT1 or GAT2). The ground references for these
inputs are the signal input grounds A1LO and A2LO, respec-
tively. Operation of the channel is unaffected when this input is
LO or left open-circuited. Signal transmission is blocked when
this input is HI. The dc output level of the channel is set to
within a few millivolts of the output ground (A1CM or A2CM),
and simultaneously the noise level drops significantly. The
reduction in noise and spurious signal feedthrough is useful
in ultrasound beam-forming applications, where many amplifier
outputs are summed.
35
30
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
G
Figure 2. S/N Ratio vs. Control Voltage Sequential Control
(1 MHz Bandwidth)
An auxiliary amplifier that senses the voltage difference
between input and output commons is provided to reject
this common voltage.
REV. D
–7–
AD600/AD602
A2
A1
–40.00dB
–41.07dB
OUTPUT
0dB
–40.00dB
C1HI C1LO
–42.14dB
C2HI C2LO
INPUT
0dB
1.07dB
41.07dB
41.07dB
41.07dB
41.07dB
41.07dB
41.07dB
V
V
G2
G1
V
= 0.592V
V
= 1.908V
O1
O2
V
= 0V
C
(a)
–0.51dB
–1.07dB
–0.51dB
C1HI C1LO
–41.63dB
C2HI C2LO
OUTPUT
40dB
INPUT
0dB
40.56dB
V
V
G2
G1
V
= 0.592V
0dB
V
= 1.908V
O1
O2
V
= 1.25V
C
(b)
38.93dB
0dB
C1LO
–2.14dB
C2HI C2LO
OUTPUT
80dB
INPUT
0dB
41.07dB
C1HI
V
V
G2
G1
V
= 0.592V
V
= 1.908V
O1
O2
V
= 2.5V
C
(c)
Figure 3. AD600 Gain Control Input Calculations for Sequential Control Operation
The gains are offset (Figure 4) such that A2’s gain is increased
only after A1’s gain has reached its maximum value. Note that
for a differential input of –700 mV or less, the gain of a single
amplifier (A1 or A2) is at its minimum value of –1.07 dB; for a
differential input of +700 mV or more, the gain is at its maxi-
mum value of 41.07 dB. Control inputs beyond these limits do
not affect the gain and can be tolerated without damage or
foldover in the response. See the Specifications section of this
data sheet for more details on the allowable voltage range. The
gain is now
When VC is set to zero, VG1 = –0.592 V and the gain of A1 is
1.07 dB (recall that the gain of each amplifier section is 0 dB for
VG = 625 mV); meanwhile, VG2 = –1.908 V, so the gain of A2
is –1.07 dB. The overall gain is thus 0 dB (see Figure 3a).
When VC = 1.25 V, VG1 = 1.25 V – 0.592 V = 0.658 V, which
sets the gain of A1 to 40.56 dB, while VG2 = 1.25 V – 1.908 V =
–0.658 V, which sets A2’s gain at –0.56 dB. The overall gain is
now 40 dB (see Figure 3b). When VC = 2.5 V, the gain of A1 is
41.07 dB and that of A2 is 38.93 dB, resulting in an overall gain
of 80 dB (see Figure 3c). This mode of operation is further
clarified by Figure 5, which is a plot of the separate gains of A1
and A2 and the overall gain versus the control voltage. Figure 6
is a plot of the gain error of the cascaded amplifiers versus the
control voltage.
Gain (dB) = 32 VC
(3)
where VC is the applied control voltage.
+41.07dB
Parallel Mode (Simplest Gain-Control Interface)
In this mode, the gain-control voltage is applied to both inputs
in parallel—C1HI and C2HI are connected to the control volt-
age, and C1LO and C2LO are optionally connected to an offset
voltage of 0.625 V. The gain scaling is then doubled to 64 dB/V,
requiring only 1.25 V for an 80 dB change of gain. The ampli-
tude of the gain ripple in this case is also doubled, as shown in
Figure 7, and the instantaneous signal-to-noise ratio at the
output of A2 decreases linearly as the gain is increased (Figure 8).
40.56dB
+38.93dB
A1
A2
20dB
*
*
+1.07dB
–0.56dB
–1.07dB
0.592
0.625
20
1.908
0
0
1.25
40
1.875
60
2.5
V (V)
C
80 82.14
GAIN
(dB)
Low Ripple Mode (Minimum Gain Error)
–2.14
As can be seen in Figures 6 and 7, the output ripple is periodic.
By offsetting the gains of A1 and A2 by half the period of the
ripple, or 3 dB, the residual gain errors of the two amplifiers
can be made to cancel. Figure 9 shows the much lower gain
ripple when configured in this manner. Figure 10 plots the
S/N ratio as a function of gain; it is very similar to that in the
Parallel Mode.
*
GAIN OFFSET OF 1.07dB, OR 33.44mV
Figure 4. Explanation of Offset Calibration for
Sequential Control
–8–
REV. D
AD600/AD602
90
80
70
60
50
40
30
20
10
0
75
70
65
60
55
50
45
40
35
30
A1
COMBINED
A2
2.5
–10
–0.5
0.0
0.5
1.0
1.5
2.0
3.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
V
C
C
Figure 5. Plot of Separate and Overall Gains in
Sequential Control
Figure 8. SNR for Cascaded Stages–Parallel
Control
5
4
3
2
1
0
1.2
1.0
0.8
0.6
0.4
0.2
–1
0.0
–2
–3
–4
–5
–6
–7
–8
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
V
C
V
C
Figure 6. Gain Error for Cascaded Stages—
Sequential Control
Figure 9. Gain Error for Cascaded Stages—
Low Ripple Mode
5
4
3
80
75
70
65
60
55
50
45
40
35
2
1
0
–1
–2
–3
–4
–5
–6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–0.1
0
0.2
0.4
0.6
0.8
1.0
1.2
V
C
V
C
Figure 7. Gain Error for Cascaded Stages—
Parallel Control
Figure 10. ISNR vs. Control Voltage—Low
Ripple Mode
REV. D
–9–
AD600/AD602
APPLICATIONS
Increasing Output Drive
The full potential of any high performance amplifier can only be
realized by careful attention to details in its applications. The
following pages describe fully tested circuits in which many such
details have already been considered. However, as is always true
of high accuracy, high speed analog circuits, the schematic is
only part of the story; this is no less true for the AD600 and
AD602. Appropriate choices in the overall board layout and the
type and placement of power supply decoupling components are
very important. As explained previously, the input grounds
A1LO and A2LO must use the shortest possible connections.
The AD600/AD602’s output stage has limited capability for
negative-load driving capability. For driving loads less than
500 Ω, the load drive may be increased by approximately 5 mA
by connecting a 1 kΩ pull-down resistor from the output to the
negative supply (Figure 12).
Driving Capacitive Loads
For driving capacitive loads of greater than 5 pF, insert a 10 Ω
resistor between the output and the load. This lowers the possi-
bility of oscillation.
The following circuits show examples of time-gain control for
ultrasound and sonar, methods for increasing the output
drive, and AGC amplifiers for audio and RF/IF signal process-
ing using both peak and rms detectors. These circuits also
illustrate methods of cascading X-AMPs for either maintaining
the optimal S/N ratio or maximizing the accuracy of the gain-
control voltage for use in signal measurement. These AGC
circuits may be modified for use as voltage-controlled amplifiers
in sonar and ultrasound applications by removing the
detector and substituting a DAC or other voltage source for
supplying the control voltage.
GAIN-CONTROL
VOLTAGE
C1LO
A1HI
C1HI
1
2
3
4
5
6
7
8
16
15
14
13
12
A1CM
A1OP
VPOS
VNEG
V
IN
+
–
A1
A1LO
GAT1
+5V
1k⍀
REF
GAT2
A2LO
A2HI
ADDED
PULL-DOWN
RESISTOR
–5V
–
+
11 A2OP
A2
Time-Gain Control (TGC) and Time-Variable Gain (TVG)
Ultrasound and sonar systems share a similar requirement: both
need to provide an exponential increase in gain in response to a
linear control voltage, that is, a gain control that is linear in
dB. Figure 11 shows the AD600/AD602 configured for a con-
trol voltage ramp starting at –625 mV and ending at +625 mV
for a gain-control range of 40 dB. The polarity of the gain-control
voltage may be reversed and the control voltage inputs C1HI and
C1LO reversed to achieve the same effect. The gain-control
voltage can be supplied by a voltage-output DAC such as the
AD7242, which contains two complete DACs, operates from 5 V
supplies, has an internal reference of +3 V, and provides 3 V of
output swing. As such, it is well suited for use with the AD600/
AD602, needing only a few resistors to scale the output volt-
age of the DACs to the levels needed by the AD600/AD602.
A2CM
C2HI
10
9
C2LO
AD600/
AD602
Figure 12. Adding a 1 kΩ Pull-Down Resistor Increases the
X-AMP’s Output Drive by About 5 mA. Only the A1 connec-
tions are shown for simplicity.
Realizing Other Gain Ranges
Larger gain ranges can be accommodated by cascading amplifi-
ers. Combinations built by cascading two amplifiers include
–20 dB to +60 dB (using one AD602), –10 dB to +70 dB (1/2
of an AD602 followed by 1/2 of an AD600), and 0 dB to 80 dB
(one AD600). In multiple-channel applications, extra protection
against oscillation can be provided by using amplifier sections
from different packages.
CONTROL VOLTAGE,
V
G
An Ultralow Noise VCA
VOLTAGE-OUTPUT
DAC
The two channels of the AD600 or AD602 can operate in
parallel to achieve a 3 dB improvement in noise level, providing
1 nV/√Hz without any loss of gain accuracy or bandwidth.
+625mV
0dB
40dB
V
G
A1
GAIN
C1LO
A1HI
C1HI
–625mV
1
2
3
4
5
6
7
8
16
In the simplest case, as shown in Figure 13, the signal inputs
A1HI and A2HI are tied directly together. The outputs A1OP
and A2OP are summed via R1 and R2 (100 Ω each), and the
control inputs C1HI/C2HI and C1LO/C2LO operate in parallel.
Using these connections, both the input and output resistances
are 50 Ω. Thus, when driven from a 50 Ω source and termi-
nated in a 50 Ω load, the gain is reduced by 12 dB, so the gain
range becomes –12 dB to +28 dB for the AD600 and –22 dB to
+18 dB for the AD602. The peak input capability remains unaf-
fected (1 V rms at the IC pins, or 2 V rms from an unloaded
50 Ω source). The loading on each output, with a 50 Ω load, is
effectively 200 Ω because the load current is shared between
the two channels, so the overall amplifier still meets its specified
maximum output and distortion levels for a 200 Ω load. This ampli-
fier can deliver a maximum sine wave power of 10 dBm to the load.
A1CM
A1OP
VPOS
15
14
13
12
+
–
A1
A1LO
GAT1
+5V
–5V
REF
VNEG
GAT2
A2LO
A2HI
–
+
11 A2OP
A2
A2CM
C2HI
10
9
C2LO
AD600 or AD602
Figure 11. The Simplest Application of the X-AMP Is as a
TGC or TVG Amplifier in Ultrasound or Sonar. Only the A1
connections are shown for simplicity.
–10–
REV. D
AD600/AD602
GAIN-CONTROL
VOLTAGE
An inexpensive circuit using complementary transistor types
chosen for their low rbb is shown in Figure 14. The gain is
determined by the ratio of the net collector load resistance to
the net emitter resistance. It is an open-loop amplifier. The gain
will be ϫ2 (6 dB) only into a 100 Ω load, assumed to be pro-
vided by the input resistance of the X-AMP; R2 and R7 are in
shunt with this load, and their value is important in defining the
gain. For small-signal inputs, both transistors contribute an
equal transconductance that is rendered less sensitive to signal
level by the emitter resistors R4 and R5. They also play a domi-
nant role in setting the gain.
V
G
+
–
C1LO
A1HI
C1HI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1CM
A1OP
+
–
A1
100ꢁ
100ꢁ
A1LO
GAT1
GAT2
A2LO
V
VPOS
VNEG
OUT
+5V
–5V
REF
V
IN
50ꢁ
A2OP
A2CM
–
+
A2
A2HI
This is a Class AB amplifier. As VIN increases in a positive
direction, Q1 conducts more heavily and its re becomes lower
while Q2 increases. Conversely, increasingly negative values
of VIN result in the re of Q2 decreasing, while the re of Q1
increases. The design is chosen such that the net emitter
resistance is essentially independent of the instantaneous value
of VIN, resulting in moderately low distortion. Low values of
resistance and moderately high bias currents are important in
achieving the low noise, wide bandwidth, and low distortion of
this preamplifier. Heavy decoupling prevents noise on the power
supply lines from being conveyed to the input of the X-AMP.
C2LO
C2HI
AD600 or AD602
Figure 13. An Ultralow Noise VCA Using the AD600 or
AD602
A Low Noise, 6 dB Preamplifier
In some ultrasound applications, a high input impedance pre-
amplifier is needed to avoid the signal attenuation that results
from loading the transducer by the 100 Ω input resistance of the
X-AMP. High gain cannot be tolerated because the peak trans-
ducer signal is typically 0.5 V, while the peak input capability
of the AD600 or AD602 is only slightly more than 1 V. A
gain of 2 is a suitable choice. It can be shown that if the
preamplifier’s overall referred-to-input (RTI) noise is to be
the same as that due to the X-AMP alone (1.4 nV/√Hz), the
input noise of nX2 preamplifier must be √(3/4) times as large,
that is, 1.2 nV/√Hz.
Table I. Measured Preamplifier Performance
Measurement
Value
Unit
Gain (f = 30 MHz)
Bandwidth (–3 dB)
Input Signal for
1 dB Compression
Distortion
6
dB
250
MHz
1
V p-p
+5V
VIN = 200 mV p-p
HD2
HD3
HD2
HD3
0.27
0.14
0.44
0.58
1.03
%
%
%
%
R1
1ꢃF
49.9ꢁ
VIN = 500 mV p-p
R2
174ꢁ
System Input Noise
Spectral Density (NSD)
(Preamp plus X-AMP)
Input Resistance
Input Capacitance
Input Bias Current
Power Supply Voltage
Quiescent Current
nV/√Hz
Q1
MRF904
1.4
15
150
5
kΩ
pF
µA
V
R3
562ꢁ
1ꢃF
0.1ꢃF
0.1ꢃF
R4
42.2ꢁ
–5V
V
INPUT
GROUND
IN
100ꢁ
OF X-AMP
+5V
15
mA
R5
42.2ꢁ
R
IN
R6
562ꢁ
1ꢃF
A Low Noise AGC Amplifier with 80 dB Gain Range
OUTPUT
GROUND
Figure 15 provides an example of the ease with which the AD600
can be connected as an AGC amplifier. A1 and A2 are cascaded,
with 6 dB of attenuation introduced by the 100 Ω resistor R1,
while a time constant of 5 ns is formed by C1 and the 50 Ω of
net resistance at the input of A2. This has the dual effect of
(a) lowering the overall gain range from 0 dB–80 dB to 6 dB–74
dB and (b) introducing a single-pole low-pass filter with a –3 dB
frequency of about 32 MHz. This ensures stability at the maxi-
mum gain for a slight reduction in the overall bandwidth. The
capacitor C4 blocks the small dc offset voltage at the output of
A1 (which might otherwise saturate A2 at its maximum gain)
and introduces a high-pass corner at about 8 kHz, useful in
eliminating low frequency noise and spurious signals that may
be present at the input.
Q2
MM4049
R7
174ꢁ
1ꢃF
R8
49.9ꢁ
–5V
Figure 14. A Low Noise Preamplifier for the AD600 and
AD602
REV. D
–11–
AD600/AD602
5V
R3
46.4k⍀
5V
R4
3.74k⍀
V
G
300A
(at 300K)
AD590
+5V
C1LO
C1HI
1
16
15
14
13
12
11
10
9
FB
FB
C2
A1HI
A1LO
GAT1
GAT2
A1CM
A1OP
0.1F
0.1F
RF
INPUT
C4
2
+
1F
R1
0.1F
+5V DEC
–5V DEC
Q1
2N3904
A1
100⍀
3
–
C1
100pF
VPOS
VNEG
4
5
+5V DEC
–5V DEC
+
REF
R2
C3
15pF
806⍀
V
PTAT
1%
–
A2LO
A2HI
A2OP
A2CM
C2HI
RF
OUTPUT
–
+
6
7
8
–5V
A2
POWER SUPPLY
DECOUPLING NETWORK
C2LO
AD600
Figure 15. This Accurate HF AGC Amplifier Uses Just Three Active Components
lesser extent, on the waveform for which the temperature
stability is to be optimized; for the devices shown and sine wave
signals, the recommended value is 806 Ω. This resistor also
serves to lower the peak current in Q1 and the 200 Hz LP
filter it forms with C2 helps to minimize distortion due to ripple
in VG. Note that the output amplitude under sine wave condi-
tions is higher than for a square wave since the average value of
the current for an ideal rectifier would be 0.637 times as large,
causing the output amplitude to be 1.88 (= 1.2/0.637) V, or
1.33 V rms. In practice, the somewhat nonideal rectifier results
in the sine wave output being regulated to about 1.275 V rms.
A simple half-wave detector is used, based on Q1 and R2. The
average current into capacitor C2 is just the difference between
the current provided by the AD590 (300 µA at 300 K, 27°C)
and the collector current of Q1. In turn, the control voltage VG
is the time integral of this error current. When VG (thus the gain)
is stable, the rectified current in Q1 must, on average, exactly
balance the current in the AD590. If the output of A2 is too
small to do this, VG will ramp up, causing the gain to increase,
until Q1 conducts sufficiently. The operation of this control
system will now be described in detail.
First, consider the particular case where R2 is zero and the out-
put voltage VOUT is a square wave at, say, 100 kHz, well above
the corner frequency of the control loop. During the time VOUT
is negative, Q1 conducts. When VOUT is positive, it is cut off.
Since the average collector current is forced to be 300 µA and the
square wave has a 50% duty-cycle, the current when conducting
must be 600 µA. With R2 omitted, the peak value of VOUT
would be just the VBE of Q1 at 600 µA (typically about 700 mV)
or 2 VBE p-p. This voltage, thus the amplitude at which the output
stabilizes, has a strong negative temperature coefficient (TC),
typically –1.7 mV/°C. While this may not be troublesome in
some applications, the correct value of R2 renders the output
stable with temperature.
An offset of 375 mV is applied to the inverting gain-control
inputs C1LO and C2LO. Thus the nominal –625 mV to +625 mV
range for VG is translated upwards (at VG´) to –0.25 V for mini-
mum gain to 1 V for maximum gain. This prevents Q1 from
going into heavy saturation at low gains and leaves sufficient
headroom of 4 V for the AD590 to operate correctly at high
gains when using a 5 V supply.
In fact, the 6 dB interstage attenuator means that the overall
gain of this AGC system actually runs from –6 dB to +74 dB.
Thus, an input of 2 V rms would be required to produce a 1 V
rms output at the minimum gain, which exceeds the 1 V rms
maximum input specification of the AD600. The available gain
range is therefore 0 dB to 74 dB (or, X1 to X5000). Since the
gain scaling is 15.625 mV/dB (because of the cascaded stages)
the minimum value of VG´ is actually increased by 6 × 15.625 mV,
or about 94 mV, to –156 mV, so the risk of saturation in Q1
is reduced.
To understand this, first note that the current in the AD590 is
closely proportional to absolute temperature (PTAT). In fact,
this IC is intended for use as a thermometer. For the moment,
assume that the signal is a square wave. When Q1 is conducting,
VOUT is the sum of VBE. VOUT is also a voltage that is PTAT and
that can be chosen to have a TC equal but opposite to the TC
of the base-to-emitter voltage. This is actually nothing more than
the band gap voltage reference principle in thinly veiled disguise.
When R2 is chosen so that the sum of the voltage across it and
the VBE of Q1 is close to the band gap voltage of about 1.2 V,
VOUT is stable over a wide range of temperatures, provided Q1
and the AD590 share the same thermal environment.
The emitter circuit of Q1 is somewhat inductive (due its finite ft
and base resistance). Consequently, the effective value of R2
increases with frequency. This would result in an increase in
the stabilized output amplitude at high frequencies, but for
the addition of C3, determined experimentally to be 15 pF for the
2N3904 for maximum response flatness. Alternatively, a faster
transistor can be used here to reduce HF peaking. Figure 16 shows
the ac response at the stabilized output level of about 1.3 V rms.
Figure 17 demonstrates the output stabilization for sine wave
inputs of 1 mV to 1 V rms at frequencies of 100 kHz, 1 MHz,
and 10 MHz.
Since the average emitter current is 600 µA during each half-cycle
of the square wave, a resistor of 833 Ω would add a PTAT volt-
age of 500 mV at 300 K, increasing by 1.66 mV/°C. In practice,
the optimum value of R2 depends on the transistor used and, to a
–12–
REV. D
AD600/AD602
A Wide Range, RMS-Linear dB Measurement System
(2 MHz AGC Amplifier with RMS Detector)
Monolithic rms-dc converters provide an inexpensive means to
measure the rms value of a signal of arbitrary waveform; they
also may provide a low accuracy logarithmic (decibel-scaled)
output. However, they have certain shortcomings. The first of
these is their restricted dynamic range, typically only 50 dB.
More troublesome is that the bandwidth is roughly proportional
to the signal level; for example, the AD636 provides a 3 dB
bandwidth of 900 kHz for an input of 100 mV rms, but has
a bandwidth of only 100 kHz for a 10 mV rms input. Its loga-
rithmic output is unbuffered, uncalibrated, and not stable
over temperature. Considerable support circuitry, including at
least two adjustments and a special high TC resistor, is required
to provide a useful output.
3dB
0.1
100
1
10
FREQUENCY – MHz
All of these problems can be eliminated using an AD636 as
the detector element in an AGC loop, in which the difference
between the rms output of the amplifier and a fixed dc refer-
ence are nulled in a loop integrator. The dynamic range and
the accuracy with which the signal can be determined are now
entirely dependent on the amplifier used in the AGC system. Since
the input to the rms-dc converter is forced to a constant ampli-
tude, close to its maximum input capability, the bandwidth is no
longer signal dependent. If the amplifier has an exactly exponen-
tial (linear-dB) gain-control law, its control voltage VG is forced
by the AGC loop to be have the general form:
Figure 16. AC Response at the Stabilized Output Level
of 1.3 V RMS
+0.2
100kHz
0
1MHz
–0.2
10MHz
VIN(RMS)
VREF
–0.4
VOUT = VSCALE log 10
(4)
Figure 19 shows a practical wide dynamic range rms-responding
measurement system using the AD600. Note that the signal
output of this system is available at A2OP, and the circuit can
be used as a wideband AGC amplifier with an rms-responding
detector. This circuit can handle inputs from 100 µV to 1 V rms
with a constant measurement bandwidth of 20 Hz to 2 MHz,
limited primarily by the AD636 rms converter. Its logarithmic
output is a loadable voltage accurately calibrated to 100 mV/dB,
or 2 V per decade, which simplifies the interpretation of the
reading when using a DVM and is arranged to be –4 V for an
input of 100 µV rms input, zero for 10 mV, and +4 V for a
1 V rms input. In terms of Equation 4, VREF is 10 mV and
VSCALE is 2 V.
0.001
0.01
0.1
1
INPUT AMPLITUDE – V RMS
Figure 17. Output Stabilization vs. RMS Input for
Sine Wave Inputs at 100 kHz, 1 MHz, and 10 MHz
While the band gap principle used here sets the output ampli-
tude to 1.2 V (for the square wave case), the stabilization point
can be set to any higher amplitude, up to the maximum output
of (VS – 2) V that the AD600 can support. It is only necessary
to split R2 into two components of appropriate ratio whose
parallel sum remains close to the zero-TC value of 806 Ω. This
is illustrated in Figure 18, which shows how the output can be
raised without altering the temperature stability.
Note that the peak log output of 4 V requires the use of
6 V supplies for the dual op amp U3 (AD712) although lower
supplies would suffice for the AD600 and AD636. If only 5 V
supplies are available, it is necessary to either use a reduced value
for VSCALE (say 1 V, in which case the peak output would be only
2 V) or restrict the dynamic range of the signal to about 60 dB.
5V
300ꢃA
AD590
(at 300K)
TO AD600 PIN 16
As in the previous case, the two amplifiers of the AD600 are
used in cascade. However, the 6 dB attenuator and low-pass
filter found in Figure 1 are replaced by a unity gain buffer
amplifier U3A, whose 4 MHz bandwidth eliminates the risk of
instability at the highest gains. The buffer also allows the use of
a high impedance coupling network (C1/R3) that introduces a
high-pass corner at about 12 Hz. An input attenuator of 10 dB
(X0.316) is now provided by R1 + R2 operating in conjunction
with the AD600’s input resistance of 100 Ω. The adjustment
provides exact calibration of the logarithmic intercept VREF in
critical applications, but R1 and R2 may be replaced by a fixed
resistor of 215 Ω if very close calibration is not needed, since the
C2
1ꢃF
Q1
2N3904
R2B
+
C3
15pF
R2 = R2A R2B ≈ 806ꢁ
V
R2A
PTAT
–
RF
OUTPUT
TO AD600 PIN 11
Figure 18. Modification in Detector to Raise Output to
2 V RMS
REV. D
–13–
AD600/AD602
V
RMS
AF/RF
OUTPUT
C1
0.1F
C4
4.7F
+6V DEC
CAL
0dB
+6V
C1LO
A1HI
C1HI
1
2
VPOS 14
VINP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R1
INPUT
1V RMS
115⍀
A1CM
FB
FB
U2
NC
13
NC
AD636
+
–
MAX
0.1F
R2 200⍀
A1
(SINEWAVE)
A1OP
VPOS
VNEG
A1LO
GAT1
GAT2
A2LO
A2HI
–6V
+6V
12 NC
3
4
VNEG
DEC
DEC
R7
+6V
56.2k⍀
11 NC
0.1F
CAVG
DEC
–6V
DEC
REF
–6V
DEC
C2
2F
10
9
VLOG COMM
NC
NC
5
6
7
R3
133k⍀
R6
3.16k⍀
A2OP
A2CM
BFOP
BFIN
LDLO
–
+
+316.2mV
A2
U1 AD600
R5
V
8
U3A
RMS
–6V
POWER SUPPLY
DECOUPLING
NETWORK
C2HI
C2LO
1/2
AD712
U3B
1/2
AD712
C3
1F
V
OUT
V
G
R4
3.01k⍀
+100mV/dB
0V = 0dB(AT 10mV RMS)
15.625mV/dB
16.2k⍀
NC = NO CONNECT
Figure 19. The Output of This Three-IC Circuit Is Proportional to the Decibel Value of the RMS Input
input resistance of the AD600 (and all other key parameters of it
and the AD636) are already laser trimmed for accurate operation.
This attenuator allows inputs as large as 4 V to be accepted,
that is, signals with an rms value of 1 V combined with a crest
factor of up to 4.
note that unlike most AGC circuits that need strong temperature
compensation for the internal kT/q scaling, these voltages,
and thus the output of this measurement system, are tempera-
ture stable, arising directly from the fundamental and exact
exponential attenuation of the ladder networks in the AD600.
The output of A2 is ac coupled via another 12 Hz high-pass filter
formed by C2 and the 6.7 kΩ input resistance of the AD636.
The averaging time constant for the rms-dc converter is deter-
mined by C4. The unbuffered output of the AD636 (at Pin 8) is
compared with a fixed voltage of 316 mV set by the positive
supply voltage of 6 V and resistors R6 and R7. VREF is propor-
tional to this voltage, and systems requiring greater calibration
accuracy should replace the supply dependent reference with a
more stable source.
Typical results are presented for a sine wave input at 100 kHz.
Figure 20 shows that the output is held very close to the set-
point of 316 mV rms over an input range in excess of 80 dB.
450
425
400
375
350
325
300
275
250
225
200
Any difference in these voltages is integrated by the op amp U3B,
with a time constant of 3 ms formed by the parallel sum of R6/R7
and C3. Now, if the output of the AD600 is too high, V rms will
be greater than the setpoint of 316 mV, causing the output of
U3B—that is, VOUT—to ramp up (note that the integrator is
noninverting). A fraction of VOUT is connected to the inverting
gain-control inputs of the AD600, so causing the gain to be
reduced, as required, until V rms is exactly equal to 316 mV, at
which time the ac voltage at the output of A2 is forced to be
exactly 316 mV rms. This fraction is set by R4 and R5 such
that a 15.625 mV change in the control voltages of A1 and
A2—which would change the gain of the cascaded amplifiers by
1 dB—requires a change of 100 mV at VOUT. Notice here that
since A2 is forced to operate at an output level well below its
capacity, waveforms of high crest factor can be tolerated through-
out the amplifier.
175
150
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
Figure 20. The RMS Output of A2 Is Held Close to the
Setpoint 316 mV for an Input Range of Over 80 dB
This system can, of course, be used as an AGC amplifier in
which the rms value of the input is leveled. Figure 21 shows
the decibel output voltage. More revealing is Figure 22, which
shows that the deviation from the ideal output predicted by
Equation 1 over the input range 80 µV to 500 mV rms is within
0.5 dB, and within 1 dB for the 80 dB range from 80 µV to
800 mV. By suitable choice of the input attenuator R1 + R2,
this could be centered to cover any range from 25 mV – 250 mV
to, say, 1 mV – 10 V, with appropriate correction to the value of
VREF. Note that VSCALE is not affected by the changes in the
range. The gain ripple of 0.2 dB seen in this curve is the result of
To check the operation, assume an input of 10 mV rms is
applied to the input, which results in a voltage of 3.16 mV rms
at the input to A1, due to the 10 dB loss in the attenuator. If
the system operates as claimed, VOUT (and hence VG) should
be zero. This being the case, the gain of both A1 and A2 is
20 dB and the output of the AD600 is therefore 100 times
(40 dB) greater than its input, which evaluates to 316 mV rms,
the input required at the AD636 to balance the loop. Finally,
–14–
REV. D
AD600/AD602
the finite interpolation error of the X-AMP. Note that it occurs
with a periodicity of 12 dB—twice the separation between the
tap points (because of the two cascaded stages).
C1HI
16
15
14
13
12
11
10
9
VINP
1
2
3
4
5
6
7
A1CM
NC
A1OP
VPOS
–6V DEC
VNEG
CAVG
5
4
U2
AD636
+6V DEC
–6V DEC
U1
AD600
VNEG
A2OP
A2CM
C2HI
C2
2F
NC
NC
VLOG
BFOP
BFIN
3
2
1
0
–46.875mV
+46.875mV
–6V
DEC
+6V
DEC
–1
10k⍀
78.7⍀ 78.7⍀
10k⍀
3dB OFFSET
MODIFICATION
NC = NO CONNECT
–2
–3
Figure 23. Reducing the Gain Error Ripple
–4
–5
The error curve shown in Figure 24 demonstrates that over the
central portion of the range the output voltage can be maintained
very close to the ideal value. The penalty for this modification is
the higher errors at the extremities of the range. The next two
applications show how three amplifier sections can be cascaded
to extend the nominal conversion range to 120 dB, with the
inclusion of simple LP filters of the type shown in Figure 15.
Very low errors can then be maintained over a 100 dB range.
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
Figure 21. The dB Output of Figure 19’s Circuit Is Linear
over an 80 dB Range
2.5
2.0
1.5
2.5
2.0
1.5
1.0
0.5
1.0
0.5
0
–0.5
–1.0
–1.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
–2.0
–2.5
Figure 22. Data from Figure 20 Presented as the Deviation
from the Ideal Output Given in Equation 4
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
This ripple can be canceled whenever the X-AMP stages are
cascaded by introducing a 3 dB offset between the two pairs
of control voltages. A simple means to achieve this is shown
in Figure 23: the voltages at C1HI and C2HI are split by
46.875 mV, or 1.5 dB. Alternatively, either one of these pins
can be individually offset by 3 dB and a 1.5 dB gain adjustment
made at the input attenuator (R1 + R2).
Figure 24. Using the 3 dB Offset Network, the Ripple
Is Reduced
100 dB to 120 dB RMS Responding Constant Bandwidth AGC
Systems with High Accuracy dB Outputs
The next two applications double as both AGC amplifiers and
measurement systems. In both, precise gain offsets are used to
achieve either (1) a very high gain linearity of 0.1 dB over
the full 100 dB range or (2) the optimal signal-to-noise ratio
at any gain.
REV. D
–15–
AD600/AD602
C1LO
C1LO
C1HI
C1HI
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
15
14
13
12
INPUT
1V RMS
A1CM
A1OP
R2
A1CM
A1OP
A1HI
A1LO
GAT1
GAT2
A1HI
A1LO
GAT1
GAT2
C1
C4
2F
487⍀
+
–
+
–
MAX
0.1F
A1
A1
U3A
(SINEWAVE)
V
R3
OUT
1/4
AD713
200⍀
R1
133k⍀
VPOS
VNEG
A2OP
VPOS
VNEG
+5V
+5V
DEC
–5V
DEC
DEC
REF
REF
–5V
DEC
C2
0.1F
R5
1.58k⍀
A2LO
A2HI
A2LO
A2HI
–
+
–
+
11 A2OP
R4
133k⍀
U3B
1/4
AD713
A2
U1 AD600
+5V
C3
220pF
A2
A2CM
10
A2CM
C2HI
C2LO
C2LO
C2HI
9
U2 AD600
–2dB
–62.5mV
+2dB
+62.5mV
0dB
+5V
–5V
FB
R7
127⍀
R8
127⍀
R9
10k⍀
R6
10k⍀
0.1F
0.1F
+5V
DEC
C5
22F
–5V
DEC
+5V DEC
FB
1
2
VPOS 14
VINP
U4
AD636
13 NC
12 NC
11 NC
10
NC
–5V
R11
46.4k⍀
POWER SUPPLY
DECOUPLING
NETWORK
–5V
DEC
3
4
VNEG
+5V DEC
R15
C6
4.7F
CAVG
R10
3.16k⍀
19.6k⍀
VLOG COMM
5
6
7
NC
NC
R16
6.65k⍀
R14
301k⍀
9
BFOP
BFIN
LDLO
U3C
1/4
AD713
V
LOG
V
8
RMS
Q1
R12
11.3k⍀
2N3906
+316.2mV
R13
3.01k⍀
NC = NO CONNECT
Figure 25. RMS Responding AGC Circuit with 100 dB Dynamic Range
5
A 100 dB RMS/AGC System with Minimal Gain Error
(Parallel Gain with Offset)
Figure 25 shows an rms-responding AGC circuit that can be
used equally well as an accurate measurement system. It
accepts inputs of 10 µV to 1 V rms (–100 dBV to 0 dBV) with
4
3
2
generous overrange. Figure 26 shows the logarithmic output, VLOG
which is accurately scaled 1 V per decade, that is 50 mV/dB, with
an intercept (VLOG = 0) at 3.16 mV rms (–50 dBV). Gain offsets
of 2 dB have been introduced between the amplifiers, provided
by the 62.5 mV introduced by R6–R9. These offsets cancel a
small gain ripple that arises in the X-AMP from its finite interpola-
tion error, which has a period of 18 dB in the individual VCA
sections. The gain ripple of all three amplifier sections without
this offset (in which case the gain errors simply add) is shown in
Figure 27; it is still a remarkably low 0.25 dB over the 108 dB
range from 6 µV to 1.5 V rms. However, with the gain offsets
connected, the gain linearity remains under 0.1 dB over the
specified 100 dB range (Figure 28).
,
1
0
–1
–2
–3
–4
–5
1
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
Figure 26. VLOG Plotted vs. VIN for Figure 25‘s Circuit
Showing 120 dB AGC Range
–16–
REV. D
AD600/AD602
2.0
1.5
1.0
0.5
slowly varying V rms is compared with a fixed reference of
316 mV, derived from the positive supply by R10/R11. Any
difference between these two voltages is integrated in C6, in
conjunction with op amp U3C, the output of which is VLOG. A
fraction of this voltage, determined by R12 and R13, is returned
to the gain control inputs of all AD600 sections. An increase in
VLOG lowers the gain because this voltage is connected to the
inverting polarity control inputs.
0.1
0
–0.1
–0.5
–1.0
In this case, the gains of all three VCA sections are being varied
simultaneously, so the scaling is not 32 dB/V but 96 dB/V, or
10.42 mV/dB. The fraction of VLOG required to set its scaling to
50 mV/dB is therefore 10.42/50, or 0.208. The resulting full-
scale range of VLOG is nominally 2.5 V. This scaling allows the
circuit to operate from 5 V supplies. Optionally, the scaling
can be altered to 100 mV/dB, which would be more easily
interpreted when VLOG is displayed on a DVM by increasing
R12 to 25.5 kΩ. The full-scale output of 5 V then requires the
use of supply voltages of at least 7.5 V.
–1.5
–2.0
1
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
Figure 27. Gain Error for Figure 19 without the 2 dB
Offset Modification
A simple attenuator of 16.6 1.25 dB is formed by R2/R3 and
the 100 Ω input resistance of the AD600. This allows the refer-
ence level of the decibel output to be precisely set to zero for an
input of 3.16 mV rms, and thus center the 100 dB range between
10 µV and 1 V. In many applications R2/R3 may be replaced
by a fixed resistor of 590 Ω. For example, in AGC applica-
tions, neither the slope nor the intercept of the logarithmic output
is important.
2.0
1.5
1.0
0.5
0.1
0
–0.1
A few additional components (R14–R16 and Q1) improve the
accuracy of VLOG at the top end of the signal range (that is, for
small gains). The gain starts rolling off when the input to the
first amplifier, U1A, reaches 0 dB. To compensate for this non-
linearity, Q1 turns on at VLOG ~ 1.5 V and increases the feedback
to the control inputs of the AD600s, thereby needing a smaller
voltage at VLOG to maintain the input to the AD636 to the set-
point of 316 mV rms.
–0.5
–1.0
–1.5
–2.0
1
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
Figure 28. Adding the 2 dB Offsets Improves the
Linearization
A 120 dB RMS/AGC System with Optimal S/N Ratio
(Sequential Gain)
The maximum gain of this circuit is 120 dB. If no filtering were
used, the noise spectral density of the AD600 (1.4 nV/√Hz)
would amount to an input noise of 8.28 µV rms in the full band-
width (35 MHz). At a gain of one million, the output noise
would dominate. Consequently, some reduction of bandwidth is
mandatory, and in the circuit of Figure 25 it is due mostly to
a single-pole low-pass filter R5/C3, which provides a –3 dB
frequency of 458 kHz, which reduces the worst-case output noise
(at VAGC) to about 100 mV rms at a gain of 100 dB. Of course,
the bandwidth (and therefore the output noise) could be further
reduced, for example, in audio applications, merely by increas-
ing C3. The value chosen for this application is optimal in
minimizing the error in the VLOG output for small input signals.
In the last case, all gains were adjusted simultaneously, resulting
in an output signal-to-noise ratio (S/N ratio) that is always less
than optimal. The use of sequential gain control results in a
major improvement in S/N ratio, with only a slight penalty in
the accuracy of VLOG, and no penalty in the stabilization accuracy
of VAGC. The idea is to increase the gain of the earlier stages
first (as the signal level decreases) and maintain the highest S/N
ratio throughout the amplifier chain. This can be easily
achieved with the AD600 because its gain is accurate even when
the control input is overdriven. That is, each gain control
window of 1.25 V is used fully before moving to the next
amplifier to the right.
Figure 29 shows the circuit for the sequential control scheme.
R6 to R9 with R16 provide offsets of 42.14 dB between the
individual amplifiers to ensure smooth transitions between the
gain of each successive X-AMP, with the sequence of gain
increase being U1A first, then U1B, and lastly U2A. The adjust-
able attenuator provided by R3 + R17 and the 100 Ω input
resistance of U1A as well as the fixed 6 dB attenuation provided
by R2 and the input resistance of U1B are included both to set
VLOG to read 0 dB when VIN is 3.16 mV rms and to center the
100 dB range between 10 µV rms and 1 V rms input. R5 and
C3 provide a 3 dB noise bandwidth of 30 kHz. R12 to R15
change the scaling from 625 mV/decade at the control inputs to
The AD600 is dc-coupled, but even miniscule offset voltages at
the input would overload the output at high gains; thus high-pass
filtering is also needed. To provide operation at low frequencies,
two simple zeros at about 12 Hz are provided by R1/C1 and
R4/C2; op amp sections U3A and U3B (AD713) are used to
provide impedance buffering, since the input resistance of the
AD600 is only 100 Ω. A further zero at 12 Hz is provided by C4
and the 6.7 kΩ input resistance of the AD636 rms converter.
The rms value of VLOG is generated at Pin 8 of the AD636; the
averaging time for this process is determined by C5, and the
value shown results in less than 1% rms error at 20 Hz. The
REV. D
–17–
AD600/AD602
0dB
ADJUST
C1LO
A1HI
C1LO
C1HI
C1HI
R3
200⍀
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
15
14
13
12
R17
115⍀
INPUT
A1CM
A1OP
R2
A1CM
A1OP
A1HI
A1LO
GAT1
GAT2
C1
C4
2F
100⍀
+
–
+
–
V
OUT
0.1F
A1
A1
U3A
A1LO
GAT1
GAT2
1/4
R1
133k⍀
AD713
VPOS
VNEG
VPOS
VNEG
A2OP
+5V
DEC
–5V
DEC
+6V
DEC
REF
REF
–6V
DEC
C2
0.1F
R5
5.36k⍀
A2LO
A2HI
A2LO
A2HI
–
+
–
+
11 A2OP
U3B
A2
A2
R4
133k⍀
C3
0.001F
A2CM
10
A2CM
C2HI
1/4
AD713
C2LO
C2LO
C2HI
9
U1 AD600
U2 AD600
R6
3.4k⍀
R9
1k⍀
R7
R8
R16
287⍀
1k⍀ 294⍀
+6V
+6V
C5
FB
FB
22F
+6V DEC
0.1F
+6V
DEC
1
2
VPOS 14
VINP
0.1F
–6V
U4
AD636
13 NC
NC
DEC
R11
56.2k⍀
–6V
DEC
12
3
4
VNEG
NC
C6
4.7F
11 NC
CAVG
R10
3.16k⍀
–6V
POWER SUPPLY
DECOUPLING
NETWORK
10
9
VLOG COMM
5
6
7
NC
NC
BFOP
BFIN
LDLO
U3C
1/4
AD713
V
+6V DEC
R15
LOG
V
8
RMS
R13
866⍀
R12
1k⍀
+316.2mV
5.11k⍀
R14
7.32k⍀
NC = NO CONNECT
Figure 29. 120 dB Dynamic Range RMS Responding Circuit Optimized for S/N Ratio
1 V/decade at the output. At the same time, R12 to R15 center the
dynamic range at 60 dB, which occurs if the VG of U1B is equal
to zero. These arrangements ensure that the VLOG still fits within
the 6 V supplies.
Figure 30 shows VLOG to be linear over a full 120 dB range.
Figure 31 shows the error ripple due to the individual gain
functions bounded by 0.2 dB (dotted lines) from 6 µV to 2 V.
The small perturbations at about 200 µV and 20 mV, caused
by the impracticality of matching the gain functions perfectly,
are the only sign that the gains are now sequential. Figure 32 is
a plot of VAGC that remains very close to its set value of 316 mV
rms over the full 120 dB range.
5
4
3
To compare the signal-to-noise ratios in the simultaneous
and sequential modes of operation more directly, all interstage
attenuation was eliminated (R2 and R3 in Figure 25, R2 in
Figure 29), the input of U1A was shorted, R5 was selected to
provide a 20 kHz bandwidth (R5 = 7.87 kΩ), and only the gain
control was varied, using an external source. The rms value of
the noise was then measured at VOUT and expressed as an S/N
ratio relative to 0 dBV, which is almost the maximum output
capability of the AD600. Results for the simultaneous mode can
be seen in Figure 33. The S/ N ratio degrades uniformly as the
gain is increased. Note that since the inverting gain control was
used, the gain in this curve and in Figure 34 decreases for more
positive values of the gain-control voltage.
2
1
0
–1
–2
–3
–4
–5
1
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
Figure 30. VLOG Is Essentially Linear over the Full 120 dB
Range
–18–
REV. D
AD600/AD602
2.0
1.5
1.0
0.5
In contrast, the S/N ratio for the sequential mode is shown in
Figure 34. U1A always acts as a fixed noise source; varying its
gain has no influence on the output noise. This is a feature of
the X-AMP technique. Thus, for the first 40 dB of control
range (actually slightly more, as explained below), when only
this VCA section has its gain varied, the S/N ratio remains con-
stant. During this time, the gains of U1B and U2A are at their
minimum value of –1.07 dB.
0.2
0
–0.2
–0.5
–1.0
90
80
70
60
50
40
30
20
–1.5
–2.0
1
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
Figure 31. Error Ripple Due to the Individual
Gain Functions
400
350
300
250
200
10
0
–1.183 –0.558 0.067 0.692 1.317 1.942 2.567 3.192 3.817
CONTROL VOLTAGE, V (31.25mV/dB) – V
C
Figure 34. S/N Ratio vs. Control Voltage for Sequential
Gain Control (Figure 29)
For the next 40 dB of control range, the gain of U1A remains
fixed at its maximum value of 41.07 dB and only the gain of
U1B is varied, while that of U2A remains at its minimum value
of –1.07 dB. In this interval, the fixed output noise of U1A is
amplified by the increasing gain of U1B and the S/N ratio pro-
gressively decreases.
1
10
100
1m
10m
100m
1
10
INPUT SIGNAL – V RMS
Once U1B reaches its maximum gain of 41.07 dB, its output
also becomes a gain independent noise source; this noise is
presented to U2A. As the control voltage is further increased,
the gains of both U1A and U1B remain fixed at their maximum
value of 41.07 dB, and the S/N ratio continues to decrease.
Figure 34 clearly shows this, because the maximum S/N ratio
of 90 dB is extended for the first 40 dB of input signal before it
starts to roll off.
Figure 32. VAGC Remains Close to Its Setpoint of
316 mV RMS over the Full 120 dB Range
90
80
70
60
50
40
30
20
10
0
This arrangement of staggered gains can be easily implemented
because when the control inputs of the AD600 are overdriven,
the gain limits to its maximum or minimum values without side
effects. This eliminates the need for awkward nonlinear shaping
circuits that have previously been used to break up the gain
range of multistage AGC amplifiers. It is the precise values of the
AD600’s maximum and minimum gain (not 0 dB and 40 dB
but –1.07 dB and +41.07 dB) that explain the rather odd values
of the offset values that are used.
–833.2 –625.0 –416.6 –208.3
0
208.3 416.6 625.0 833.2
The optimization of the output S/N ratio is of obvious value in
AGC systems. However, in applications where these circuits are
considered for their wide range logarithmic measurement capa-
bilities, the inevitable degradation of the S/N ratio at high gains
need not seriously impair their utility. In fact, the bandwidth of
the circuit shown in Figure 25 was specifically chosen to improve
measurement accuracy by altering the shape of the log error curve
(Figure 31) at low signal levels.
CONTROL VOLTAGE, V (10.417mV/dB) – mV
C
Figure 33. S/N Ratio vs. Control Voltage for Parallel Gain
Control (Figure 25)
REV. D
–19–
AD600/AD602
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
Dimensions shown in inches and (mm)
16-Lead Plastic DIP Package
(N-16)
16-Lead Cerdip Package
(Q-16)
0.005
(0.13)
MIN
0.098 (2.49)
0.785 (19.94)
0.765 (19.43)
0.745 (18.92)
0.285 (7.24)
0.310 (7.87)
0.220 (5.59)
MAX
0.295 (7.49)
16
9
8
PIN 1
0.275 (6.99)
1
16
1
9
0.060 (1.52)
0.015 (0.38)
8
0.320 (8.13)
0.290 (7.37)
0.200 (5.08)
MAX
0.840 (21.34) MAX
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.150 (3.81)
MIN
0.015 (0.38)
MIN
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15
0
0.180 (4.57)
MAX
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
0.100
(2.54)
BSC
0.023 (0.58)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Dimensions shown in millimeters and (inches)
16-Lead SOIC Package
(R-16)
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
؋
45؇ 0.30 (0.0118)
0.10 (0.0039)
8؇
0؇
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–20–
REV. D
AD600/AD602
Revision History
Location
Page
3/04—Data Sheet changed from REV. C to REV. D.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Changes to Figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5/02—Data Sheet changed from REV. B to REV. C.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Renumber Tables and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
8/01—Data Sheet changed from REV. A to REV. B.
Changes to Accuracy Section of AD600A/AD602A column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
REV. D
–21–
–22–
–23–
–24–
相关型号：
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