AD603AR-REEL7 [ADI]
Low Noise, 90 MHz Variable-Gain Amplifier; 低噪声， 90 MHz可变增益放大器
| 型号： | AD603AR-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Noise, 90 MHz Variable-Gain Amplifier |
| 文件： | 总14页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, 90 MHz
Variable-Gain Amplifier
a
AD603*
FEATURES
“Linear in dB” Gain Control
Pin Programmable Gain Ranges
1 V to span the central 40 dB of the gain range. An over- and
under-range of 1 dB is provided whatever the selected range. The
gain-control response time is less than 1 µs for a 40 dB change.
–11 dB to +31 dB with 90 MHz Bandwidth
+9 dB to +51 dB with 9 MHz Bandwidth
Any Intermediate Range, e.g., –1 dB to +41 dB with
30 MHz Bandwidth
Bandwidth Independent of Variable Gain
1.3 nV/√Hz Input Noise Spectral Density
؎0.5 dB Typical Gain Accuracy
The differential gain-control interface allows the use of either
differential or single-ended positive or negative control voltages.
Several of these amplifiers may be cascaded and their gain-con-
trol gains offset to optimize the system S/N ratio.
The AD603 can drive a load impedance as low as 100 Ω with
low distortion. For a 500 Ω load in shunt with 5 pF, the total
harmonic distortion for a ±1 V sinusoidal output at 10 MHz is
typically –60 dBc. The peak specified output is ±2.5 V mini-
mum into a 500 Ω load, or ±1 V into a 100 Ω load.
MIL-STD-883 Compliant and DESC Versions Available
APPLICATIONS
RF/IF AGC Amplifier
Video Gain Control
A/D Range Extension
Signal Measurement
The AD603 uses a proprietary circuit topology—the X-AMP™.
The X-AMP comprises a variable attenuator of 0 dB to
–42.14 dB followed by a fixed-gain amplifier. Because of the
attenuator, the amplifier never has to cope with large inputs and
can use negative feedback to define its (fixed) gain and dynamic
performance. The attenuator has an input resistance of 100 Ω,
laser trimmed to ±3%, and comprises a seven-stage R-2R ladder
network, resulting in an attenuation between tap points of
6.021 dB. A proprietary interpolation technique provides a
continuous gain-control function which is linear in dB.
PRODUCT DESCRIPTION
The AD603 is a low noise, voltage-controlled amplifier for use
in RF and IF AGC systems. It provides accurate, pin selectable
gains of –11 dB to +31 dB with a bandwidth of 90 MHz or
+9 dB to +51 dB with a bandwidth of 9 MHz. Any intermediate
gain range may be arranged using one external resistor. The
input referred noise spectral density is only 1.3 nV/√Hz and power
consumption is 125 mW at the recommended ±5 V supplies.
The AD603A is specified for operation from –40°C to +85°C
and is available in both 8-lead SOIC (R) and 8-lead ceramic
DIP (Q). The AD603S is specified for operation from –55°C to
+125°C and is available in an 8-lead ceramic DIP (Q). The
AD603 is also available under DESC SMD 5962-94572.
The decibel gain is “linear in dB,” accurately calibrated, and
stable over temperature and supply. The gain is controlled at a
high impedance (50 MΩ), low bias (200 nA) differential input;
the scaling is 25 mV/dB, requiring a gain-control voltage of only
FUNCTIONAL BLOCK DIAGRAM
VPOS
VNEG
SCALING
REFERENCE
PRECISION PASSIVE
INPUT ATTENUATOR
FIXED GAIN
AMPLIFIER
GPOS
GNEG
V
OUT
V
G
6.44k⍀*
GAIN
CONTROL
INTERFACE
AD603
FDBK
694⍀*
20⍀*
0dB
–6.02dB –12.04dB–18.06dB –24.08dB –30.1dB –36.12dB –42.14dB
VINP
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
R
COMM
R = 2R LADDER NETWORK
*NORMAL VALUES
*Patented.
X-AMP is a trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ TA = +25؇C, VS = ؎5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB Gain
AD603–SPECIFICATIONS Range, RL = 500 ⍀, and CL = 5 pF, unless otherwise noted.)
Model
AD603
Typ
Parameter
Conditions
Min
Max
103
Unit
INPUT CHARACTERISTICS
Input Resistance
Pins 3 to 4
97
100
2
1.3
8.8
–11
±1.4
Ω
pF
nV/√Hz
dB
dBm
V
Input Capacitance
Input Noise Spectral Density1
Noise Figure
Input Short Circuited
f = 10 MHz, Gain = max, RS = 10 Ω
f = 10 MHz, Gain = max, RS = 10 Ω
1 dB Compression Point
Peak Input Voltage
±2
OUTPUT CHARACTERISTICS
–3 dB Bandwidth
VOUT = 100 mV rms
RL ≥ 500 Ω
RL ≥ 500 Ω
90
MHz
V/µs
V
Slew Rate
275
±3.0
2
Peak Output2
±2.5
Output Impedance
f ≤ 10 MHz
Ω
Output Short-Circuit Current
Group Delay Change vs. Gain
Group Delay Change vs. Frequency VG = 0 V; f = 1 MHz to 10 MHz
Differential Gain
Differential Phase
Total Harmonic Distortion
3rd Order Intercept
50
mA
ns
ns
f = 3 MHz; Full Gain Range
±2
±2
0.2
0.2
–60
15
%
Degree
dBc
dBm
f = 10 MHz, VOUT = 1 V rms
f = 40 MHz, Gain = max, RS = 50 Ω
ACCURACY
Gain Accuracy
–500 mV ≤ VG ≤ +500 mV
VG = 0 V
±0.5
؎
±1.5
20
30
20
30
1
dB
dB
mV
mV
mV
mV
T
MIN to TMAX
Output Offset Voltage3
TMIN to TMAX
Output Offset Variation vs. VG
TMIN to TMAX
–500 mV ≤ VG ≤ +500 mV
GAIN CONTROL INTERFACE
Gain Scaling Factor
39.4
38
–1.2
40
40.6
42
+2.0
dB/V
dB/V
V
nA
nA
TMIN to TMAX
GNEG, GPOS Voltage Range4
Input Bias Current
200
10
50
Input Offset Current
Differential Input Resistance
Response Rate
Pins 1 to 2
Full 40 dB Gain Change
MΩ
dB/µs
40
POWER SUPPLY
Specified Operating Range
Quiescent Current
TMIN to TMAX
±4.75
±6.3
17
20
V
mA
mA
12.5
NOTES
1Typical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. This figure includes the effects of both voltage
and current noise sources.
2Using resistive loads of 500 Ω or greater, or with the addition of a 1 kΩ pull-down resistor when driving lower loads.
3The dc gain of the main amplifier in the AD603 is ×35.7; thus, an input offset of 100 µV becomes a 3.57 mV output offset.
4GNEG and GPOS, gain control, voltage range is guaranteed to be within the range of –VS + 4.2 V to +VS – 3.4 V over the full temperature range of –40°C to +85°C.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
–2–
REV. C
AD603
ABSOLUTE MAXIMUM RATINGS1
PIN FUNCTION DESCRIPTIONS
Supply Voltage ±VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7.5 V
Internal Voltage VINP (Pin 3) . . . . . . . . . . . ±2 V Continuous
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS for 10 ms
GPOS, GNEG (Pins 1, 2) . . . . . . . . . . . . . . . . . . . . . . . ±VS
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 400 mW
Operating Temperature Range
AD603A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD603S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Pin
Mnemonic
Description
Pin 1
GPOS
Gain-Control Input “HI”
(Positive Voltage Increases Gain)
Gain-Control Input “LO”
(Negative Voltage Increases Gain)
Amplifier Input
Pin 2
GNEG
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
VINP
COMM
FDBK
VNEG
VOUT
VPOS
Amplifier Ground
Connection to Feedback Network
Negative Supply Input
Amplifier Output
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Thermal Characteristics:
Positive Supply Input
CONNECTION DIAGRAMS
8-Lead Plastic SOIC (R) Package
8-Lead Ceramic DIP (Q) Package
8-Lead SOIC Package: θJA = 155°C/W, θJC = 33°C/W
8-Lead Ceramic Package: θJA = 140°C/W, θJC = 15°C/W
1
2
3
4
8
7
6
5
VPOS
VOUT
VNEG
FDBK
GPOS
GNEG
VINP
AD603
TOP VIEW
(Not to Scale)
COMM
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Part Number
AD603AR
AD603AQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
8-Lead SOIC
8-Lead Ceramic DIP
8-Lead Ceramic DIP
Evaluation Board
Die
SO-8
Q-8
Q-8
AD603SQ/883B*
AD603-EB
AD603ACHIPS
AD603AR-REEL
AD603AR-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
13" Reel
7" Reel
SO-8
SO-8
*Refer to AD603 Military data sheet. Also available as 5962-9457203MPA.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD603 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
AD603
indicated by the “slider” in Figure 1, thus providing continuous
attenuation from 0 dB to 42.14 dB. It will help, in understanding
the AD603, to think in terms of a mechanical means for moving
this slider from left to right; in fact, its “position” is controlled
by the voltage between Pins 1 and 2. The details of the gain-
control interface are discussed later.
THEORY OF OPERATION
The AD603 comprises a fixed-gain amplifier, preceded by a
broadband passive attenuator of 0 dB to 42.14 dB, having a
gain-control scaling factor of 40 dB per volt. The fixed gain is
laser-trimmed in two ranges, to either 31.07 dB (×35.8) or
50 dB (×358), or may be set to any range in between using one
external resistor between Pins 5 and 7. Somewhat higher gain
can be obtained by connecting the resistor from Pin 5 to com-
mon, but the increase in output offset voltage limits the
maximum gain to about 60 dB. For any given range, the band-
width is independent of the voltage-controlled gain. This system
provides an under- and overrange of 1.07 dB in all cases;
for example, the overall gain is –11.07 dB to 31.07 dB in the
maximum-bandwidth mode (Pin 5 and Pin 7 strapped).
The gain is at all times very exactly determined, and a linear-in-
dB relationship is automatically guaranteed by the exponential
nature of the attenuation in the ladder network (the X-AMP
principle). In practice, the gain deviates slightly from the ideal
law, by about ±0.2 dB peak (see, for example, Figure 16).
Noise Performance
An important advantage of the X-AMP is its superior noise per-
formance. The nominal resistance seen at inner tap points is
41.7 Ω (one third of 125 Ω), which exhibits a Johnson noise-
spectral density (NSD) of 0.83 nV/√Hz (that is, √4kTR) at 27°C,
which is a large fraction of the total input noise. The first stage
of the amplifier contributes a further 1 nV/√Hz, for a total input
noise of 1.3 nV/√Hz. It will be apparent that it is essential to use
a low resistance in the ladder network to achieve the very low
specified noise level. The signal’s source impedance forms a
voltage divider with the AD603’s 100 Ω input resistance. In
some applications, the resulting attenuation may be unaccept-
able, requiring the use of an external buffer or preamplifier to
match a high impedance source to the low impedance AD603.
This X-AMP structure has many advantages over former methods
of gain-control based on nonlinear elements. Most importantly,
the fixed-gain amplifier can use negative feedback to increase its
accuracy. Since large inputs are first attenuated, the amplifier
input is always small. For example, to deliver a ±1 V output in
the –1 dB/+41 dB mode (that is, using a fixed amplifier gain of
41.07 dB) its input is only 8.84 mV; thus the distortion can be
very low. Equally important, the small-signal gain and phase
response, and thus the pulse response, are essentially indepen-
dent of gain.
Figure 1 is a simplified schematic. The input attenuator is a
seven-section R-2R ladder network, using untrimmed resistors
of nominally R = 62.5 Ω, which results in a characteristic resis-
tance of 125 Ω ± 20%. A shunt resistor is included at the input
and laser trimmed to establish a more exact input resistance of
100 Ω ± 3%, which ensures accurate operation (gain and HP
corner frequency) when used in conjunction with external resistors
or capacitors.
The noise at maximum gain (that is, at the 0 dB tap) depends
on whether the input is short-circuited or open-circuited: when
shorted, the minimum NSD of slightly over 1 nV/√Hz is achieved;
when open, the resistance of 100 Ω looking into the first tap
generates 1.29 nV/√Hz, so the noise increases to a total of
1.63 nV/√Hz. (This last calculation would be important if the
AD603 were preceded by, for example, a 900 Ω resistor to allow
operation from inputs up to 10 V rms.) As the selected tap
moves away from the input, the dependence of the noise on
source impedance quickly diminishes.
The nominal maximum signal at input VINP is 1 V rms (±1.4 V
peak) when using the recommended ±5 V supplies, although
operation to ±2 V peak is permissible with some increase in HF
distortion and feedthrough. Pin 4 (SIGNAL COMMON) must
be connected directly to the input ground; significant impedance in
this connection will reduce the gain accuracy.
Apart from the small variations just discussed, the signal-to-
noise (S/N) ratio at the output is essentially independent of the
attenuator setting. For example, on the –11 dB/+31 dB range
the fixed gain of ×35.8 raises the output NSD to 46.5 nV/√Hz.
Thus, for the maximum undistorted output of 1 V rms and a
1 MHz bandwidth, the output S/N ratio would be 86.6 dB, that
is, 20 log (1 V/46.5 µV).
The signal applied at the input of the ladder network is attenu-
ated by 6.02 dB by each section; thus, the attenuation to each of
the taps is progressively 0 dB, 6.02 dB, 12.04 dB, 18.06 dB,
24.08 dB, 30.1 dB, 36.12 dB and 42.14 dB. A unique circuit
technique is employed to interpolate between these tap-points,
VPOS
VNEG
SCALING
REFERENCE
PRECISION PASSIVE
INPUT ATTENUATOR
FIXED GAIN
AMPLIFIER
GPOS
GNEG
V
OUT
V
G
6.44k⍀*
GAIN
CONTROL
INTERFACE
AD603
FDBK
694⍀*
20⍀*
0dB
–6.02dB –12.04dB–18.06dB –24.08dB –30.1dB –36.12dB –42.14dB
VINP
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
R
COMM
R = 2R LADDER NETWORK
*NORMAL VALUES
Figure 1. Simplified Block Diagram of the AD603
–4–
REV. C
AD603
The Gain-Control Interface
GPOS
VPOS
VPOS
VNEG
VC1
VC2
The attenuation is controlled through a differential, high-
impedance (50 MΩ) input, with a scaling factor which is
laser-trimmed to 40 dB per volt, that is, 25 mV/dB. An internal
bandgap reference ensures stability of the scaling with respect to
supply and temperature variations.
AD603
GNEG
VINP
V
V
OUT
OUT
VNEG
V
IN
When the differential input voltage VG = 0 V, the attenuator
“slider” is centered, providing an attenuation of 21.07 dB. For
the maximum bandwidth range, this results in an overall gain of
10 dB (= –21.07 dB + 31.07 dB). When the control input is
–500 mV, the gain is lowered by 20 dB (= 0.500 V × 40 dB/V),
to –10 dB; when set to +500 mV, the gain is increased by 20 dB, to
30 dB. When this interface is overdriven in either direction, the
gain approaches either –11.07 dB (= –42.14 dB + 31.07 dB) or
31.07 dB (= 0 + 31.07 dB), respectively. The only constraint on
the gain-control voltage is that it be kept within the common-mode
range (–1.2 V to +2.0 V assuming +5 V supplies) of the gain
control interface.
COMM FDBK
a. –10 dB to +30 dB; 90 MHz Bandwidth
GPOS
VPOS
VPOS
VC1
VC2
AD603
GNEG
V
V
OUT
OUT
VINP
VNEG
V
VNEG
IN
2.15k⍀
COMM FDBK
5.6pF
The basic gain of the AD603 can thus be calculated using the
following simple expression:
b. 0 dB to +40 dB; 30 MHz Bandwidth
Gain (dB) = 40 VG + 10
(1)
where VG is in volts. When Pins 5 and 7 are strapped (see next
section) the gain becomes
GPOS
VPOS
VPOS
VC1
VC2
AD603
GNEG
V
V
OUT
OUT
Gain (dB) = 40 VG + 20 for 0 to +40 dB
and
VINP
VNEG
V
VNEG
18pF
IN
Gain (dB) = 40 VG + 30 for +10 to +50 dB
(2)
COMM FDBK
The high impedance gain-control input ensures minimal loading
when driving many amplifiers in multiple channel or cascaded
applications. The differential capability provides flexibility in
choosing the appropriate signal levels and polarities for various
control schemes.
c. +10 dB to +50 dB; 9 MHz Bandwidth
Figure 2. Pin Strapping to Set Gain
For example, if the gain is to be controlled by a DAC providing
a positive only ground-referenced output, the “Gain Control
LO” (GNEG) pin should be biased to a fixed offset of +500 mV,
to set the gain to –10 dB when “Gain Control HI” (GPOS) is at
zero, and to 30 dB when at +1.00 V.
52
50
48
46
44
42
40
38
36
34
32
30
–1:VdB (OUT)
It is a simple matter to include a voltage divider to achieve other
scaling factors. When using an 8-bit DAC having an FS output
of +2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)
would result in a gain-setting resolution of 0.2 dB/bit. The use
of such offsets is valuable when two AD603s are cascaded, when
various options exist for optimizing the S/N profile, as will be
shown later.
VdB (OUT)
–2:VdB (OUT)
Programming the Fixed-Gain Amplifier Using Pin Strapping
Access to the feedback network is provided at Pin 5 (FDBK).
The user may program the gain of the AD603’s output amplifier
using this pin, as shown in Figure 2. There are three modes: in
the default mode, FDBK is unconnected, providing the range
+9 dB/+51 dB; when VOUT and FDBK are shorted, the gain is
lowered to –11 dB/+31 dB; when an external resistor is placed
between VOUT and FDBK any intermediate gain can be achieved,
for example, –1 dB/+41 dB. Figure 3 shows the nominal maxi-
mum gain versus external resistor for this mode.
10
100
1k
10k
100k
1M
R
EXT
Figure 3. Gain vs. REXT, Showing Worst-Case Limits
Assuming Internal Resistors Have a Maximum Tolerance
of 20%
REV. C
–5–
AD603
Optionally, when a resistor is placed from FDBK to COMM,
higher gains can be achieved. This fourth mode is of limited
value because of the low bandwidth and the elevated output off-
sets; it is thus not included in Figure 2.
There are several ways of connecting the gain-control inputs in
cascaded operation. The choice depends on whether it is impor-
tant to achieve the highest possible Instantaneous Signal-to-Noise
Ratio (ISNR), or, alternatively, to minimize the ripple in the gain
error. The following examples feature the AD603 programmed
for maximum bandwidth; the explanations apply to other gain/
bandwidth combinations with appropriate changes to the arrange-
ments for setting the maximum gain.
The gain of this amplifier in the first two modes is set by the
ratio of on-chip laser-trimmed resistors. While the ratio of these
resistors is very accurate, the absolute value of these resistors
can vary by as much as ±20%. Thus, when an external resistor
is connected in parallel with the nominal 6.44 kΩ ± 20% inter-
nal resistor, the overall gain accuracy is somewhat poorer. The
worst-case error occurs at about 2 kΩ (see Figure 4).
Sequential Mode (Optimal S/N Ratio)
In the sequential mode of operation, the ISNR is maintained at
its highest level for as much of the gain control range possible.
Figure 5 shows the SNR over a gain range of –22 dB to +62 dB,
assuming an output of 1 V rms and a 1 MHz bandwidth; Figure
6 shows the general connections to accomplish this. Here, both
the positive gain-control inputs (GPOS) are driven in parallel by
a positive-only, ground-referenced source with a range of 0 V to
+2 V, while the negative gain-control inputs (GNEG) arc biased
by stable voltages to provide the needed gain-offsets. These volt-
ages may be provided by resistive dividers operating from a
common voltage reference.
1.2
–1:VdB (OUT) – (–1):VdB (O
)
REF
1.0
0.8
0.6
0.4
0.2
0.0
VdB (OUT) – VdB (O
)
REF
–0.2
–0.4
–0.6
–0.8
–1.0
90
85
80
75
70
65
60
55
50
10
100
1k
10k
100k
1M
R
EXT
Figure 4. Worst-Case Gain Error, Assuming Internal Resis-
tors Have a Maximum Tolerance of –20% (Top Curve) or
+20% (Bottom Curve)
While the gain-bandwidth product of the fixed-gain amplifier is
about 4 GHz, the actual bandwidth is not exactly related to the
maximum gain. This is because there is a slight enhancing of the
ac response magnitude on the maximum bandwidth range, due
to higher order poles in the open-loop gain function; this mild
peaking is not present on the higher gain ranges. Figure 2 shows
how optional capacitors may be added to extend the frequency
response in high gain modes.
–0.2
0.2
0.6
1.0
1.4
1.8
2.2
V
C
Figure 5. SNR vs. Control Voltage—Sequential Control
(1 MHz Bandwidth)
The gains are offset (Figure 7) such that A2’s gain is increased
only after A1’s gain has reached its maximum value. Note that
for a differential input of –600 mV or less, the gain of a single
amplifier (A1 or A2) will be at its minimum value of –11.07 dB;
for a differential input of +600 mV or more, the gain will be at
its maximum value of 31.07 dB. Control inputs beyond these
limits will not affect the gain and can be tolerated without dam-
age or foldover in the response. This is an important aspect of
the AD603’s gain-control response. (See the Specifications sec-
tion of this data sheet for more details on the allowable voltage
range) The gain is now
CASCADING TWO AD603S
Two or more AD603s can be connected in series to achieve
higher gain. Invariably, ac coupling must be used to prevent the
dc offset voltage at the output of each amplifier from overload-
ing the following amplifier at maximum gain. The required high
pass coupling network will usually be just a capacitor, chosen to
set the desired corner frequency in conjunction with the well-
defined 100 Ω input resistance of the following amplifier.
For two AD603s, the total gain-control range becomes 84 dB
(two times 42.14 dB); the overall –3 dB bandwidth of cascaded
stages will be somewhat reduced. Depending on the pin-strapping,
the gain and bandwidth for two cascaded amplifiers can range
from –22 dB to +62 dB (with a bandwidth of about 70 MHz) to
+22 dB to +102 dB (with a bandwidth of about 6 MHz).
Gain (dB) = 40 VG + GO
(3)
where VG is the applied control voltage and GO is determined
by the gain range chosen. In the explanatory notes that follow,
we assume the maximum-bandwidth connections are used, for
which GO is –20 dB.
–6–
REV. C
AD603
A1
A2
–40.00dB
–51.07dB
–42.14dB
GPOS GNEG
–42.14dB
GPOS GNEG
–8.93dB
INPUT
0dB
31.07dB
31.07dB
31.07dB
31.07dB
OUTPUT
–20dB
V
V
G2
G1
V
= 0.473V
V
= 1.526V
O1
O2
V
= 0V
C
a.
0dB
–11.07dB
0dB
–42.14dB
GPOS GNEG
31.07dB
INPUT
0dB
31.07dB
OUTPUT
20dB
GPOS
GNEG
V
V
G2
G1
V
= 0.473V
V
= 1.526V
O1
O2
V
= 1.0V
C
b.
0dB
–28.93dB
0dB
–2.14dB
GPOS GNEG
31.07dB
INPUT
0dB
31.07dB
OUTPUT
60dB
GPOS
GNEG
V
V
G2
G1
V
= 0.473V
V
= 1.526V
O1
O2
V
= 2.0V
C
c.
Figure 6. AD603 Gain Control Input Calculations for Sequential Control Operation
When VG = +2.0 V, the gain of A1 is pinned at 31.07 dB and
that of A2 is near its maximum value of 28.93 dB, resulting in
an overall gain of 60 dB (see Figure 6c). This mode of operation
is further clarified by Figure 8, which is a plot of the separate
gains of A1 and A2 and the overall gain versus the control voltage.
Figure 9 is a plot of the gain error of the cascaded amplifiers versus
the control voltage. Figure 10 is a plot of the gain error of the
cascaded stages versus the control voltages.
+31.07dB
+10dB
+31.07dB
+28.96dB
–11.07dB
A1
A2
*
*
–11.07dB
–8.93dB
0.473
1.526
0
0.5
0
1.0
20
1.50
40
2.0
60
V (V)
C
62.14
GAIN
(dB) –22.14 –20
70
60
*GAIN OFFSET OF 1.07dB, OR 26.75mV
Figure 7. Explanation of Offset Calibration for Sequential
Control
COMBINED
50
40
With reference to Figure 6, note that VG1 refers to the differen-
tial gain-control input to A1 and VG2 refers to the differential
gain-control input to A2. When VG is zero, VG1 = –473 mV and
thus the gain of A1 is –8.93 dB (recall that the gain of each indi-
vidual amplifier in the maximum-bandwidth mode is –10 dB
A1
30
20
10
A2
for VG = –500 mV and 10 dB for VG = 0 V); meanwhile, VG2
=
0
–1.908 V so the gain of A2 is “pinned” at –11.07 dB. The over-
all gain is thus –20 dB. This situation is shown in Figure 6a.
–10
–20
–30
When VG = +1.00 V, VG1 = 1.00 V – 0.473 V = +0.526 V,
which sets the gain of A1 to at nearly its maximum value of
31.07 dB, while VG2 = 1.00 V – 1.526 V = 0.526 V, which sets
A2’s gain at nearly its minimum value –11.07 dB. Close analysis
shows that the degree to which neither AD603 is completely
pushed to its maximum or minimum gain exactly cancels in the
overall gain, which is now +20 dB. This is depicted in Figure 6b.
–0.2
0.2
0.6
0.1
1.4
1.8
2.2
V
C
Figure 8. Plot of Separate and Overall Gains in Sequential
Control
REV. C
–7–
AD603
2.0
1.5
90
80
70
60
50
40
30
20
10
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–0.2
0.2
0.6
1.0
1.4
1.8
2.2
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
V
C
V
C
Figure 9. SNR for Cascaded Stages—Sequential Control
Figure 11. Gain Error for Cascaded Stages–Parallel
Control
2.0
1.5
90
85
1.0
80
75
70
65
60
55
50
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
–0.2
0.2
0.4
0.6
0.8
1.0
1.2
–0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
V
V
C
C
Figure 10. Gain Error for Cascaded Stages—Sequential
Control
Figure 12. ISNR for Cascaded Stages–Parallel Control
Parallel Mode (Simplest Gain-Control Interface)
In this mode, the gain-control of voltage is applied to both inputs
in parallel—the GPOS pins of both A1 and A2 are connected to
the control voltage and the GNEW inputs are grounded. The
gain scaling is then doubled to 80 dB/V, requiring only a 1.00 V
change for an 80 dB change of gain:
Low Gain Ripple Mode (Minimum Gain Error)
As can be seen from Figures 9 and 10, the error in the gain is
periodic, that is, it shows a small ripple. (Note that there is also
a variation in the output offset voltage, which is due to the gain
interpolation, but this is not exact in amplitude.) By offsetting
the gains of A1 and A2 by half the period of the ripple, that is,
by 3 dB, the residual gain errors of the two amplifiers can be
made to cancel. Figure 13 shows that much lower gain ripple
when configured in this manner. Figure 14 plots the ISNR as a
function of gain; it is very similar to that in the “Parallel Mode.”
Gain (dB) = 80 VG + GO
(4)
where, as before GO depends on the range selected; for example,
in the maximum-bandwidth mode, GO is +20 dB. Alternatively,
the GNEG pins may be connected to an offset voltage of
+0.500 V, in which case, GO is –20 dB.
The amplitude of the gain ripple in this case is also doubled, as
shown in Figure 11, while the instantaneous signal-to-noise ratio
at the output of A2 now decreases linearly as the gain increased
(Figure 12).
–8–
REV. C
AD603
THEORY OF THE AD603
A Low Noise AGC Amplifier
3.0
2.5
2.0
Figure 15 shows the ease with which the AD603 can be connected
as an AGC amplifier. The circuit illustrates many of the points
previously discussed: It uses few parts, has linear-in-dB gain,
operates from a single supply, uses two cascaded amplifiers in
sequential gain mode for maximum S/N ratio, and an external
resistor programs each amplifier’s gain. It also uses a simple
temperature-compensated detector.
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
The circuit operates from a single 10 V supply. Resistors R1,
R2, R3, and R4 bias the common pins of A1 and A2 at 5 V.
This pin is a low impedance point and must have a low impedance
path to ground, here provided by the 100 µF tantalum capacitors
and the 0.1 µF ceramic capacitors.
–3.0
–0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
V
C
The cascaded amplifiers operate in sequential gain. Here, the
offset voltage between the pins 2 (GNEG) of A1 and A2 is
1.05 V (42.14 dB × 25 mV/dB), provided by a voltage divider
consisting of resistors R5, R6, and R7. Using standard values,
the offset is not exact, but it is not critical for this application.
Figure 13. Gain Error for Cascaded Stages–Low Ripple
Mode
90
85
The gain of both A1 and A2 is programmed by resistors R13
and R14, respectively, to be about 42 dB; thus the maximum
gain of the circuit is twice that, or 84 dB. The gain-control
range can be shifted up by as much as 20 dB by appropriate
choices of R13 and R14.
80
75
70
65
60
55
50
The circuit operates as follows. A1 and A2 are cascaded.
Capacitor C1 and the 100 Ω of resistance at the input of A1
form a time-constant of 10 µs. C2 blocks the small dc offset
voltage at the output of A1 (which might otherwise saturate A2
at its maximum gain) and introduces a high-pass corner at about
16 kHz, eliminating low frequency noise.
A half-wave detector is used, based on Q1 and R8. The current
into capacitor CAV is just the difference between the collector
current of Q2 (biased to be 300 µA at 300 K, 27°C) and the col-
lector current of Q1, which increases with the amplitude of the
0
–0.2
0.2
0.4
0.6
0.8
1.0
1.2
V
C
Figure 14. ISNR vs. Control Voltage–Low Ripple Mode
10V
C11
0.1F
R9
1.54k⍀
R10
1.24k⍀
THIS CAPACITOR SETS
AGC TIME CONSTANT
Q2
2N3906
V
AGC
C7
0.1F
R11
3.83k⍀
10V
C8
0.1F
10V
C
0.1F
AV
5V
R13
2.49k⍀
Q1
2N3904
C1
0.1F
C9
0.1F
R12
4.99k⍀
R14
2.49k⍀
C2
0.1F
J1
R8
806⍀
A1
AD603
RT
100⍀
10V
R1
1
A2
AD603
10V
R3
J2
C10
0.1F
2.49k⍀
2.49k⍀
+
R2
2.49k⍀
C3
100F
C4
0.1F
2
+
R4
2.49k⍀
C5
100F
C6
0.1F
2
AGC LINE
1V OFFSET FOR
SEQUENTIAL GAIN
R5
5.49k⍀
R7
3.48k⍀
10V
5.5V
6.5V
R6
1.05k⍀
NOTES
1
R
PROVIDES A 50⍀ INPUT IMPEDANCE
T
2
C3 AND C5 ARE TANTALUM
Figure 15. A Low Noise AGC Amplifier
–9–
REV. C
AD603
output signal. The automatic gain control voltage, VAGC, is the
time-integral of this error current. In order for VAGC (and thus
the gain) to remain insensitive to short-term amplitude fluctuations
in the output signal, the rectified current in Q1 must, on average,
exactly balance the current in Q2. If the output of A2 is too small
to do this, VAGC will increase, causing the gain to increase, until
Q1 conducts sufficiently.
This resistor also serves to lower the peak current in Q1 when
more typical signals (usually, sinusoidal) are involved, and the
1.8 kHz LP filter it forms with CAV helps to minimize distortion
due to ripple in VAGC. Note that the output amplitude under
sine wave conditions will be higher than for a square wave, since
the average value of the current for an ideal rectifier would be
0.637 times as large, causing the output amplitude to be
1.88 (=1.2/0.637) V, or 1.33 V rms. In practice, the somewhat
nonideal rectifier results in the sine wave output being regulated
to about 1.4 V rms, or 3.6 V p-p.
Consider the case where R8 is zero and the output voltage VOUT
is a square wave at, say, 455 kHz, which is well above the corner
frequency of the control loop.
The bandwidth of the circuit exceeds 40 MHz. At 10.7 MHz,
the AGC threshold is 100 µV (–67 dBm) and its maximum gain
is 83 dB (20 log 1.4 V/100 µV). The circuit holds its output at
1.4 V rms for inputs as low as –67 dBm to +15 dBm (82 dB),
where the input signal exceeds the AD603’s maximum input
rating. For a 30 dBm input at 10.7 MHz, the second harmonic
is 34 dB down from the fundamental and the third harmonic is
35 dB down.
During the time VOUT is negative with respect to the base voltage
of Q1, Q1 conducts; when VOUT is positive, it is cut off. Since
the average collector current of Q1 is forced to be 300 µA, and
the square wave has a duty-cycle of 1:1, Q1’s collector current
when conducting must be 600 µA. With R8 omitted, the peak
amplitude of VOUT is forced to be just the VBE of Q1 at 600 µA,
typically about 700 mV, or 2 VBE peak-to-peak. This voltage,
hence the amplitude at which the output stabilizes, has a strong
negative temperature coefficient (TC), typically –1.7 mV/°C.
Although this may not be troublesome in some applications, the
correct value of R8 will render the output stable with temperature.
CAUTION
Careful component selection, circuit layout, power-supply
decoupling, and shielding are needed to minimize the AD603’s
susceptibility to interference from radio and TV stations, etc. In
bench evaluation, we recommend placing all of the components
in a shielded box and using feedthrough decoupling networks
for the supply voltage. Circuit layout and construction are also
critical, since stray capacitances and lead inductances can form
resonant circuits and are a potential source of circuit peaking,
oscillation, or both.
To understand this, first note that the current in Q2 is made
to be proportional to absolute temperature (PTAT). For the
moment, continue to assume that the signal is a square wave.
When Q1 is conducting, VOUT is now the sum of VBE and a
voltage that is PTAT and which can be chosen to have an equal
but opposite TC to that of the VBE. This is actually nothing more
than an application of the “bandgap voltage reference” principle.
When R8 is chosen such that the sum of the voltage across it
and the VBE of Q1 is close to the bandgap voltage of about 1.2 V,
VOUT will be stable over a wide range of temperatures, provided,
of course, that Q1 and Q2 share the same thermal environment.
Since the average emitter current is 600 µA during each half-
cycle of the square wave a resistor of 833 Ω would add a PTAT
voltage of 500 mV at 300 K, increasing by 1.66 mV/°C. In prac-
tice, the optimum value will depend on the type of transistor
used and, to a lesser extent, on the waveform for which the
temperature stability is to be optimized; for the inexpensive
2N3904/2N306 pair and sine wave signals, the recommended
value is 806 Ω.
–10–
REV. C
AD603
2.50
2.00
45MHz
1.50
70MHz
1.00
10.7MHz
0.50
0.00
455kHz
–0.50
–1.00
–1.50
70MHz
–0.5 –0.4 –0.3 –0.2 –0.1 0.0 0.2 0.3 0.4 0.5 0.6
GAIN VOLTAGE – Volts
100k
1M
10M
100M
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 16. Gain Error vs. Gain Control
Voltage at 455 kHz, 10.7 MHz, 45 MHz,
70 MHz
Figure 17. Frequency and Phase
Response vs. Gain (Gain = –10 dB,
PIN = –30 dBm, Pin 5 Connected to
Pin 7)
Figure 18. Frequency and Phase
Response vs. Gain (Gain = +10 dB,
PIN = –30 dBm, Pin 5 Connected to
Pin 7)
7.60
7.40
7.20
7.00
6.80
6.60
6.40
+5V
0.1F
HP3326A
DUAL
CHANNEL
HP3585A
SPECTRUM
ANALYZER
10
؋
PROBE
SYNTHESIZER
AD603
100⍀
0.1F
511⍀
–5V
DATEL
DVC 8500
–0.6
–0.4 –0.2
0
0.2
0.4
0.6
100k
1M
10M
100M
GAIN CONTROL VOLTAGE – Volts
FREQUENCY – Hz
Figure 19. Frequency and Phase
Response vs. Gain (Gain = +30 dB,
PIN = –30 dBm, Pin 5 Connected to
Pin 7)
Figure 20. Group Delay vs. Gain
Control Voltage
Figure 21. Third Order Intermodula-
tion Distortion Test Setup
–1.0
–1.2
–1.4
10dB/DIV
10dB/DIV
–1.6
–1.8
–2.0
–2.2
–2.4
–2.6
–2.8
–3.0
–3.2
–3.4
0
50
100 200 500 1000 2000
LOAD RESISTANCE – ⍀
Figure 22. Third Order Intermodula-
tion Distortion at 455 kHz (10× Probe
Used to HP3585A Spectrum Analyzer,
Gain = 0 dB, PIN = 0 dBm, Pin 5 Con-
nected to Pin 7)
Figure 23. Third Order Intermodula-
tion Distortion at 10.7 MHz (10× Probe
Used to HP3585A Spectrum Analyzer,
Gain = 0 dB, PIN = 0 dBm, Pin 5 Con-
nected to Pin 7)
Figure 24. Typical Output Voltage
Swing vs. Load Resistance (Negative
Output Swing Limits First)
REV. C
–11–
AD603
102
100
98
102
100
98
102
100
98
96
96
96
94
94
94
100k
1M
10M
100M
100k
1M
10M
100M
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 25. Input Impedance vs.
Frequency (Gain = –10 dB)
Figure 26. Input Impedance vs.
Frequency (Gain = +10 dB)
Figure 27. Input Impedance vs.
Frequency (Gain = +30 dB)
8V
4.5V
1V
INPUT GND
1V/DIV
100
90
INPUT GND
100mV/DIV
1V
500mV
OUTPUT GND
1V/DIV
10
0%
OUTPUT GND
500mV/DIV
200ns
1V
–2V
–49ns
–500mV
–49ns
50ns
451ns
50ns
451ns
Figure 28. Gain-Control Channel
Response Time
Figure 29. Input Stage Overload
Recovery Time, Pin 5 Connected to
Pin 7 (Input Is 500 ns Period, 50%
Duty-Cycle Square Wave, Output Is
Captured Using Tektronix 11402
Digitizing Oscilloscope)
Figure 30. Output Stage Overload
Recovery Time, Pin 5 Connected to
Pin 7 (Input Is 500 ns Period, 50%
Duty-Cycle Square Wave, Output Is
Captured Using Tektronix 11402
Digitizing Oscilloscope)
3.5V
3.5V
0
–10
–20
–30
INPUT
500mV/DIV
INPUT GND
100mV/DIV
GND
GND
500mV
500mV
–40
–50
–60
OUTPUT
500mV/DIV
OUTPUT GND
500mV/DIV
–1.5V
–44ns
–1.5V
–44ns
50ns
456ns
50ns
456ns
100k
1M
10M
100M
FREQUENCY – Hz
Figure 31. Transient Response,
G = 0 dB, Pin 5 Connected to Pin 7
(Input is 500 ns Period, 50% Duty-
Cycle Square Wave, Output Is
Captured Using Tektronix 11402
Digitizing Oscilloscope)
Figure 32. Transient Response,
G = +20 dB, Pin 5 Connected to Pin 7
(Input is 500 ns Period, 50% Duty-
Cycle Square Wave, Output Is
Captured Using Tektronix 11402
Digitizing Oscilloscope)
Figure 33. PSRR vs. Frequency (Worst
Case Is Negative Supply PSRR,
Shown Here)
–12–
REV. C
AD603
21
19
17
15
13
11
9
23
21
19
T
R
= 25؇C
= 50⍀
30MHz
A
10MHz
T
R
= 25؇C
= 50⍀
A
+5V
0.1F
S
S
TEST SETUP
FIGURE 34
TEST SETUP
FIGURE 34
70MHz
HP3326A
DUAL
CHANNEL
SYNTHESIZER
17
15
20MHz
HP3585A
SPECTRUM
ANALYZER
50⍀
AD603
50MHz
100⍀
0.1F
13
11
9
10MHz
–5V
DATEL
DVC 8500
7
7
5
5
20 21 22 23 24 25 26 27 28 29 30
GAIN – dB
30 31 32 33 34 35 36 37 38 39 40
GAIN – dB
Figure 34. Test Setup Used for: Noise
Figure, 3rd Order Intercept and 1 dB
Compression Point Measurements
Figure 35. Noise Figure in –10 dB/
+30 dB Mode
Figure 36. Noise Figure in 0 dB/+40 dB
Mode
0
20
20
T
= 25؇C
= 50⍀
= 50⍀
A
T
= 25؇C
T = 25؇C
A
TEST SETUP
FIGURE 34
A
R
R
R
S
TEST SETUP
FIGURE 34
18
16
14
12
18
16
14
12
–5
IN
30MHz
30MHz
= 100⍀
L
TEST SETUP
FIGURE 34
–10
40MHz
40MHz
–15
–20
70MHz
70MHz
10
10
–25
8
8
10
30
50
70
–20
–10
INPUT LEVEL – dBm
0
–40
–30
INPUT LEVEL – dBm
–20
INPUT FREQUENCY – MHz
Figure 37. 1 dB Compression Point,
–10 dB/+30 dB Mode, Gain = 30 dB
Figure 38. 3rd Order Intercept –10 dB/
+30 dB Mode, Gain = 10 dB
Figure 39. 3rd Order Intercept, –10 dB/
+30 dB Mode, Gain = 30 dB
REV. C
–13–
AD603
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Cerdip (Q-8)
0.055 (1.4)
MAX
0.005 (0.13)
MIN
8
5
0.310 (7.87)
0.220 (5.59)
1
4
PIN 1
0.320 (8.13)
0.290 (7.37)
0.405 (10.29)
MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
0.070 (1.78)
0.023 (0.58)
0.100
(2.54)
BSC
15°
0°
PLANE
0.014 (0.36)
0.030 (0.76)
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
؋
45؇ 0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8؇
0؇
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
–14–
REV. C
相关型号：
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