AD621ANZ [ADI]
Low Drift, Low Power Instrumentation Amplifier; 低漂移，低功耗仪表放大器
| 型号： | AD621ANZ |
| 厂家： | 
ADI |
| 描述： | Low Drift, Low Power Instrumentation Amplifier |
| 文件： | 总16页 (文件大小：520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Drift, Low Power
Instrumentation Amplifier
a
AD621
CONNECTION DIAGRAM
8-Lead Plastic Mini-DIP (N), Cerdip (Q)
and SOIC (R) Packages
FEATURES
EASY TO USE
Pin-Strappable Gains of 10 and 100
All Errors Specified for Total System Performance
Higher Performance than Discrete In Amp Designs
Available in 8-Lead DIP and SOIC
Low Power, 1.3 mA Max Supply Current
Wide Power Supply Range (؎2.3 V to ؎18 V)
1
2
3
4
8
7
6
5
G = 10/100
G = 10/100
–IN
+V
S
AD621
TOPVIEW
+IN
OUTPUT
REF
(Not to Scale)
–V
S
EXCELLENT DC PERFORMANCE
0.15% Max, Total Gain Error
gain drift errors are achieved by the use of internal gain setting
resistors. Fixed gains of 10 and 100 can easily be set via external
pin strapping. The AD621 is fully specified as a total system,
therefore, simplifying the design process.
؎5 ppm/؇C, Total Gain Drift
125 V Max, Total Offset Voltage
1.0 V/؇C Max, Offset Voltage Drift
LOW NOISE
9 nV/√Hz, @ 1 kHz, Input Voltage Noise
For portable or remote applications, where power dissipation,
size, and weight are critical, the AD621 features a very low
supply current of 1.3 mA max and is packaged in a compact
8-lead SOIC, 8-lead plastic DIP or 8-lead cerdip. The AD621
also excels in applications requiring high total accuracy, such
as precision data acquisition systems used in weigh scales and
transducer interface circuits. Low maximum error specifications
including nonlinearity of 10 ppm, gain drift of 5 ppm/°C, 50 µV
offset voltage, and 0.6 µV/°C offset drift (“B” grade), make
possible total system performance at a lower cost than has been
previously achieved with discrete designs or with other mono-
lithic instrumentation amplifiers.
0.28 V p-p Noise (0.1 Hz to 10 Hz)
EXCELLENT AC SPECIFICATIONS
800 kHz Bandwidth (G = 10), 200 kHz (G = 100)
12 s Settling Time to 0.01%
APPLICATIONS
Weigh Scales
Transducer Interface and Data Acquisition Systems
Industrial Process Controls
Battery-Powered and Portable Equipment
PRODUCT DESCRIPTION
The AD621 is an easy to use, low cost, low power, high accu-
racy instrumentation amplifier that is ideally suited for a wide
range of applications. Its unique combination of high perfor-
mance, small size and low power, outperforms discrete in amp
implementations. High functionality, low gain errors, and low
When operating from high source impedances, as in ECG and
blood pressure monitors, the AD621 features the ideal combina-
tion of low noise and low input bias currents. Voltage noise is
specified as 9 nV/√Hz at 1 kHz and 0.28 µV p-p from 0.1 Hz to
10 Hz. Input current noise is also extremely low at 0.1 pA/√Hz.
The AD621 outperforms FET input devices with an input bias
current specification of 1.5 nA max over the full industrial tem-
perature range.
30,000
25,000
3 OP AMP
IN AMP
10,000
20,000
15,000
10,000
5,000
0
(3 OP 07S)
1,000
TYPICAL STANDARD
BIPOLAR INPUT
IN AMP
AD621A
100
10
AD621 SUPERETA
BIPOLAR INPUT
0
5
10
SUPPLY CURRENT – mA
15
20
IN AMP
1
Figure 1. Three Op Amp IA Designs vs. AD621
0.1
1k
10k
100k
1M
10M
100M
SOURCE RESISTANCE – ⍀
Figure 2. Total Voltage Noise vs. Source Resistance
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2001
AD621–SPECIFICATIONS
(Typical @ 25؇C, V =
؎
15 V, and RL = 2 k
⍀
, unless otherwise noted.)
Gain = 10
S
AD621A
Typ
AD621B
AD621S1
Typ
Model
Conditions
Min
Max
Min
Typ
Max
Min
Max
Unit
GAIN
Gain Error
Nonlinearity,
VOUT
=
10 V
0.15
0.05
0.15
%
V
OUT = –10 V to +10 V RL = 2 kΩ
2
–1.5
10
5
2
–1.5
10
5
2
–1
10
5
ppm of FS
ppm/°C
Gain vs. Temperature
TOTAL VOLTAGE OFFSET
Offset (RTI)
VS
VS
VS
=
=
=
15 V
5 V to 15 V
5 V to 15 V
75
250
400
2.5
50
125
215
1.5
75
250
500
2.5
µV
µV
µV/°C
Over Temperature
Average TC
1.0
120
0.6
120
1.0
120
Offset Referred to the
Input vs. Supply (PSR)2 VS
=
2.3 V to 18 V 95
100
95
dB
Total NOISE
Voltage Noise (RTI)
RTI
Current Noise
1 kHz
0.1 Hz to 10 Hz
f = 1 kHz
13
17
13
17
0.8
13
17
0.8
nV/√Hz
µV p-p
fA/√Hz
pA p-p
0.55
100
10
0.55
100
10
0.55
100
10
0.1 Hz–10 Hz
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
VS
=
15 V
0.5
2.0
2.5
0.5
1.0
1.5
0.5
2
4
nA
nA
pA/°C
nA
nA
3.0
0.3
3.0
0.3
8.0
0.3
1.0
1.5
0.5
0.75
1.0
2.0
1.5
1.5
8.0
pA/°C
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range3
Over Temperature
10ʈ2
10ʈ2
10ʈ2
10ʈ2
10ʈ2
10ʈ2
GΩʈpF
GΩʈpF
V
V
V
V
VS
VS
=
=
2.3 V to 5 V
5 V to 18 V
–VS + 1.9
–VS + 2.1
–VS + 1.9
–VS + 2.1
+VS – 1.2 –VS + 1.9
+VS – 1.3 –VS + 2.1
+VS – 1.4 –VS + 1.9
+VS – 1.4 –VS + 2.1
+VS – 1.2 –VS + 1.9
+VS – 1.3 –VS + 2.1
+VS – 1.4 –VS + 1.9
+VS – 1.4 –VS + 2.3
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.4
Over Temperature
Common-Mode Rejection
Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to 10 V
OUTPUT
Output Swing
93
110
100
110
93
110
dB
RL = 10 kΩ,
VS
=
2.3 V to 5 V
–VS + 1.1
–VS + 1.4
–VS + 1.2
–VS + 1.6
+VS – 1.2 –VS + 1.1
+VS – 1.3 –VS + 1.4
+VS – 1.4 –VS + 1.2
+VS – 1.5 –VS + 1.6
+VS – 1.2 –VS + 1.1
+VS – 1.3 –VS + 1.6
+VS – 1.4 –VS + 1.2
+VS – 1.5 –VS + 2.3
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.5
V
V
V
V
Over Temperature
VS
=
5 V to 18 V
Over Temperature
Short Current Circuit
18
18
18
mA
DYNAMIC RESPONSE
Small Signal,
–3 dB Bandwidth
Slew Rate
Settling Time to 0.01%
800
1.2
12
800
1.2
12
800
1.2
12
kHz
V/µs
µs
0.75
0.75
0.75
10 V Step
REFERENCE INPUT
RIN
IIN
20
50
20
50
20
+50
kΩ
µA
V
VIN +, VREF = 0
60
60
+60
+VS – 1.6
0.0001
Voltage Range
Gain to Output
–VS + 1.6
2.3
+VS – 1.6 –VS + 1.6
+VS – 1.6 VS + 1.6
1
0.0001
1
0.0001
1
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
18
1.3
1.6
2.3
18
1.3
1.6
2.3
18
1.3
1.6
V
mA
mA
VS
=
2.3 V to 18 V
0.9
1.1
0.9
1.1
0.9
1.1
TEMPERATURE RANGE
For Specified Performance
–40 to +85
–40 to +85
–55 to +125
°C
NOTES
1See Analog Devices’ military data sheet for 883B tested specifications.
2This is defined as the supply range over which PSRR is defined.
3Input Voltage Range = CMV + (Gain × VDIFF).
Specifications subject to change without notice.
–2–
REV. B
AD621
(Typical @ 25
؇
C, VS =
؎
15 V, and RL = 2 k⍀, unless otherwise noted.)
Gain = 100
AD621A
AD621B
AD621S1
Typ
Model
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Max
Unit
GAIN
Gain Error
Nonlinearity,
VOUT
=
10 V
0.15
0.05
0.15
%
V
OUT = –10 V to +10 V RL = 2 kΩ
2
–1
10
5
2
–1
10
5
2
–1
10
5
ppm of FS
ppm/°C
Gain vs. Temperature
TOTAL VOLTAGE OFFSET
Offset (RTI)
VS
VS
VS
=
=
=
15 V
5 V to 15 V
5 V to 15 V
35
125
185
1.0
25
50
215
0.6
35
125
225
1.0
µV
µV
µV/°C
Over Temperature
Average TC
0.3
140
0.1
140
0.3
140
Offset Referred to the
Input vs. Supply (PSR)2 VS
=
2.3 V to 18 V 110
120
110
dB
Total NOISE
Voltage Noise (RTI)
RTI
Current Noise
1 kHz
0.1 Hz to 10 Hz
f = 1 kHz
9
13
9
13
0.4
9
13
0.4
nV/√Hz
µV p-p
fA/√Hz
pA p-p
0.28
100
10
0.28
100
10
0.28
100
10
0.1 Hz–10 Hz
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
VS
=
15 V
0.5
2.0
2.5
0.5
1.0
1.5
0.5
2
4
nA
nA
pA/°C
nA
nA
3.0
0.3
3.0
0.3
8.0
0.3
1.0
1.5
0.5
0.75
1.0
2.0
1.5
1.5
8.0
pA/°C
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range3
Over Temperature
10ʈ2
10ʈ2
10ʈ2
10ʈ2
10ʈ2
10ʈ2
GΩʈpF
GΩʈpF
V
V
V
V
VS
VS
=
=
2.3 V to 5 V
5 V to 18 V
–VS + 1.9
–VS + 2.1
–VS + 1.9
–VS + 2.1
+VS – 1.2 –VS + 1.9
+VS – 1.3 –VS + 2.1
+VS – 1.4 –VS + 1.9
+VS – 1.4 –VS + 2.1
+VS – 1.2 –VS + 1.9
+VS – 1.3 –VS + 2.1
+VS – 1.4 –VS + 1.9
+VS – 1.4 –VS + 2.3
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.4
Over Temperature
Common-Mode Rejection
Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to 10 V
OUTPUT
Output Swing
110
130
120
130
110
130
dB
RL = 10 kΩ,
VS
=
2.3 V to 5 V
–VS + 1.1
–VS + 1.4
–VS + 1.2
–VS + 1.6
+VS – 1.2 –VS + 1.1
+VS – 1.3 –VS + 1.4
+VS – 1.4 –VS + 1.2
+VS – 1.5 –VS + 1.6
+VS – 1.2 –VS + 1.1
+VS – 1.3 –VS + 1.6
+VS – 1.4 –VS + 1.2
+VS – 1.5 –VS + 2.3
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.5
V
V
V
V
Over Temperature
VS
=
5 V to 18 V
Over Temperature
Short Current Circuit
18
18
18
mA
DYNAMIC RESPONSE
Small Signal,
–3 dB Bandwidth
Slew Rate
Settling Time to 0.01%
200
1.2
12
200
1.2
12
200
1.2
12
kHz
V/µs
µs
0.75
0.75
0.75
10 V Step
REFERENCE INPUT
RIN
IIN
20
50
20
50
20
50
kΩ
µA
V
VIN +, VREF = 0
60
60
60
+VS – 1.6
0.0001
Voltage Range
Gain to Output
–VS + 1.6
2.3
+VS – 1.6 –VS + 1.6
+VS – 1.6 VS + 1.6
1
0.0001
1
0.0001
1
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
18
1.3
1.6
2.3
18
1.3
1.6
2.3
18
1.3
1.6
V
mA
mA
VS
=
2.3 V to 18 V
0.9
1.1
0.9
1.1
0.9
1.1
TEMPERATURE RANGE
For Specified Performance
–40 to +85
–40 to +85
–55 to +125
°C
NOTES
1See Analog Devices’ military data sheet for 883B tested specifications.
2This is defined as the supply range over which PSEE is defined.
3Input Voltage Range = CMV + (Gain × VDIFF).
Specifications subject to change without notice.
–3–
REV. B
AD621
ABSOLUTE MAXIMUM RATINGS1
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without
detection. Although the AD621 features proprietary ESD pro-
tection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 650 mW
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 25 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Operating Temperature Range
AD621 (A, B) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD621 (S) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option1
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Model
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
AD621AN
AD621BN
AD621AR
AD621BR
–40°C to +85°C 8-Lead Plastic DIP
–40°C to +85°C 8-Lead Plastic DIP
N-8
N-8
–40°C to +85°C 8-Lead Plastic SOIC R-8
–40°C to +85°C 8-Lead Plastic SOIC R-8
AD621SQ/883B2 –55°C to +125°C 8-Lead Cerdip
AD621ACHIPS –40°C to +85°C Die
Q-8
8-Lead Plastic Package: θJA = 95°C/W
8-Lead Cerdip Package: θJA = 110°C/W
NOTES
8-Lead SOIC Package: θJA = 155°C/W
1N = Plastic DIP; Q = Cerdip; R = SOIC.
2See Analog Devices’ military data sheet for 883B specifications.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
1.125 (3.57)
+V
7
S
OUTPUT
6
RG 8
5
REFERENCE
0.0708
(2.545)
RG 1
4 –V
S
2
–IN
3
+IN
–4–
REV. B
Typical Performance Characteristics–AD621
50
50
40
30
20
10
0
SAMPLE SIZE = 90
SAMPLE SIZE = 90
40
30
20
10
0
–800
–400
0
+400
+800
–200
–100
0
+100
+200
INPUT BIAS CURRENT – pA
INPUT OFFSET VOLTAGE – V
TPC 1. Typical Distribution of VOS, Gain = 10
TPC 4. Typical Distribution of Input Bias Current
50
2.0
1.5
1.0
0.5
0
SAMPLE SIZE = 90
40
30
20
10
0
–80
–40
0
+40
+80
0
1
2
3
4
5
INPUT OFFSET VOLTAGE – V
WARM-UP TIME – Minutes
TPC 2. Typical Distribution of VOS, Gain = 100
TPC 5. Change in Input Offset Voltage vs. Warm-Up Time
50
1000
SAMPLE SIZE = 90
40
30
20
10
0
100
GAIN = 10
10
GAIN = 100
1
–400
–200
0
+200
+400
1
10
100
1k
10k
100k
INPUT OFFSET CURRENT – pA
FREQUENCY – Hz
TPC 3. Typical Distribution of Input Offset Current
TPC 6. Voltage Noise Spectral Density
REV. B
–5–
AD621
1000
100mV
1s
100
90
100
10
0%
10
10
100
FREQUENCY – Hz
1
1000
TPC 7. Current Noise Spectral Density vs. Frequency
TPC 9. 0.1 Hz to 10 Hz Current Noise, 5 pA per Vertical
Div, 1 Second per Horizontal Div
100,000
10,000
FET INPUT
IN AMP
1000
100
AD621A
10
TIME – 1 sec/div
1k
10k
100k
1M
10M
SOURCE RESISTANCE – ⍀
TPC 10. Total Drift vs. Source Resistance
TPC 8a. 0.1 Hz to 10 Hz RTI Voltage Noise, Gain = 10
160
GAIN = 100
GAIN = 10
140
120
100
80
60
40
20
0
TIME – 1 sec/div
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY – Hz
TPC 11. CMR vs. Frequency, RTI, for a Zero to 1 kΩ
Source Imbalance
TPC 8b. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100
–6–
REV. B
AD621
180
160
35
G = 10 & 100
30
25
G = 100
G = 10
140
120
20
15
100
80
10
5
60
40
20
0.1
0
1k
1
10
100
1k
10k
100k
1M
1M
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 12. Positive PSR vs. Frequency
TPC 15. Large Signal Frequency Response
180
160
–0.0
+V
S
–0.5
–1.0
–1.5
G = 100
G = 10
140
120
100
80
+1.5
+1.0
+0.5
+0.0
60
40
20
0.1
–V
S
1
10
100
1k
10k
100k
1M
0
5
10
15
20
FREQUENCY – Hz
SUPPLY VOLTAGE ؎ Volts
TPC 13. Negative PSR vs. Frequency
TPC 16. Input Voltage Range vs. Supply Voltage
1000
100
10
–0.0
–0.5
+V
S
R
= 10k⍀
L
–1.0
–1.5
R
= 2k⍀
L
+1.5
+1.0
+0.5
+0.0
R
= 2k⍀
L
1
R
= 10k⍀
L
0.1
100
–V
S
0
5
10
SUPPLY VOLTAGE ؎ Volts
15
20
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 14. Closed-Loop Gain vs. Frequency
TPC 17. Output Voltage Swing vs. Supply Voltage,
G = 10
–7–
REV. B
AD621
30
5V
1mV
10s
V
= ؎ 15V
S
G = 10
100
90
20
10
0
10
0%
0
100
1k
10k
LOAD RESISTANCE – ⍀
TPC 21. Large Signal Pulse Response and Settling
TPC 18. Output Voltage Swing vs. Resistive Load
Time, G = 100 (0.5 mV = 0.1%), RL = 2 kΩ, CL = 100 pF
20mV
10s
5V
1mV
10s
100
90
100
90
10
10
0%
0%
TPC 19. Large Signal Pulse Response and Settling
Time Gain, G = 10 (0.5 mV = 0.01%), RL = 1 kΩ,
CL = 100 pF
TPC 22. Small Signal Pulse Response, G = 100,
RL = 2 kΩ, CL = 100 pF
20
20mV
10s
TO 0.01%
100
90
15
TO 0.1%
10
10
5
0
0%
0
5
10
15
20
OUTPUT STEP SIZE – Volts
TPC 20. Small Signal Pulse Response, G = 10,
TPC 23. Settling Time vs. Step Size, G = 10
RL = 1 kΩ, CL = 100 pF
–8–
REV. B
AD621
20
15
10
100V
2V
TO 0.01%
100
90
TO 0.1%
10
5
0
0%
0
5
10
15
20
OUTPUT STEP SIZE – Volts
TPC 27. Gain Nonlinearity, G = 10, RL = 10 kΩ, Vertical
Scale: 100 µV/Div = 100 ppm/Div, Horizontal Scale:
2 Volts/Div
TPC 24. Settling Time vs. Step Size, Gain = 100
2.0
1.5
10k⍀
1%
1k⍀
10T
10k⍀
1%
+I
B
1.0
0.5
0
V
OUT
+V
S
100k⍀
1%
INPUT
20V p-p
–
–I
B
G = 10
G = 100
G = 10
AD621
11k⍀
0.1%
1k⍀
0.1%
G = 100
–0.5
–1.0
–1.5
–2.0
+
–V
S
–125
–75
–25
25
75
125
175
TEMPERATURE – ؇C
TPC 28. Settling Time Test Circuit
TPC 25. Input Bias Current vs. Temperature
0PW 0
VZR 0
100V
2V
100
90
10
0%
0 WFM
20 WFM AQR WARNING
TPC 26. Gain Nonlinearity, G = 100, RL = 10 kΩ,
CL = 0 pF. Vertical Scale: 100 µV/Div = 100 ppm/Div
Horizontal Scale: 2 Volts/Div
–9–
REV. B
AD621
+V
S
R5 at a gain of 10 or the parallel combination of R5 and R6 at a
gain of 100.
7
V
I1
20A
20A
I2
B
This creates a differential gain from the inputs to the A1/A2
outputs given by G = (R1 + R2) / RG + 1. The unity-gain
subtracter A3 removes any common-mode signal, yielding a
single-ended output referred to the REF pin potential.
–
–
A1
A2
10k⍀
C1
C2
10k⍀
10k⍀
The value of RG also determines the transconductance of the
preamp stage. As RG is reduced for larger gains, the transcon-
ductance increases asymptotically to that of the input transistors.
This has three important advantages: (a) Open-loop gain is
boosted for increasing programmed gain, thus reducing gain-
related errors. (b) The gain-bandwidth product (determined by
C1, C2 and the preamp transconductance) increases with pro-
grammed gain, thus optimizing frequency response. (c) The
input voltage noise is reduced to a value of 9 nV/√Hz, deter-
mined mainly by the collector current and base resistance of the
input devices.
–
A3
+
OUTPUT
6
R1 25k⍀ R2 25k⍀
10k⍀
R3
400⍀
REF
R5
5555.6⍀
5
–IN
Q1
Q2
+IN
R4
400⍀
3
2
R6
555.6⍀
1
8
G = 100
G = 100
4
S
–V
Figure 3. Simplified Schematic of AD621
THEORY OF OPERATION
The AD621 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp circuit. Careful layout
of the chip, with particular attention to thermal symmetry builds
in tight matching and tracking of critical components, thus
preserving the high level of performance inherent in this circuit,
at a low price.
Make vs. Buy: A Typical Bridge Application Error Budget
The AD621 offers improved performance over discrete three op
amp IA designs, along with smaller size, fewer components and
10 times lower supply current. In the typical application, shown
in Figure 4, a gain of 100 is required to amplify a bridge output of
20 mV full scale over the industrial temperature range of –40°C to
+85°C. The error budget table below shows how to calculate
the effect various error sources have on circuit accuracy.
Regardless of the system it is being used in, the AD621 provides
greater accuracy, and at low power and price. In simple systems,
absolute accuracy and drift errors are by far the most significant
contributors to error. In more complex systems with an intelligent
processor, an autogain/autozero cycle will remove all absolute
accuracy and drift errors leaving only the resolution errors of
gain nonlinearity and noise, thus allowing full 14-bit accuracy.
On chip gain resistors are pretrimmed for gains of 10 and 100.
The AD621 is preset to a gain of 10. A single external jumper
(between Pins 1 and 8) is all that is needed to select a gain of
100. Special design techniques assure a low gain TC of 5 ppm/°C
max, even at a gain of 100.
Figure 3 is a simplified schematic of the AD621. The input
transistors Q1 and Q2 provide a single differential-pair bipolar
input for high precision, yet offer 10× lower Input Bias Current,
thanks to Superβeta processing. Feedback through the Q1-A1-R1
loop and the Q2-A2-R2 loop maintains constant collector cur-
rent of the input devices Q1 and Q2, thereby impressing the
input voltage across the gain-setting resistor, RG, which equals
Note that for the discrete circuit, the OP07 specifications for
input voltage offset and noise have been multiplied by 2. This is
because a three op amp type in amp has two op amps at its inputs,
both contributing to the overall input error.
10V
+
10k⍀* 10k⍀*
OP07D
–
10k⍀**
+
R = 350⍀
R = 350⍀
R = 350⍀
R = 350⍀
–
AD621A
–
OP07D
+
100k⍀**
REFERENCE
10k⍀**
–
OP07D
+
10k⍀* 10k⍀*
AD621A MONOLITHIC
INSTRUMENTATION
AMPLIFIER, G = 100
3 OP AMP, IN AMP, G = 100
* 0.02% RESISTOR MATCH, 3PPM/؇C TRACKING
** DISCRETE 1% RESISTOR, 100PPM/؇C TRACKING
SUPPLY CURRENT = 15mA MAX
PRECISION BRIDGE TRANSDUCER
SUPPLY CURRENT = 1.3mA MAX
Figure 4. Make vs. Buy
–10–
REV. B
AD621
5V
20k⍀
10k⍀
+
3k⍀
3k⍀
3k⍀
3k⍀
REF
IN
AD621B
DIGITAL
DATA
OUTPUT
ADC
–
+
AD705
–
AGND
20k⍀
1.7mA
1.3mA
MAX
0.10mA
0.6mA
MAX
Figure 5. A Pressure Monitor Circuit which Operates on a 5 V Power Supply
presence of large, unwanted common-mode signals or offsets.
Many monolithic in amps achieve low total input drift and noise
errors only at relatively high gains (~100). In contrast the AD621’s
low output errors allow such performance at a gain of 10, thus
allowing larger input signals and therefore greater dynamic
range. The circuit of Figure 6 ( 15 V supply, G = 10) has
only 2.5 µV/°C max. VOS drift and 0.55 µ/V p-p typical 0.1 Hz
to 10 Hz noise, yet will amplify a 0.5 V differential signal while
suppressing a 10 V common-mode signal, or it will amplify a
1.25 V differential signal while suppressing a 1 V offset by use
of the DAC driving the reference pin of the AD621. An added
benefit, the offsetting DAC connected to the reference pin allows
removal of a dc signal without the associated time-constant
of ac coupling. Note the representations of a differential and
common-mode signal shown in Figure 6 such that a single-ended
(or normal mode) signal of 1 V would be composed of a 0.5 V
common-mode component and a 1 V differential component.
Pressure Measurement
Although useful in many bridge applications such as weigh-scales,
the AD621 is especially suited for higher resistance pressure
sensors powered at lower voltages where small size and low
power become more even significant.
Figure 5 shows a 3 kΩ pressure transducer bridge powered from
5 V. In such a circuit, the bridge consumes only 1.7 mA. Adding
the AD621 and a buffered voltage divider allows the signal to be
conditioned for only 3.8 mA of total supply current.
Small size and low cost make the AD621 especially attractive for
voltage output pressure transducers. Since it delivers low noise
and drift, it will also serve applications such as diagnostic non-
invasion blood pressure measurement.
Wide Dynamic Range Gain Block Suppresses Large Common-
Mode and Offset Signals
The AD621 is especially useful in wide dynamic range applica-
tions such as those requiring the amplification of signals in the
Table I. Make vs. Buy Error Budget
AD621 Circuit
Calculation
Discrete Circuit
Calculation
Error, ppm of Full Scale
Error Source
AD621
Discrete
ABSOLUTE ACCURACY at TA = +25°C
Input Offset Voltage, µV
Output Offset Voltage, µV
Input Offset Current, nA
CMR, dB
125 µV/20 mV
N/A
2 nA × 350 Ω/20 mV
(150 µV × 2/20 mV
((150 µV × 2)/100)/20 mV
(6 nA × 350 Ω)/20 mV
16,250
N/A
12,118
12,791
15,000
12,150
121,53
14,988
110 dB→3.16 ppm, × 5 V/20 mV (0.02% Match × 5 V)/20 mV
Total Absolute Error
17,558
20,191
DRIFT TO +85°C
Gain Drift, ppm/°C
Input Offset Voltage Drift, µV/°C
Output Offset Voltage Drift, µV/°C
5 ppm × 60°C
1 µV/°C × 60°C/20 mV
N/A
100 ppm/°C Track × 60°C
(2.5 µV/°C × 2 × 60°C)/20 mV
(2.5 µV/°C × 2 × 60°C)/100/20 mV
13,300
13,000
N/A
12,600
15,000
12,150
Total Drift Error
13,690
15,750
RESOLUTION
Gain Nonlinearity, ppm of Full Scale
Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV
40 ppm
40 ppm
(0.38 µV p-p × √2)120 mV
12,140
121,14
12,140
12,127
Total Resolution Error
Grand Total Error
121,54
11,472
121,67
36,008
G = 100, VS
= 15 V.
(All errors are min/max and referred to input.)
–11–
REV. B
AD621
INPUT A:
؎10V CM
+
V
DIFF
؎0.5V
–
+
V
COM
OPTIONAL
–
؎10V–
V
10k⍀
؋
10 AD621
OUT1
–
G = 10
V
OUT2
؋
10 AD621
+
TOTAL GAIN = 100
DAC
0 TO ؎10V
INPUT B:
10k⍀
؎1V
+
+
OFFSET
V
+ V
OFFSET
DIFF
؎(1.25V + 1V)
–
USE THIS IN PLACE OF THE DAC FOR ZERO SUPPRESSION FUNCTION.
TO
REF
TO
OUT1
C
V
R
–
AD548
+
Figure 6. Suppressing a Large Common-Mode or Offset Voltage in Order to Measure a Small Differential Signal
(VS = 15 V)
The AD621, as well as many other monolithic instrumentation
amplifiers, is based on the “three op amp” in amp circuit (Fig-
ure 7) amplifier. Since the input amplifiers (A1 and A2) have a
common-mode gain of unity and a differential gain equal to the
set gain of the overall in amp, the voltages V1 and V2 are defined
by the equations
The AD621’s input amplifiers can provide output voltage within
2.5 V of the supplies. To avoid saturation of the input amplifier
the input voltage must therefore obey the equations:
VCM + G × VDIFF/2 ≤ (Upper Supply – 2.5 V)
CM – G × VDIFF/2 ≥ (Lower Supply + 2.5 V)
V
Figure 8 shows the trade-off between common-mode and
differential-mode input for 15 V supplies and G = 10.
V1 = VCM + G × VDIFF/2
V2 = VCM – G × VDIFF/2
By cascading with use of the optional AD621, the circuit of
Figure 6 will provide 1 V of zero suppression at gains of 10
and 100 (at VOUT1 and VOUT2 respectively) with maximum TCs
of 4 ppm/°C and 8 ppm/°C, respectively. Therefore, depend-
ing on the magnitude of the differential input signal, either
VOUT1 or VOUT2 may be used as the output.
The common-mode voltage will drive the outputs of amplifiers
A1 and A2 to the differential-signal voltage, multiplied by the
gain, spreads them apart. For a 10 V common-mode 0.1 V
differential input, V1 would be at 10.5 V and V2 at 9.5 V.
INPUT AMPLIFIER
OUTPUT AMPLIFIER
DIFFERENTIAL GAIN = 10
COMMON MODE GAIN = 1
DIFFERENTIAL GAIN = 1
COMMON MODE GAIN = 1/1000
1.2
1.0
0.8
0.6
0.4
+
V1
10k⍀
A1
10k⍀
–
20k⍀
–
A3
4.44k⍀
+
20k⍀
–
10k⍀
A2
10k⍀
+
V2
0.2
0
Figure 7. Typical Three Op Amp Instrumentation
Amplifier, Differential Gain = 10
0
2
4
6
8
10
12
V
– ؎Volts
CM
Figure 8. Trade-Off Between VCM and VDIFF Range (VS =
15 V, G = 10), for Reference Pin at Ground
–12–
REV. B
AD621
INPUT OVERLOAD CONSIDERATIONS
Precision V-I Converter
Failure of a transducer, faults on input lines, or power supply
sequencing can subject the inputs of an instrumentation ampli-
fier to voltages well beyond their linear range, or even the supply
voltage, so it is essential that the amplifier handle these over-
loads without being damaged.
The AD621 along with another op amp and two resistors make
a precision current source (Figure 9). The op amp buffers the
reference terminal to maintain good CMR. The output voltage
VX of the AD621 appears across R1 which converts it to a cur-
rent. This current less only the input bias current of the op amp
then flows out to the load.
The AD621 will safely withstand continuous input overloads of
3.0 volts ( 6.0 mA). This is true for gains of 10 and 100, with
power on or off.
+V
S
The inputs of the AD621 are protected by high current capacity
dielectrically isolated 400 Ω thin-film resistors R3 and R4 (Fig-
ure 3) and by diodes which protect the input transistors Q1 and
Q2 from reverse breakdown. If reverse breakdown occurred, there
would be a permanent increase in the amplifier’s input current.
R1
+V
V
IN+
X–
AD621
V
IN–
I
L
–V
S
AD705
The input overload capability of the AD621 can be easily increased
while only slightly degrading the noise, common-mode rejection
and offset drift of the device by adding external resistors in series
with the amplifier’s inputs as shown in Figure 10.
V
(V ) – (V ) G
IN+ IN–
X
I
=
=
L
LOAD
R1
R1
Table II summarizes the overload voltages and total input
noise for a range of range of r values. Note that a 2 kΩ resis-
tor in series with each input will protect the AD621 from a
15 volt continuous overload, while only increasing input noise
to 13 nV√Hz—about the same level as would be expected from
a typical unprotected 3 op amp in amp.
Figure 9. Precision Voltage to Current Converter
(Operates on 1.8 mA, 3 V)
INPUT AND OUTPUT OFFSET VOLTAGE
The AD621 is fully specified for total input errors at gains of 10
and 100. That is, effects of all error sources within the AD621
are properly included in the guaranteed input error specs, elimi-
nating the need for separate error calculation.
Table II. Input Overload Protection vs. Value of Resistor RP
Total Input Noise
Maximum Continuous
Overload Voltage, VOL
Total Error RTI = Input Error + (Output Error/G)
Total Error RTO = (Input Error × G) + Output Error
@
in nV√Hz 1 kHz
Value of
Resistor RP G = 10
G = 100 In Volts
0
14
14
14
15
16
17
9
3
6
9
15
21
33
REFERENCE TERMINAL
499 Ω
10
11
13
14
16
Although usually grounded, the reference terminal may be used
to offset the output of the AD621. This is useful when the load
is “floating” or does not share a ground with the rest of the system.
It also provides a direct means of injecting a precise offset.
1.00 kΩ
2.00 kΩ
3.01 kΩ*
4.99 kΩ*
Another benefit of having a reference terminal is that it can be
quite effective in eliminating ground loops and noise in a circuit
or system.
*1/4 watt, 1% metal-film resistor. All others are 1/8 watt, 1% RN55
or equivalent.
+V
S
R
R
P
V
OUT
V
OL
AD621
V
P
OL
GAIN = 10 OR 100
–V
S
Figure 10. Input Overload Protection
–13–
REV. B
AD621
Gain Selection
+V
S
+V
S
The AD621 has accurate, low temperature coefficient (TC),
gains of 10 and 100 available. The gain of the AD621 is nomi-
nally set at 10; this is easily changed to a gain of 100 by simply
connecting a jumper between Pins 1 and 8.
0.1F
0.1F
–
–
INPUTS
+
–
AD621
+
OUTPUT
AD526
2
+
G = 10
20k⍀
555.5⍀
0.1F
–V
S
R
5,555.5⍀
AD621
EXT
0.1F
–V
S
Figure 12. A High Performance Programmable Gain
Amplifier
Figure 11. Programming the AD621 for Gains Between
10 and 100
COMMON-MODE REJECTION
Instrumentation amplifiers like the AD621 offer high CMR
which is a measure of the change in output voltage when both
inputs arc changed by equal amounts. These specifications are
usually given for a full-range input voltage change and a speci-
fied source imbalance.
As shown in Figure 11, the device can be programmed for any
gain between 10 and 100 by connecting a single external resistor
between Pins 1 and 8. Note that adding the external resistor will
degrade both the gain accuracy and gain TC. Since the gain
equation of the AD621 yields:
For optimal CMR, the reference terminal should be tied to a
low impedance point, and differences in capacitance and resis-
tance should be kept to a minimum between the two inputs. In
many applications shielded cables are used to minimize noise,
and for best CMR over frequency the shield should he properly
driven. Figures 13 and 14 show active data guards that are config-
ured to improve ac common-mode rejections by “bootstrapping”
the capacitances of input cable shields, thus minimizing the
capacitance mismatch between the inputs.
9(RX + 6,111.111)
G = 1+
(RX + 555.555)
This can be solved for the nominal value of external resistor for
gains between 10 and 100:
(G – 1)555.555 – 55,000
RX
=
(10 – G)
Table III gives practical 1% resistor values for several com-
mon gains.
+V
S
–INPUT
–
AD648
100⍀
Table III. Practical 1% External Resistor
Values for Gains Between 10 and 100
100k⍀
V
OUT
AD621
100k⍀
Desired Recommended
Temperature
Gain Error Coefficient (TC)
100⍀
–V
S
Gain
1% Resistor Value
REFERENCE
+
10
20
∞ (Pins 1 and 8 Open)
4.42 kΩ
*
5 ppm/°C max
≈0.4 (50 ppm/°C
+ Resistor TC)
≈0.4 (50 ppm/°C
+ Resistor TC)
5 ppm/°C max
+INPUT
10%
10%
–V
S
50
698 Ω
Figure 13. Differential Shield Driver, G = 10
100
0 (Pins 1 and 8 Shorted)
*
+V
S
*Factory trimmed–exact value depends on grade.
– INPUT
2
1
7
A High Performance Programmable Gain Amplifier
The excellent performance of the AD621 at a gain of 10 makes
it a good choice to team up with the AD526 programmable gain
amplifier (PGA) to yield a differential input PGA with gains of
10, 20, 40, 80, 160. As shown in Figure 12, the low offset of the
AD621 allows total circuit offset to be trimmed using the offset
null of the AD526, with only a negligible increase in total drift
error. The total gain TC will be 9 ppm/°C max, with 2 µV/°C
typical input offset drift. Bandwidth is 600 kHz to gains of 10 to
80, and 350 kHz at G = 160. Settling time is 13 µs to 0.01%
for a 10 V output step for all gains.
V
OUT
100⍀
AD621
6
AD548
5
8
3
REFERENCE
4
+ INPUT
–V
S
Figure 14. Common-Mode Shield Driver, G = 100
–14–
REV. B
AD621
+V
S
GROUNDING
Since the AD621 output voltage is developed with respect to the
potential on the reference terminal, it can solve many ground-
ing problems by simply tying the REF pin to the appropriate
“local ground.”
–INPUT
V
AD621
OUT
LOAD
+INPUT
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground pins (Figure 15). It would be conve-
nient to use a single ground line; however, current through
ground wires and PC runs of the circuit card can cause hundreds
of millivolts of error. Therefore, separate ground returns should
be provided to minimize the current flow from the sensitive
points to the system ground. These ground returns must be tied
together at some point, usually best at the ADC package as shown.
–V
S
REFERENCE
TO POWER SUPPLY GROUND
Figure 16a. Ground Returns for Bias Currents when Using
Transformer Input Coupling
+V
S
DIGITAL P.S.
ANALOG P.S.
–INPUT
C
+15V
–15V
C
+5V
AD621
V
OUT
0.1F
0.1F
1F 1F
1F
LOAD
+INPUT
7
2
3
–V
+
4
11
4
S
REFERENCE
1
9
11 15
7
6
AD585
S/H
AD621
DIGITAL
DATA
OUTPUT
6
AD574A
ADC
5
TO POWER SUPPLY GROUND
Figure 16b. Ground Returns for Bias Currents when Using
a Thermocouple Input
Figure 15. Basic Grounding Practice
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of an amplifier. There must be a direct return path
for these currents; therefore when amplifying “floating” input
sources such as transformers, or ac-coupled sources, there must
be a dc path from each input to ground as shown in Figures 16a
through 16c. Refer to the Instrumentation Amplifier Application
Guide (free from Analog Devices) for more information regard-
ing in amp applications.
+V
S
–INPUT
V
AD621
OUT
LOAD
+INPUT
REFERENCE
100k⍀
100k⍀
–V
S
TO POWER SUPPLY GROUND
Figure 16c. Ground Returns for Bias Currents when Using
AC Input Coupling
–15–
REV. B
AD621
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
8
5
0.25
(6.35)
0.31
(7.87)
1
4
0.30 (7.62)
REF
0.39 (9.91)
MAX
0.035 0.01
(0.89 0.25)
0.165 0.01
(4.19 0.25)
SEATING PLANE
0.011 0.003
(4.57 0.76)
0.125 (3.18)
MIN
0.18 0.03
(4.57 0.76)
0.10
(2.54)
TYP
0
- 15
0.018 0.003
(0.46 0.08)
0.033
(0.84)
NOM
Cerdip (Q-8) Package
0.005 (0.13) MIN
0.055 (1.4) MAX
8
5
0.310 (7.87)
0.220 (5.59)
1
4
0.070 (1.78)
0.030 (0.76)
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150
(3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
BSC
0
- 15
SEATING PLANE
SOIC (R-8) Package
0.198 (5.03)
0.188 (4.77)
5
8
0.158 (4.00)
0.150 (3.80)
0.244 (6.200)
0.228 (5.80)
1
4
0.018 (0.46)
0.014 (0.36)
0.050 (1.27)
TYP
0.205 (5.20)
0.181 (4.60)
0.094(2.39)
0.010 (0.25)
0.004 (0.10)
0.015 (0.38)
0.007 (0.18)
0.045 (1.15)
0.020 (0.50)
0.100 (2.59)
–16–
REV. B
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