AD623ARM-REEL [ADI]
Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier; 单电源，轨到轨，低成本仪表放大器
| 型号： | AD623ARM-REEL |
| 厂家： | 
ADI |
| 描述： | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| 文件： | 总16页 (文件大小：960K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply, Rail-to-Rail, Low Cost
Instrumentation Amplifier
a
AD623
FEATURES
Easy to Use
Higher Performance than Discrete Design
Single and Dual Supply Operation
Rail-to-Rail Output Swing
CONNECTION DIAGRAM
8-Lead Plastic DIP (N),
SOIC (R) and SOIC (RM) Packages
Input Voltage Range Extends 150 mV Below Ground
(Single Supply)
Low Power, 575 A Max Supply Current
Gain Set with One External Resistor
Gain Range 1 (No Resistor) to 1,000
1
2
3
4
8
7
6
5
؉R
؉V
؊R
G
G
؊IN
؉IN
S
OUTPUT
؊V
REF
S
AD623
HIGH ACCURACY DC PERFORMANCE
0.1% Gain Accuracy (G = 1)
0.35% Gain Accuracy (G > 1)
25 ppm Gain Drift (G = 1)
200 V Max Input Offset Voltage (AD623A)
2 V/؇C Max Input Offset Drift (AD623A)
100 V Max Input Offset Voltage (AD623B)
1 V/؇C Max Input Offset Drift (AD623B)
25 nA Max Input Bias Current
common-mode range and can amplify signals that have a
common-mode voltage 150 mV below ground. Although the
design of the AD623 has been optimized to operate from a single
supply, the AD623 still provides superior performance when
operated from a dual voltage supply (±2.5 V to ±6.0 V).
NOISE
35 nV/√Hz RTI Noise @ 1 kHz (G = 1)
EXCELLENT AC SPECIFICATIONS
90 dB Min CMRR (G = 10); 84 dB Min CMRR (G = 5)
(@ 60 Hz, 1K Source Imbalance)
800 kHz Bandwidth (G = 1)
20 s Settling Time to 0.01% (G = 10)
Low power consumption (1.5 mW at 3 V), wide supply voltage
range, and rail-to-rail output swing make the AD623 ideal for
battery powered applications. The rail-to-rail output stage maxi-
mizes the dynamic range when operating from low supply volt-
ages. The AD623 replaces discrete instrumentation amplifier
designs and offers superior linearity, temperature stability and
reliability in a minimum of space. Until the AD623, this level of
instrumentation amplifier performance has not been achieved.
APPLICATIONS
Low Power Medical Instrumentation
Transducer Interface
Thermocouple Amplifier
Industrial Process Controls
Difference Amplifier
120
110
Low Power Data Acquisition
100
90
x1000
PRODUCT DESCRIPTION
x100
The AD623 is an integrated single supply instrumentation am-
plifier that delivers rail-to-rail output swing on a single supply
(+3 V to +12 V supplies). The AD623 offers superior user flex-
ibility by allowing single gain set resistor programming, and
conforming to the 8-lead industry standard pinout configura-
tion. With no external resistor, the AD623 is configured for
unity gain (G = 1) and with an external resistor, the AD623 can
be programmed for gains up to 1,000.
80
70
60
50
40
30
x10
x1
The AD623 holds errors to a minimum by providing superior
AC CMRR that increases with increasing gain. Line noise, as
well as line harmonics, will be rejected since the CMRR re-
mains constant up to 200 Hz. The AD623 has a wide input
1
100k
10
100
1k
10k
FREQUENCY – Hz
Figure 1. CMR vs. Frequency, +5 VS, 0 VS
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD623–SPECIFICATIONS
SINGLE SUPPLY
(typical @ +25؇C Single Supply, VS = +5 V, and RL = 10 k⍀, unless otherwise noted)
Model
AD623A
Typ Max
AD623ARM
Typ Max
AD623B
Typ Max
Specification
Conditions
Min
Min
Min
Units
GAIN
G = 1 + (100 k/RG)
Gain Range
Gain Error1
1
1000
1
1000
1
1000
G1 VOUT
0.05 V to 3.5 V
G > 1 VOUT
0.05 V to 4.5 V
=
=
G = 1
G = 10
G = 100
G = 1000
Nonlinearity,
0.03 0.10
0.10 0.35
0.10 0.35
0.10 0.35
0.03 0.10
0.10 0.35
0.10 0.35
0.10 0.35
0.03 0.05
0.10 0.35
0.10 0.35
0.10 0.35
%
%
%
%
G1 VOUT
0.05 V to 3.5 V
G > 1 VOUT
=
=
0.05 V to 4.5 V
G = 1–1000
50
50
50
ppm
Gain vs. Temperature
G = 1
5
50
10
5
50
10
5
50
10
ppm/°C
ppm/°C
G > 11
VOLTAGE OFFSET
Total RTI Error =
VOSI + VOSO/G
Input Offset, VOSI
Over Temperature
Average TC
Output Offset, VOSO
Over Temperature
Average TC
25
200
350
2
200 500
650
25
100
160
1
µV
µV
µV/°C
µV
µV
0.1
200 1000
1500
0.1
2
0.1
500 2000
2600
200 500
1100
10
2.5
10
2.5
10
2.5
µV/°C
Offset Referred to the Input
vs. Supply (PSR)
G = 1
80
100
120
140
140
80
100
120
140
140
80
100
120
140
140
dB
dB
dB
dB
G = 10
G = 100
G = 1000
100
120
120
100
120
120
100
120
120
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
17
25
27.5
17
25
27.5
17
25
27.5
nA
nA
pA/°C
nA
nA
25
0.25
25
0.25
25
0.25
2
2.5
2
2.5
2
2.5
5
5
5
pA/°C
INPUT
Input Impedance
Differential
2ʈ2
2ʈ2
2ʈ2
2ʈ2
2ʈ2
2ʈ2
GΩʈpF
GΩʈpF
V
Common-Mode
Input Voltage Range2
Common-Mode Rejection at
60 Hz with 1 kΩ Source
Imbalance
VS = +3 V to +12 V (–VS) – 0.15
(+VS) – 1.5 (–VS) – 0.15
(+VS) – 1.5 (–VS) – 0.15
(+VS) – 1.5
G = 1
G = 10
G = 100
G = 1000
VCM = 0 V to 3 V
VCM = 0 V to 3 V
VCM = 0 V to 3 V
VCM = 0 V to 3 V
70
90
105
105
80
70
90
105
105
80
77
94
105
105
86
dB
dB
dB
dB
100
110
110
100
110
110
100
110
110
OUTPUT
Output Swing
RL = 10 kΩ
RL = 100 kΩ
+0.01
+0.01
(+VS) – 0.5 +0.01
(+VS) – 0.15 +0.01
(+VS) – 0.5 +0.01
(+VS) – 0.15 +0.01
(+VS) – 0.5
(+VS) – 0.15
V
V
DYNAMIC RESPONSE
Small Signal –3 dB
Bandwidth
G = 1
G = 10
G = 100
G = 1000
800
100
10
2
0.3
800
100
10
2
0.3
800
100
10
2
0.3
kHz
kHz
kHz
kHz
V/µs
Slew Rate
Settling Time to 0.01%
G = 1
G = 10
VS = +5 V
Step Size: 3.5 V
Step Size: 4 V,
VCM = 1.8 V
30
20
30
20
30
20
µs
µs
–2–
REV. C
AD623
DUAL SUPPLIES
(typical @ +25؇C Dual Supply, VS = ؎5 V, and RL = 10 k⍀, unless otherwise noted)
Model
AD623A
Typ Max
AD623ARM
Typ Max
AD623B
Typ Max
Specification
Conditions
Min
Min
Min
Units
GAIN
G = 1 + (100 k/RG)
Gain Range
Gain Error1
1
1000
1
1000
1
1000
G1 VOUT
–4.8 V to 3.5 V
G > 1 VOUT
0.05 V to 4.5 V
=
=
G = 1
G = 10
G = 100
G = 1000
Nonlinearity,
0.03 0.10
0.10 0.35
0.10 0.35
0.10 0.35
0.03 0.10
0.10 0.35
0.10 0.35
0.10 0.35
0.03 0.05
0.10 0.35
0.10 0.35
0.10 0.35
%
%
%
%
G1 VOUT
–4.8 V to 3.5 V
G > 1 VOUT
=
=
–4.8 V to 4.5 V
G = 1–1000
Gain vs. Temperature
G = 1
50
50
50
ppm
5
50
10
5
50
10
5
50
10
ppm/°C
ppm/°C
G > 11
VOLTAGE OFFSET
Total RTI Error =
VOSI + VOSO/G
Input Offset, VOSI
Over Temperature
Average TC
Output Offset, VOSO
Over Temperature
Average TC
25
200
350
2
200 500
650
25
100
160
1
µV
µV
µV/°C
µV
µV
0.1
200 1000
1500
0.1
2
0.1
500 2000
2600
2.5 10
200 500
1100
10
2.5
10
2.5
µV/°C
Offset Referred to the Input
vs. Supply (PSR)
G = 1
80
100
120
140
140
80
100
120
140
140
80
100
120
140
140
dB
dB
dB
dB
G = 10
G = 100
G = 1000
100
120
120
100
120
120
100
120
120
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
17
25
27.5
17 25
27.5
25
17
25
27.5
nA
nA
pA/°C
nA
nA
25
0.25
25
0.25
2
2.5
0.25
2
2
2.5
2.5
5
5
5
pA/°C
INPUT
Input Impedance
Differential
2ʈ2
2ʈ2
2ʈ2
2ʈ2
2ʈ2
2ʈ2
GΩʈpF
GΩʈpF
V
Common-Mode
Input Voltage Range2
Common-Mode Rejection at
60 Hz with 1 kΩ Source
Imbalance
VS = +2.5 V to ±6 V
(–VS) – 0.15
(+VS) – 1.5 (–VS) –0.15
(+VS) – 1.5
(–VS) – 0.15
(+VS) – 1.5
G = 1
G = 10
G = 100
G = 1000
VCM = +3.5 V to –5.15 V 70
VCM = +3.5 V to –5.15 V 90
VCM = +3.5 V to –5.15 V 105
VCM = +3.5 V to –5.15 V 105
80
70
90
105
105
80
77
94
105
105
86
dB
dB
dB
dB
100
110
110
100
110
110
100
110
110
OUTPUT
Output Swing
RL = 10 kΩ, VS = ±5 V
RL = 100 kΩ
(–VS) +0. 2
(–VS) + 0.05
(+VS) – 0.5 (–VS) + 0.2
(+VS) – 0.15 (–VS) + 0.05
(+VS) – 0.5
(+VS) – 0.15 (–VS) + 0.05
(–VS) + 0.2
(+VS) – 0.5
(+VS) – 0.15 V
V
DYNAMIC RESPONSE
Small Signal –3 dB
Bandwidth
G = 1
G = 10
G = 100
G = 1000
800
100
10
2
0.3
800
100
10
2
0.3
800
100
10
2
0.3
kHz
kHz
kHz
kHz
V/µs
Slew Rate
Settling Time to 0.01%
G = 1
G = 10
VS = ±5 V, 5 V Step
30
20
30
20
30
20
µs
µs
REV. C
–3–
AD623–SPECIFICATIONS
BOTH DUAL AND SINGLE SUPPLIES
Model
AD623A
Typ
AD623ARM
Typ
AD623B
Min Typ
Specification
Conditions
Min
Max
Min
Max
Max
Units
NOISE
2
2
Voltage Noise, 1 kHz
Input, Voltage Noise, eni
Output, Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G = 1
Total RTI Noise =
e
+
e
/G
ni
no
35
50
35
50
35
50
nV/√Hz
nV/√Hz
3.0
1.5
100
1.5
3.0
1.5
100
1.5
3.0
1.5
100
1.5
µV p-p
µV p-p
fA/√Hz
pA p-p
G = 1000
Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
REFERENCE INPUT
RIN
IIN
100
+50
±20%
+60
+VS
100
+50
±20%
+60
+VS
100
+50
±20%
+60
+VS
kΩ
µA
V
VIN+, VREF = 0
Voltage Range
Gain to Output
–VS
–VS
–VS
1 ± 0.0002
1 ± 0.0002
1 ± 0.0002
V
POWER SUPPLY
Operating Range
Dual Supply
Single Supply
Dual Supply
Single Supply
±2.5
+2.7
±6
±2.5
+2.7
±6
±2.5
+2.7
±6
V
V
µA
µA
µA
+12
550
480
625
+12
550
480
625
+12
550
480
625
Quiescent Current
Over Temperature
375
305
375
305
375
305
TEMPERATURE RANGE
For Specified Performance
–40 to +85
–40 to +85
–40 to +85
°C
NOTES
1Does not include effects of external resistor RG.
2One input grounded. G = 1.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Lead Temperature Range
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . +300°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 650 mW
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
(N, R, RM) . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
(A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
8-Lead Plastic DIP Package: θJA = 95°C/W
8-Lead SOIC Package: θJA = 155°C/W
8-Lead µSOIC Package: θJA = 200°C/W
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Brand
Code
Model
AD623AN
AD623AR
AD623ARM
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Plastic DIP
8-Lead SOIC
8-Lead µSOIC
13" Tape and Reel
7" Tape and Reel
13" Tape and Reel
7" Tape and Reel
8-Lead Plastic DIP
8-Lead SOIC
N-8
SO-8
RM-8
SO-8
SO-8
RM-8
RM-8
N-8
SO-8
SO-8
SO-8
J0A
AD623AR-REEL
AD623AR-REEL7
AD623ARM-REEL
AD623ARM-REEL7
AD623BN
AD623BR
AD623BR-REEL
AD623BR-REEL7
J0A
J0A
13" Tape and Reel
7" Tape and Reel
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which
readily accumulate on the human body and on test equipment, can discharge without detection.
Although the AD623 features proprietary ESD protection circuitry, permanent damage may still
occur on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid any performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. C
Typical Characteristics
(@ +25؇C VS = ؎5 V, RL = 10 k⍀ unless otherwise noted)
–
AD623
300
280
260
240
220
200
180
160
140
120
100
80
22
20
18
16
14
12
10
8
6
4
2
0
60
40
20
0
0
100 200 300 400 500
–600 –500 –400 –300 –200 –100
0
20 40 60 80 100 120 140
–100 –80 –60 –40 –20
OUTPUT OFFSET VOLTAGE – V
INPUT OFFSET VOLTAGE – V
Figure 5. Typical Distribution of Output Offset Voltage,
VS = +5, Single Supply, VREF = –0.125 V; Package Option
N-8, SO-8
Figure 2. Typical Distribution of Input Offset Voltage;
Package Option N-8, SO-8
210
480
420
360
300
240
180
150
120
90
60
30
180
120
60
0
0
–0.245 –0.24 –0.235 –0.23 –0.225 –0.22 –0.215 –0.21
INPUT OFFSET CURRENT – nA
0
200 400 600 800
–800 –600 –400 –200
OUTPUT OFFSET VOLTAGE ؊ V
Figure 3. Typical Distribution of Output Offset Voltage;
Package Option N-8, SO-8
Figure 6. Typical Distribution for Input Offset Current;
Package Option N-8, SO-8
20
18
16
22
20
18
16
14
12
10
8
14
12
10
8
6
4
6
4
2
0
2
0
0
20
40
60
80 100
–80 –60 –40 –20
0
0.005
0.01
–0.025 –0.02 –0.015 –0.01 –0.005
INPUT OFFSET VOLTAGE – V
INPUT OFFSET CURRENT – nA
Figure 7. Typical Distribution for Input Offset Current,
VS = +5, Single Supply, VREF = –0.125 V; Package Option
N-8, SO-8
Figure 4. Typical Distribution of Input Offset Voltage,
VS = +5, Single Supply, VREF = –0.125 V; Package Option
N-8, SO-8
REV. C
–5–
AD623
30
25
20
1600
1400
1200
1000
800
600
400
200
0
15
10
5
0
75 80 85 90 95
105 110 115 120 125 130
100
–60 –40
–20
0
20
40
60
80 100 120
140
CMRR ؊ dB
TEMPERATURE – ؇C
Figure 11. IBIAS vs. Temp
Figure 8. Typical Distribution for CMRR (G = 1)
1k
100
10
1k
GAIN = 1
100
GAIN = 10
GAIN = 100
GAIN = 1000
10
10
100
FREQUENCY – Hz
1k
1
1
10
100
FREQUENCY – Hz
100k
10k
1k
Figure 9. Voltage Noise Spectral Density vs. Frequency
Figure 12. Current Noise Spectral Density vs. Frequency
21
20
19
18
17
16
15
19.5
19.0
18.5
18.0
17.5
17.0
16.5
–5
0
2
4
–4
–2
0
1
–3
–2
–1
CMV – Volts
CMV – Volts
Figure 10. IBIAS vs. CMV, VS = ±5 V
Figure 13. IBIAS vs. CMV, VS = ±2.5 V
–6–
REV. C
AD623
120
110
x1000
100
90
80
70
60
50
40
30
x10
x1
x100
1
100k
10
100
1k
10k
FREQUENCY – Hz
Figure 14. 0.1 Hz to 10 Hz Current Noise (0.71 pA/Div)
Figure 17. CMR vs. Frequency, ±5 VS
70
60
50
40
30
20
10
RTO
RTI
0
–10
–20
–30
100
1k
10k
100k
1M
FREQUENCY – Hz
Figure 15. 0.1 Hz to 10 Hz RTI Voltage Noise
Figure 18. Gain vs. Frequency (VS = +5 V, 0 V), VREF = 2.5 V
(1 Div = 1 µV p-p)
5
4
120
110
V
= ؎5
S
3
2
1
0
100
90
x1000
V
= ؎2.5
S
x100
80
70
60
50
40
30
–1
x10
–2
–3
–4
–5
x1
1
100k
10
100
1k
10k
–6
–5 –4
–3
–2
–1
0
1
2
3
4
5
FREQUENCY – Hz
COMMON MODE INPUT – Volts
Figure 19. Maximum Output Voltage vs. Common Mode,
G = 1, RL = 100 kΩ
Figure 16. CMR vs. Frequency, +5, 0 VS, VREF = 2.5 V
REV. C
–7–
AD623
140
120
100
80
5
G = 1000
4
3
2
V
= ؎5
S
V
= ؎2.5
S
G = 100
1
0
60
–1
40
–2
–3
–4
–5
G = 10
20
G = 1
0
1
10
100
1k
10k
100k
–6
–5 –4
–3
–2
–1
0
1
2
3
4
5
FREQUENCY – Hz
COMMON MODE INPUT – Volts
Figure 20. Maximum Output Voltage vs. Common Mode,
G ≥ 10, RL = 100 kΩ
Figure 23. Positive PSRR vs. Frequency, ±5 VS
5
4
3
2
1
0
140
G = 1000
120
G = 100
100
80
60
40
G = 10
20
G = 1
0
–1
0
1
2
3
4
5
1
100k
10
100
1k
10k
COMMON MODE INPUT – Volts
FREQUENCY – Hz
Figure 24. Positive PSRR vs. Frequency, +5 VS, 0 VS
Figure 21. Maximum Output Voltage vs. Common Mode,
G = 1, VS = +5 V, RL = 100 kΩ
140
5
4
3
2
1
0
G = 1000
120
100
80
G = 100
G = 10
60
40
20
0
G = 1
1
100k
10
100
1k
10k
–1
0
1
2
3
4
5
FREQUENCY – Hz
COMMON MODE INPUT – Volts
Figure 22. Maximum Output Voltage vs. Common Mode,
Figure 25. Negative PSRR vs. Frequency, ±5 VS
G ≥ 10, VS = +5 V, RL = 100 kΩ
–8–
REV. C
AD623
10
8
6
4
V
= ؎5
S
V
= ؎2.5
S
2
0
0
20
80
100
40
60
FREQUENCY – kHz
Figure 26. Large Signal Response, G ≤ 10
Figure 29. Large Signal Pulse Response and Settling Time,
G = –10 (0.250 mV = 0.01%), CL = 100 pF
1000
100
10
1
10
1
100
1000
GAIN – V/V
Figure 27. Settling Time to 0.01% vs. Gain, for a 5 V Step
at Output, CL = 100 pF, VS = ±5 V
Figure 30. Large Signal Pulse Response and Settling
Time, G = 100, CL = 100 pF
Figure 28. Large Signal Pulse Response and Settling
Time, G = –1 (0.250 mV = 0.01%), CL = 100 pF
Figure 31. Large Signal Pulse Response and Settling
Time, G = –1000 (5 mV = 0.01%), CL = 100 pF
REV. C
–9–
AD623
Figure 35. Small Signal Pulse Response, G = 1000,
Figure 32. Small Signal Pulse Response, G = 1, RL = 10 kΩ,
RL = 10 kΩ, CL = 100 pF
CL = 100 pF
Figure 36. Gain Nonlinearity, G = –1 (50 ppm/Div)
Figure 33. Small Signal Pulse Response, G = 10,
RL = 10 kΩ, CL = 100 pF
Figure 34. Small Signal Pulse Response G = 100,
Figure 37. Gain Nonlinearity, G = –10 (6 ppm/Div)
RL = 10 kΩ, CL = 100 pF
–10–
REV. C
AD623
The output voltage at Pin 6 is measured with respect to the
potential at Pin 5. The impedance of the reference pin is 100 kΩ,
so in applications requiring V/I conversion, a small resistor
between Pins 5 and 6 is all that is needed.
POS SUPPLY
7
+
INVERTING
–
2
4
50k⍀
50k⍀
50k⍀
50k⍀
1
–
+
OUT
6
GAIN
50k⍀
50k⍀
REF
5
8
7
4
Figure 38. Gain Nonlinearity (G = –100, 15 ppm/Div)
–
NON-
INVERTING
3
+
V+
NEG SUPPLY
Figure 40. Simplified Schematic
(V+) –0.5
The bandwidth of the AD623 is reduced as the gain is increased,
since all the amplifiers are of voltage feedback type. At unity
gain, it is the output amplifier that limits the bandwidth. There-
fore even at higher gains the AD623 bandwidth does not roll off
as quickly.
(V+) –1.5
(V+) –1.5
APPLICATIONS
Basic Connection
(V–) +0.5
V–
Figure 41 shows the basic connection circuit for the AD623.
The +VS and –VS terminals are connected to the power supply.
The supply can be either bipolar (VS = ±2.5 V to ±6 V) or
single supply (–VS = 0 V, +VS = 3.0 V to 12 V). Power supplies
should be capacitively decoupled close to the devices power
pins. For best results, use surface mount 0.1 µF ceramic chip
capacitors and 10 µF electrolytic tantalum capacitors.
0
0.5
1.5
1
2
OUTPUT CURRENT – mA
Figure 39. Output Voltage Swing vs. Output Current
THEORY OF OPERATION
The input voltage, which can be either single-ended (tie either
–IN or +IN to ground) or differential is amplified by the pro-
grammed gain. The output signal appears as the voltage difference
between the Output pin and the externally applied voltage on
the REF input. For a ground referenced output, REF should be
grounded.
The AD623 is an instrumentation amplifier based on a modified
classic three op amp approach, to assure single or dual supply
operation even at common-mode voltages at the negative supply
rail. Low voltage offsets, input and output, as well as absolute
gain accuracy, and one external resistor to set the gain, make the
AD623 one of the most versatile instrumentation amplifiers in
its class.
GAIN SELECTION
The input signal is applied to PNP transistors acting as voltage
buffers and providing a common-mode signal to the input
amplifiers (Figure 40). An absolute value 50 kΩ resistor in each
of the amplifiers’ feedback assures gain programmability.
The AD623’s gain is resistor programmed by RG, or more pre-
cisely, by whatever impedance appears between Pins 1 and 8.
The AD623 is designed to offer accurate gains using 0.1%–1%
tolerance resistors. Table I shows required values of RG for
various gains. Note that for G = 1, the RG terminals are uncon-
The differential output is
nected (RG =
by using the formula
ϱ). For any arbitrary gain, RG can be calculated
100 kΩ
VO = 1+
VC
RG
RG = 100 kΩ/(G – 1)
The differential voltage is then converted to a single-ended
voltage using the output amplifier, which also rejects any common-
mode signal at the output of the input amplifiers.
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output. The reference terminal is
also useful when bipolar signals are being amplified as it can be
used to provide a virtual ground voltage. The voltage on the
reference terminal can be varied from –VS to +VS.
Since all the amplifiers can swing to either supply rails, as well
as have their common-mode range extended to below the nega-
tive supply rail, the range over which the AD623 can operate is
further enhanced (Figures 19 and 20).
REV. C
–11–
AD623
+V
+V
S
S
+2.5V TO +6V
+3V TO +12V
10F
10F
0.1F
0.1F
R
R
G
G
V
R
V
R
G
OUTPUT
REF
OUTPUT
REF
V
V
OUT
IN
G
IN
OUT
R
R
G
G
REF (INPUT)
REF (INPUT)
10F
0.1F
–2.5V TO –6V
–V
S
a. Dual Supply
b. Single Supply
Figure 41. Basic Connections
Table I. Required Values of Gain Resistors INPUT PROTECTION
Internal supply referenced clamping diodes allow the input,
reference, output and gain terminals of the AD623 to safely
withstand overvoltages of 0.3 V above or below the supplies.
This is true for all gains, and for power on and off. This last
case is particularly important since the signal source and ampli-
fier may be powered separately.
Desired
Gain
1% Std Table
Value of RG, ⍀
Calculated Gain
Using 1% Resistors
2
5
10
20
33
40
50
65
100
200
500
1000
100 k
24.9 k
11 k
5.23 k
3.09 k
2.55 k
2.05 k
1.58 k
1.02 k
499
2
5.02
10.09
20.12
33.36
40.21
49.78
64.29
99.04
201.4
501
If the overvoltage is expected to exceed this value, the current
through these diodes should be limited to about 10 mA using
external current limiting resistors. This is shown in Figure 42.
The size of this resistor is defined by the supply voltage and the
required overvoltage protection.
+V
S
200
100
1 = 10mA MAX
R
LIM
1001
V
OVER
R
AD623
R
OUTPUT
G
INPUT AND OUTPUT OFFSET VOLTAGE
R
LIM
The low errors of the AD623 are attributed to two sources,
input and output errors. The output error is divided by the
programmed gain when referred to the input. In practice, the
input errors dominate at high gains and the output errors domi-
nate at low gains. The total VOS for a given gain is calculated as:
V
V
؊V +0.7V
OVER
S
OVER
=
LIM
10mA
؊V
S
Figure 42. Input Protection
RF INTERFERENCE
Total Error RTI = Input Error + (Output Error/G)
Total Error RTO = (Input Error × G) + Output Error
All instrumentation amplifiers can rectify high frequency out-of-
band signals. Once rectified, these signals appear as dc offset
errors at the output. The circuit of Figure 43 provides good RFI
suppression without reducing performance within the in amps
pass band. Resistor R1 and capacitor C1 (and likewise, R2 and
C2) form a low-pass RC filter that has a –3 dB BW equal to:
F = 1/(2 π R1C1). Using the component values shown, this
filter has a –3 dB bandwidth of approximately 40 kHz. Resistors
R1 and R2 were selected to be large enough to isolate the
circuit’s input from the capacitors, but not large enough to
significantly increase the circuit’s noise. To preserve common-
mode rejection in the amplifier’s pass band, capacitors C1 and
C2 need to be 5% or better units, or low cost 20% units can be
tested and “binned” to provide closely matched devices.
RTI offset errors and noise voltages for different gains are shown
below in Table II.
Table II. RTI Error Sources
Max
Max
Total Input
Offset Error
Total Input
Offset Drift
Total Input
Referred Noise
(nV/√Hz)
Gain V
V
V/؇C
V/؇C
AD623A AD623B AD623A AD623B AD623A & AD623B
1
2
5
10
20
50
1200
700
400
300
250
220
600
350
200
150
125
110
105
100
12
7
4
11
6
3
62
45
38
35
35
35
35
35
Capacitor C3 is needed to maintain common-mode rejection at
the low frequencies. R1/R2 and C1/C2 form a bridge circuit
whose output appears across the in amp’s input pins. Any
mismatch between C1 and C2 will unbalance the bridge and
reduce common-mode rejection. C3 ensures that any RF signals
3
2
2.5
2.2
2.1
2
1.5
1.2
1.1
1
100 210
1000 200
–12–
REV. C
AD623
are common mode (the same on both in amp inputs) and are
not applied differentially. This second low pass network, R1+R2
and C3, has a –3 dB frequency equal to: 1/(2 π (R1+R2) (C3)).
Using a C3 value of 0.047 µF as shown, the –3 dB signal BW of
this circuit is approximately 400 Hz. The typical dc offset shift
over frequency will be less than 1.5 µV and the circuit’s RF
signal rejection will be better than 71 dB. The 3 dB signal band-
width of this circuit may be increased to 900 Hz by reducing
resistors R1 and R2 to 2.2 kΩ. The performance is similar to
that using 4 kΩ resistors, except that the circuitry preceding the
in amp must drive a lower impedance load.
In many applications shielded cables are used to minimize noise;
for best CMR over frequency the shield should be properly
driven. Figure 44 shows an active guard drive that is configured
to improve ac common-mode rejection by “bootstrapping” the
capacitances of input cable shields, thus minimizing the capaci-
tance mismatch between the inputs.
+V
S
–INPUT
R
G
2
100⍀
V
AD623
AD8031
+INPUT
OUT
R
G
The circuit of Figure 43 should be built using a PC board with a
ground plane on both sides. All component leads should be as
short as possible. Resistors R1 and R2 can be common 1% metal
film units but capacitors C1 and C2 need to be ±5% tolerance
devices to avoid degrading the circuit’s common-mode rejection.
Either the traditional 5% silver mica units or Panasonic ±2%
PPS film capacitors are recommended.
2
REFERENCE
–V
S
Figure 44. Common-Mode Shield Driver
GROUNDING
Since the AD623 output voltage is developed with respect to the
potential on the reference terminal, many grounding problems
can be solved by simply by tying the REF pin to the appropri-
ate “local ground.” The REF pin should, however, be tied to a
low impedance point for optimal CMR.
+V
S
0.33F
0.01F
R1
4.02k⍀
1%
C1
1000pF
5%
–IN
+IN
R2
4.02k⍀
1%
C3
0.047F
The use of ground planes is recommended to minimize the
impedance of ground returns (and hence the size of dc errors).
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground returns (Figure 45). All ground pins
from mixed signal components such as analog-to-digital converters
should be returned through the “high quality” analog ground
R
V
AD623
G
OUT
REFERENCE
C2
1000pF
5%
0.33F
0.01F
LOCATE C1–C3 AS CLOSE
TO THE INPUT PINS AS POSSIBLE
–V
S
Figure 43. Circuit to Attenuate RF Interference
ANALOG POWER SUPPLY
DIGITAL POWER SUPPLY
GND
+5V
–5V
+5V
GND
0.1F
0.1F 0.1F
0.1F
AGND
V
DD
V
AGND DGND
V
12
AD623
DD
IN1
PROCESSOR
ADC
AD7892-2
V
IN2
Figure 45. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies
POWER SUPPLY
GND
+5V
0.1F
0.1F
0.1F
V
DGND
V
DGND
AGND
12
DD
DD
AD623
V
IN
PROCESSOR
ADC
AD7892-2
Figure 46. Optimal Ground Practice in a Single Supply Environment
–13–
REV. C
AD623
plane. Maximum isolation between analog and digital is achieved
by connecting the ground planes back at the supplies. The digi-
tal return currents from the ADC, which flow in the analog ground
plane will, in general, have a negligible effect on noise performance.
applications, providing this path is generally not necessary as the
bias current simply flows from the bridge supply through the
bridge and into the amplifier. However, if the impedances that
the two inputs see are large and differ by a large amount (>10 kΩ),
the offset current of the input stage will cause dc errors propor-
tional with the input offset voltage of the amplifier.
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 46 shows how to
minimize interference between the digital and analog circuitry.
As in the previous case, separate analog and digital ground
planes should be used (reasonably thick traces can be used as an
alternative to a digital ground plane). These ground planes
should be connected at the power supply’s ground pin. Separate
traces should be run from the power supply to the supply pins of
the digital and analog circuits. Ideally, each device should have
its own power supply trace, but these can be shared by a num-
ber of devices as long as a single trace is not used to route cur-
rent to both digital and analog circuitry.
Output Buffering
The AD623 is designed to drive loads of 10 kΩ or greater. If the
load is less that this value, the AD623’s output should be buff-
ered with a precision single supply op amp such as the OP113.
This op amp can swing from 0 V to 4 V on its output while
driving a load as small as 600 Ω. Table III summarizes the per-
formance of some other buffer op amps.
+5V
0.1F
+5V
Ground Returns for Input Bias Currents
0.1F
Input bias currents are those dc currents that must flow in order
to bias the input transistors of an amplifier. These are usually
transistor base currents. When amplifying “floating” input sources
such as transformers or ac-coupled sources, there must be a
direct dc path into each input in order that the bias current can
flow. Figure 47 shows how a bias current path can be provided
for the cases of transformer coupling, capacitive ac-coupling and
for a thermocouple application. In dc-coupled resistive bridge
V
R
G
AD623
IN
OP113
V
OUT
REF
Figure 48. Output Buffering
Table III. Buffering Options
+V
S
–INPUT
Op Amp Comments
OP113
OP191
OP150
Single Supply, High Output Current
Rail-to-Rail Input and Output, Low Supply Current
Rail-to-Rail Input and Output, High Output Current
R
V
AD623
G
OUT
+INPUT
REFERENCE
LOAD
–V
S
A Single Supply Data Acquisition System
TO POWER
SUPPLY
Interfacing bipolar signals to single supply analog to digital
converters (ADCs) presents a challenge. The bipolar signal
must be “mapped” into the input range of the ADC. Figure 49
shows how this translation can be achieved.
GROUND
Figure 47a. Ground Returns for Bias Currents with
Transformer Coupled Inputs
+V
S
+5V
–INPUT
+5V
+5V
0.1F
0.1F
R
AD623
V
G
OUT
AD7776
+INPUT
REFERENCE
LOAD
R
G
؎10mV
AD623
A
IN
1.02k⍀
–V
S
REF
TO POWER
SUPPLY
GROUND
REF
OUT
REF
IN
Figure 47b. Ground Returns for Bias Currents with
Thermocouple Inputs
Figure 49. A Single Supply Data Acquisition System
+V
S
–INPUT
The bridge circuit is excited by a +5 V supply. The full-scale
output voltage from the bridge (± 10 mV) therefore has a
common-mode level of 2.5 V. The AD623 removes the common-
mode component and amplifies the input signal by a factor of
100 (RGAIN = 1.02 kΩ). This results in an output signal of ±1 V.
In order to prevent this signal from running into the AD623’s
ground rail, the voltage on the REF pin has to be raised to at
least 1 V. In this example, the 2 V reference voltage from the
AD7776 ADC is used to bias the AD623’s output voltage to 2 V
±1 V. This corresponds to the input range of the ADC.
R
V
AD623
G
OUT
+INPUT
REFERENCE
LOAD
100k⍀
100k⍀
–V
S
TO POWER
SUPPLY
GROUND
Figure 47c. Ground Returns for Bias Currents with AC
Coupled Inputs
–14–
REV. C
AD623
Amplifying Signals with Low Common-Mode Voltage
Because the common-mode input range of the AD623 extends
0.1 V below ground, it is possible to measure small differential
signals which have low, or no, common mode component. Fig-
ure 50 shows a thermocouple application where one side of the
J-type thermocouple is grounded.
The voltages on these internal nodes are critical in determining
whether or not the output voltage will be clipped. The voltages
A1 and VA2 can swing from about 10 mV above the negative
supply (V– or Ground) to within about 100 mV of the positive
rail before clipping occurs. Based on this and from the above
equations, the maximum and minimum input common-mode
voltages are given by the equations
V
+5V
VCMMAX = V+ – 0.7 V – VDIFF × Gain/2
0.1F
VCMMIN = V– – 0.590 V + VDIFF × Gain/2
These equations can be rearranged to give the maximum possible
differential voltage (positive or negative) for a particular common-
mode voltage, gain, and power supply. Because the signals on A1
and A2, can clip on either rail, the maximum differential voltage
will be the lesser of the two equations.
R
J-TYPE
THERMOCOUPLE
G
AD623
V
OUT
1.02k⍀
REF
2V
|VDIFFMAX| = 2 (V+ – 0.7 V – VCM)/Gain
|VDIFFMAX| = 2 (VCM – V– +0.590 V)/Gain
Figure 50. Amplifying Bipolar Signals with Low Common-
Mode Voltage
However, the range on the differential input voltage range is also
constrained by the output swing. So the range of VDIFF may have
to be lower according the equation.
Over a temperature range from –200°C to +200°C, the J-type
thermocouple delivers a voltage ranging from –7.890 mV to
10.777 mV. A programmed gain on the AD623 of 100 (RG =
1.02 kΩ) and a voltage on the AD623 REF pin of 2 V, results in
the AD623’s output voltage ranging from 1.110 V to 3.077 V
relative to ground.
Input Range ≤ Available Output Swing/Gain
For a bipolar input voltage with a common-mode voltage that is
roughly half way between the rails, VDIFFMAX will be half the
value that the above equations yield because the REF pin will be
at midsupply. Note that the available output swing is given for
different supply conditions in the Specifications section.
INPUT DIFFERENTIAL AND COMMON-MODE RANGE
VS. SUPPLY AND GAIN
Figure 51 shows a simplified block diagram of the AD623. The
voltages at the outputs of the amplifiers A1 and A2 are given by
the equations
The equations can be rearranged to give the maximum gain for a
fixed set of input conditions. Again, the maximum gain will be
the lesser of the two equations.
VA2 = VCM + VDIFF/2 + 0.6 V + VDIFF × RF/RG
= VCM + 0.6 V + VDIFF × Gain/2
GainMAX = 2 (V+ – 0.7 V – VCM)/VDIFF
GainMAX = 2 (VCM – V– +0.590 V)/VDIFF
VA1 = VCM – VDIFF/2 + 0.6 V – VDIFF × RF/RG
= VCM + 0.6 V – VDIFF × Gain/2
Again, we must ensure that the resulting gain times the input
range is less than the available output swing. If this is not the
case, the maximum gain is given by,
POS SUPPLY
7
GainMAX = Available Output Swing/Input Range
Also for bipolar inputs (i.e., input range = 2 VDIFF), the maxi-
mum gain will be half the value yielded by the above equations
because the REF pin must be at midsupply.
INVERTING
A1
2
R
F
50k⍀
4
50k⍀
The maximum gain and resulting output swing for different
input conditions is given in Table IV. Output voltages are refer-
enced to the voltage on the REF pin.
50k⍀
50k⍀
V
1
DIFF
2
V
OUT
6
R
A3
50k⍀
GAIN
G
V
CM
R
F
For the purposes of computation, it is necessary to break down
the input voltage into its differential and common-mode compo-
nent. So when one of the inputs is grounded or at a fixed voltage,
the common-mode voltage changes as the differential voltage
changes. Take the case of the thermocouple amplifier in Figure
50. The inverting input on the AD623 is grounded. So when the
input voltage is –10 mV, the voltage on the noninverting input is
–10 mV. For the purposes of signal swing calculations, this input
voltage should be considered to be composed of a common-mode
voltage of –5 mV (i.e., (+IN + –IN)/2) and a differential input
voltage of –10 mV (i.e., +IN – –IN).
REF
5
50k⍀
8
7
V
DIFF
2
A2
3
NONINVERTING
4
NEG SUPPLY
Figure 51. Simplified Block Diagram
REV. C
–15–
AD623
Table IV. Maximum Attainable Gain and Resulting Output Swing for Different Input Conditions
Supply
Voltages
Max
Gain
Closest 1%
Gain Resistor, ⍀
Resulting
Gain
Output
Swing
VCM
VDIFF
REF Pin
0 V
0 V
0 V
0 V
±10 mV
±100 mV
±10 mV
±100 mV
±1 V
±10 mV
±100 mV
±1 V
±10 mV
±100 mV
±10 mV
±100 mV
2.5 V
2.5 V
0 V
0 V
0 V
2.5 V
2.5 V
2.5 V
1.5 V
1.5 V
1.5 V
1.5 V
+5 V
+5 V
±5 V
±5 V
±5 V
+5 V
+5 V
+5 V
+3 V
+3 V
+3 V
+3 V
118
11.8
490
49
866
9.31 k
205
2.1 k
26.1 k
422
4.32 k
71.5 k
715
116
11.7
488
48.61
4.83
238
24.1
2.4
141
14
116
11.74
±1.2 V
±1.1 V
±4.8 V
±4.8 V
±4.8 V
±2.3 V
±2.4 V
±2.4 V
±1.4 V
±1.4 V
±1.1 V
±1.1 V
0 V
4.9
2.5 V
2.5 V
2.5 V
1.5 V
1.5 V
0 V
242
24.2
2.42
142
14.2
118
11.8
7.68 k
866
9.31 k
0 V
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8-Lead SOIC
(RM-8)
0.430 (10.92)
0.348 (8.84)
0.122 (3.10)
0.114 (2.90)
8
5
4
0.280 (7.11)
0.240 (6.10)
5
4
8
1
1
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.195 (4.95)
0.210 (5.33)
0.115 (2.93)
PIN 1
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.0256 (0.65) BSC
0.015 (0.381)
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.008 (0.204)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33°
27°
0.018 (0.46)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
SEATING
PLANE
0.008 (0.20)
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
؋
45؇ 0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8؇
0؇
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
–16–
REV. C
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