AD6402ARS [ADI]

IF Transceiver Subsystem; IF收发器子系统


型号：	AD6402ARS
厂家：	ADI
描述：	IF Transceiver Subsystem IF收发器子系统
文件：	总8页 (文件大小：113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IF Transceiver Subsystem

AD6402

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

On-Chip Regulator

PLL Dem odulator

On-Chip VCO

No Trim s

Excellent Sensitivity

28-Lead SSOP Package

RSSI

CFILT

LIMITER/FILTER

IFIN

PLL

DEMOD

DOUT

DFILP

TXOUT

TXOUTB

APPLICATIONS

DECT/ PWT/ WLAN

TDMA FM/ FSK System s

PLLOUT

AD6402

VCO

REFSEL

COFF

OFFSET

COMP

VOLTAGE

REGULATOR

REFIN

MODE

CONTROL

FMMOD2

FMMOD1

REF

GENERAL D ESCRIP TIO N

T he AD6402 is a complete transceiver subsystem for use in

high bit rate radio systems employing FM or FSK modulation.

It is optimized for use in time domain multiple access (T DMA)

systems with communications rates of approximately 1 MBPS.

T he AD6402 integrates key functions, including VCOs and a

low drop-out voltage regulator. T he AD6402 operates directly

from an unregulated battery supply of 3.1 V to 4.5 V and pro-

vides a regulated voltage output which can be used for VCO

supply regulation on a companion RF chip such as the AD6401.

VREG VBATT SLREF

CTL1...3

MODOUT

data output. On transmit, it accepts a Gaussian Frequency Shift

Keying (GFSK) baseband signal, low-pass filters the signal if

required using the on-chip op amp and modulates the IF VCO

by varying the bias voltage on an off-chip varactor diode used in

the tank circuit.

T he AD6402 has multiple power-down modes to maximize

battery life. It operates over a temperature range of –25°C to

+85°C and is packaged in a JEDEC standard 28-lead small-

shrink outline (SSOP) surface-mount package.

T he AD6402 transceiver consists of a mixer, integrated IF

bandpass filter, IF limiter with RSSI detection, VCO, PLL

demodulator and a low dropout voltage regulator. On receive, it

downconverts an IF signal in the 110 MHz range to a second

IF frequency, this frequency being determined by the demodu-

lator reference divide ratios. It then filters, amplifies, and de-

modulates this signal. T he AD6402 provides a filtered baseband

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

AD6402–SPECIFICATIONS

AD 6402ARS

Typ

P aram eter

Conditions

Min

Max

Units

IF BANDPASS FILT ER

Center Frequency Rejection

REFIN = 13.824 MHz, REFSEL <0.2 V_CC

F_O±3.0 MHz

F_O±4.7 MHz

20.736

MHz

dBc

_O± 6.0 MHz

Stop Band Rejection

RECEIVER

Sensitivity

FM Modulated 576 kHz, FM Deviation 288 kHz

–80

dBm

BT = 0.5, Demod Output SNR = 10 dB, R_S= 150 Ω

RSSI

Low

High

Slope

Output Impedance

V_OUT= 0.2 V, R_S= 150 Ω

V_OUT= 1.8 V, R_S= 150 Ω

See Figure 4

–85

–5

dBm

mV/dB

kΩ

DEMODULAT OR

Gain

Offset

At Data Filter Output

Referred to SLREF

From SLEEP Mode

From RXLOCK Mode

1.2

–200

1.55

+200

V/MHz

µs

Lock T ime

200

µs

DAT A FILT ER OP AMP

Gain

Slew Rate

C_LOAD= 30 pF

0.2

V/µs

MHz

Ω

Gain Bandwidth

Output Swing Low

Output Swing High

Output Impedance

_CC–0.2

IF VCO

Frequency

Note 1

131

–139

–12

–22

–24

MHz

dBc/Hz

dBm

SSB Phase Noise

Output Power

2nd Harmonic

3rd Harmonic

@ 5 MHz Offset

Differential R_LOAD= 300 Ω

T RANSMIT FILT ER OP AMP

Open Loop Gain

Unity Gain Bandwidth

Output Slew Rate

Minimum Input Voltage

Maximum Input Voltage

Minimum Output Voltage

Maximum Output Voltage

MHz

V/µs

C_LOAD= 30 pF

V_CC–0.2

0.2

V_CC–0.2

POWER CONT ROL

Logical High T hreshold

Logical Low T hreshold

T urn-On Response T ime

0.8 × V_CC

0.2 × V_CC

0.5

µs

V_CCSteady State

VOLT AGE REFERENCE

SLREF

1.3

1.5

SUPPLY REGULAT OR

Output Voltage

T urn-On T ime

Line Regulation

Load Regulation

For Battery Voltages from 3.1 V to 4.5 V

1 mV Settling, C_LOAD= 100 nF

200 mV Battery Step; 5 mV Settling

10 µA to 30 mA Step; 5 mV Settling

2.75

2.95

200

µs

POWER SUPPLY

Supply Current

All V_CCat 2.85 V

RXLOCKP

RXLOCK

RXDEMOD

T RANSMIT

ST ANDBY

SLEEP

300

µA

NOT ES

¹Using test tank circuit as shown.

Specifications subject to change without notice.

–2–

REV. 0

AD6402

RECO MMEND ED O P ERATING CO ND ITIO NS

P IN CO NFIGURATIO N

VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 V–4.5 V

IFVCC1, IFVCC2, PLLVCC . . . . . . . . . . . . . . . . . . . .2.85 V

Operating T emperature Range . . . . . . . . . . . –25°C to +85°C

28 TXOUT

TXOUTB

MODOUT

FMMOD2

FMMOD1

VCOGND

VCO

ABSO LUTE MAXIMUM RATINGS*

27 REFSEL

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V

Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C

Lead T emperature, Soldering (60 sec) . . . . . . . . . . . . +300°C

IFVCC1

25 IFIN

24 IFGND

AD6402

TOP VIEW

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. T his is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended rating conditions for extended periods may affect device

reliability.

RSSI

(Not to Scale)

VREG

IFVCC2

PLLGND

VBAT

CTL3

CTL2

PLLVCC

SLREF

DOUT

T hermal Characteristics:

28-lead SSOP package: θ_JA= 109°C/W.

CTL1

CFILT

COFF

REXT

DFILP

PLLOUT

REFIN

O RD ERING GUID E

Tem perature

Range

P ackage

D escription

Model

AD6402ARS

AD6402ARS-REEL

–25°C to +85°C

28-Lead SSOP

P IN FUNCTIO N D ESCRIP TIO NS

P in

Mnem onic

Function

T XOUT B

MODOUT

FMMOD2

FMMOD1

VCOGND

VCO

T ransmit IF VCO Buffer Inverting Output

Frequency Modulator Filter Op Amp Output

Frequency Modulator Filter Op Amp Noninverting input

Frequency Modulator Filter Op Amp Inverting input

IF VCO Ground

IF VCO T ank Connection

Regulated Supply Output for RF VCO (Supplies Internal IF VCO, Mode Control, Bandgap Reference,

and COFF Buffer)

VREG

VBAT

CT L3

CT L2

CT L1

CFILT

COFF

REXT

REFIN

PLLOUT

DFILP

DOUT

SLREF

PLLVCC

PLLGND

IFVCC2

RSSI

IFGND

IFIN

IFVCC1

REFSEL

T XOUT

Battery Supply Voltage Input to Internal Regulator and COFF Charge Pump

Mode Control Input 3, CMOS Logical Level

Mode Control Input 2, CMOS Logical Level

Mode Control Input 1, CMOS Logical Level

PLL Demodulator Loop Filter Capacitor

PLL Demodulator Frequency Offset Voltage T rack/Hold Capacitor

External Current-Setting Resistor

Baseband Reference Frequency Input, 100 mV p-p, AC Coupled

PLL Demodulator Output

Data Filter Voltage-Follower Input

Data Filter Voltage-Follower Output

PLL Demodulator Output DC Reference Voltage

PLL Demodulator and Data Filter Supply Input

PLL Demodulator and Data Filter Ground

IF Limiter Supply Input 1

RSSI Output

IF Stage, Mixer, Band Pass Filter, IF VCO Buffer, T x Op Amp, Mode Control, and Regulator Ground

IF Mixer Input, Z_O= 150 Z

IF Mixer, Limiter 1, IF Filter, IF VCO Buffer

Reference Frequency Select; IF = 1.5× or 2.5× Reference Frequency, CMOS Logical Level Input

T ransmit IF VCO Buffer Output

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD6402 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–3–

AD6402

VCO

VCOGND

1.2kΩ

8pF

47pF

TUNE

39nH

AD6402

1nF

SMV

1204-37

SMV

1204-36

4.7nF

330Ω

1nF

FMMOD2

FMMOD1

TXOUT

TXOUTB

330Ω

TXMOD

TXIF+

100pF

240Ω

180pF

TXIF–

MODOUT

150pF

VCCI

Figure 1.

O VERVIEW

equal to the sum of the IF frequency plus the frequency of the

PLL demodulator input as defined by the reference clock

divider ratios.

T he AD6402 forms the basis of a highly integrated RF trans-

ceiver with the benefits of increased sensitivity and wide dy-

namic range that a dual-conversion architecture provides. T he

IC contains a low dropout voltage regulator to isolate the IF and

demodulator VCOs from variation in the battery voltage, such

as power-supply transients caused by the PA. T he AD6402 also

provides control circuitry that allows subcircuits to be turned off

and on as necessary to minimize power consumption.

T he transmit IF VCO uses an external tank circuit. T his signal

is upconverted to the transmit frequency in the RF mixer sec-

tion of the radio. Using a transmit IF VCO prevents two prob-

lems: feedback from the PA at the RF frequency does not cause

distortion in the modulating circuit because the frequencies are

widely separated and the IF tank circuit can be optimized for

modulation linearity.

O per ation D ur ing Receive

T he AD6402 contains the second mixer, integrated second-IF

bandpass filter, logarithmic-limiting amplifier, and PLL de-

modulator. A SAW IF bandpass filter is usually required at the

IF input in order to provide channel selectivity.

T he output of the transmit VCO passes through buffer amplifier

and leaves the AD6402 via an optional LC filter between the RF

and IF ICs. T he output of the LC filter may then be fed to a

transmit upconversion mixer for conversion to the final RF

frequency.

T he placement of the SAW filter in the signal path between

the AD6402 and the RF section and the partitioning of the

receiver’s RF and IF receive circuits minimizes the leakage

around the SAW filter and maximizes the RF to IF isolation.

O nboar d Voltage Regulation

T he AD6402 contains a low dropout voltage regulator to spe-

cifically isolate the VCOs and synthesizer from the voltage

“kick” that occurs when a power amplifier switches on and the

battery voltage abruptly drops. T he AD6402 uses an integral

vertical PNP pass transistor.

T he output of the SAW filter enters the AD6402 via the second

downconversion mixer. T his mixer is a high gain, doubly-

balanced Gilbert-cell type. T he mixer downconverts the signal

to the second IF, which is 1.5 × or 2.5 × the reference frequency.

T his multiple is determined by the state of the REFSEL pin. An

on-chip two section bandpass filter provides additional selectiv-

ity to provide attenuation of adjacent channels. T he VCO con-

trol voltage output of the PLL demodulator tunes this filter to

the second IF.

T he regulator in the AD6402 IF IC supplies the voltage for the

VCOs on both the RF section and AD6402. T he other sections

of the AD6402 should be powered from an independently regu-

lated source at 2.85 V. Since the VCOs are isolated from this

source, possible problems due to VCO supply pushing are con-

siderably reduced.

T he bandpass filter’s output enters a successive-detection loga-

rithmic-limiting IF amplifier. T he RSSI detectors are distrib-

uted across the entire IF strip, including the mixer, and provide

80 dB RSSI range. T he IF strip’s limiting gain also exceeds 80

dB. T he RSSI signal is low-pass filtered and proceeds off-chip

to the baseband subsystem. T he limited output of the logarith-

mic amplifier enters a PLL demodulator, which provides de-

modulation of the received signal. T he PLL uses an integrated

VCO with no external components.

Fr equency Contr ol

T he AD6402 requires an external synthesizer to provide the

control voltages for the tank circuit of the IF VCO. Normally

this will be the IF section of a dual synthesizer controlling both

IF and RF frequency generation.

It is recommended that the VCO on the RF section implement

the channel selection on transmit and receive; the VCO on the

AD6402 may therefore operate at a fixed frequency. T his ac-

complishes two goals: first, the IF VCO being modulated can be

optimized for modulation linearity and the RF VCO can be

optimized for tuning range, and second, feedback from the PA

at will not couple into the modulating circuit to cause spurious

responses.

O per ation D ur ing Tr ansm it

T he transmit signal path consists of a low-pass filter that can be

user configured for antialiasing of a baseband transmit signal.

An IF VCO, which should be tuned to a frequency equal to the

receive IF frequency plus the desired demodulator input fre-

quency, may be open-loop modulated by the transmit signal for

FM and FSK schemes. T he receive IF mixer uses high side

mixing and therefore the IF VCO should be set to a frequency

All key sections of the AD6402 may be powered up or down as

necessary to minimize power consumption and maximize

battery life.

–4–

REV. 0

AD6402

Table I. P ower Managem ent Functionality

P LL

TL1

CTL2

CTL3

BIAS

LO CK

D MO D

REF

REG

VCO

MO D E

–

OFF

–

SLEEP

ST ANDBY

RXLOCK

RXDMOD

T RANSMIT

RXLOCKP

OFF

T he AD6402 has six operating modes: SLEEP, ST ANDBY,

RXLOCK, RXDMOD, T RANSMIT and RXLOCKP. T hese

are summarized in T able I. T he blocks referred to in T able I are

shown also in Figure 4. T hese modes are described as follows:

IFVCC1

IFVCC2

RSSI

DOUT

IFIN

SLEEP:

T he entire device is shut down.

DFLIP

IFGND

ST ANDBY: All functions except the regulator are shut down.

PLL DMOD

RXLOCK:

T he device locks to a local reference clock using

the lock PLL. T he lock charge pump and divid-

ers are powered up. The VCO is also powered up.

PLLOUT

PLLVCC

PLLGND

REXT

VBAT

VREG

REG

PLL BIAS

REF

RXDMOD: In this mode the lock charge pump and loop

dividers are shut down. The receive mixer, IF strip,

reference and demodulator are powered up.

SLREF

REF

CFILT

COFF

VCO

PLL LOCK

VCOGND

T RANSMIT : T his mode enables the VCO and transmit op

amp. The reference and regulator are also enabled.

REFIN

CTL3

CTL2

/3,/5

RXLOCKP: T his mode may be used in a “prior to” timeslot,

i.e., the slot before the actual active receive

timeslot. In this mode, after lock has been

achieved in the RXLOCK mode, the receive

mixer, VCO and IF strip may then be indepen-

dently powered up from the demodulator loop.

T his can result is power savings, since the de-

modulator may be powered down during the

IF VCO lock acquisition time.

REFSEL

CTL1

VCO

FMMOD2

FMMOD1

TXOUT

TXOUTB

MODOUT

Figure 2. Power Managem ent Schem e

REV. 0

–5–

AD6402

CFILT

COFF

220 A/RAD

CFILT

LIMITER

500Ω

160 A/RAD

CPUMP

VCO

REFIN

COFFSET

34pF

1.4kΩ

/3,/5

VCO

CPUMP

PLLOUT

COFF

14 A/RAD

COFFSET

34pF

Figure 3a. Dem odulator Block Diagram (Lock Mode)

Figure 3b. Dem odulator Block Diagram (Dm od Mode)

D em odulator O per ation

timeslot, thereby enabling a very accurate dc offset compensa-

tion of system frequency errors.

T he PLL itself uses two loops: one for rapid frequency acquisi-

tion and a second for demodulation. T he first, or frequency-

acquisition loop, locks the VCO to a noninteger multiple of the

system clock, either 3/2 or 5/2 (using one fixed /2 and one pro-

grammable /3 or /5 divider). T his allows not only a choice of IF

and system clocks but also prevents blocking of the receiver by

keeping integer multiples of the system clock out of the IF

passband.

T he on-chip IF filter has been designed to provide some rejec-

tion of adjacent channel signals for channel bandwidths in the

1 MHz–2 MHz range. T his filter has the benefit of reducing the

contribution of broadband noise through the IF strip, hence

improving the overall sensitivity of the receiver for a given

demodulator output signal to noise ratio.

It is also possible to use the AD6402 in applications where non-

constant envelope modulation schemes are used, such as QPSK.

In these applications the amplitude information will be lost

through the limiting action of the IF strip, but in certain appli-

cations, sufficient eye-opening will be observed in the demodu-

lated signal to allow the use of hard decision bit-slicers as in the

FM or FSK case. T he actual performance of the subsystem in

the presence of a QPSK signal will depend on factors such as bit

rate, modulation index and BT employed.

Once locked, this loop voltage is stored on an external capacitor

and this sets the free-running frequency of the VCO during

demodulation. T he first loop is opened and, using the second

loop and phase detector, the PLL compares the free-running

frequency of its VCO to the frequency of the incoming IF. T he

VCO is then fast frequency locked, and slow phase locked to the

incoming IF. Preconditioning of the PLL to the local reference

clock facilitates the fast frequency lock to the received IF. T he

PLL now generates a baseband voltage proportional to the fre-

quency deviation of the received signal.

Figure 4 shows the RSSI response to a DECT signal at the IF

port. It can be seen from the plot that the AD6402 can detect

signals below –85 dBm and continues to detect linearly up to

and above –5 dBm.

T he demodulator uses a third-order PLL to track the incoming

modulation signal. A simplified diagram of the demodulator is

shown in Figures 3a and 3b. T he loop bandwidth and damping

factor can be adjusted by changing the values of C and R as

indicated. An internal pole is present on the demodulator loop

at approximately 9 MHz. For a loop ω_nof 800 kHz, values of

910 pF and 330 Ω respectively are optimum. T he loop band-

width will approximately scale inversely as the square root of the

value of C. T o preserve a satisfactory damping factor, R should

be adjusted linearly with the loop bandwidth. At low loop band-

widths however the value of C offset must also be increased to

enable the loop to lock to the reference frequency during prior

to receive time slots.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

AP P LICATIO NS

T he AD6402 is optimized for use in applications where a data

rate of the order of 1 megabit per second is required and the

modulation scheme employed is constant envelope, i.e., FM or

FSK. Because the demodulator uses a track and hold technique

that locks to an externally supplied reference clock, the device is

optimized for use in T DMA systems. If used in continuous

demodulation applications, the dc offset hold voltage on the

demodulator differential amplifier will ultimately leak away,

resulting in the average dc value of the demodulator output

eventually limiting against the supply rail. In a T DMA system,

the voltage on the capacitor is refreshed just before the active

–95

–91

–87

–75

–55

–35

–15

–3

INPUT POWER – dBm

Figure 4. RSSI Response

Figure 5 shows an implementation for a DECT IF subsystem.

DECT is a 1.152 megabit/second radio, employing Gaussian

FSK modulation at a BT = 0.5 and uses a channel spacing of

1.728 MHz. It is a T DMA/T DD system. T he IF frequency used

in this application is 110.592 MHz. T he AD6402’s flexible

power management scheme enables the part to operate at low

–6–

REV. 0

AD6402

VRF

C44

C71

1nF

100nF

4.7kΩ

3.3nF

IFVCC1

IFVCC2

RSSI

DOUT

AD6402

RXBB

IFIN

C69

C58

47pF

R30

2kΩ

R35

4.7kΩ

100nH

C10

1nF

C12

33pF

1nF

IFIN

DFILP

12pF

R10

2kΩ

1kΩ

150nH

PLLOUT

IFGND

B4535

C14

68pF

PLLVCC

PLLGND

REXT

VBAT

VREG

VRF

C11

100pF

C44

1nF

R17

10kΩ

REG

VIF

C43

100nF

CFILT

COFF

SLREF

R22

330Ω

VREF

C45

131nF

REF

VCO

C32

100nF

C31

VCOGND

C42

47pF

C41

8pF

R26

1.2kΩ

REFIN

RCLK

TXBB

/3,/5

L11

39nH

CTL3

CTL2

CTL1

TUNE

R70

C13

1nF

IFC2

IFC1

IFC0

REFSEL

C25

1nF

R28

330Ω

R32

330Ω

C50

4.7nF

SMV

1204-36

SMV

1204-37

FMMOD2

FMMOD1

C28

1nF

C52

100pF

TXOUT

TXIF+

TXIF–

R21

240Ω

C51

180pF

TXOUTB

MODOUT

C29

1nF

C30

150pF

R16

330Ω

Figure 5. Application Circuit for DECT GFSK Transceiver

transfer characteristic of the loop filter and hence the lock time,

settling time and bandwidth of the loop. REXT should use the

recommended value as shown.

supply current levels when not allocated to an active transmit or

receive timeslot in a T DMA system.. T he respective transmit

and receive blocks can be turned on only as needed thereby

reducing power consumption and extending battery life of

handheld terminals.

Finally, the demodulator is followed by a voltage follower,

which is configured as a data filter. T his data filter is used to

bandlimit the FM noise generated in the demodulator. It also

attenuates undesired adjacent channel interferers. T he compo-

nent values chosen will be a trade-off between the amount of

band limiting required and attenuation of the in-band desired

signal.

T he component selection in Figure 5 is explained as follows:

T he IF input is driven from the output of a SAW filter via an

impedance matching circuit as shown. T his matching minimizes

the insertion loss of the filter and follows the filter manufactur-

ers recommendations. T he tank circuit shown uses two varactor

diodes. One diode (D3) is biased by the output of the IF PLL

loop filter and ensures that the IF VCO frequency is correctly

centered. T he second diode is provided to enable a modulation

signal, which is generated at the output of the on-chip op amp

(MODOUT ), to be coupled into the VCO tank and thereby

implement a modulation of the VCO frequency. In the case of

DECT , the IF VCO control loop is opened while the VCO is

being modulated by the transmit bit stream. T he loop is opened

by tri-stating the output of the IF VCO PLL charge pump.

D ECT Application Cir cuit Notes (Figur e 5)

1. Signal Description

VRF: Regulated Supply Voltage; Nominal Value 2.85 V.

V_CC: Unregulated battery voltage; 3.1 V–4.5 V

VT UNE: Synthesizer Control Voltage; Range dependent on

loop filter and synth charge pump compliance.

T XBB: Baseband transmit modulation voltage; typically

SLREF ±0.7 V

T he exact component values used around the modulation am-

plifier will be determined by the amount of attenuation required

for suppression of baseband transmit spurii and images. T hese

artifacts are usually present if the baseband FSK signal is gener-

ated by a ROMDAC. In most instances a second or third order

Bessel or Butterworth filter will be required.

RCLK: Reference clock for PLL demodulator; 13.824 MHz

(2nd IF frequency = (N/M) × Frclk where N = 3 or 5, and

M = 2. Maximum 2nd IF = c.26 MHz)

2. T ypical IF input sensitivity referred to the input of SAW

filter for the above application will be –72 dBm.

A capacitor to ground is required to be connected to COFF.

T his capacitor stores the demodulator charge-pump voltage

required to lock the demodulator VCO to the reference fre-

quency. T he dynamic response of the demodulator loop is con-

trolled by selection of the values for C45 and R22 which are

connected in series to CFILT . T hese components determine the

3. T xBB filter is user configurable. In the above application, the

filter is implemented to remove images generated by ROM

DAC baseband signal generators. Other implementations are

possible including passive pulse shaping circuits which elimi-

nate the need for such filtering.

REV. 0

–7–

AD6402

EVALUATIO N BO ARD

your local ADI sales office or ADI representative for further

details on pricing and availability of the evaluation boards.

An evaluation board is available for the AD6402. T his board

facilitates test and measurement of the subsystem. Parameters

such as sensitivity, ACI, CCI, demodulator gain, demodulator

offset, etc., can be quickly evaluated using this board. Contact

Header connections details are shown in Figure 6 and available

signals are shown in Figure 7. A schematic for the evaluation

board is shown in Figure 8.

33pF

19 NC

PLLOUT

DOUT

MODOUT

MODIN

33nH

MODIN

MODOUT

CTL1

SLREF

PLLVCC

GND

3pF

TXOUTB

TP11

TP2

330Ω

0.1

CTL2

TP9

1000pF

CTL3

100nF

IFVCC2

RSSI

TP10

VBATX

8kΩ

56pF

1nF

VBAT

GND

14 13 12 11 10

GND

IFVCC1

REFSEL

VREG

AD6402

NC = NO CONNECT

Figure 6. Evaluation Board Header

15 16 17 18 19 20 21 22 23 24 25 26 27 28

SYNTH IN

REFIN

56pF

TP7

0.01

100pF

0.01

TP5

100Ω

0.01

TP8

91pF

TXOUT

TXOUTB

TXOUT

TP6

2.2nF

1.3kΩ

100pF

TO REFSEL

PIN 2

AD6402

PLLOUT

2.2kΩ

47pF

DOUT

CONNECTOR

RSSI

IF INPUT

IFIN

REFIN

Figure 8. Evaluation Board Schem atic

IFIN

NOTE:

SYNTH IN, TXOUTB, TXOUT, IFIN AND REFIN

CONNECTED VIA SMA CONNECTORS

Figure 7. Evaluation Board Connectors

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

28-Lead Sm all Shrink O utline P ackage

(RS-28)

0.407 (10.34)

0.397 (10.08)

0.07 (1.79)

0.078 (1.98)

PIN 1

0.066 (1.67)

0.068 (1.73)

0.03 (0.762)

8°

0°

0.0256

(0.65)

BSC

0.015 (0.38)

0.010 (0.25)

0.022 (0.558)

0.008 (0.203)

0.002 (0.050)

SEATING

PLANE

0.009 (0.229)

0.005 (0.127)

–8–

REV. 0

AD6402ARS [ADI]

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