AD6411ASTRL [ADI]
IC TRANSCEIVER, PQFP48, PLASTIC, LQFP-48, ATM/SONET/SDH IC;
| 型号： | AD6411ASTRL |
| 厂家： | 
ADI |
| 描述： | IC TRANSCEIVER, PQFP48, PLASTIC, LQFP-48, ATM/SONET/SDH IC ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总11页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
DECT RF Transceiver
AD6411
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fully Compliant with DECT Specifications
Single IC DECT Radio
Integrated UHF VCO (External Resonator)
Integrated Synthesizer Supporting Extended Frequency
Allocation
Built-In Supply Regulation
Direct VCO Modulation for DECT Transmit Path
PLL-Based Demodulator
RX
DATA
PLL
DEMODULATOR
LNA
RSSI
PFD
PLL
Use with Low Cost Plastic Packaged SAW Filters
Ultralow Power Design
TX
DATA
VCO
PA
Operates from +3.0 V to +5.5 V Battery
User-Selectable Power-Down Modes
Small 48-Lead LQFP Package
CONTROL
INTERFACE
AD6411
APPLICATIONS
DECT Cordless Telephones
DECT-Based Wireless Local Loop Systems
DECT-Based Wireless Data Systems
DESCRIPTION
The transmit path accepts baseband data, which is filtered and
applied to the VCO directly. The VCO operates at half the RF
carrier frequency, and is doubled to avoid pulling due to leakage
from the output.
The AD6411 provides the complete transmit and receive RF
signal processing necessary to implement a digital wireless
transceiver based on the Digital Enhanced Cordless Telecom-
munications (DECT) standard.
An on-chip PLL frequency synthesizer provides channel selec-
tion. Operating modes are selected either through a serial bus or
asynchronous control pins. This allows compatibility with most
of the available DECT baseband controller ASICs.
The AD6411’s receive signal path consists of a mixer, IF ampli-
fiers and PLL demodulator. The low noise, high intercept mixer
is a development of the doubly-balanced Gilbert-Cell type. It
has a nominal –16 dBm input-referred 1 dB compression point
and a –8 dBm input referred third-order intercept. The limiter
amplifier provides sufficient gain to drive the PLL demodulator,
which provides selectable analog or sliced outputs. The RSSI
output provides a voltage proportional to the receive signal
strength. It measures nearly 100 dB IF signal strength range
with 14 mV/dB gain scaling.
The AD6411 is packaged in a 48-lead LQFP.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
(TA = 25؇C, 3.0 V < VBAT < 5.5 V unless otherwise noted)
AD6411–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Units
RECEIVE RF MIXER
RF Input Frequency
1880 to
1930
MHz
Power Gain
ZSOURCE = 50 Ω, ZLOAD = 200 Ω
15
–21
19
–16
–8
21
dB
Input 1 dB Compression Point
Input Third-Order Intercept
SSB Noise Figure
ZSOURCE = 50 Ω, ZLOAD = 200 Ω
ZSOURCE = 50 Ω, ZLOAD = 200 Ω
ZSOURCE = 50 Ω, ZLOAD = 200 Ω
100 MHz–120 MHz
dBm
dBm
dB
11
Output VSWR
1.5:1
Output Impedance
Input Impedance
200
50
Ω
Ω
RX IF AMPLIFIERS
Differential Input Impedance
Input VSWR
200
6
Ω
Input Power < –11 dBm
ZSOURCE = 200 Ω Differential
1.5:1
IF Noise Figure
dB
RSSI
RSSI Upper Limit
RSSI Lower Limit
RSSI High Level Voltage
RSSI Low Level Voltage
RSSI Slope
RSSI Output Impedance
RSSI Output Response Time
ZSOURCE = 200 Ω Differential
ZSOURCE = 200 Ω Differential
Input Power = 0 dBm (at IF Input)
Input Power = –90 dBm (at IF Input)
–90 dBm < Input Power < 0 dBm (at IF Input)
VRSSI = 0.3 V
–5
+3
dBm
dBm
V
–95
1.7
0.3
14
V
mV/dB
Ω
700
Settling to 95% Value for a 40 dB Input Step,
20 pF External Load
2
µs
PLL DEMODULATOR
PLL Demodulator Phase Detector Gain
Leakage Current at COFF
Recommended External VCO Gain
Demodulator Gain
@ 90 Degree Relative Phase
Charge Pump Disabled
80
115
100
1.152
1.736
150
µA/rad
pA
MHz/V
V/MHz
VCO Gain Set to 1.152 MHz/V
THD for FM Tone @ 576 kHz,
Peak Deviation 288 kHz
Demodulator Linearity
–30
dBc
VOLTAGE REFERENCE
Output Voltage
Output Current
1.3
–3
1.37
1.44
100
V
µA
TRANSMIT SECTION
Output Power
Harmonically Related Spurii
ZL = 50 Ω
+1
–10
–20
+4
dBm
dBc
dBc
At 0.5 × DECT_Tx: (940 MHz–950 MHz)
At 1.5 × DECT_Tx: (2820 MHz–2850 MHz)
100 MHz–3000 MHz, Outside DECT Band
1 MHz Measurement Bandwidth
With UHF Resonator Qu > 30
Other Spurii
–73
dBc
Output Phase Noise
1.2 MHz
3.0 MHz
>4.7 MHz
VCO Operating Frequency Range
Oscillator Push
–120
–130
–135
dBc/Hz
dBc/Hz
dBc/Hz
MHz
With Suitable External Resonator
Using On-Chip Regulator, 250 mV VBAT
Step Change with 5 µs Rise/Fall Time
∆VSWR = 2:1 Any Phase
700
1200
6
55
kHz
kHz
Oscillator Pull
SYNTHESIZER
Reference Input Impedance
Reference Input Level
Reference Input Frequency
VCO Signal Input Range
Charge Pump Current – “Up”
Charge Pump Current – “Down”
Charge Pump Leakage
>5
kΩ
100
10
700
–1.30
0.66
1000
20
1200
–0.77
1.15
mV p-p
MHz
MHz
mA
mA
nA
Voltage On Loop Filter (Pin 38) = 1.4 V
Voltage On Loop Filter (Pin 38) = 1.4 V
Output Disabled
1.0
1.0
<±1
BSW Output “High” Voltage
at ILOAD < = 2 mA
2.5
V
–2–
REV. 0
AD6411
Parameter
Conditions
LOAD = 60 mA max
ILOAD = 60 mA; BCW68F or
Equivalent Pass Transistor
VS1: 10 mA < ILOAD < 60 mA
VS2: 1 mA < ILOAD < 15 mA
ILOAD = 10 mA , ∆VBAT = 250 mV,
Rise/Fall Time = 2 µs
Min
Typ
Max
Units
VOLTAGE REGULATORS (VS1, VS2)
Regulated Voltage Output
Dropout Voltage
I
2.675
2.725
150
2.825
V
mV
mV
mV
Load Regulation
20
Line Transient Response
Line Rejection
1.5
ILOAD = 60 mA, ∆VBAT = 250 mV,
Static Change
DC-1 MHz
0.5
35
mV
dB
Power Supply Rejection
POWER CONSUMPTION
Supply Voltage
All Off Mode
Standby Mode
Prior to TX Slot
Active TX Slot
VBAT
3.0
5.5
V
µA
µA
mA
mA
mA
mA
<1
200
52
52
20
100
400
60
60
25
75
Prior to RX Slot
Active RX Slot
15
45
(Synthesizer Dividers On, Charge Pump Off)
57
OPERATING TEMPERATURE RANGE
–25
+85
°C
ABSOLUTE MAXIMUM RATINGS1
PIN CONFIGURATION
48-Lead LQFP (ST-48)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW
Operating Temperature Range . . . . . . . . . . . –25°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 sec . . . . . . . . . . . . . .+300°C
NOTES
48 47 46 45 44 43 42 41 40 39 38 37
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended rating conditions for extended periods may affect device
reliability.
1
2
REF
SFS
36
35
GND
PIN 1
IDENTIFIER
VCCTX
GND
3
DEMOD DATA
34
4
5
TX ENAB
COFF
33
32
GND
TXOP
AD6411
TOP VIEW
(Not to Scale)
6
2Thermal Characteristics: 48-lead LQFP package: θJA = +126°C/W.
DMR
31
GND
7
8
IFLF
IFCP
30
29
RX
ENAB
GND
9
IFVCO
VREF
28
27
RFIN
GND
ORDERING GUIDE
10
11
12
GND
26
25
VCCRX
GND
Temperature
Range
Package
Description
Package
Option
VCCDM
Model
13 14 15 16 17 18 19 20 21 22 23 24
AD6411AST –25°C to +85°C 48-Lead Plastic LQFP ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6411 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD6411
PIN FUNCTION DESCRIPTIONS
Pin No.
Label
Description
Type
Comments
1
2
3
REF
SFS
DECT Reference Clock Input
S-Field Sample
Input
Input
HIGH = Sample; LOW = Hold
DEMOD_DATA Demodulator Output OR Sliced Demodulator
Output
Output Mode Controlled by DSD Bit in
Control Register
4
TX_ENAB
Transmit Section Power Control Input
Input
Active-High or Active-Low Set by
TSB Bit in Setup Word
5
COFF
DMR
IFLF
Demodulator Offset Capacitor
Output Connect to External Capacitor
6
Input for IF PLL Loop Filter Voltage after Data Filter Input
7
Drive for IF PLL Active Loop Filter
Virtual Ground for IF PLL Active Loop Filter
External Resonator for Demodulator VCO
Voltage Reference Output
Output
Input
8
IFCP
9
IFVCO
VREF
Input
10
Output 1.3 V; Can Be Used for A/D Converter
Reference in Soft-Decision Applications
11, 15, 18,
25, 27, 29,
31, 33, 34,
36, 39
GND
Ground
Power
12
13
14
16
17
19
20
21
22
VCCDM
RSSI
PLL Demodulator Supply
Receive Signal Strength Indicator Output
IF Supply 2
Power
Output
Power
Input
Normally Connected to VS1
VCCIF2
IFINB
IFIN
Normally Connected to VS1
IF Input
Balanced Input from IF SAW Filter
Balanced Input from IF SAW Filter
Normally Connected to VS1
IF Input
Input
VCCIF1
VS1
IF Supply 1
Power
Input
Regulator Sense
Connect to Collector of VS1 Pass Device
VF1
Regulator Force
Output Connect to Base of VS1 Pass Device
SYN_ENAB
Synthesizer Section Power Control Input
Input
Active-High or Active-Low Set by
SSB Bit in Setup Word
23
24
26
28
30
VBAT2
MXOP
Connect to Battery
Power
Output
Power
Input
Receive Mixer Output
Receive RF Supply
VCCRX
RFIN
Normally Connected to VS1
Receive Mixer Input
RX_ENAB
Receive Section Power Control Input
Input
Active-High or Active-Low Set by RSB
Bit in Setup Word
32
35
37
38
40
41
42
43
44
45
46
47
48
TXOP
VCCTX
VCCPD
LF
Transmit Output
Output Open Collector Output
Transmit Supply
Power
Power
Output
Input
Normally Connected to VS1
Normally Connected to VS1
Phase Detector and Charge Pump Supply
Loop Filter (from Charge Pump Output)
UHF Oscillator
VCOB
VCCVCO
VCO
VCO Tank Circuit
Supply for Second Regulator Sense
UHF Oscillator
Power
Input
Connect to Collector of VS2 Pass Device
VCO Tank Circuit
BSW
Resonator Band Switch Output
Regulator Force
Output Controls Tank Circuit Band Segment
VF2
Output Connect to Base of VS2 Pass Device
VBAT1
EN
Connect to Battery
Power
Input
Input
Input
3-Wire Bus Enable
DATA
CLK
3-Wire Bus Data
3-Wire Bus Clock
–4–
REV. 0
AD6411
VCC
L3
C2
R2
V1
L4
C5
R3
C3
TCI
R1
C4
L2
VCC
SAW
C14
C13
+
LNA BPF2
BPF1
DMOD DATA
+
VCC
S1
REF
DC RESTORE
L1
PA
C6
LOAD
SYNTH
C1
SFS
VREF
R4
X2
REFERENCE
0...31
32/33
C7
VBAT
Q1
BSW
12/16
32/34
TXDATA
REGULATOR #1
PFD
VBAT
Q2
C8
CONTROLLER
INTERFACE
AD6411
REGULATOR #2
C9
C10
REF
R6
VBAT
RSSI
C11
R5
C12
Figure 1. Functional Block Diagram
PRODUCT OVERVIEW
The AD6411 provides most of the active circuitry required to
realize a complete low power DECT transceiver.
The output of the mixer is single-ended. The nominal conver-
sion gain is specified for operation into a 110.592 MHz or
112.32 MHz SAW IF DECT bandpass filter. The power gain
of 17 dB is measured between the mixer input and the input of
this filter.
Figure 1 shows the main sections of the AD6411. It consists, in
the receive path, of a UHF mixer and two-stage IF strip with
integrated demodulator and data slicer. The transmit path con-
sists of a VCO, frequency doubler and buffer amplifier.
IF Circuits and Demodulator
Demodulation is achieved via a PLL. This is shown in detail in
Figure 2. An external manufacturing trim is required to achieve
the required level of frequency accuracy. The approach is to
adjust the capacitor TC1 (with the presence of an unmodulated
carrier) such that the dc level at Pin 3 (DEMOD_DATA) is
equal to the voltage on the external reference pin VREF.
Channel selection is performed by an on-chip PLL synthesizer.
All AD6411 operating modes can be controlled by parallel con-
trol inputs or the serial interface.
Receive Mixer
The UHF mixer is an improved Gilbert-cell design. The dy-
namic range at the input of the mixer is determined, at the up-
per end, by the maximum input signal level of –16 dBm in 50 Ω
at RFIN up to which the mixer remains linear and a valid RSSI
signal is provided and, at the lower end, by the noise level.
Two demodulation modes are supported. In one mode any
frequency offset due to reference drift or frequency offsets on
the incoming carrier are propagated to the output (referred to as
“Normal” demodulation). The other method is to use a feature
of the DECT system that enables a secondary compensation
circuit to track out frequency offsets (“S-field sampling,” which
is enabled by the pin SFS—active high together with the con-
figuration bit SFM set over the serial interface).
The local oscillator input of the receive mixer is internally pro-
vided by the LO, which is obtained by doubling the on-chip
VCO frequency.
REV. 0
–5–
AD6411
VCC
150nH
6.8pF
8pF
DATA FILTER
1k⍀
ZC830
DMR
GM3
VREF
VREF
TC1
AD6411
IFLF
DEMOD DATA
LOOP
FILTER
SW3
SW1
IFVCO
GM2
COFF
IFCP
96.768MHz
GM1
SW2
IF/110.592MHz
VARACTOR
TEMP Co
COMPENSATION
13.824MHz
Figure 2. PLL Demodulator Block Diagram
The block diagram shows the principle of operation of these two
modes together with the internal switch settings as shown in
Figure 2.
UHF VCO
A single UHF VCO oscillator is provided operating at one-half
the required frequency. Therefore, in transmit mode the
oscillator operates from (approximately) 940 MHz to 950 MHz,
and in receive mode the oscillator operates from (approxi-
mately) 884 MHz–895 MHz. This requires a switched resona-
tor design, and band switch control is provided by the AD6411.
Table I. Supported Demodulation Modes
Mode
SW1 SW2 SW3
Comment
Prior to RX
SFS = Don’t Care
SFM = 0
Open Closed Closed Precharge Loop
Filter and C Offset
A balanced oscillator configuration is used which has the advan-
tages of rejection of common-mode interference and noise, and
less coupling to and from other parts of the IC and radio.
Capacitor
Normal Demod –
Active RX
SFS = Don’t Care
SFM = 0
Open Closed Open Use Temperature
Compensated
Transmit Functions
The DECT transmit function is achieved by direct modulation
of the UHF VCO operating at half the final transmit output
frequency. An on-chip doubler converts this to the final carrier
frequency. In this mode the synthesizer is set to a high imped-
ance mode i.e., “fly-wheeled.” The drift is sufficiently low for
both single-slot and double-slot transmit operation.
Reference Voltage
S-Field Sample
SFS = 1
SFM = 1
Closed Open Open
Open Open Open
Synthesizer and LO Functions
S-Field Hold
SFS = 0
SFM = 1
A complete synthesizer is implemented on the IC that is capable
of generating all the required DECT channel allocations (in-
cluding the extended DECT bands). This synthesizer can use
reference frequencies of either 13.824 MHz or 10.368 MHz,
controlled by the RD bit in the control register.
An important consideration in normal demodulation mode is
any drift after the initial setup of the VCO. One mechanism is
the Capacitance vs. Temperature coefficient of the external
varactor. This has a known characteristic which is compensated
by an internal reference voltage generation circuit.
Synthesizer Programming
The required channels are programmed by setting the RD bit in
the control register to the correct value, then programming the
A and M Counters as shown below through the serial interface.
–6–
REV. 0
AD6411
Transmit
t
DHD
t
HEN
t
CLK
t
DEN
t
DST
DECT
EN
Channel
A Counter
M Counter
Frequency/MHz
CLK
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
34
34
34
34
34
34
34
34
34
34
1881.792
1883.520
1885.248
1886.976
1888.704
1890.432
1892.160
1893.888
1893.888
1897.344
DATA
MSB
LSB
Figure 3. Serial Interface Timing Diagram
Parameter
Symbol Typ
Unit
Maximum Serial Clock Frequency f_clk
Serial Data Set Up Time
Serial Data Hold Time
Enable Set Up to Clock High
Clock Low to Enable Low
13.824 MHz
9
10
t_dst
8
8
ns
ns
ns
ns
t_dhd
t_hen
t_den
10
5
The A Counter range is 0–31, allowing the AD6411 to be used
in the extended DECT bands, up to the following maximum
frequency:
The Least Significant Bit of the serial control word selects either
the “one-time setup” register or the operating mode register,
with the remaining 15 bits as data. Table II below details the
internal IC register mapping.
A Counter
M Counter
Frequency/MHz
31
34
1933.632
Table II. Register Mapping
Receive (Local Oscillator Frequency)
Main values are shown for a 110.592 MHz IF frequency. Values
in parentheses are for the 112.32 MHz.
Address (D0)
Function
Comments
0
1
One-Time IC Setup
IC Operating Mode
See Table III
See Table IV
DECT
Channel
A Counter
M Counter Frequency/MHz
AD6411 INITIAL SETUP
9
8
7
6
5
4
3
2
1
0
1 (0)
2 (1)
3 (2)
4 (3)
5 (4)
6 (5)
7 (6)
8 (7)
9 (8)
10 (9)
32
32
32
32
32
32
32
32
32
32
1771.200 (1769.472)
1772.928 (1771.200)
1774.656 (1772.928)
1776.384 (1774.656)
1778.112 (1776.384)
1779.840 (1778.112)
1781.568 (1779.840)
1783.296 (1781.568)
1785.024 (1783.296)
1786.752 (1785.024)
On power-up the state of the IC is not defined. A one-time setup
register must be loaded through the serial interface port, and is
selected when the LSB of the serial word is 0. After this one-
time setup, a single serial word controls operation of the IC.
Table III. One-Time IC Setup Register
D15
D14
D13
D12
D11
D10
D9
D8
X
RSB
TSB
SSB
RXM1 RXM0 TXM BSWS
Serial Interface
The IC operating modes can be controlled via the 3-wire
serial interface or via the three external control lines provided
(TX_ENAB, RX_ENAB, SYN_ENAB). The three external
control lines allow mode control of the IC if the baseband con-
troller cannot access the serial interface between slots. In either
case the 3-wire serial interface is used to program the channel
number. Detailed below is the register setup and the serial
interface operation.
D7
D6
D5
D4
D3
D2
D1
D0
CF0
CT1
CT0
DSD SFM PDS
RD
0
The serial interface consists of a 16-bit shift register and two
registers for configuration of the IC and mode control. This
allows mode control of the IC with a single 16-bit write. DATA
is the serial data input (data MSB first), CLK is the shift regis-
ter clock (positive edge trigger), EN (positive edge trigger) is the
serial interface enable. All internal register values are retained
when sections of the IC are powered down. Figure 3 shows the
timing diagram for the serial interface.
REV. 0
–7–
AD6411
CF0: Configuration Bit 0
One-Time Setup Register Bit Definitions
CF0
Function
RSB: Receive Control Line Sense Bit
0
1
Use Serial Interface for Mode Control
Use External Control Lines for Mode Control
RSB
Function
0
1
Receive Section POWER UP Active HIGH
Receive Section POWER UP Active LOW
CT1, CT0: Charge Pump Test Bits
CT1
CT0
Function
TSB: Transmit Control Line Sense Bit
0
0
1
1
0
1
0
1
Three-State Output
TSB
Function
Force Pump UP Current (Nom 1 mA)
Force Pump DOWN Current (Nom 1 mA)
Normal Operation (Driven from PFD)
0
1
Transmit Section POWER UP Active HIGH
Transmit Section POWER UP Active LOW
DSD: Disable Data Slicer
SSB: Synthesizer Control Line Sense Bit
DSD
Function
SSB
Function
0
Disable On-Chip Data Slicer. Analog Output at Pin
DEMOD_DATA
0
1
Synthesizer POWER UP Active LOW
Synthesizer POWER UP Active HIGH
1
Enable On-Chip Data Slicer. Digital Output at Pin
DEMOD_DATA
RXM1, RXM0: Divider Power Mode In Active Receive Slot
RXM1
RXM0
Function
DSD bit is configured at power-up depending on whether an
external data slicer is being used in the system. Data slicer is
disabled when the IF strip is powered down irrespective of the
status of bit DSD.
0
0
Dividers Powered Down, VCO Fly-
wheeled in Active Receive Mode
0
1
1
1
0
1
Dividers Powered Up, VCO Fly-
wheeled in Active Receive Mode
SFM: S-Field Mode
SFM
Function
Dividers Powered Up, VCO Locked
to Synthesizer in Active Receive Mode
0
1
Normal Demodulation Mode
S-Field Sampling Mode
Dividers Powered Up, VCO Locked
to Synthesizer in Active Receive Mode
PDS: Phase Detector Sense
TXM: Divider Power Mode In Active Transmit Slot
PDS
Function
TXM
Function
0
1
PFD Pumps UP when Fvco > Fref
PFD Pumps UP when Fref > Fvco
0
Dividers Powered Down, VCO Flywheeled in
Active Mode
Dividers Powered Up, VCO Flywheeled in Active
Mode
RD: Reference Divide Ratio
1
RD
Function
0
1
Reference Frequency = 10.368 MHz
Reference Frequency = 13.824 MHz
BSWS: Band Switch Sense (Control with External Lines)
BSWS
Function
0
Band Switch Output High in Receive Slot, PIN
Diode ON
1
Band Switch Output Low in Receive Slot, PIN
Diode ON
–8–
REV. 0
AD6411
CONTROLLING THE AD6411 OPERATING MODE
Table IV. Operating Mode Control Register
CHANNEL SELECTION/FREQUENCY CONTROL
The M0 and A4–A0 bits in the operating mode register control
the channel selection for the AD6411 synthesizer. The M0 bit
selects the M Counter division ratio.
D15
D14 D13 D12 D11 D10
A4 A3 A2 A1 A0
D9
D8
M0: M Counter Divide Ratio
M0
IF/RSSI RXMixer
M0
Function
0
1
M Divide Ratio 32
M Divide Ratio 34
D7
D6
D5
D4
TX
BUF VCO
D3
D2
D1
D0
DMOD DIV
CP
UHF
BSW REGS
1
The A4 through A0 bits control the A counter division ratio,
and control the channel selection. Refer to the section of this
data sheet on Synthesizer Programming for a mapping of chan-
nel frequency to synthesizer divider words.
The operating mode register, loaded through the serial port
when the LSB is “1,” allows any circuit block to be indepen-
dently powered on or off. This can be bypassed to enable mode
control of the IC via the three external control lines. Transitions
between major DECT modes can be made with a single word
program (including channel change) when using the serial inter-
face only. Table V defines the bit status for the various IC oper-
ating modes when used with the serial interface only.
A4–A0: A Counter Division Ratio
“A”
A4
A3
A2
A1
A0
0
1
2
3
–
30
31
0
0
0
0
–
1
1
0
0
0
0
–
1
1
0
0
0
0
–
1
1
0
0
1
1
–
1
1
0
1
0
1
–
0
1
Table V. Bit Status for the Different Operating Modes
Data Bits
(D9 . . . D0)
Operating
Mode Register Function
ANALOG/RF INTERFACE DETAILS
Comments
The AD6411 is an advanced 1.9 GHz radio transceiver circuit
and requires careful attention to the selection of external com-
ponents. The AD6411 is readily capable of performance that
meets the ETS-300-176-1 (formerly TBR06) DECT radio
specifications. This section of the data sheet will describe sug-
gestions for external componentry that will allow the design of a
complete DECT RF transceiver.
00 0000 0101
00 0000 0111
00 0111 1111
All Off Mode
All Circuits Off
Regulators On
Stand-By Mode
Prior to TX Slot
VCO, TX Buffer,
Dividers, Charge Pump,
Regulators Active,
VREF (1.4 V) Active
Low Noise Amplifier
00 0101 1111
00 1110 1011
Active TX Slot
Prior to RX Slot
VCO, TX Buffer, Di-
viders, Regulator
An external LNA is required to meet the RF leakage specifica-
tions in ETS-300-176-1. The following circuit, based on a Si-
emens BFP405 discrete transistor, is representative of a suitable
LNA. The SC1.89 SAW filter removes images prior to the down
converter. The filter is matched to the AD6411 input with a
printed inductor and fixed capacitor. Complete details of the
circuit, with transmission-line dimensions, can be found in
Siemens Application Note No. 020.
Circuits Active,
VREF (1.4 V) Active1
VCO2, Dividers, Charge
Pump, Regulators, De-
modulator Precharge
Circuits Active,
VREF (1.4 V) Active
100pF
+3V
11 1100 1011
Active RX Slot
RX Mixer, VCO2, Divid-
ers, Regulators, De-
modulator, Receive
Strip Circuits Active,
VREF (1.4 V) Active
10nF
100⍀
33pF
TL6
39k⍀
TL5
33pF
RF OUT
NOTES
10pF
1Alternatively it may be possible to power-down the dividers in an active trans-
mit slot depending on the effect of thermal transients on VCO pulling. In this
mode the dividers are biased but inactive. This can also be implemented when
external control lines are used with bits TXM, RXM1, RXM0.
10⍀
TL4
BFP405
TL1
22pF
RF IN
TL3
TL2
2Band switch output is determined by the status of BSW. Band switch output is
Low when BSW is high, high when BSW is low. In Table V, band switch
output is high for AcRx and PrRx slots, otherwise it is low.
Figure 4. LNA circuit
REV. 0
–9–
AD6411
UHF VCO Tank Circuit
The UHF VCO is probably the most critical part of an AD6411-
based DECT radio. The design shown in Figure 5 uses a
printed inductor, a BBY53 (or equivalent) common-cathode
dual varactor, and a PIN-diode (BAR63-03W or equivalent)
band switch to cover the DECT band. The capacitance added
to the tank circuit by the PIN-diode is needed to switch the VCO
to the DECT receive band. It is switched out of the circuit in the
transmit mode, in which the VCO is directly modulated by
baseband transmit data. With this scheme, no manufacturing
trim is needed to tune the VCO to the DECT band. Tank com-
ponent values will need slight modification to cover the “ex-
tended DECT” frequency bands. The dimensions of tank
inductor L1 will depend on the circuit board material and thick-
ness used. Contact Analog Devices for assistance on UHF tank
inductor layout.
VBAT
VBAT
AD6411
10nF
10nF
REGULATOR #1
10nF
10pF
REGULATOR #2
TO PIN 40 (VCOB)
1nF
PASS TRANSISTORS: BCW68F OR EQUIVALENT
Figure 6. Voltage Regulator Circuitry
Transmit/Receive Switching
Since the same antenna is used for both transmit and receive, a
switch consisting of PIN diodes and printed transmission lines is
used to disconnect the receive path from the antenna during
transmit periods. A suggested circuit is shown in Figure 7.
Complete details can be found in Siemens Application Note
No. 007.
VCCVCO
VCOB
2k⍀
BSW
BAR63-03W
AD6411
2pF
2k⍀ 2pF
ANT
1.2pF
L1
VCO
8.2pF
8.2pF
20k⍀
20k⍀
TX
DATA
IN
50⍀
/4
BAR63-03W
BAR80
TO RX IN
FROM PA
10k⍀
10k⍀
27nH
BAR80
10k⍀
LF
47pF
330pF
6.8pF
6.8k⍀
1nF
470pF
TX/RX
1=TX
0=RX
Figure 5. UHF VCO Circuit
Power Management
The AD6411 reduces the external components needed for
power management in a DECT radio by integrating voltage
regulators on-chip. The circuit can therefore operate directly
from a 3.0 V to 5.5 V unregulated battery supply.
Figure 7. T/R Switch
There are two regulators. The first, VS1 (Pins 20, 21 and 23),
uses an external BCW68F (or similar) PNP pass transistor to
provide a regulated 2.75 V nominal supply voltage to most of
the AD6411 circuitry. The second regulator, VS2 (Pins 41, 44,
and 45), is intended to provide the regulated voltage to the
UHF VCO section and should not be used for other circuitry.
–10–
REV. 0
AD6411
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Plastic LQFP
(ST-48)
0.362 (9.2)
0.346 (8.8)
SQ
0.280 (7.10)
0.272 (6.90)
0.063 (1.60) MAX
SQ
0.020 (0.52)
0.019 (0.48)
37
36
48
1
SEATING
PLANE
0.217
(5.50)
BSC
SQ
TOP VIEW
(PINS DOWN)
0.006 (0.15)
0.002 (0.05)
12
13
25
24
0.006 (0.15) MAX
0.011 (0.27)
0.006 (0.17)
0.0197 (0.50)
TYP
0.057 (1.45)
0.053 (1.35)
REV. 0
–11–
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