AD6426XB [ADI]
Enhanced GSM Processor; 增强型GSM处理器
| 型号： | AD6426XB |
| 厂家： | 
ADI |
| 描述： | Enhanced GSM Processor |
| 文件： | 总50页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Enhanced GSM Processor
a
Preliminary Technical Information
FEATURES
AD6426
VOICEBAND /
BASEBAND
CODEC
UNIVERSAL
Complete Single Chip GSM Processor
SYSTEM CONN.
INTERFACE
CHANNEL
CODEC
Channel Codec Subsystem including
Channel Coder/Decoder
INTERFACE
Interleaver/De-interleaver
Encryption/Decryption
TEST
INTERFACE
DSP
DISPLAY
INTERFACE
Control Processor Subsystem including
CHANNEL
EQUALIZER
16-bit Control Processor (H8/300H)
Parallel and Serial Display Interface
SIM
INTERFACE
RADIO
INTERFACE
Keypad Interface
EEPROM Interface
SPEECH
CODEC
EEPROM
ACCESSORY
INTERFACE
SIM-Interface
INTERFACE
Universal System Connector Interface
Interface to AD6425
Control of Radio Subsystem
Programmable backlight duty cycle
Real Time Clock with Alarm
CONTROL
PROCESSOR
KEYPAD /
BACKLIGHT
INTERFACE
MEMORY
INTERFACE
Battery ID Chip Interface
DSP Subsystem including
Figure 1. Functional Block Diagram
16-bit DSP with ROM coded firmware for
Full rate Speech Encoding/Decoding (GSM 06.10)
Enhanced Full Rate Speech
In addition, the EGSMP supports both A5/1 and A5/2
encryption algorithms as well as operation in non-encrypted
mode.
Encoding/Decoding (GSM 06.60)
Equalization with 16-state Viterbi (Soft Decision)
DTMF and Call Progress Tone Generation
Power Management of Mobile Radio
Slow Clocking scheme for low Idle Mode current
Ultra Low Power Design
On-chip GSM Data Services up to 14.4 kbit/s
JTAG Test Interface
2.4V to 3.3V Operating Voltage
144-Lead LQFP and 144-Lead PBGA packages
The EGSMP integrates a high performance 16-bit
microprocessor (Hitachi H8/300H), that supports all the GSM
terminal software, including Layer 1, 2 and 3 of the GSM
protocol stack, the MMI and applications software such as
data services, test and maintenance.
The use of the standard H8 processor allows the use of HIOS,
the Hitachi real time kernel, as well as a full range of software
development tools including C compilers, debuggers and in-
circuit emulators. The EGSMP also integrates a high
performance 16-bit Digital Signal Processor (DSP), which
provides speech transcoding and supports all audio functions
in both transmit and receive. In receive it equalizes the
received signal using a 16-state (Viterbi) soft decision
equalizer.
APPLICATIONS
GSM 900 / DCS1800 / PCS1900 Mobile Stations (MS)
Compliant to Phase 1 and Phase 2 specifications
GENERAL DESCRIPTION
The EGSMP interfaces with all the peripheral sub-systems of
the terminal, including the keypad, memories, display driver,
SIM, DTE and DTA data services interface and radio. It also
has a general purpose interface that can be used to support an
external connection to a car kit or battery charger.
The AD6426 Enhanced GSM Processor (EGSMP) is the
central component of the highly integrated AD20msp425 GSM
Chipset. Offering a low total chip count, low bill of materials
cost and long talk and standby times, the chipset offers
designers a straightforward route to a highly competitive
product in the GSM/DCS1800 market.
The EGSMP interfaces with the AD6425 or the AD6421
Voiceband/Baseband Codec through a dedicated serial port.
The EGSMP performs all the baseband functions of the Layer
1 processing of the GSM air interface. This includes all data
encoding and decoding processes as well as timing and radio
sub-system control functions.
ORDERING GUIDE
Model
Temperature Range
Package
AD6426XST
AD6426XB
-25°C to +85°C
-25°C to +85°C
144-Lead LQFP
144-Lead PBGA
The EGSMP supports full rate and enhanced full rate speech
traffic as well as a full range of data services including F14.4.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 1 -
Confidential Information
Preliminary Technical Information
AD6426
CLKIN
OSC13MON
OSCIN
VCTCXO
USCRI
USCRX
SYSTEM
USCTX
OSCOUT
CONNECTOR
USCCTS
USCRTS
JTAGEN
TCK
JTAG
PORT
TMS
TDI
TDO
GPIO [9:0]
GPCS
GPPWRCTL
ACCESSORY
SIMCARD
SIMDATAOP
SIMDATAIP
SIMCLK
SIMRESET
SIMPROG
SIMSUPPLY
VBC / EVBC
AD6421 / 25
SIM
CLKOUT
VBCRESET
MCLK
RESET
ASDO
ASDI
ASOFS
ASDIFS
ASDOFS
ASCLK
ASDO
EEPROMEN
EEPROMDATA
EEPROMCLK
EEPROM
ASCLK
ASDI
BACKLIGHT
KEYPAD
BACKLIGHT
ENHANCED
GSM
PROCESSOR
BSDO
BSOFS
BSCLK
BSDI
BSDI
BSDIFS
BSCLK
BSDO
KEYPADROW [5:0]
KEYPADCOL [3:0]
BSIFS
BSDOFS
FLASHPWD
ROMCS
ADD [20:0]
DATA [15:0]
AD6426
FLASH
ROM
MODE
VSDO
VSDI
VSCLK
VSFS
VSDI
VSDO
VSCLK
VSFS
RAMCS
SRAM
RD
WR
HWR
LWR
RXON
TXON
DISPLAY
LCDCTL
RXON
TXENABLE
TXPHASE
DISPLAYCS
TXPA
POWER
SUB-
SYSTEM
VDDRTC
PWRON
CALIBRATERADIO
RADIOPWRCTL
SYNTHEN0
SYNTHEN1
SYNTHDATA
SYNTHCLK
AGCA
RADIO
IRQ6
RESET
BOOTCODE
AGCB
VDD(10)
GND(10)
Figure 2. External Interfaces of the AD6426
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 2 -
Confidential Information
Preliminary Technical Information
AD6426
Table of Contents
GENERAL DESCRIPTION ...................................................1
PIN FUNCTIONALITY ( Normal Mode)...............................4
OVERVIEW..........................................................................7
FUNCTIONAL PARTITIONING...........................................7
Channel Codec Sub-System ...............................................7
Processor Sub-System........................................................8
DSP Sub-System................................................................8
Speech Transcoding .......................................................8
Equalization...................................................................8
Audio Control ................................................................8
Tone Generation ............................................................8
Automatic Frequency Control (AFC) ..............................8
Automatic Gain Control (AGC)......................................8
REGISTERS..........................................................................9
GENERAL CONTROL........................................................14
Clocks .............................................................................14
Slow Clocking .................................................................14
Real Time Clock and Alarm.............................................14
Reset ...............................................................................15
Interrupts.........................................................................15
NMI.................................................................................15
Wait ................................................................................16
Automatic Booting...........................................................16
Power Control..................................................................16
INTERFACES.....................................................................16
Memory Interface.............................................................16
EEPROM Interface ..........................................................16
SIM Interface...................................................................17
Accessory Interface ..........................................................17
Universal System Connector Interface..............................18
Operating modes of the USC............................................18
Buffered UART Mode (Booting/Data Services)................18
Keypad / Backlight / Display Interface .............................19
Battery ID Interface..........................................................20
EVBC Interface ...............................................................20
Radio Interface ................................................................22
Dual Band Control .......................................................22
Tx Timing Control .......................................................23
Rx Timing Control.......................................................24
Synthesizer Control......................................................24
AGC Control................................................................25
TEST INTERFACE .............................................................27
JTAG Port....................................................................27
Debug Port Interface ....................................................29
MODES OF OPERATION...................................................29
Normal Mode (Mode A) ..................................................29
Emulation Mode (Mode D)..............................................29
FEATURE MODES.............................................................30
DAI Mode........................................................................30
High Speed Logging.........................................................30
SPECIFICATIONS ..............................................................32
General............................................................................32
ABSOLUTE MAXIMUM RATINGS...............................32
TIMING CHARACTERISTICS............................................33
Clocks .............................................................................33
Memory Interface.............................................................34
Radio Interface ................................................................35
High Speed Logging Interface ..........................................36
Data Interface ..................................................................37
Test Interface...................................................................38
EVBC Interface ASPORT ................................................39
EVBC Interface BSPORT ................................................40
EVBC Interface VSPORT................................................41
Parallel Display Interface.................................................42
Serial Display Interface....................................................43
PACKAGING......................................................................44
LQFP Pin Locations.........................................................44
PBGA Pin Locations........................................................45
LQFP Outline Dimensions...............................................47
PBGA Outline Dimensions ..............................................48
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 3 -
Confidential Information
Preliminary Technical Information
AD6426
PIN FUNCTIONALITY ( Normal Mode)
Group
Pin Name
CLKIN
Pins
1
I/O
I
Default / Alternative Function(s) *
13 MHz Clock Input
General
RESET
IRQ6
1
I
Reset input
1
I / I
O
I
Interrupt Request # 6 / Non-Maskable Interrupt (NMI) *
13 MHz Oscillator Power Control Signal
Boot Code Enable
OSC13MON
BOOTCODE
VDD
1
1
10
10
20
1
Supply Voltage
GND
Ground
Memory
Interface
ADD19 : 0
GPO10
DATA15 : 0
RD
O
O / O
I/O
O
Processor Address Bus
General Purpose Output 10 / Address (20) *
Processor Data Bus
16
1
Processor Read Strobe
HWR
1
O
Processor High Write Strobe / Upper Byte Strobe
Processor Low Write Strobe / Lower Byte Strobe
Processor Write Strobe
LWR
1
O
WR
1
O
FLASHPWD
1
O / I /
O
FLASH Power Down / WAIT / General Purpose Output
11*
RAMCS
ROMCS
SIMCARD
1
1
1
O
O
External RAM Chip Select
External ROM Chip Select
SIM
I /
SIM Card Detect / General Purpose I/O 16 *
I/O
Interface
SIMDATAOP
SIMDATAIP
SIMCLK
1
1
1
1
1
O
I
SIM Data Output
SIM Data Input
O
O
SIM Clock
SIMRESET
SIMPROG
SIM Reset
O /
I/O
SIM Program Enable / General Purpose I/O 15 *
SIMSUPPLY
1
1
1
1
1
1
1
6
4
O
I/O
O
O
O
O
O
I
SIM Supply Enable
EEPRROM
Interface
EEPROMDATA
EEPROMCLK
EEPROMEN
EEPROM Data
EEPROM Clock / High Speed Logger Clock
EEPROM Enable / High Speed Logger Frame Sync
Display Controller Chip Select / Chip Enable
LCD Control / Serial Display Data Output
Backlight Control
Display /
Backlight /
Keypad
DISPLAYCS
LCDCTL
BACKLIGHT
KEYPADROW5 : 0
KEYPADCOL3 : 0
Interface
Keypad Row Inputs
O
Keypad Column Strobes (open drain, pull low)
* Note: Functionality of these pins can be changed under software control.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 4 -
Confidential Information
Preliminary Technical Information
AD6426
Pin Functionality ( NORMAL MODE)
Group
Pin Name
CLKOUT
EVBCRESET
ASDO
Pins
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O
O
Default / Alternative Function(s) *
Clock Output to EVBC
EVBC Interface
O
EVBC Reset Output (also for Display reset)
EVBC Auxiliary Serial Port Data Output
ASPORT
BSPORT
O
ASOFS
O
EVBC Auxiliary Serial Port Output Framing Signal
EVBC Auxiliary Serial Port Clock Output
EVBC Auxiliary Serial Port Data Input
EVBC Baseband Serial Port Data Output
EVBC Baseband Serial Port Output Framing Signal
EVBC Baseband Serial Port Clock Input
EVBC Baseband Serial Port Data Input
EVBC Baseband Serial Port Input Framing Signal
EVBC Voiceband Serial Port Data Output
EVBC Voiceband Serial Port Data Input
EVBC Voiceband Serial Port Clock Input
EVBC Voiceband Serial Port Framing Signal
Receiver On
ASCLK
O
ASDI
I
BSDO
O
BSOFS
O
BSCLK
I
BSDI
I
BSIFS
I
VSPORT
VSDO
O
VSDI
I
VSCLK
I
VSFS
I
Radio Interface
RXON
O
TXPHASE
TXENABLE
TXPA
O
Switches between Rx and Tx
O
Transmit Enable / General Purpose Output 14 *
Power Amplifier Enable / General Purpose Output 12 *
Radio Calibration / General Purpose Output 13 *
Radio Power-Down Control
O / O
O / O
O
CALIBRATERADIO
RADIOPWRCTL
SYNTHEN0
SYNTHEN1
SYNTHDATA
SYNTHCLK
AGCA
O
Synthesizer 1 Enable
O
Synthesizer 2 Enable / General Purpose Output 17 *
RF Serial Port Data
O
O
RF Serial Port Clock
O
AGC Gain Select / General Purpose Output 18
AGC Gain Select / General Purpose Output 19
USC Ring Indicator / Serial Clock / GPO20
USC Receive Data
AGCB
O
Universal
System
USCRI
1/O
I
USCRX
Connector
Interface
USCTX
O
USC Transmit Data / Baseband Serial Port Data Input
USC Clear to Send / Serial Frame Sync / GPI22
USC Ready to Send / GPO21
USCCTS
USCRTS
I/O
O
* Note: Functionality of these pins can be changed under software control.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 5 -
Confidential Information
Preliminary Technical Information
AD6426
Pin Functionality ( NORMAL MODE)
Group
Pin Name
GPIO0
Pins
I/O
I/O
I/O
Default / Alternative Function(s) *
Accessory
Interface
1
1
General Purpose Inputs/Output 0
GPIO1
General Purpose Inputs/Output 1 / Radio BANDSELECT1
*
GPIO2
GPIO3
GPIO4
1
1
1
I/O
I/O
I/O
General Purpose Inputs/Output 2 / Radio BANDSELECT0
*
General Purpose Inputs/Outputs 3 / Serial Display Address
Output *
General Purpose Inputs/Outputs 4 / Serial Display Clock
Output *
GPIO5
GPIO6
GPIO7
GPIO8
1
1
1
1
I/O
I/O
I/O
I/O
General Purpose Inputs/Outputs 5 / Battery ID Interface *
General Purpose Inputs/Output 6 / VBIAS *
General Purpose Inputs/Output 7 / Antenna Select *
General Purpose Inputs/Output 8 / DEBUG UART
Transmit Data *
GPIO9
1
I/O
General Purpose Inputs/Output 9 / DEBUG UART
Receive Data *
GPCS
1
1
1
1
1
1
1
1
1
1
O
I
General Purpose Chip Select
Real Time
Clock
OSCIN
OSCOUT
VDDRTC
PWRON
JTAGEN
TCK
32.768 kHz Crystal Input
O
32.768 kHz Oscillator Output and Feedback to Crystal
RTC Supply Voltage
Interface
O
I
Power ON/OFF Control
Test Interface
JTAG Enable
I
JTAG Test Clock / HSL Data 0
TMS
I
JTAG Test Mode Select / HSL Data 1 / DAI Reset
JTAG Test Data Input / HSL Data 3 / DAI Data 1
JTAG Test Data Output / HSL Data 2 / DAI Data 0
TDI
I
TDO
O
* Note: Functionality of these pins can be changed under software control.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 6 -
Confidential Information
Preliminary Technical Information
AD6426
OVERVIEW
ENCODE
INTERLEAVE
ENCRYPT
The GSM air interface has been formulated to provide high
quality digital mobile communication. As well as supporting
the traffic channels (speech and/or data), the air interface
specifies a number of signaling channels that are used for call
set up and communications between the network infrastructure
and the mobile. These signaling channels provide the mobile
specific features such as handover, as well as a number of
other intelligent features.
DSP
INTERFACE
VBC
INTERFACE
DECRYPT
DECODE
DEINTERLEAVE
The GSM system closely follows the OSI 7-layer model for
communications. Specifically, GSM defines Layers 1, 2 and 3
of the protocols. The lowest level being Layer 1, or the
Physical Layer. It is this part of the network processing for
which the EGSMP is responsible, performing some of the
Layer 1 functions in dedicated hardware for minimum power
consumption and some in software for increased flexibility.
TEST
INTERFACE
REGISTERS
H8
RADIO / SYNTHESIZER
TIMING AND CONTROL
INTERFACE
Figure 3. Channel Codec Subsystem
The transmit and receive functions of the Channel Codec are
timed by an internal timebase that maintains accurate timing
of all sub-systems. This timebase is aligned with the on-air
receive signal and all system control signals, both internal and
external, are derived from it.
Layer 1 covers those signal processing functions required to
format the speech/data for transmission on the physical
medium. Data must be structured to allow for identification,
recovery and error correction so that the information can be
supplied error free to the layer 2 sub-systems and to the traffic
sources. In addition, the physical layer processing includes the
timing of both transmit and receive data, the encryption of
data for security purposes and the control of the Radio sub-
system to provide timing and to optimize the radio frequency
characteristics. An object code license to Layer 1 software is
supplied with the AD20msp425 chipset.
The physical layer processing can be divided into 4 phases,
two each for up- and downlink. The data in the transmit path
undergoes an ENCODE phase and then a TRANSMIT phase.
Similarly, data in the downlink path is termed the receive data
and it undergoes a RECEIVE phase followed by a DECODE
phase. The buffer between the ENCODE and TRANSMIT
functions is the INTERLEAVE module that holds the data and
permits the building of the transmit burst structure. Similarly
the DEINTERLEAVE module forms the buffer between the
RECEIVE and the DECODE processes.
FUNCTIONAL PARTITIONING
This datasheet gives only an overview about the functionality
of the EGSMP. The EGSMP consists of three main elements;
the Channel Codec and the Control Processor Sub-System
including several interfaces and the DSP as shown in Figure
1. The Channel Codec is responsible for the Layer 1 channel
coding and decoding of traffic and control information. The
Processor Sub-system supports the software functions of the
protocol stack and interfaces with the bus peripheral sub-
systems of the terminal. The DSP performs the channel
equalization and speech transcoding.
Each of these four phases is controlled explicitly by the
Control Processor via control registers that define the mode of
operation of each sub-module and the data source they should
process. Typically these control values are updated every
TDMA frame in response to interrupts from the internal
timebase.
The ENCODE process involves the incorporation of error
protection codes. All data is sourced in packets and two forms
of error coding applied; block coding (parity or Fire code) and
convolution coding. The resultant data block is then written to
the INTERLEAVE module where it is buffered in a RAM.
Data is read from the interleave buffer memories contiguously
but written in non-contiguous manner, thereby implementing
the interleaving function. The TRANSMIT process uses a
different time structure now associated with the on-air TDMA
structure. The data is read from the INTERLEAVE module
and formatted into bursts with the requisite timing. This
involves adding fixed patterns such as the tail bits and training
sequence code. The resultant burst is written to the external
Baseband Converter where the modulation is performed and
the output timed to the system timebase before transmission.
Channel Codec Sub-System
The Channel Codec processes data from two principal sources;
traffic and signaling. The former is normally continuous and
the latter determined on demand. Traffic comes in two forms;
speech and user data. The various traffic sources and the
signaling sources are all processed differently at the physical
layer. Speech traffic data is supplied by the speech transcoder
and the remaining data types are sourced from the Control
Processor and interfaced via a dedicated data interface. The
Channel Codec subsystem functional block diagram is shown
in Figure 3.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 7 -
Confidential Information
Preliminary Technical Information
AD6426
A feature of the GSM system is the application, as part of the
TRANSMIT process, of data encryption for the purpose of link
security. After the INTERLEAVE module the data may be
encrypted using the prescribed A5/1 or A5/2 encryption
algorithm.
Alternatively the DSP receives encoded speech data from the
channel codec sub-system including the Bad Frame Indicator
(BFI). The Speech decoder supports a Comfort Noise Insertion
(CNI) function that inserts a predefined silence descriptor into
the decoding process. The resulting data, at 104 kbit/s, is
transferred to the EVBC.
The RECEIVE function requires unmodulated baseband data
from the equalizer. As necessary the data is decrypted and
written to the DEINTERLEAVE module. This is conducted at
TDMA frame rate, although precise timing is not necessary at
this stage.
Equalization
The Equalizer recovers and demodulates the received signal
and establishes local timing and frequency references for the
mobile terminal as well as RSSI calculation. The equalization
algorithm is a version of the Maximum Likelihood Sequence
Estimation (MLSE) using the Viterbi algorithm. Two
confidence bits per symbol provide additional information
about the accuracy of each decision to the channel codec’s
convolutional decoder. The equalizer outputs a sequence of
bits including the confidence bits to the channel codec sub-
system.
The DECODING process reads data from the
DEINTERLEAVE module, inverting the interleave algorithm
and decodes the error control codes, correcting and flagging
errors as appropriate. The data also includes a measure of
confidence expressed as two additional bits per received
symbol. These are used in the convolution decoder to improve
the error decoding performance. The resultant data is then
presented to the original sources as determined by the control
programming. The Channel Codec interfaces with the speech
transcoder for speech traffic data and with an equalizer for
recovered receive data. In the AD6426 the equalizer and
speech transcoder are implemented in the DSP.
Audio Control
The DSP subsystem is also responsible for the control of the
audio path. The EVBC provides two audio inputs and two
audio outputs, as well as a separate buzzer output, which are
switched and controlled by the DSP. Furthermore the EVBC
provides for variable gain and sensitivity which is also
controlled by the DSP under command of the Layer 1
software.
Processor Sub-System
The Processor Sub-System consists of a high performance 16-
bit microcontroller together with a selection of peripheral
elements. The processor is a version of the Hitachi H8/300H
that has been developed to support GSM applications and
which is well suited to support the Protocol Stack and
Application Layer software.
Tone Generation
All alert signals are generated by the DSP and output to the
EVBC. These alerts can be used for the buzzer or for the
earpiece. The tones used for alert signals can be fully defined
by the user by means of a description which provides all the
parameters required such as frequency content and duration of
components of the tone. The tone descriptions are provided by
the Layer 1 software.
DSP Sub-System
The DSP Sub-System consists of a high performance 16-bit
digital signal processor (DSP) with integrated RAM and ROM
memories. The DSP performs two major tasks: speech
transcoding and channel equalization. Additionally several
support functions are performed by the DSP. The instruction
code, which advises the DSP to perform these tasks, is stored
in the internal ROM. The DSP sub-system is completely self-
contained, no external memory or user-programming is
necessary.
Automatic Frequency Control (AFC)
The detection of the frequency correction burst provides the
frequency offset between the mobile terminal and the received
signal. This measure is supplied to the Layer 1 software which
then requests a correction of the master clock oscillator
frequency via the AFC-DAC in the EVBC. In order to do so
the Layer 1 software includes a transfer function for the
oscillator frequency against the voltage applied. The DSP
provides the measurements for the AFC.
Speech Transcoding
In Full Rate mode the DSP receives the speech data stream
from the EVBC and encodes the data from 104 kbit/s to 13
kbit/s. The algorithm used is Regular Pulse Excitation, with
Long Term Prediction (RPE-LTP) as specified in the 06-series
GSM Recommendations.
Automatic Gain Control (AGC)
The DSP is also responsible for making measurements of the
power in the received signal. This is used for a number of
functions including RSSI measurement, adjacent channel
monitoring and AGC. The Layer 1 software passes the
requested gain level to the DSP, which then analyzes the
received signal and generates an AGC control signal.
Depending on the radio architecture, this control signal will be
used in digital form or, converted by the AD6425 in analog
form.
In Enhanced Full Rate mode, the DSP encodes the 104 kbit/s
speech data into 12.2 kbit/s (speech) +0.8 kbit/s (CRC and
repetition bits) as additionally specified in the Phase 2 version
of the 06-series GSM Recommendations. In both modes, the
DSP also performs the appropriate voice activity detection and
discontinuous transmission (VAD/DTX) functions.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 8 -
Confidential Information
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AD6426
REGISTERS
Address Name
The AD6426 contains 88 Channel Codec Control Registers, 69
H8 Peripheral Registers mapped into the Channel Codec
address space starting at 8000h. All registers are normally
accessed by the Layer 1 software provided with the
AD20msp425 chipset. The user is not expected to read or
write to any registers other than through the Layer 1 software.
Therefore only a limited description of these registers is given
here to ease the understanding of the functional behavior of
the AD6426. Only registers which can be modified or
monitored by the user under control of the Layer 1 software
are shown. The Channel Codec Control Registers are listed in
Table 1, and the H8 Peripheral Control Registers in Table 3
72 48 H
73 49 H
74 4A H
75 4B H
76 4C H
77 4D H
78 4E H
79 4F H
88 58 H
SYNTHESIZER PROGRAM
R/W
R/W
R/W
R/W
R/W
R/W
RMW
R/W
R/W
TXPA OFFSET 1
TXPA OFFSET 2
TXPA WIDTH 1
TXPA WIDTH 2
IRQ ENABLE
IRQ LATCH
CC GPIO
ccGPO
A description of the Channel Codec Control Register contents
is shown in Table 2, and of the H8 Peripheral Registers in
Table 4.
Table 1. CC Control Registers
Address Name
0
2
4
5
6
7
8
9
00 H
02 H
04 H
05 H
06 H
07 H
08 H
09 H
SYSTEM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RD
RADIO CONTROL
BSIC
TSC
TRAFFIC MODE
DAI
EEPROM
KEYPAD COLUMN
KEYPAD ROW
EVBC SERIAL 1
EVBC SERIAL 2
EVBC IF CONTROL
RESET
10 0A H
28 1C H
29 1D H
30 1E H
35 23 H
37 25 H
38 26 H
39 27 H
40 28 H
41 29 H
42 2A H
43 2B H
44 2C H
45 2D H
46 2E H
47 2F H
48 30 H
49 31 H
50 32 H
51 33 H
RMW
RMW
R/W
R/W
R/W
R/W
RMW
WR
SYNTH BIT COUNT
SYNTH CONTROL
ERROR COUNT
SYNTHESIZER 1
SYNTHESIZER 2
SYNTHESIZER 3
SYNTHESIZER 4
POWER CONTROL INT
POWER CONTROL EXTERNAL
SWRESET 1
WR
WR
WR
R/W
R/W
R/W
R/W
R/W
R/W
WR
SWRESET 2
INTERRUPT COUNTER
BBC TX ADDRESS
BACKLIGHT
VERSION CONTROL
RD
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
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AD6426
Table 2. CC Control Register Contents
#
7
6
5
4
3
2
1
0
0
Autocalibrate
Backlight 1
Test Data Enable Calibrate Radio Encryption Type Encrypt Key Load
Tx Monitor
Enable
Tx Phase
Polarity
Rx Radio Control Tx Radio Control
Polarity Polarity
Tx PHASE
Enable
Monitor
Enable
Receive
Enable
Transmit
Enable
2
4
5
Base Station Identity Code
Training Sequence Code
TxPA
Polarity
INT COUNT[8]
BAND ENABLE
OCE OVERRIDE Interrupt Counter Autocalibration
Traffic Frame
Enable
Decryption
Enable
Encryption
Enable
6
7
8
Override
Type
NMI Select
GPO10 Data
GPO10 Select
Data Ser. Select
DAIRESET
EEPROM Data
Output Enable
EERPOM
Clock
EEPROM
Enable
EERPOM
Data
9
Keypad Column
10
28
29
30
35
Keypad Row
EVBC Serial Port ( 15 : 8 )
EVBC Serial Port ( 7 : 0 )
Tx Data Delay
EVBC Rx-Buff. full EVBC Tx-Buf.empty
CC Reset
EVBC Reset
DSP Reset
Isolate
Synthesizer
Config. Dynam.
Synthesizer
Synthesizer
Interface active
37
38
Synthesizer Bit Count
Synthesizer
Enable Polarity
Synthesizer
Enable Type
Synthesizer
Clock Polarity
Synthesizer
Load Dynamic 1
Synthesizer
Load Dynamic 2
Synthesizer
Clock
39
40
41
42
43
Error Count
Synthesizer (31: 24)
Synthesizer (23: 16)
Synthesizer (15: 8)
Synthesizer (7: 0)
Synth. Interface
Power Enable
DSP Interface
Power Enable
Encryption Power
Enable
44
45
46
47
Backlight Duty Cycle
Coprocessor
Power Control
Output Clock
Enable
GP Power
Control
DSP Power
Control
Radio Power
Control
Encryption
SW-Reset
EVBC Interface
SW-Reset
DSP Interface
SW-Reset
Synthes. Interface
SW-Reset
INT CNT RST
Decode
SW-Reset
Deinterleave
SW-Reset
interleave
SW-Reset
Encode
SW-Reset
48
49
50
51
72
73
74
75
76
77
78
79
88
Interrupt Counter
EVBC Read
EVBC Tx Address
Version
Modulate 1
Backlight LED Control
Disable Synth.1
Disable Synth. 0 Synt. Enable Sel.
Synt. Mode
Pin Mode
TD ( 9 : 8 )
TD ( 7 : 0 )
TW ( 9 : 8 )
TW ( 7 : 0 )
GPO11 Data
GPO11 Select
IRQ5 Enable
IRQ5 active
GPIO9 OP En
GPO18 Sel
IRQ4 Enable
IRQ4 active
IRQ3 Enable
IRQ3 active
IRQ2 Enable
IRQ2 active
FLASHPWD dis.
NMI Edge Pol.
GPIO8 OP En
GPIO9 Data
GPIO8 Data
GPO17 Sel
GPO19 Sel
GPO19
GPO18
GPO17
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
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Preliminary Technical Information
AD6426
Address
Name
Table 3. H8 Peripheral Control Registers
64/65
8040/1h
DISPDDR
W
Address
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8010h
8010h
8010h
8011h
8011h
8012h
8012h
8013h
8014h
8015h
8016h
8017h
8018h
8018h
8019H
801AH
801BH
801CH
801Dh
8020h
8020h
8020h
8021h
8021h
8022h
8023h
8024h
8025h
8026h
8027h
8030h
8031h
8032h
8033h
8034h
8035h
Name
66
67
8042h
8043h
8044h
8045h
8048h
8050h
8051h
8052h
8054h
8055h
8060h
8061h
8062h
8063h
8064h
8065h
8066h
8067h
8068h
8069h
8074h
DISPCR
DDOR
R/W
W
0
SMSMR
R/W
R/W
R/W
W
1
SMBRR
SMSCR
68
DDIR
R
2
69
DRR
R/W
W
3
SMDR
72
WDTR
4
SMSSR
R/W
R
80
MEM IF
PERST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
5
SMDR
81
6
SMSCMR
BUFRBR
BUFTHR
BUFDLL
BUFIER
BUFDLM
BUFIIR
R/W
R
82
PERCR
10
10
10
11
11
12
12
13
14
15
16
17
18
18
19
26
27
28
29
32
32
32
33
33
34
35
36
37
38
39
48
49
50
51
52
53
84
TAR
W
85
PERCLK
RTCTR1
RTCTR2
RTCTR3
RTCTR4
RTCTR5
RTCAR1
RTCAR2
RTCAR3
RTCCR
RTCSRZ
SERDISPLAY/NMI
R/W
R/W
R/W
R
96
97
98
99
BUFFCR
BUFLCR
BUFMCR
BUFLSR
BUFMSR
BUFSCR
UIBRBR
UIBTHR
UIBSSR
UIBER
W
100
101
102
103
104
105
106
R/W
R/W
R/W
R/W
R/W
R
W
R/W
R
UIBTSR
UIBTLR
UIBBLR
FIXRBR
FIXTHR
FIXDLL
FIXIER
R
R/W
R
R
W
R/W
R/W
R/W
R
FIXDLM
FIXIIR
FIXLCR
FIXMCR
FIXLSR
FIXMSR
FIXSCR
SCCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
SPSSR
SDIR1 (MS)
SDIR0 (LS)
SDOR1 (MS)
SDOR0 (LS)
R
W
W
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 11 -
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Preliminary Technical Information
AD6426
Table 4. H8 Peripheral Register Contents
#
7
6
5
4
3
2
1
0
0
ODD
1
BRR[3:0]
2
TIE
RIE
TE
RE
AE
DATEN
CLKPOL
CLKEN
3
Transmit[7:0]
ERS
4
TDRE
RDRF
ORER
PER
TEND
5
Receive[7:0]
6
10
10
10
11
11
12
12
13
14
15
16
17
18
18
19
26
27
28
29
32
32
32
33
33
34
35
36
37
38
39
48
RxData[7:0]
TxData[7:0]
BRR[7:0]
EDSSI
ELSI
ETBEI
ERBFI
BRR[15:8]
FIFO ST
FIFO ST
InterruptID[2:0]
TX FIFO
Stop Bits
Out1
Int Pend
RxLevel[1:0]
DMA
Parity EN
Out2
RX FIFO
FIFO EN
DLAB
SET BRK
Stick Par.
Ev. Parity
Loop
WLS[1:0]
RTS
DTR
Error Rx FIFO
DCD
TEMT
RI
THRE
DSR
Break Interrupt
CTS
Framing Error
DDCD
Parity Error
TERI
Overrun Error Data Ready
DDSR
DCTS
SCR[7:0]
RxData[7:0]
TxData[7:0]
MRESET
PE
UIB Enable
BI
PROC
OE
TE
RE
FE
MODEM
TX Level
RX Time
RX Level
Tx Trigger Level [3:0]
Chars in TX Buffer [3:0]
Rx Trigger Level [3:0]
Chars in Rx Buffer [3:0]
RxData[7:0]
TxData[7:0]
BRR[7:0]
EDSSI
ELSI
ETBEI
ERBFI
BRR[15:8]
FIFO ST
DLAB
FIFO ST
InterruptID[2:0]
Parity EN
Out2
Int Pend
Stop Bits
Out1
R
SET BRK
Stick Par.
Ev. Parity
Loop
WLS[1:0]
RTS
R/W
DTR
Error Rx FIFO
DCD
TEMT
RI
THRE
DSR
Break Interrupt
CTS
Framing Error
DDCD
Parity Error
TERI
Overrun Error Data Ready
DDSR
DCTS
SCR[7:0]
TX ENABLE
TEST
RX MODE
SDORIE
CLOCK
CROSSPOINT
SWITCH
UCONN
SWITCH
R/W
49
50
SDIROE IE
SDIRIE
SDOR EMT
SDIR OE
SDIR FULL
Receive[15:8]
Receive[7:0]
Transmit[15:8]
Transmit[7:0]
Data[7:0]
51
52
53
64/65
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
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Preliminary Technical Information
AD6426
H8 Peripheral Register Contents (Continued)
#
7
6
5
4
3
2
1
0
66
67
SDISP POL
DISP CLKEN
CLK FREQ
DDREMT
Transmit Data [7:0]
Receive Data [7:0]
Reset Data [7:0]
WDT[7:0]
68
69
72
80
TEST CLK
WDT INT
WDT IE
Unused
RTC INT
RTC IE
Unused
KEYINT
KEY IE
UART SEL
DALLAS INT
DALLAS IE
DALLAS EN
RAM SEL7
UA INT
UA IE
DISP
SSINT
SS IE
SRAM16
MONINT
MONIE
81
FA INT
FA IE
82
84
Test Key[7:0]
BUCLK EN
TR[1]
85
USCCLK EN
FUCLK EN
DSPPLL[2:0]
96
97
TR[2]
TR[3]
TR[4]
TR[5]
AR[1]
AR[2]
AR[3]
98
99
100
101
102
103
104
105
106
TIMWEN
TIMER
ALAWEN
ALARM
PWRUEN
AGCENN
APWRUP
FBENN
Unused
Unused
INTEN
INT
OSCFAIL
32K PRESENT TESTOUT
TXENABLE SERDISP MODE
NMI
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
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Preliminary Technical Information
AD6426
under all circumstances. The active-high OSC13MON output
is prevented from becoming inactive if the 32.768kHz signal is
not present. The following table describes the functionality of
the relevant pins.
GENERAL CONTROL
Clocks
Clock Input
The AD6426 requires a single 13 MHz, low level clock signal,
which has to be provided at the pin CLKIN. For proper
operation a signal level of 250 mVPP minimum is required.
This feature eases system design and reduces the need for
external clock buffering. Only minimal external components
are required as shown in Figure 4.
Name
I/O Function
OSCIN
I
32.768kHz Crystal Input
OSCOUT
O
32.768kHz Oscillator
Output
OSC13MON
PWRON
O
O
13 MHz Oscillator Power
Control
The internal clock buffer can accept any regular waveform as
long as it can find voltage points in the signal, for which a
50% duty cycle can be determined. This condition is met for
sinewaves, triangles, or slew-limited square waves. Dedicated
circuitry searches for these points and generates the respective
bias voltage internally.
Power ON/OFF Control
The following table lists the recommended specification for a
32kHz crystal.
The external capacitor (1nF) decouples the bias voltage of the
clock signal generated by the oscillator from the internally
generated bias voltage of the clock buffer circuitry.
Parameter
Min
Typ
Max
Units
ESR
50
2
kW
pF
pF
°C
Shunt Capacitance
Load Capacitance
The LC-filter shown is optional. It ensures, that the input
signal is “well behaved” and sinusoidal. Additionally it filters
out harmonics and noise, that may be on top of the pure 13
MHz signal.
6
12.5
25
30
Turnover
Temperature (To)
Optional
13 MHz Filter
Parabolic Curvature
Constant (K)
0.040
ppm/°C
2.2 mH
1nF
13 MHz
VCTCXO
OUT
CLKIN
AD6422
Real Time Clock and Alarm
68 pF
The AD6426 provides a simple Real Time Clock (RTC) using
the 32.768kHz clock input. A 40 bit counter allows for more
than one year of resolution. The RTC module contains a
32.768kHz on chip oscillator buffer designed for very low
power consumption and a set of registers for a timer, alarm,
control and status functions.
Figure 4. Clock Input Circuitry
Clock Output
The input clock drives both the H8 and the Channel Codec
directly. A gated version, controlled by the Output Clock
Enable flag in CC Control Register 45, drives the CLKOUT
pin of the EVBC interface. The stand-by state of CLKOUT is
logic zero. The CLKOUT output will be active on reset.
The RTC circuit is supplied by two sources; a VDDRTC
supply pin and the main system VDD. It is the handset
designer’s responsibility to provide suitable switching
between the main system VDD and a backup supply to ensure
the RTC module is permanently powered.
Slow Clocking
To reduce power consumption of AD20msp425 solutions, a
new slow clocking scheme has been designed into the
AD6426. This scheme allows the VCTCXO to be powered
down between paging blocks during Idle Mode and for a
32.768kHz oscillator to keep the time reference during this
period. Only a common 32.768kHz watch crystal is required to
take advantage of this scheme. As in previous generations,
power consumption is also kept to a minimum using
asynchronous design techniques and by stopping all
unnecessary clocks.
The VDDRTC pin is intended to interface to a backup battery
circuit or charge holding network in order for the RTC to
maintain timing accuracy when the main battery is removed
and the handset is powered down.
The user can set an alarm time at which the handset powers
up. If an alarm time is set, the current time matches the alarm
time, and the power on alarm feature is enabled, the handset is
powered up by asserting the PWRON pin for a period of
approximately 2 seconds.
Layer 1 software and logic built into the AD6426 are
responsible for maintaining synchronization and calibration of
the slow clock and ensure the validity of the time reference
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
The VDDRTC was designed to interface with either a:
The H8 fetches its program start vector from location 0x0000
in segment zero. This can either be from external ROM or
internal Boot ROM, depending on the status of the
BOOTCODE pin.
·
·
Lithium Battery or
Capacitor in the range of 0.4F (maximum for ~24 hours
standby) to 8mF (~30 minutes standby)
Interrupts
Reset
The interrupts are controlled by the two CC Control Registers
77 and 78. These registers only apply to Emulation Mode, in
that they define which of the interrupts are able to assert
CCIRQ2.
The AD6426 is reset by setting the RESET pin to GND. This
will reset the H8-processor, the Channel Codec, the internal
DSP as well as the LCD controller interface and Boot ROM
logic. Both the DSP and the Channel Codec will be held in
reset until the RESET register is written to by the H8. At least
50 CLKIN cycles must elapse before deasserting the RESET
pin and at least a further 100 cycles before writing to the
RESET register.
Bit IRQ ENABLE CC Control Register 77
5
4
3
2
IRQ 5 Enable
IRQ 4 Enable
IRQ 3 Enable
IRQ 2 Enable
For reset at power up, the DSP must be held in reset for at
least 2000 clock cycles to enable the internal PLL to lock.
The RESET CC Control Register 35 contains the following
flags:
Bit IRQ LATCH CC Control Register 78
5
4
3
2
IRQ 5 active
IRQ 4 active
IRQ 3 active
IRQ 2 active
Bit Function
3
2
0
EVBC Reset
DSP Reset
Channel Codec Reset
NMI
Additionally 8 functional modules can be reset under control
of the two SWRESET registers:
The non-maskable interrupt NMI input of the H8 processor is
multiplexed with the IRQ6 pin. IRQ6 is the default function,
though asserting the NMI Select flag in CC Control Register 7
will select the NMI function. When not selected, NMI will be
tied off high internally, though it remains driven by the JTAG
port for test purposes. The signal is programmable to be edge
or level sensitive. It defaults to falling edge. The edge polarity
can be changed by programming the H8. However, if
FLASHPWD is used then the same setting must be applied to
CC Control Register 77. The default of zero implies falling
edge sensitive. This way NMI going active can correctly de-
assert FLASHPWD. The NMI can be used for test purposes or
user defined features. NMI is capable of bringing the control
processor out of software standby mode and therefore suitable
for functions such as alarm inputs, power management etc.
During manufacture the NMI can be used to trigger special
test code.
Bit SWRESET 1 CC Control Register 46
3
2
1
0
Encryption Software Reset
EVBC Interface Software Reset
DSP Interface Software Reset
Synthesizer Interface Software Reset
Bit SWRESET 2 CC Control Register 47
3
2
1
0
Decode Software Reset
Deinterleave Software Reset
Interleave Software Reset
Encode Software Reset
In addition NMI can be generated internally thus freeing up
the IRQ6 PIN. In this mode the TXENABLE NMI will occur
on the rising edge of the TXENABLE as seen at the pin. The
H8 should be set up for a negative edge NMI in this case.
Setting bit 5 in the SERDISPLAY/NMI H8 Peripheral Control
Register 106 to a ONE enables the TXENABLE NMI.
However, the Layer 1 Software must program the external INT
pin to INT6 before the register bit is set.
The JTAG circuitry is reset by a power-on reset mechanism.
Further resets must be done by asserting the TMS input high
for at least five TCK clock cycles. When JTAG compliance is
re-enabled, the JTAG is reset forcing the AD6426 into its
normal mode of operation, selecting the BYPASS register by
default.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
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AD6426
Memory Interface
Wait
The memory interface of the AD6426 serves two purposes.
Primarily, it provides the data, address, and control lines for
the external memories (RAM and ROM / FLASH Memory).
Secondly, the data and address lines are used to interface with
the display. The pins of the memory interface are listed in
Table 5.
The H8 microprocessor WAIT input signal can be controlled
externally by programming the FLASHPWD pin to switch to
the WAIT input function. Setting the flag FLASHPWD Disable
in CC Control Register 77 to 1 and GPO11 Select to 0,
transforms the FLASHPWD output pin into a WAIT input pin.
External devices driving WAIT must drive high on reset and
until the software has changed the FLASHPWD pin to the
WAIT function.
Table 5. Memory Interface
Name
I/O Function
Address bus
I/O Data bus
Automatic Booting
ADD20 : 0
DATA15:0
RD
O
To allow download of FLASH memory code into the final
system, the AD6426 provides a small dedicated routine to
transfer code through the Data Interface into the FLASH
memory. This routine is activated by asserting the
BOOTCODE pin.
O
O
Read strobe
HWR
High write strobe / Upper
Byte Strobe
LWR
O
Low write strobe / Lower
Byte Strobe
Power Control
The AD6426 and Layer 1 software is optimized to minimize
the mobile radio power consumption in all modes of operation.
Two power control registers are dedicated for activating and
deactivating functional modules:
WR
O
O
O
O
Write Strobe
RAMCS
ROMCS
FLASHPWD
RAM chip select
FLASH / ROM chip select
FLASH Powerdown
Bit POWER CONTROL INTERNAL CC Control
Register 44
The HWR and LWR pins can be configured to function as
UBS and LBS, respectively, by setting the SRAM16 bit (bit 0)
of the MEMIF H8 Peripheral Control Register 80. This bit is
reset at power-up. When configured as UBS and LBS, these
pins facilitate access of 16-bit SRAM in conjunction with the
Read/Write Strobes.
2
1
0
Synthesizer Interface Power Enable
DSP Interface Power Enable
Encryption Power Enable
Bit POWER CONTROL EXTERNAL CC Control
Register 45
The pin FLASHPWD is automatically asserted low when the
H8 enters the Software Standby Mode, and de-asserted when
an interrupt causes the H8 to exit the Software Standby Mode.
This allows the use of “deep power down mode” for certain
FLASH memories. Also the entire data bus is driven low
during software standby mode.
5
4
2
1
Output Clock Enable (will reset to 1)
General Purpose Power Control
DSP Power Control
Radio Power Control
EEPROM Interface
The AD6426 provides a 3-wire interface to an external
EEPROM by using three GPIOs of the control processor.
Table 6 shows the functionality of these three pins.
INTERFACES
The GSM Processor provides eleven external interfaces for
dedicated purposes:
Table 6. EEPROM Interface
1. Memory Interface
2. EEPROM Interface
3. SIM Interface
Name
I/O Function
4. Accessory Interface
EEPROMDATA
EEPROMCLK
EEPROMEN
I/O EEPROM data
5. Universal System Connector Interface
6. Keypad / Backlight / Display Interface
7. Battery ID Interface
O
O
EEPROM clock
EEPROM enable
8. Voiceband/Baseband Converter (EVBC)
Interface
9. Radio Interface
10. Test Interface
11. Debug Interface
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
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AD6426
The EEPROM interface is controlled entirely through software
via the EEPROM register. This allows support for every
desired timing and protocol.
reflects the input pin state when read and writing to GPIOn
Data has no effect.
When the GPIOn OP Enable flag is set to 1, the GPIOn Data
flag returns when read the last value written to it and controls
the GPIOn pin when written to it.
Bit EEPROM CC Control Register 8
4
EEPROM Data Output Enable
when set to 1, the content of bit 0 will be written to
the pin.
Additional general purpose inputs and outputs are available
under software control. The following pins shown in Table 9
become general purpose inputs/outputs or outputs.
2
1
0
EEPROM Clock
Connected to the EEPROMCLK pin
Table 9. Additional GPIO / GPO Pins
EEPROM Enable
Connected to the EEPROMENABLE pin
Pin Name
I/O New Function
SIMCARD
SIMPROG
ADD20
I/O GPIO16
I/O GPIO15
EEPROM Data
Connected to the EEPROMDATA pin
O
O
O
O
O
O
O
O
O
O
I
GPO10
GPO11
GPO12
GPO13
GPO14
GPO17
GPO18
GPO19
GPO20
GPO21
GPI22
SIM Interface
FLASHPWD
TXPA
The AD6426 allows direct interfacing to the SIM card via a
dedicated SIM interface. This interface consists of 7 pins as
shown in Table 7. Some applications may not require
SIMPROG and SIMCARD; thus SIMPROG and SIMCARD
can be re-used as additional general purpose I/O-pins.
CALIBRATERADIO
TXENABLE
SYNTHEN1
AGCA
Table 7. SIM Interface
AGCB
Name
I/O Function
USCRI
SIMCARD
SIMDATAOP
SIMDATAIP
SIMCLK
I
SIM card detect
USCRTS
O
I
SIM data output
SIM data input
SIM clock
USCCTS
O
O
O
O
If the pins SIMCARD and SIMPROG are not required in the
application, they can be used as additional H8 programmable
general purpose inputs or outputs.
SIMRESET
SIMPROG
SIMSUPPLY
SIM reset
SIM program enable
SIM supply enable
Setting GPO10 Select (CC Control Register 7) to 1, will
transform the pin ADD20 into a general purpose output
allowing the pin to be directly controlled via GPO10 Data.
Accessory Interface
The AD6426 provides 12 interface pins listed in Table 8 for
control of peripheral devices such as a car kit. However, two
general purpose I/O-pins of the Accessory Interface are
proposed to be used for additional control of the radio section
as described in the Radio Interface chapter.
By setting GPO11 Select (CC Control Register 77) to 1 and
FLASHPWD Disable to 1, the pin FLASHPWD becomes a
general purpose output. The pin state is toggled by setting the
GPO11 Data flag.
Table 8. Accessory Interface
To increase the flexibility of the AD6426, three pins in the
Radio Interface are multiplexed within GPO functions. The
pins multiplexed are: SYNTHEN1, AGCA and AGCB, with
the default function being the Radio Interface. The mode of
these pins is controlled by the Channel Codec Register
ccGPO.
Name
I/O
Function
GPIO9:0
I/O
General purpose
inputs/outputs
GPCS
O
General purpose chip select
The GPO[n]Sel bit selects the function of the pin. Setting
GPO[n]Sel to one will enable the pin to be controlled by the
GPO[n] bit. The GPO[n]Sel bit will override any other pin
function selection.
All GPIO pins start up as inputs. GPIO8 and GPIO9 are
controlled by flags in CC Control Register 79. When the
GPIOn OP Enable flag is set to 0, the GPIOn Data flag
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
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AD6426
To transform the TXPA pin into a general purpose output, set
TXPA Width = 0 (CC Control Register 75 and 76), then use
TxPA Polarity flag (CC Control Register 6) to toggle pin state.
Operating modes of the USC
Buffered UART Mode (Booting/Data Services)
This mode attaches the H8/DSP buffered UART to the USC,
bringing out either the serial bit rate clock or the Modem
Control Signal RI. This is the default mode when the phone is
powered up.
To use the CALIBRATERADIO pin as a general purpose
output, set the AUTOCALIBRATE flag to zero and use the
CALIBRATERADIO flag to toggle pin state.
Universal System Connector Interface
The BOOTCODE pin will be latched on RESET high. If
BOOTCODE is high at RESET, execution begins from the
Boot ROM which will configure the buffered UART to
download the FLASH programming code into RAM. The
FLASH program itself is also downloaded via the UART.
A typical GSM handset requires multiple serial connections to
provide data during normal phone operation, manufacturing,
testing, and debug. In an ideal case many of these functions
could be combined into a single multi-purpose system
connector. For example, the USC port can be used for:
An external Data Terminal Adapter can also be used. In this
case Data Services are done external to the phone and then
transferred to and from the H8. With the external Data
Terminal Adapter, the serial bit rate clock output is selected
for USCRI pin.
·
·
Flash code download for manufacturing and updates
Booting - UART interface used to download programs to
H8 memory
DAI Acoustic mode testing - connects System Simulator
(SS) directly to EVBC
DAI Transcoding mode - connects SS to 6426 for speech
codec testing
External DTA (Data Terminal Adapter) - asynchronous
link for MSDI interface
RS232 port - for on-board data services
H8 debug / monitor
Hands-free operation - time shared VBC and H8 port
Receive I/Q monitoring
·
·
·
This mode can be used for a variety of H8 debug tasks as the
UART can be used to simply shift debug information out.
Note that when in this mode if the handshake signals and
serial bit clock are not required, the RTS and RI pins can be
used as extra GPO, and the CTS pin used as an extra GPI.
·
·
·
·
Time-shared Mode (Multi-switch)
This mode allows time multiplexed communication with both
the H8 and DSP. This is most useful as a hands-free solution,
but can be used for other purposes also e.g., DAI Transcoding
Testing. This mode is used for DAI testing of the DSP’s
speech transcoder in which the DSP’s SPORT0 is connected to
the USC through the Multi-switch.
The Universal System Connector (USC) of the 6426 is
designed such that no external glue logic is required to achieve
this multi-purpose functionality. Furthermore, since the USC’s
function is related to the voiceband and I/Q data serial ports,
the USC block is also responsible for the correct configuration
of these serial data streams.
DAI Acoustic Mode Testing
This mode is used for DAI testing of the 6425’s phone’s
acoustic properties. The VSPORT of the 6425 connects to the
USC through the Multi-switch.
The actual system connector has the minimum number of pins
to achieve the needed functionality. This save system pins, and
allows for a more reliable connector from a manufacturing and
mechanical standpoint. The USC defines a 5 pin connector
that multiplexes asynchronous, synchronous, and modem
control signals as needed:
IQ Monitoring
This mode is used for testing the RF receive path and allows
access to the I and Q samples from the AD6425. The AD6425
signals are simply routed to the USC. This means that the
clock and frame sync are provided by the 6425 as well.
Name
I/O Function
I
Receive Data
USCRX
USCTX
USCRTS
USCCTS
USCRI
16 bit Mode
O
O
Transmit Data
Ready to Send
This mode connects the synchronous data path to the
SDIR/SDOR H8 Peripheral Control Registers, giving the H8
full access to the synchronous port bandwidth. This allows a
fast synchronous communication to an external device, and is
intended to be used for a fast download mechanism.
I/O Clear to Send / Transmit Frame Sync
1/O Ring Indicator / Serial Clock
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obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
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AD6426
Keypad / Backlight / Display Interface
Bit BACKLIGHT CC Control Register 50
This interface combines all functions of display and keyboard
as shown in Table 10.
2
Modulate 1
Table 10. Keypad / Backlight / Display Interface
1: 0
Backlight LED Control (1:0)
Name
I/O Function
The frequency is determined by the flags Backlight LED
Control (1:0) in the same register as shown in Table 11.
KEYPADROW5 : 0
KEYPADCOL3 : 0
BACKLIGHT
I
Keypad row inputs
O
O
O
Keypad column strobes
Backlight control
Table 11. Backlight Frequency
Bit 1
Bit 0
Frequency
DISPLAYCS
Display Controller chip
select
0
0
1
1
0
1
0
1
6.3475 kHz
12.695 kHz
25.390 kHz
50.780 kHz
LCDCTL
O
LCD Control / Serial Display
Data Output
GPIO3
GPIO4
O
O
Serial Display Data Output
Serial Display Clock Output
Duty cycle can be selected between 0 and 124/128 in 32 steps
of 4/128 by programming the Backlight Duty Cycle (4:0) flags
in the POWER CONTROL INTERNAL CC Control Register
44.
By providing 4 keypad-column outputs (open drain, pull low)
and 6 keypad-row inputs the AD6426 can monitor up to 24
keys. Additionally, an extra column can be implemented by
using the “ghost column” method for a total of 30 keys. The
H8 processor is interrupted whenever a key is pressed. The
KEYPADCOL pins are connected to the Keypad Column3-0
flags in the KEYPAD COLUMN CC Control Register 9.
Bit POWER CONTROL INTERNAL CC Control
Register 44
7 : 3
Backlight Duty Cycle (4:0)
Bit KEYPAD COLUMN CC Control Register 9
The active period is determined according to the formula:
3 : 0
Keypad Column 3-0
Backlight Duty Cycle (4:0) × 4
Active (high) Period =
128
The six KEYPADROW pins are connected to the Keypad Row
5-0 flags in the KEYPADROW CC Control Register 10.
The 6426 offers both parallel and serial interfaces for
connecting to LCD display controllers.
Bit KEYPADROW CC Control Register 10
5 : 0
Keypad Row 5-0
The parallel interface to a LCD controller is provided by two
dedicated control signals (LCDCTL and DISPLAYCS) and
parts of the address and data bus. A typical interface is shown
in Figure 5.
One backlight control output (BACKLIGHT) is provided,
which can be modulated to provide the same perceived
brightness for a reduced average current. Switching frequency
as well as duty cycle can be modified to compensate for
ambient lighting levels and changing battery voltage.
LCD
AD6426
DATA (15:8)
HWR
Controller
DATA (7:0)
The BACKLIGHT output is activated by setting the
Backlight1 flag in the SYSTEM CC Control Register 0.
R/W
E
LCDCTL
ADD(0)
Bit SYSTEM CC Control Register 0
RS
CS
5
Backlight 1
Once activated, an internal PWM circuit can control the
frequency and the duty cycle of the output signal. The PWM
circuit is enabled by the Modulate1 flag in the BACKLIGHT
CC Control Register 50. To switch the backlight continuously
on, enable the Backlight 1 flag and disable the Modulate 1
flag.
DISPLAYCS
Figure 5. Parallel Display Interface
The on-chip control circuit automatically generates wait states
for interfacing to external display devices.
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obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
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AD6426
Bit 3 (DALLAS EN) of the MEMIF H8 Peripheral Control
Register 80 controls the enabling of the battery ID interface
module. Setting this bit to zero enables the interface, resetting
the bit disables it. This bit is set to one on reset.
Serial Display Interface
The serial display interface is compatible with display drivers
by Motorola and Seiko-Epson. The display driver by Motorola
uses an SPI serial bus which requires an inverted or delayed
clock in comparison to the Seiko-Epson type display driver.
EVBC Interface
In the Motorola mode the data is delayed by one half clock
cycle such that the data is driven on the rising edge of SCLK
instead of on the falling edge.
The AD6426 interfaces directly to the Enhanced Voiceband
Baseband Converter AD6425 through the pins shown in Table
12.The communication is performed through three serial ports:
the Auxiliary Serial Port (ASPORT), the Baseband Serial Port
(BSPORT) and the Voiceband Serial Port (VSPORT). Layer 1
software enables/disables the clock output in order to reduce
system power consumption to a minimum if operation of the
AD6425 is not required. Figure 6 shows the interface between
the AD6426 and the AD6425 as well as to the AD6432 IF
chip.
The serial display interface consists of four pins; a serial data
output (DISPD0), clock (DISPCLK), chip enable (DISPEN)
and address (DISPA0). These pins are multiplexed with
GPIO4, GPIO3, LCDCTL and DISPLAYCS.
Bit 1 (DISP) of the MEMIF H8 Peripheral Control Register 80
controls the configuration of the display interface. With this
set to 0, the parallel display interface is used. Setting this bit
to one enables the use of the serial display interface. This bit
is set to 0 on reset.
Table 12. EVBC Interface
Name
I/O Function
CLKOUT
O
O
Clock Output to EVBC
Bit 4 (SERDISP MODE) of the SERDISPLAY/NMI H8
Peripheral Control Register 106 controls the serial display
mode. The default setting is Seiko-Epson mode. To enable the
Motorola mode the user must set the register bit to ONE.
EVBCRESET
Reset Output to EVBC
ASPORT
ASDO
ASOFS
ASCLK
ASDI
O
O
O
I
Data Output
Display Reset
Output Framing Signal
Clock Output
No dedicated pin is used to reset the display sub system. It is
recommended that the VBCRESET pin is used for this
function by connecting the Reset input on the display and the
Reset input on the VBC to the AD6426 VBCRESET pin. The
VBC and display cannot be reset independently. However one
of the GPIO pins can be used to reset the display separately.
Data Input
BSPORT
BSDO
BSOFS
BSCLK
BSIFS
BSDI
O
O
I
Data Output
Output Framing Signal
Clock Input
Battery ID Interface
I
Input Framing Signal
Data Input
The AD6426 provides a single-wire interface compatible with
the Dallas SemiconductorÔ DS2434or DS2435 Battery
Identification chip. The communication protocol supports three
operations: RESET, READ and WRITE. These operations
permit reading the present status off the battery and writing
updated information to the ID chip. The interface is available
as the BATID function multiplexed on the GPIO5 pin.
I
VSPORT
VSDO
VSDI
O
I
Data Output
Data Input
VSCLK
VSFS
I
Clock Input
I
Input/Output Framing Signal
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obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
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AD6426
AD6426
CLKIN
CLKOUT
VBCRESET
MCLK
RESET
13 MHz
XTAL
AD6425
AFC
ASDO
ASOFS
ASDI
XTAL TCOR
RFCLK
ASDIFS
ASDOFS
ASCLK
ASDO
BREFOUT
GREFAD6432
ASCLK
ASDI
MXOP
IFHI
FILTER
FILTER
AGC
GAIN
BSDO
BSOFS
BSCLK
BSDI
BSDI
BSDIFS
BSCLK
BSDO
ITXP
ITXN
ITXP
ITXN
RFHI
RFLO
BSIFS
BSDOFS
QTXP
QTXN
QTXP
QTXN
MODE
RMX_OUT FREF
TX_IN
IRXP
IRXN
IRXP
IRXN
VSDO
VSDI
VSCLK
VSFS
VSDI
PAs &
Control
MODP
MODM
VSDO
VSCLK
VSFS
TX
TMX_OUT
QRXP
QRXN
QRXN
QRXP
FILTERS
LNA-IN
RX
DUALBAND
RF FRONT-END
RAMP
RXON TXON
OSEN RXPU TXPU
RXON
TXON
GSM_ON
DCS_ON
RXON
TXENABLE
GPIO2
BANDSELECT0
BANDSELECT1
RFLO
GPIO1
RADIOPWRCTL
RFLO
GSM_ON
DCS_ON
SYNTHCLK
SYNTHDATA
SYNTHEN0
DCLK
DATA
RFCLK
VCOs
ENB
+
GPIO7
TXPHASE
TXPA
SYNTHESIZERS
ANTENNASELECT
Figure 6. EVBC and Radio Interface
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
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AD6426
CONTROL), gated with RADIO POWER CONTROL to force
a low output when the Radio is off.
Radio Interface
The AD6426 Radio Interface has been designed to support
direct connection to the ADI IF-Chips AD6432, while
providing full backwards compatibility to existing radio
designs interfacing to the AD20msp410 and AD20msp415.
Additionally the AD6426 Radio Interface supports radio
architectures based on Siemens, TTP/Hitachi or Philips RF
chipsets.
In order to increase the flexibility of the AD6426, three pins in
the Radio Interface are multiplexed with GPO functions. The
pins multiplexed are: SYTHEN1, AGCA and AGCB, with the
default function being the Radio Interface.
The mode of these pins is controlled by the new ccGPO
Channel Codec Register:
The Radio Interface of the AD6426 consists of 16 dedicated
output pins listed in Table 13. Together with two optional
general purpose I/O-pins they provide a flexible interface to a
variety of radio architectures for both 900 MHz and 1800/1900
MHz operation.
The GPO[n]Sel bit selects the function of the pin. Setting
GPO[n]Sel to one will enable the pin to be controlled by the
GPO[n] bit. The GPO[n]Sel bit will override any other pin
function selection.
Dual Band Control
Generic Pins
The following three pins have the same functionality in all
types of radio architectures:
To support dual band handsets BANDSELECT[1:0] signals
are provided. BANDSELECT0 is multiplexed with GPIO[2],
with the default function of this being GPIO[2].
BANDSELECT1 is multiplexed with GPIO[1], the default
function being GPIO[1].
RADIOPWRCTL
This output signal is typically used to power down the
oscillators and prescalers during Idle mode and is directly
controlled by the Radio Power Control flag in the POWER
CONTROL EXTERNAL CC Control Register 45.
For Dual Band solutions requiring a single band select bit, the
BANDSELECT0 function is enabled by asserting the BAND
EN bit. In order to set BANDSELECT0 high/low and cause
the radio module to operate in the appropriate band, the least
significant bit (bit 0) of the relevant 32 bit register for
Dynamic Synthesizer 1 must be written, i.e. different values
may be set for Rx, Tx and Monitor but only for Dynamic
Synthesizer 1.
Bit POWER CONTROL EXTERNAL CC Control
Register 45
1
Radio Power Control
Table 13. Radio Interface
BANDSELECT0 is sampled internally and is valid from the
beginning of data serialization, both for on demand
(immediate) loading and ordinary interrupt driven loading.
The BANDSELECT0 signal will remain in this known state
until the next time there is any serialization of data for
Dynamic Synthesizer 1, when a new sample will be taken of
the least significant bit of the 32 bit synthesizer register
currently being serialized.
Name
I/O Function
BANDSELECT1
GPIO1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
GPIO2
BANDSELECT0
RADIOPWRCTL
GPIO6
Radio Powerdown Control
VBIAS
GPIO7
ANTENNASELECT
Switches PLLs (Rx / Tx)
Transmit Enable
Full control is provided over the number of bits to be shifted
out to the synthesizer and so it is intended that this bit count
will always be less than 32 when using the BANDSELECT0
feature in order to prevent shifting the control bit out.
BANDSELECT0 is gated with RADIO POWER CONTROL to
ensure that whenever the RADIO is off, BANDSELECT0 is
forced to a low state.
TXPHASE
TXENABLE
TXPA
Power Amplifier Enable
Receiver on
RXON
CALIBRATERADIO
SYNTHEN0
SYNTHEN1
SYNTHDATA
SYNTHCLK
AGCA
Radio Calibration
Synthesizer 0 Enable
Synthesizer 1 Enable
Synthesizer Port Serial Data
Synthesizer Port Clock
AGC Control A
For Dual Band Solution requiring two band select bits, one for
GSM900, and one for DCS1800, then both BANDSELECT0
and BANDSELECT1 are enabled by asserting both the BAND
EN and DCSSEL EN bits. The BANDSELECT0 output is
driven as in the single enable mode (described above), and the
BANDSELECT1 output is the inverted output of the raw
BANDSELECT0 output (prior to gating with RADIO POWER
AGCB
AGC Control B
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
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AD6426
GPIO6 - VBIAS
TXPA
This general purpose I/O pin can be used to control the
powering up/down of a separate voltage converter, which may
be needed to provide the supply voltage for GaAs RF Power
Amplifiers. Significant turn-on time of the voltage converter
requires an early power-up signal, which is provided by
GPIO6. This control is achieved entirely through a software
driver, without hardware support. Since this function is not
needed for all radio solutions, the GPIO pin can be used for
other functions if not required.
This signal is used as a power amplifier (PA) enable and/or as
a control signal for the PA control loop. This allows the PA to
be isolated from the supply outside the Tx-slot to save current.
In the PA control loop it can be used to control the dynamics
of the loop. The flag Tx Pa Polarity in the TRAFFIC MODE
CC Control Register 6, provides independent control for the
TXPA signal.
Bit TRAFFIC MODE CC Control Register 6
7
Tx Pa Polarity;
active high, when reset
GPIO7 - ANTENNASELECT
This general purpose I/O pin can be used to switch between
two different antennas, as required, when the mobile radio is
used in conjunction with a car-kit with external antenna. This
control is achieved entirely through a software driver, without
hardware support. Since this function is not needed for all
radio solutions, the GPIO pin can be used for other functions if
not required.
TXPA is derived from the leading edge of TXENABLE signal
shown in Figure 7.
TXENABLE
TW
TD
Tx Timing Control
TXPA
The following 5 radio interface pins serve different functions
depending on the radio architecture:
Figure 7. Timing of TXPA
The parameter TD is a programmable delay (0 to 1023 QBIT) to
accommodate the EVBC settling time. TD is therefore a 10 bit
value, accessed via the TXPA OFFSET 1 CC Control Register
73 and the TXPA OFFSET 2 CC Control Register 74.
TXPHASE
The purpose of this signal is to switch PLLs between Rx and
Tx modes. The signal is generated under control of the flags
TXPHASE Enable and TXPHASE Polarity of the RADIO
CONTROL CC Control Register 2.
Bit TXPA OFFSET 1 CC Control Register 73
Bit RADIO CONTROL CC Control Register 2
1 : 0
TD (9:8)
6
TXPHASE Polarity
Controls the polarity of the output TXPHASE.
When set to 1, TXPHASE is active low;
When set to 0, TXPHASE is active high.
Bit TXPA OFFSET 2 CC Control Register 74
7 : 0
TD (7:0)
3
0
TXPHASE Enable
Enables the output pin TXPHASE if set to 1.
The parameter TW is a programmable width (0 to 1023 QBIT
)
which defines the PA enable time. TW is therefore a 10 bit
value, accessed via the TXPA WIDTH 1 CC Control Register
75 and the TXPA WIDTH 2 CC Control Register 76.
Transmit Enable
Enables the output pin TXENABLE if set to 1.
In radios based on the TTP/Hitachi solution, this signal can be
used to switch the VCO´s.
In radios based on the Siemens or Philips solution, this signal
can be used for control switching PLLs, or band switching
UHF PLLs.
Bit TXPA WIDTH 1 CC Control Register 75
1 : 0
TW (9:8)
Bit TXPA WIDTH 2 CC Control Register 76
7 : 0
TW (7:0)
TXENABLE
This signal enables the RF modulator and transmit chain
including the PA, and controls the TXON-pin of the AD6425.
The signal is generated under control of flag Transmit Enable
of the RADIO CONTROL CC Control Register 2.
If TW is set to zero, then TXPA will be disabled.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
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AD6426
Rx Timing Control
Synthesizer Control
RXON
The radio interface of the AD6426 supports 2 dynamic
synthesizers, with each capable of downloading data on
demand.
The two Synthesizer Load Dynamic flags located in the
SYNTH CONTROL CC Control Register 38, will set the
synthesizer interface to load 3 consecutive long-words from
Layer 1.
The signal at the output pin RXON is generated by the
function Receive Enable OR Monitor Enable of the RADIO
CONTROL CC Control Register 2. It can be used to enable
the RF receiver and controls the RXON-pin of the AD6425. In
radios based on the Siemens solution this signal would be
connected to the RXON1 input. Additional RXON derived
signals are provided to support this solution.
Bit SYNTH CONTROL CC Control Register 38
Bit RADIO CONTROL CC Control Register 2
7
Synthesizer Enable Polarity
2
1
Monitor Enable
Receive Enable
Selects the polarity of the SYNTHEN outputs.
If set to 0, SYNTHEN is an active low signal,
if set to 1, SYNTHEN is an active high signal.
6
Synthesizer Enable Type
CALIBRATERADIO
Selects the active period of the SYNTHEN outputs.
When set to 0, SYTHEN is active for all data values
determined by SYNTHESIZER BIT COUNT; when
set to 1, SYNTHEN goes active after the last bit for
one SYNTHCLK period.
The 4 modes of the Autocalibrate signal (Type 0 & 1, AutoCal
on/off) are provided as required by the ADI or Philips solution
and shown in Figure 8.
RXON
2
1
Synthesizer Load Dynamic 1 (SLD1)
Synthesizer Load Dynamic 0 (SLD0)
RxEnable
Start (late)
RxEnable
Start (early)
AutoCalibrateEnd
RxEnableEnd
TYPE=0, AUTOCAL=0
TYPE=0, AUTOCAL=1
TYPE=1, AUTOCAL=0
TYPE=1, AUTOCAL=1
When using the Configure Dynamic Synthesizer flag in the
SYNTH BIT COUNT CC Control Register 37, the download-
on-demand function is applied to the synthesizer selected by
SLD0 or SLD1.
Bit SYNTH BIT COUNT CC Control Register 37,
6
Configure Dynamic Synthesizer
Figure 8. Autocalibration
The flags Autocalibrate and Calibrate Radio in the SYSTEM
CC Control Register 0 are OR´ed and connected to the output
pin CALIBRATERADIO.
Each dynamic synthesizer is comprised of three 32-bit word
registers, for the Rx, Tx and Monitor phases. The download
on demand uses the Rx register only for the respective
synthesizer.
Bit the SYSTEM CC Control Register 0
Bit SYNTHESIZER 1 CC Control Register 40
7 : 0 Synthesizer (31:24)
7
Autocalibrate
Enables the autocalibrate function if set to 1;
3
Calibrate Radio
Bit SYNTHESIZER 2 CC Control Register 41
7 : 0 Synthesizer (23:16)
The type of autocalibration is set in the TRAFFIC MODE CC
Control Register 6
Bit SYNTHESIZER 3 CC Control Register 42
7 : 0 Synthesizer (15:8)
Bit TRAFFIC MODE CC Control Register 6
3
Autocalibration Type
Bit SYNTHESIZER 4 CC Control Register 43
7 : 0 Synthesizer (7:0)
In radios based on the Siemens chipset, this signal would
connect to the RXON2 input. The required behavior is enabled
by selecting the Type 1 CalibrateRadio function.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
The two dynamic synthesizers are programmable as follows,
while each synthesizer may be independently disabled,
through the two Disable Synthesizer flags in the
Bit SYNTH CONTROL CC Control Register 38
5
Synthesizer Clock Polarity
SYNTHESIZER PROGRAM CC Control Register 72.
Selects the edge, on which synthesizer data and
enable will be clocked out. Negative edge, when set
to 0; positive edge, when set to 1.
Bit SYNTHESIZER PROGRAM CC Control Register
72
0
Synthesizer Clock;
5
4
Disable Synthesizer 1
Disable Synthesizer 0
Synthesizer Enable Select
Synthesizer Mode
selects the frequency of SYNTHCLK output.
SYNTHCLK = 1.625 MHz if set to 0 (default),
SYNTHCLK = 6.5 MHz if set to 1.
3
2
In Modes 2 and 3, the outputs of these two pins are
multiplexed with flags of the internal DSP as indicated in
Table 16. The function of DSPFLAG1 ô Synthesizer Data is
defined as: The output is that of DSPFLAG1 except when the
synthesizer interface is active. In this case the synthesizer
output has priority. The same applies to DSPFLAG2 ô
Synthesizer Clock.
1 : 0
Pin Mode (1:0)
SYNTHEN0 : 1
The AD6426 provides enable signals for two independent
synthesizers. These signals are available at the output pins
SYNTHEN0 and SYNTHEN1. The polarities of these signals
are individually programmable; i.e. bit 7 of CC Control
Register 38 is applied to the synthesizer selected by either bit
2 or bit 1 of the same register.
Table 16. Pin Function in Modes 2 and 3
AD6426 Pin
Function
SYNTHDATA
SYNTHCLK
DSPFLAG1 ô Synthesizer Data
DSPFLAG2 ô Synthesizer Clock
SYNTHDATA and SYNTHCLK
Three Modes can be selected to support different radio
architectures. The selection of the Pin-Mode is done by the
two Pin Mode flags in the SYNTHESIZER PROGRAM CC
Control Register 72 as shown in Table 14.
AGC Control
AGC programming is achieved in one of three ways:
Table 14. Pin Mode
The first is a gain select approach, whereby the DSPFLAG0
and DSPFLAG1 are used as a 2-bit gain selector (AGCA,
AGCB). This is available in Mode 1 and the flags are under
direct control of the internal DSP and are timing independent
of the synthesizer interface.
Bit 1
Bit 0
Mode
Mode 1 (default)
Mode 1
0
0
1
1
0
1
0
1
Mode 2
Table 17. Pin Function in Mode 1
Mode 3
AD6426 Pin
Function
The default is Mode 1, which supports TTP/Hitachi Bright
and Philips radio architectures. Mode 2 also supports a Philips
architecture, while Mode 3 supports a Siemens architecture. In
Mode 1, the pins SYNTHDATA and SYNTHCLK have their
original functionality; i.e. SYNTHDATA is the data output
and SYNTHCLK is the clock output of the serial synthesizer
interface. Clock polarity and frequency are programmed in the
SYNTH CONTROL CC Control Register 38.
AGCA
AGCB
DSPFLAG0
DSPFLAG1
The second is through the DSP combined with the serial
synthesizer interface, as defined in Mode 2. The function of
DSPFLAG0 ô SYNTHEN1 is defined as: The output is that of
DSPFLAG0 except when the synthesizer interface is active.
Table 15. Pin Function in Mode 1
To support the Philips chipset whereby the AGC and the PLL
are programmed over the same enable line, the AGCA pin is
multiplexed to provide a SYNTHEN1 gated with DSPFLAG0.
This pin would be wired instead of the SYNTHEN1 pin. Since
the DSP would program the AGC during RXON, and the
synthesizers are reprogrammed following the end of the active
phase, no conflict can occur.
AD6426 Pin
Function
SYNTHDATA
SYNTHCLK
Synthesizer Data
Synthesizer Clock
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
In Modes 2 and 3, PLL programming occurs on any of Rx, Tx
and MonEnableEnd through the synthesizer interface.
Additionally, AGC programming, controlled via the DSP, is
performed during RXON.
Table 18. Pin Function in Mode 2
AD6426 Pin
Function
AGCA
AGCB
DSPFLAG0 ô SYNTHEN1
DSPFLAG1
The third mode is for support of the Siemens chipset,
providing an independent AGC enable from SYNTHEN using
the DSP Flag 0. The same serial interface constraints from
Mode 2 apply. Additionally, the output OCE is provided. This
is the Offset Correction Enable, derived from the
RxEnableStartEarly and RxEnableStartLate timing signals as
shown in Figure 9.
Table 19. Pin Function in Mode 3
AD6426 Pin
Function
AGCA
AGCB
DSPFLAG0
OCE
RxEnableStartEarly
RxEnableStartLate
RXON
OCE
Figure 9. OCE Signal
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Table 21. JTAG Instructions
Code Comments
TEST INTERFACE
The AD6426 provides a complete JTAG test interface. The
functionality of these pins are shown in Table 20.
Furthermore, these pins can assume a different functionality
described in detail in the chapter MODES OF OPERATION.
Instr.
Register
4 3 2 1
0 0 0 0
0 0 0 1
0 0 1 0
ExTest
Clamp
Public Instruction
Table 20. Test Interface
Optional Public Instruction
Name
I/O
Function
Sample/PreLoad Public Instruction
I
JTAG enable (internal pull
down resistor)
JTAGEN
Private Instruction
DoBist
0 0 1 1
Engineering Mode Test
I
I
JTAG test clock input
JTAG test mode select
JTAG test data input
JTAG test data output
TCK
TMS
TDI
0 1 0 0 -
0 1 0 1
Reserved
I
Private Instruction
Mode D
0 1 1 0
H8 Emulation
Reserved
O
TDO
0 1 1 1
1 0 0 0 -
1 1 1 0
Public Instruction
Bypass
JTAG Port
Selects Mode A
The AD6426 provides full IEEE 1149.1 compliance. The
JTAG Port must be run at a frequency of 5 MHz or less.
Public Instruction
Bypass
1 1 1 1
Selects Mode A (default)
The JTAG Port is explicitly enabled through JTAGEN. When
disabled, the corresponding pins are re-used for the AD6426
Feature Modes. The JTAG interface implements four registers
shown in Figure 10. The content of the Instruction register
selects one of these four registers.
ExTest Instruction
The ExTest instruction is used to force input or output
conditions on the boundary scan cell.
Clamp Instruction
This optional public instruction is similar to the Bypass
instruction, except that once loaded, it will force the values
held in the boundary scan chain onto the corresponding
outputs of the device. This enables all output and bi-
directional pads to be fixed, allowing other parts on the PC-
board to be tested without interference from the AD6426,
while at the same time selecting the Bypass register for the
shortest possible scan path.
Boundary Register
161
3
162
2
Bypass Register
1
163
1
T D I
Bist Register
6
T D O
All input activity to the AD6426 will be ignored during this
time, since all inputs are driven from the preloaded values in
the boundary scan chain. Typically therefore this instruction
would be preceded by the Sample/Preload instruction. This
instruction is only valid during the normal operation of the
AD6426; i.e. in Mode A.
8
1
7
2
3
5
4
4
1
Instruction Register
3
2
Sample/Preload Instruction
The Sample/Preload instruction is fully IEEE compliant.
Figure 10. JTAG Registers
The instruction register contains 4 bits, and supports the
instructions listed in Table 21.
Boundary Register
The boundary cell structure is based on the I/O definition in
Mode A, and hence pins which are outputs only in this mode,
but become inputs in another mode, do not support input scan
cells, and vice versa. Table 22 shows the complete Boundary
register.
Instruction register values 01XX all select the bypass register
when JTAG compliance is enabled. Values 00XX control the
AD6426 I/O as defined in Mode A, and therefore should not
be used in any other mode.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Table 22. Boundary Scan Path
TDO
#
Cell Name
#
Cell Name
#
Cell Name
#
Cell Name
1
2
SIMCARD
SIMCARD
B
O
44 DATA8
45 DATA8
O
I
87 USCCTS
I
O
130 GPIO6
131 GPIO6
O
I
88
89
USCTX
3
4
5
6
7
8
9
SIMCARD
I
46 DATA9
47 DATA9
48 DATA10
49 DATA10
50 DATA11
51 DATA11
52 DATA12
53 DATA12
54 DATA13
55 DATA13
56 DATA14
57 DATA14
58 DATA15
59 DATA15
60 ROMCS
61 RAMCS
62 ADD0
O
I
B
O
I
132
B
O
I
USCRXEN
GPIO7EN
SIMCLK
O
T
O
I
90 USCRX
91 USCRX
92 USCRI
133 GPIO7
O
I
134 GPIO7
SIMDATAOPEN
SIMDATAOP
SIMDATAIP
SIMRESET
SIMPROG
I
135 CLKIN
I
O
I
93
B
O
I
136 TXENABLE
137 RADIOPWRCTL
138 CALIBRATERADIO
139 TXPA
O
O
O
O
O
O
O
O
O
O
O
I
GPIO9EN
O
B
O
I
94 GPIO9
95 GPIO9
O
I
10 SIMPROG
11 SIMPROG
12 SIMSUPPLY
96
B
O
I
GPIO8EN
O
I
97 GPIO8
140 AGCB
O
B
O
I
98 GPIO8
141 AGCA
13
O
I
99 IRQ6
I
142 SYNTHCLK
143 SYNTHDATA
144 SYNTHEN0
145 SYNTHEN1
146 PWRON
GPIO0EN
14 GPIO0
15 GPIO0
100 RESET
I
O
I
101 KEYPADROW0
102 KEYPADROW1
103 KEYPADROW2
104 KEYPADROW3
105 KEYPADROW4
106 KEYPADROW5
I
16
B
O
I
I
GPIO1EN
17 GPIO1
O
O
O
O
O
O
O
O
O
O
O
I
I
18 GPIO1
I
147 OSCIN
19 WR
O
B
O
I
I
148
B
O
I
GPIO2EN
20 FLASHPWD
21 FLASHPWD
22 FLASHPWD
63 ADD1
I
149 GPIO2
150 GPIO2
151 TXPHASE
152 ASDO
153 ASOFS
154 ASDI
64 ADD2
107
108 KEYPADCOL0
109
110 KEYPADCOL1
111
112 KEYPADCOL2
113
T
O
T
O
T
O
T
O
O
O
O
O
O
B
O
I
KEYPADCOL0EN
65 ADD 3
66 ADD4
O
O
O
I
23
B
O
I
DATA0 : 7EN
KEYPADCOL1EN
24 DATA0
25 DATA0
26 DATA1
27 DATA1
28 DATA2
29 DATA2
30 DATA3
31 DATA3
32 DATA4
33 DATA4
34 DATA5
35 DATA5
36 DATA6
37 DATA6
38 DATA7
39 DATA7
40 LBS
67 ADD5
68 ADD6
KEYPADCOL2EN
O
I
69 ADD7
155 ASCLK
156 BSCLK
157 BSDI
O
I
70 ADD8
KEYPADCOL3EN
O
I
71 BOOTCODEEN
72 ADD9
114 KEYPADCOL3
115 GPCS
I
O
O
O
O
O
O
O
O
O
O
O
O
I
158 BSIFS
159 BSOFS
160 BSDO
161 CLKOUT
162 RXON
163 VBCRESET
164 VSCLK
165 VSDI
I
O
I
73 ADD10
74 ADD11
75 ADD12
76 ADD13
77 ADD14
78 ADD15
79 ADD16
80 ADD17
81 ADD18
82 ADD19
83 ADD20
84 USCRTS
116 OSC13MON
117 BACKLIGHT
118 DISPLAYCS
119 LCDCTL
O
O
O
O
O
I
O
I
O
I
120
GPIO3EN
121 GPIO3
122 GPIO3
O
I
I
123
B
O
I
166 VSFS
I
GPIO4EN
O
I
124 GPIO4
125 GPIO4
167
T
O
B
O
I
VSDOEN
168 VSDO
169
O
O
O
B
126
B
O
I
GPIO5EN
EEPROMDATAEN
41 UBS
127 GPIO5
128 GPIO5
170 EEPROMDATA
171 EEPROMDATA
172 EEPROMCLK
173 EEPROMEN
TDI
42 RD
85
86 USCCTS
B
O
USCCTSEN
43
129
B
O
O
DATA8 : 15 EN
GPIO6EN
Notes: The boundary scan supports only pin functionality and signal directions of Normal Mode (A); see chapter “Modes of Operation”. Cells can be input (I) or output cells (O) which
correspond to the pins with the same name, or internal control cells shown in ITALIC. Control cells are either bi-directional control cells (B), or tri-state output control cells (T). When
type-B cells are loaded with 0, the referred pins become driving output pins, otherwise the pins are inputs. When type-T cells are loaded with 1, the referred pin will be tri-stated,
otherwise the pin is an output.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Table 23. Modes of Operation
DoBist Instruction
This instruction is provided to support engineering mode test.
When the instruction is loaded, it will generate an NMI to the
H8 processor. This will enable special software to be executed
which can be used to test the operation of the device. During
this time, the 8-bit DoBist register is selected for scan,
enabling a result code for the test to be scanned out. For the
duration of the test, all I/O retain their normal function. The
test program must therefore cope with undefined inputs, but is
able to communicate with other devices to extend the test
procedure. This allows the NMI to be generated during normal
phone operation. This instruction is only valid during the
normal operation of the AD6426; i.e. in Mode A.
Mode of Operation
Normal Mode
Reserved
A
B
C
D
Reserved
Emulation Mode (H8)
Normal Mode (Mode A)
This mode is used during normal operation of the AD6426. All
JTAG-pins have their normal functionality, when enabled by
JTAGEN and can be used for production test.
Emulation Mode (Mode D)
Mode D Instruction
This instruction switches the AD6426 into the H8 Emulation
Mode (Mode D). It is only valid to switch modes while the
AD6426 is held in reset.
Selecting Mode D allows the emulation of the internal H8
processor. In this Mode several pins assume a new
functionality or are no longer available. Table 24 lists all pins,
which have different functionality or direction in the
Emulation Mode compared to the Normal Mode.
Reset
To comply with the IEEE specification, the JTAG interface
will be forced to reset whenever the JTAG Port is re-enabled.
This will select the Bypass register and force the AD6426 into
the Normal Mode (Mode A).
In Emulation Mode the internal DSP remains active but will
not have access to external memory devices. The internal H8
will be switched into hardware stand-by mode; the LCD
controller interface and Boot Code ROM remain functional.
Debug Port Interface
In normal (voice-service) operation, the Universal Serial Port
can be used as a monitor port, which allows monitoring
internal operation of the channel codec section. However,
during the use of GSM Data Services, the USC is engaged in
data communication and cannot be used for monitoring. The
6426 provides a Debug Port to enable monitoring and
debugging in this case. This is in the form of a simple 2 pin
UART. The communication format is fixed at 9600 baud, 8
data bits, one stop bit, no parity, asynchronous
CCIRQ0 : 2 are channel codec interrupts to the emulator.
CCIRQ2 is defined in CC Control Registers 77 and 78.
Table 24. Pin Functions in Mode D
Pin Name in
Pin Function in
Normal Mode (A)
Emulation Mode (D)
IRQ6
CCCS
-
I
ADD19 : 16
ADD15 : 0
DATA7 : 0
RD
TRI
communication. Operation of the Debug Port is under control
of the Layer 1 software.
ADD15 : 0
I
-
TRI
RD
I
Two of the GPIO pins can be programmed to be used as the
Debug Port:
HWR
HWR
I
LWR
-
TRI
RAMCS
SIMCARD
SIMDATAOP
SIMDATAIP
SIMCLK
SIMRESET
SIMPROG
SIMSUPPLY
GPIO9
-
TRI
Pin Name
New Function
-
TRI
GPIO8
GPIO9
TXDATA
RXDATA
-
TRI - O
-
I
-
O
O
O
O
I
The serial port can be enabled by asserting the flag DATA
SERIAL PORT SELECT in CC Control Register 7.
CCIRQ0
CCIRQ2
CCIRQ1
H8CS0
CCGPIO8
MODES OF OPERATION
The AD6426 can be switched between two main operating
modes, using instructions downloaded via the JTAG interface.
This must be done while the AD6426 is held in reset. Once
the instruction load is completed the pins are immediately set
to reflect the new operating mode. Table 23 shows these
modes. The modes B and C are reserved and are not available
to the user.
GPIO8
I/O -
TRI
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obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
High Speed Logging
Pin Name in
Pin Function in
This mode is selected for monitoring the operation of the
internal DSP during the development and field test phase.
When the JTAGEN pin is de-asserted and the HSLEnable flag
in the TESTADDRESS CC Control Register 33 is set, a high
speed logging port is mapped on the JTAG- and EEPROM
pins as shown in Table 26. The internal DSP must then be
instructed via Layer 1 to output logging messages onto the
HSL pins.
Normal Mode (A)
Emulation Mode (D)
GPO10
WAIT
-
O
TRI
O
GPCS
FLASHPWD
DISPLAYCS
GPIO0
Forced High
DISPLAYCS
Reserved
I/O
O
GPIO1
Forced High/
O
BANDSELECT1
Table 26. HSL Mode
GPIO2
Forced High/
BANDSELECT0
O
AD6426 Pin
Function in HSL Mode
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
Forced High/DISPA0
Forced High/DISPCLK
Forced High/BATID
Reserved
O
O
TCK
HSLDO0
HSLDO1
HSLDO2
HSLDO3
HSLCLK
HSLFS
O
O
O
O
O
O
TMS
O
TDO
O
TDI
Reserved
TRI
EEPROMCLK
EERPROMEN
FLASHPWD can also be used as WAIT input, in which case it
is routed through and gated with the LCDWAIT to be output
on the WAIT output pin GPO10/ADD20. If the on-chip LCD
controller is not used in emulation, then ADD20 pin can be
used as ccGPO(10).
The High Speed Logging port (HSL) is an unidirectional port
which supplies nibble-wide synchronous data from the internal
DSP to an external data logger. The data logger will be
connected to a PC which will be responsible for presenting the
data to the user. The PC is able to configure the HSL via
either one of the serial interfaces.
FEATURE MODES
Two additional features can be enabled under software
control.
These are; DAI Mode (Digital Audio Interface) and HSL
Mode (High Speed Logging) used to monitor the operation of
the on-chip DSP.
The HSL is enabled as follows:
·
·
The JTAGEN pin is set to 0
The H8 enables the HSL logic by setting the HSLEnable
flag
DAI Mode
This mode is selected during type approval, when Digital
Audio Interface is required. To enable this feature, the
JTAGEN pin must be de-asserted, upon which the JTAG pins
TMS, TDI and TDO are re-assigned as shown in Table 25.
The default feature mode thus enabled is DAI. In addition, the
voiceband serial port signals are made available through the
USC to facilitate testing of the speech transcoder as well as
the phone’s acoustic properties. The DAI box interface product
is available upon request from Analog Devices.
·
On a command issued through the Data Interface, the H8
configures the DSP software to enable HSL
The HSLEnable flag is used to deselect DAIRESET in favor of
the HSL onto the JTAG pins, and enable the HSL onto
EEPROMCLK and EEPROMEN.
The DSP sends data over the port by writing to address 0x000
in the Data Memory map. The writes are full 16-bit writes,
and can occur at a maximum rate of one write per five 39 MHz
clock cycles. Five cycles allow time for the HSL circuit to
serialize the 16 bits of data onto the 4-bit data bus with one
cycle to spare. HSLFS is used to frame the valid data nibbles.
Note that HSCLK is free-running , and that HSLFS and
HSLDO3-0 are synchronized to the rising edge of HSCLK.
Table 25. DAI Mode
AD6426 Pin
Function in DAI Mode
I/O
VSCLK
VSFS
VSDO
VSDI
TMS
MSCLK
MSFS
I
I
MSRXD
MSTXD
DAIRESET
DAI1
O
I
O
O
I
TDI
TDO
DAI0
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
The mapping of the DSP data bits to the HSL port bits is:
Table 27. Mapping of HSL Port Nibbles
DSP
Data Bits
HSLDO
Nibble
23 : 20
19 : 16
15 : 12
11 : 8
1
2
3
4
HSCLK
HSLFS
HSLDO (3:0)
1
2
3
4
1
Figure 11. HSL Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
General
SPECIFICATIONS
Parameter
Min
-25
Typ
Max
+85
3.3
Units Comments
TA , Ambient Operating Temperature
VDD , Supply Voltage
°C
2.4
Volt
IDD , Supply Current (Idle Mode)
IDD , Supply Current (Talk Mode)
fCLKIN , Clock Input Frequency
VCLKIN , Clock Input Voltage
RCLKIN, Clock Input Resistance (see Note)
Logic Inputs
TBD
TBD
13
mA
mA
@ VDD = 3.0 V
@ VDD = 3.0 V
MHz
VPP
0.250
sine wave, ac-coupled
sine wave, ac-coupled
19.5
kW
VIH , Input High Voltage
VIL , Input Low Voltage
VDD - 0.8
-10
Volt
Volt
mA
0.8
10
IIH , IIL Input Current
CIN , Input Capacitance
TBD
pF
Logic Outputs
VOH , Output High Voltage
VOL , Output Low Voltage
VDD - 0.4
0.4
10
10
IOZL , Low Level Output 3-State Leakage Current
IOZH , High Level Output 3-State Leakage Current
-10
-10
mA
mA
Note:
The input impedance of the clock buffer is a function of the voltage and waveform of the clock input signal. For sinusoidal input
signals the typical input impedance can be calculated by: RIN [kW] = VCLKIN [VPP] ´ 78
ABSOLUTE MAXIMUM RATINGS
VDD to GND ............................................. -0.3V to + TBD V
Digital I/O Voltage to GND ...................-0.3V to VDD + 0.3V
Operating Temperature Range ........................ -25°C to +85°C
LQFP Package
PBGA Package
Storage Temperature Range.......................... -65°C to +150°C
Maximum Junction Temperature ................................ +150°C
QJA Thermal Impedance..............................................28°C/W
Lead temperature, Soldering
Storage Temperature Range.......................... -65°C to +150°C
Maximum Junction Temperature ................................ +150°C
QJA Thermal Impedance..............................................30°C/W
Lead temperature, Soldering
Vapor Phase (60 sec)........................................... +215°C
Infrared (15 sec).................................................. +220°C
Vapor Phase (60 sec)........................................... +215°C
Infrared (15 sec).................................................. +220°C
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the operational sections is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. TA= +25°C unless otherwise stated.
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which
WARNING!
readily accumulate on the human body and on test equipment, can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may still occur
on this device if it is subjected to high energy electrostatic discharges. Therefore, proper precautions
are recommended to avoid any performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Clocks
TIMING CHARACTERISTICS
Parameter
Comment
Min
Typ
Max
Units
ns
t1
t2
t3
t4
t5
t6
CLKIN Period (see Figure 13)
CLKIN Width Low
76.9
30
30
45
45
ns
CLKIN Width High
ns
CLKOUT Period (see Figure 14)
CLKOUT Width Low
CLKOUT Width High
76.9
ns
30
30
45
45
ns
ns
t1
100 mA
IOL
t3
t2
CLKIN
To Ouput
Pin
+2.1V
Figure 13. Clock Input
CL
50pF
t4
t6
t5
100 mA
IOH
CLKOUT
Figure 12. Load Circuit for Timing Specifications
Figure 14. Clock Output
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Memory Interface
TIMING SPECIFICATION
Parameter
Comment ( Timing for 3-state access, see Figure 15 )
Min
Max
Units
Timing Requirement
t10b
t12b
t17
Control Processor read chip select to data valid
158
162
129
ns
ns
ns
ns
Control Processor read address to data valid
Control Processor read enable to data valid
Control Processor data hold
t19
0
Switching Characteristic
t10a
t11
t12a
t13
t14
t15
t16
t18
Control Processor write chip select setup
10
5
ns
ns
ns
ns
ns
ns
ns
ns
Control Processor chip select hold
Control Processor write address setup
Control Processor address hold
Control Processor write pulse width
Control Processor data setup
10
5
111
68
15
145
Control Processor data hold
Control Processor read pulse width
WRITE
CS
t11
t10a
t12a
t13
ADD 15:0
t14
HWR/LWR
t15
t16
DATA15:0
READ
CS
t10b
t13
ADD15:0
t12b
t11
t17
RD
t18
t19
DATA7:0
Figure 15. Memory Interface Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Radio Interface
TIMING CHARACTERISTICS
Parameter
Comment ( see Figure 16 )
Synthesizer clock period
Min
152
76
Max
Units
ns
t40
t41
615
307
85
Synthesizer clock high
ns
t42a
t42b
t43a
t43b
t44
Synthesizer data setup
60
ns
Synthesizer data hold
60
85
ns
Synthesizer enable delay for Type 0
Synthesizer enable delay for Type 1
Synthesizer enable width for Type 1
60
85
ns
-15
50
10
ns
90
ns
t41
t40
SYNTHCLK
t42a
0
1
2
n-2
n-1
n
SYNTHDATA
t42b
t43a
SYNTHEN[0:1]
TYPE 0
t41
t40
SYNTHCLK
t42a
0
1
2
n-2
n-1
n
SYNTHDATA
t42b
t43b
SYNTHEN[0:1]
TYPE 1
t44
Figure 16. Synthesizer Interface Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
High Speed Logging Interface
TIMING CHARACTERISTICS
Parameter
Comment ( see Figure 17)
HSCLK Period
Min
Typ
Max
Units
ns
t50
t51
t52
t53
t54
25.6
HSCLK Width Low
HSCLK Width High
HSCLK to HSLDO
HSCLK to HSLFS
8.3
8.3
0
ns
ns
15
15
ns
0
ns
t50
t52 t51
HSCLK
t54
HSLFS
t53
1
2
3
4
1
HSLDO3:0
Figure 17. High Speed Logging Interface
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Data Interface
TIMING CHARACTERISTICS
Parameter
Data Interface (see Figure 18)
Clock Period
Min
Typ
Max
Units
ns
t60
t61
t62
t63
Transmit Data Delay time
Receive Data Setup time
Receive Data Hold time
100
ns
100
0
ns
ns
t60
MONCLK
t61
MONTX
MONRX
t63
t62
Figure 18: Data Interface Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Test Interface
TIMING CHARACTERISTICS
Parameter
JTAG Port
Min
200
80
Typ
Max
Units
ns
t64
t65
t66
TCK Period*
TCK Width Low*
TCK Width High*
120
120
ns
80
ns
* Note: These parameters have been functionally verified, but not tested.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
EVBC Interface ASPORT
TIMING CHARACTERISTICS
Parameter
Comment (see Figure 19)
Min
Typ
Max
Units
ns
t70
t71
t72
t73
t74
t75
ASCLK period
384
ASOFS setup time before ASCLK high
ASOFS hold time after ASCLK high
ASDI setup time before clock low
ASDI hold time after clock low
ASDO delay after clock high
20
20
20
20
0
ns
ns
ns
ns
20
ns
t70
ASCLK (O)
t71
t72
ASOFS (O)
t74
t73
ASDI (i)
D9
D8
t75
D7
D7
A2
A1
A1
A0
ASDO (O)
D9
D8
A2
A0
Figure 19. EVBC Interface ASPORT Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
EVBC Interface BSPORT
TIMING CHARACTERISTICS
Parameter
Comment (see Figure 20)
Min
76.9
4
Typ
Max
Units
ns
t80
t81
t82
t83
t84
t85
t86
BSCLK period
BSIFS setup time before BSCLK low
BSIFS hold time after BSCLK low
BSDI setup time before BSCLK low
BSDI hold time after BSCLK low
BSOFS delay after BSCLK high
BSDO delay after BSCLK high
ns
7
ns
4
ns
7
ns
15
15
ns
0
t80
BSCLK (I)
t81
t82
BSIFS (I)
t83
t84
BSDI (I)
D15
D14
t85
BSOFS (O)
BSDO (O)
t86
D15
D14
Figure 20. EVBC Interface BSPORT Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
EVBC Interface VSPORT
TIMING CHARACTERISTICS
Parameter
Comment (see Figure 21)
Min
Typ
Max
Units
ns
t90
t91
t92
t93
t94
t95
VSCLK period
76.9
VSFS setup time before VSCLK low
VSFS hold time after VSCLK low
VSDI setup time before VSCLK low
VSDI hold time after VSCLK low
VSDO delay after VSCLK high
4
7
4
7
0
ns
ns
ns
ns
15
ns
t90
VSCLK (I)
t92
t91
VSFS (I)
t94
t93
VSDI (I)
D15
D14
t95
D14
VSDO (O)
D15
D13
Figure 21. EVBC Interface VSPORT Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Parallel Display Interface
TIMING CHARACTERISTICS
Parameter
Comments (see Figure 22)
Min
462
462
77
Typ
Max
Units
ns
t100
t101
t102
LCD Control low width (6 CLKIN cycles)
LCD Control high width (6 CLKIN cycles)
ns
LCD Control high width read extension (1 CLKIN
cycle)
ns
ADD 19:O
DISPLAYCS
RD or HWR
t100
t101
t102
LCDCTL
Figure 22. Parallel Display Interface Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
Serial Display Interface
TIMING CHARACTERISTICS
Parameter
Comment (see Figure 23)
Min
Typ
t1*8 or t1*16
0.25 *t103+ 5
5
Max
Units
ns
t103
t104
t105
t106
t107
DISP_CLK Period
DISP_CS Low to Data Valid
DISP_CLK Low to Data Valid
DISP_CLK Low to DISP_CS high
Data Valid to DISP_CLK High
ns
ns
0.25 *t103
0.25 *t103- 5
ns
ns
t103
DISP_CLK
//
//
//
t107
DISP_D0
D7
D6
D0
t104
t106
t105
DISP_CS
DISP_A0
Figure 23. Serial Display Interface
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
PACKAGING
LQFP Pin Locations
#
Pin Name
USCRI (MONCLK)
USCRX (MONRX)
USCTX (MONTX)
USCCTS (ADD20)
USCRTS (GPIO9)
GPO10 (GPIO8)
ADD19
#
Pin Name
DATA12
DATA11
DATA10
DATA9
#
Pin Name
TDI
#
Pin Name
AGCB
1
2
3
4
5
6
7
8
9
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
74
JTAGEN
EEPROMEN
EEPROMCLK
EEPROMDATA
GND
TXPA
75
CALIBRATERADIO
RADIOPWRCTL
TXENABLE
GND
76
DATA8
77
RD
78
GND
79
VDD
CLKIN
ADD18
VDD
80
VSDO
VDD
ADD17
UBS (HWR)
LBS (LWR)
DATA7
81
VSFS
GPIO7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ADD16
82
VSDI
GPIO6
ADD15
83
VSCLK
GPIO5
ADD14
DATA6
84
VBCRESET
RXON
GPIO4
ADD13
DATA5
85
GPIO3
ADD12
DATA4
86
CLKOUT
BSDO
LCDCTL
ADD11
DATA3
87
DISPLAYCS
BACKLIGHT
VDD
GND
DATA2
88
BSOFS
VDD
DATA1
89
BSIFS
ADD10
DATA0
90
BSDI
GND
ADD9
GND
91
BSCLK
OSC13MON (GPPWRCTL)
GPCS
BOOTCODE (GND)
ADD8
VDD
92
ASCLK
FLASHPWD
WR (GPIO2)
GND
93
ASDI
KEYPADCOL3
KEYPADCOL2
KEYPADCOL1
KEYPADCOL0
GND
ADD7
94
ASOFS
ADD6
95
ASDO
ADD5
VDD
96
TXPHASE
GPIO2 (CPPWD)
VDD (GND)
GND (VDD)
OSCIN (SAMCS)
OSCOUT (CPFS)
VDDRTC (CPDO)
PWRON (CPDI)
SYNTHEN1
SYNTHEN0
SYNTHDATA
SYNTHCLK
AGCA
ADD4
GPIO1
97
ADD3
GPIO0
98
KEYPADROW5
KEYPADROW4
KEYPADROW3
KEYPADROW2
KEYPADROW1
KEYPADROW0
VDD
ADD2
SIMSUPPLY
SIMPROG
SIMRESET
SIMDATAIP
SIMDATAOP
SIMCLK
SIMCARD
TCK
99
ADD1
100
101
102
103
104
105
106
107
108
ADD0
RAMCS
GND
VDD
ROMCS
DATA15
DATA14
DATA13
RESET
IRQ6
TMS
GPIO8 (BOOTCODE)
GPIO9 (H8MODE)
TDO
Note: pin names in ( ) are the AD6422 pin names from the AD20msp415 chipset.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
PBGA Pin Locations
#
Pin Name
#
Pin Name
ADD16
#
Pin Name
BOOTCODE
ADD7
#
Pin Name
GND
ROMCS
A1 USCR1
D1
D2
D3
D4
D5
D6
D7
D8
D9
G1
G2
G3
G4
G5
G6
G7
G8
G9
K1
K2
K3
K4
K5
K6
K7
K8
K9
A2 IRQ6
ADD17
A3 KEYPADROW0
A4 KEYPADROW4
A5 KEYPADCOL1
A6 GPCS
USCCTS
GPIO8
ADD9
DATA10
DATA9
VDD
ADD4
VDD
ADD1
GND
ADD11
DATA3
ASDI
DATA6
GND
A7 VDD
BACKLIGHT
GPIO5
A8 VDD
VDD
A9 CLKIN
SYNTHCLK
BSOFS
SIMRESET
A10 GND
D10 PWRON
D11 OSCOUT
D12 VDD
G10 VBCRESET
G11 BSDI
K10 EEPROMEN
K11 EEPROMDATA
K12 GND
A11 TXPA
A12 AGCB
G12 BSIFS
B1 USCRX
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
F1
ADD13
H1
H2
H3
H4
H5
H6
H7
H8
H9
ADD6
L1
DATA15
DATA13
DATA8
UBS
B2 GPIO9
ADD12
ADD3
L2
B3 RESET
ADD18
ADD5
L3
B4 KEYPADROW1
B5 KEYPADROW5
B6 KEYPADCOL2
B7 GND
ADD15
VDD
L4
ADD19
GND
L5
DATA4
DATA0
WR
KEYPADROW3
KEYPADCOL3
LCDCTL
SYNTHEN1
TXPHASE
GND
FLASHPWD
SIMPROG
VDD
L6
L7
B8 GPIO3
L8
GPIO0
B9 GPIO7
VSCLK
L9
SIMDATAIP
SIMCARD
TDO
B10 TXENABLE
B11 AGCA
H10 VSDO
H11 CLKOUT
H12 RXON
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
B12 SYNTHDATA
C1 GPIO10
ASDO
JTAGEN
DATA12
DATA11
RD
VDD
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
ADD2
C2 USCRTS
C3 USCTX
F2
ADD10
RAMCS
ADD0
F3
ADD14
C4 KEYPADROW2
C5 KEYPADCOL0
C6 OSC13MON
C7 GPIO4
F4
GND
DATA14
DATA7
DATA2
GPIO1
LWR
F5
ADD8
DATA5
DATA1
VDD
F6
DISPLAYCS
BSDO
F7
C8 GPIO6
F8
VDDRTC
GPIO2
SIMCLK
TMS
GND
C9 RADIOPWRCTL
C10 CALIBRATERADIO
F9
SIMSUPPLY
F10
BSCLK
EEPROMCLK
M10 SIMDATAOP
C11 SYNTHEN0
C12 OSCIN
F11
F12
ASOFS
ASCLK
J11
J12
VSFS
VSDI
M11 TCK
M12 TDI
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
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AD6426
144
109
1
108
USCRI
USCRX
USCTX
USCCTS
USCRTS
GPIO10
ADD19
ADD18
ADD17
ADD16
ADD15
ADD14
ADD13
ADD12
ADD11
AGCA
SYNTHCLK
SYNTHDATA
SYNTHEN0
SYNTHEN1
PWRON
VDDRTC
OSCOUT
OSCIN
GND
VDD
GPIO2
TXPHASE
ASDO
ASOFS
ASDI
ASCLK
BSCLK
BSDI
BSIFS
BSOFS
BSDO
CLKOUT
RXON
VBCRESET
VSCLK
AD6426
GND
VDD
ADD10
ADD9
TOP VIEW
(PINS DOWN)
BOOTCODE
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
VSDI
VSFS
VSDO
VDD
RAMCS
GND
GND
VDD
EEPROMDATA
EEPROMCLK
EEPROMEN
JTAGEN
TDI
ROMCS
DATA15
DATA14
DATA13
36
73
37
72
Figure 24: LQFP Pin Locations
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 46 -
Confidential Information
Preliminary Technical Information
AD6426
LQFP Outline Dimensions
D
A
D1
L
144
109
1
108
TQFP 144
E1
E
TOP VIEW
(PINS DOWN)
36
73
Ç
37
72
A1
A2
B
e
MILLIMETERS
TYP
INCHES
TYP
DIM
MIN
MAX
1.60
MIN
MAX
0.063
0.006
0.057
0.874
0.791
0.030
A
A1
0.05
1.35
0.15
0.002
0.053
0.858
0.783
0.019
A2
1.40
22.00
20.00
0.6
1.45
0.055
0.866
0.787
0.024
0.020
0.009
D, E
D1 , E1
L
21.80
19.90
0.5
22.20
20.10
0.75
e
0.50
0.22
B
Ç
0.17
0.27
0.08
0.007
0.011
0.003
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 47 -
Confidential Information
Preliminary Technical Information
AD6426
PBGA Outline Dimensions
D
D2
12 11 10 9 8 7 6 5 4 3
2
1
A
B
C
D
E
F
G
H
J
e
E2
E
E1
TOP VIEW
(Pins Down)
K
L
M
e
b
0.10
D1
ccc
C
//
ccc
C
//
-C-
aaa
C
A2
c
A1
A
MILLIMETERS
TYP
INCHES
TYP
DIM
MIN
MAX
MIN
MAX
A
A1
A2
D
1.42
0.30
0.75
1.65
0.40
0.90
1.80
0.50
0.97
0.05591
0.01181
0.02953
0.50590
0.06496
0.01575
0.03543
0.51181
0.07087
0.01968
0.03819
0.51772
12.85
13.00
13.15
D1
D2
E
11.00 BSC
10.75
0.43307 BSC
0.42323
9.95
12.85
11.55
13.15
0.39173
0.50591
0.45472
0.51772
13.00
0.51181
E1
E2
b
11.00 BSC
10.75
0.43307 BSC
0.42323
9.95
0.45
0.27
11.55
0.65
0.43
0.39173
0.17716
0.01063
0.45472
0.02559
0.01693
0.55
0.35
0.02165
0.01378
c
e
1.00 BSC
0.03937 BSC
aaa
bbb
ccc
0.15
0.20
0.25
0.00591
0.00787
0.00984
NOTE:
1. BSC - Between Spacing Centers
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 48 -
Confidential Information
AD6426 Data Sheet Change Summary
AD6426 Preliminary Revision 2.3
(Changes from Revision 1.0)
Number
Date
Description of Change
1
2
3
4
5
5/19/98 Motorola Serial Display mode added.
5/19/98 TXENABLE NMI function freeing up the IRQ6 pin added.
5/19/98 Dimensional tolerances for BGA package outline drawing added.
5/19/98 Memory I/F timing specs separated into characteristics and requirements.
5/19/98 Dual band control signals renamed- BANDSELECT0 is multiplexed with GPIO[2], BANDSELECT1
is multiplexed with GPIO[1]. For DB radios requiring a single Bandselect bit, BANDSELECT0 is
enabled. For DB radios requiring 2 Bandselect bits then both BANSELECT0,1 can be enabled.
These signals were previously referred to as BANDSELECT and DCSSEL.
6
7
8
5/19/98 VBC and radio I/F diagram in Figure 6 updated to show a generic DB radio I/F.
5/19/98 DAI I/F Pins updated to be consistent with DAI Box users manual.
5/19/98 GPIO[7:0] Pin functions in Mode D (Table 24) were incorrectly listed as being all Tristate outputs.
The correct function is GPIO7 = TRI and GPIO[6:0] = O.
9
5/20/98 Requirements for 32kHz crystal for slow clocking added.
10
11
5/20/98 Pin functions in Emulation mode GPO 0,6,7 in Table 24 are renamed to reserve.
5/20/98 Memory Interface Timing Specification: read timing specs changed to max with the exception of
Control Processor data hold and Parameters broken out separately into requirements and
characteristics.
12
6/9/98
In Fig 24 the following pins were incorrectly labeled and thus changed;
a) Pin 45 from HWR to UBS
b) Pin 46 from LWR to LBS
c) Pin 98 from GND to VDD
d) Pin 99 from VDD to GND
June 10, 1998
Page 1 of 2
AD6426 Data Sheet Change Summary
AD6426 Preliminary Revision 1.0
(Changes from Revision 0.1)
Number
Date
Description of Change
1
2
3
4
5
6
7
1/15/98 Dallas I/F added to Feature list.
1/15/98 Dallas I/F enable bit polarity changed from logic 1 to 0.
1/15/98 Dual Band control section added describing BANDSELECT and DCSSEL signals.
1/15/96 Serial Display Interface Timing Characteristics and Diagram added as Figure 23.
1/15/98 General Description: F7.2 data services deleted, this is not supported on the EGSMP.
1/15/98 General Description: AD6421/25 interfaces to the EGSMP.
1/15/98 Serial Display Reset signal removed from Figure 2.
Display driver chip reset input is connected to the AD6425 VBC Reset Input and both are driven by
the AD6426 VBC reset output.
8
9
1/15/98 Pin Functionality: VBCRESET added note, also used for Display Reset.
1/15/98 Pin Functionality: GPIO1 added note, alternate function DCS_ON.
1/15/98 CC Control Registers: Interrupt counter (Addr. 48) changed from 7 to 8 bits.
10
11
1/15/98 SIM Interface timing characteristics deleted - SIM signals are completely asynchronous with respect
to SIMCLK.
12
13
14
15
1/15/98 Plastic Ball Grid Array (PBGA) Package pinout and outline drawing added.
2/16/98 EVBC and radio Interface block diagram in Figure 6 updated with dual band control signals.
2/16/98 VCLKIN, Clock Input Voltage for ac-coupled sine wave input changed from 100 mVPP to 250 mVPP.
2/16/98 Added scan registers USCRX (O), USCRXEN (B), and VSDOEN (T)
Corrected output polarity in Notes to active-low (0=output).
16
17
18
19
20
2/16/98 Added H8 Control registers and register contents in Tables 3 and 4.
2/16/98 Buffered UART Register Contents added in Table 5.
2/26/98
2/26/98
2/26/98
IIH, IIL Input Current spec min -10, max 10 mA added.
IIH, IIL Input Current spec min -10, max 10 mA added.
IOZL, Low Level Output 3-State Leakage Current min 10, max 10 mA IOZH, High Level Output 3-State
Leakage Current min 10, max 10 mA.
21
22
23
2/26/98 Absolute Max ratings broken out separately for PBGA package.
2/26/98 Control Processor Data setup time changed from 10 to 68 ns.
2/26/98 Radio interface section: a reference to the TTP/Hitachi radios added “AD6426 Radio Interface
supports radio architectures based on Siemens, Philips, and TTP/Hitachi RF chipsets”.
24
25
26
2/27/98 Pin Functionality: OSC13MON pin moved from RTC section to general section.
2/27/98 Memory interface timing diagram replaced with one used in 6422 data sheet.
2/27/98 CC register 46 bits 4-7 SIMCLOCK Polarity, SIMCLOCK off. SIMCLOCK Control, STBYCLKON
removed no longer used on 6426.
27
28
29
3/9/98
3/9/98
3/9/98
CC registers 80-87 slow clocking control removed from Table 1 & 2 per TTP’s request.
Peripheral registers 83, 106-109 removed from Table 3 & 4 per TTP’s request.
All Buffered UART registers removed per TTP’s request.
June 10, 1998
Page 2 of 2
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