AD6439BS [ADI]
IC SPECIALTY TELECOM CIRCUIT, PQFP128, PLASTIC, MQFP-128, Telecom IC:Other;
| 型号： | AD6439BS |
| 厂家： | 
ADI |
| 描述： | IC SPECIALTY TELECOM CIRCUIT, PQFP128, PLASTIC, MQFP-128, Telecom IC:Other 电信 电信集成电路 |
| 文件： | 总12页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Discrete Multitone (DMT) Coprocessor
for ADSL Chipsets
a
AD6439
FEATURES
GENERAL DESCRIPTION
Component in Analog Devices’ AD20msp918 ADSL
Chipset
Designed to ANSI T1.413 Issue 2/ETSI TR238/ITU
G.992.1 and G.992.2
The AD6439 Discrete Multitone (DMT) Coprocessor is part of
Analog Devices ADSL solution, a series of flexible, standards-
based chipsets for creating high performance ADSL and SDSL
modems that implement a superset of standard Category 2
functionality.
Higher Performance
Improved Data Rates or Longer Reach
Suitable for CO or Residence (ATU-R and ATU-C)
Performs All DMT Functions and Operations
Trellis Coding
Echo Cancellation
Symmetric Transforms (512 Point)
Flexible Allocation of Tones Upstream/Downstream
Supports Symmetric Services (SDSL)
Increased Upstream (e.g., 1 Mbps)
Supports ADSL Over ISDN (Shifted U/S)
Strict Filters for Spectral Compatibility
128-Lead MQFP
A high performance alternative to the AD6436 DMT Coprocessor,
the AD6439 meets the functionality requirements of ANSI
T1.413 Category 2 (trellis coding, echo cancellation), but is
considerably more versatile. It implements both transmit and
receive paths (trellis coding/decoding, IFFT/FFT, filtering and
echo cancellation). Symmetric transforms allow flexible alloca-
tion of upstream and downstream bandwidth, including sym-
metric data rates. Improved digital filters exceed the requirements
of T1.413 and deliver strict spectral masks (e.g., for VDSL
compatibility).
–40؇C to +85؇C, 3.3 V Operation, 1.1 W
FUNCTIONAL BLOCK DIAGRAM
DIGITAL FILTER
TX PATH
FILTERS
IFFT
16
16
512/512PT
TX SERIAL
RX SERIAL
TRELLIS
AD6435
OR
AD6436
INTERFACE
FRAMER
DAC
EC
AD6440
OR
ENCODE/
DECODE
AD6437
IFFT
512/512PT
RX PATH
FILTERS
ADC
CONTROL LOGIC
DSP PORT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD6439–SPECIFICATIONS
Parameter
Value
Comments
Transmit DAC Port—Data Width
Transmit DAC Port—Rates
Receive ADC Port—Data Width
Receive ADC Port—Rates
Downstream FFT/IFFT
Upstream FFT/IFFT
Bits/Carrier (Max)
16 Bit
17.664 MHz, 8.832 MHz, 2.208 MHz
16 Bit
8.832 MHz or 2.208 MHz
512 Points
512 Points
At Either CO or RT
At Either CO or RT
256 Tones
256 Tones
15
Interface to AD6435/AD6438
Power Supply
Serial 35.328 MHz
Both Transmit and Receive
VDD
+3.0 V to +3.6 V
PDISS
Temperature Range
< 1.25 W Max at 3.6 V
–40°C to +85°C
Specifications subject to change without notice.
ELECTRICAL SPECIFICATIONS
Parameter
Typ Value
Comments
VOH
VOL
VIH
VIL
IIH
VDD – 0.4 V dc
0.4 V dc
2.0 V dc
1.0 V dc
±500 nA
±500 nA
At IOH = –0.5 mA
VIN = VDD = 3.6 V
VIN = 0 V, VDD = 3.6 V
IIL
Specifications subject to change without notice.
TIMING SPECIFICATIONS
TX TIMING
Parameter
Description
Typ
Units
tTX–SR
tTX-HR
tTX-SF
tTX-HF
Setup Time of TX_AEC[15:0] from Rising Edge of TX_CLK
Hold Time of TX_AEC[15:0] from Rising Edge of TX_CLK
Setup Time of TX_AEC[15:0] from Falling Edge of TX_CLK
Hold Time of TX_AEC[15:0] from Falling Edge of TX_CLK
12
6
12
6
ns
ns
ns
ns
TX_CLK
TX_AEC [15:0]
VALID DATA
VALID DATA
tTX-SR tTX-HR
tTX-SF tTX-HF
Figure 1. TX Timing
RX TIMING
Parameter
Description
Typ
Units
tRX–S
tRX–H
Setup Time of RX[15:0] from Rising Edge of RX_CLK
Hold Time of RX[15:0] from Rising Edge of RX_CLK
25
0
ns
ns
RX_CLK
RX[15:0]
VALID DATA
tRX-S
tRX-H
Figure 2. RX Timing
–2–
REV. 0
AD6439
TX SERIAL I/F TIMING
Parameter
Description
Typ
Units
tTFRM–DV
tTFRM–D
tTDREQ–DV
tTDREQ–H
tTBS–S
tTBS–H
tTD–S
tTD–H
TX_FRM Valid to Falling Edge of TX_RX_SCLK
Hold Time of TX_FRM from Falling Edge of TX_RX_SCLK
TX_DREQ Valid to Rising Edge of TX_RX_SCLK
Hold Time of TX_DREQ from Rising Edge of TX_RX_SCLK
Setup Time of TX_BS from Rising Edge of TX_RX_SCLK
Hold Time of TX_BS from Rising Edge of TX_RX_SCLK
Setup Time of TX_SDATA from Rising Edge of TX_RX_SCLK
Hold Time of TX_SDATA from Rising Edge of TX_RX_SCLK
5
10
5
10
10
0
10
0
ns
ns
ns
ns
ns
ns
ns
ns
TX_RX_SCLK
TX_FRM
tTFRM-DV tTFRM-H
TX_DREQ
tDREQ-DV tDREQ-H
TX_BS
tRBS-S tRBS-H
TX_SDATA
VALID DATA
tRD-S tRD-S
Figure 3. TX Serial IF Timing
RX SERIAL I/F TIMING
Parameter
Description
RX_FRM Valid to Falling Edge of TX_RX_SCLK
Hold Time of RX_FRM from Falling Edge of TX_RX_SCLK
Setup Time of RX_DREQ from Rising Edge of TX_RX_SCLK
Hold Time of RX_DREQ from Rising Edge of TX_RX_SCLK
RX_BS Valid to Rising Edge of TX_RX_SCLK
Hold Time of RX_BS from Rising Edge of TX_RX_SCLK
RX_SDATA Valid to Rising Edge of TX_RX_SCLK
Hold Time of RX_SDATA from Rising Edge of TX_RX_SCLK
Typ
Units
tRFRM-DV
tRFRM-H
tRDREQ-S
tRDREQ-H
tRBS-DV
tRBS-H
5
ns
ns
ns
ns
ns
ns
ns
ns
10
10
0
5
10
5
tRD-DV
tRD-H
10
TX_RX_SCLK
RX_FRM
tRFRM-H
tRFRM-DV
RX_DREQ
RX_BS
tRDREQ-S tRDREQ-H
tRBS-DV tRBS-H
RX_SDATA
VALID DATA
tRD-DV
tRD-H
Figure 4. RX Serial IF Timing
REV. 0
–3–
AD6439
READ OPERATION
Parameter
Description
Min
Max
Units
Timing Requirements:
tRDD
tAA
tRDH
NRD Low to Data Valid
A0–A13, NCS to Data Valid
Data Hold from NRD High
17 + W
19 + W
ns
ns
ns
0
Switching Characteristics:
tRP
NRD Pulsewidth
DSP_CLK High to NRD Low
A0–A13, NCS Setup Before NRD Low
A0–A13, NCS Hold After NRD Deasserted
NRD High to NRD or NWR Low
20 + W
3
2
5
ns
ns
ns
ns
ns
tCRD
tASR
tRDA
tRWR
16
12
NOTES
W = wait state x (DSP_CLK period).
AD6439 accesses faster than 20 MHz (DSP_CLK) requires one wait state.
DSP_CLK
A0-A13
NCS
tRDA
NRD
D
tASR
tCRD
tRWR
tRP
tRDH
tRDD
tAA
NWR
Figure 5. Read Operation
–4–
REV. 0
AD6439
WRITE OPERATION
Parameter
Description
Min
Max
Units
Switching Characteristics:
tDW
tDH
tWP
tASW
tDDR
tCWR
tAW
tWRA
tWWR
Data Setup Before NWR High
Data Hold After NWR High
NWR Pulsewidth
A0–A13, NCS Setup Before NWR Low
Data Disable Before NWR or NRD Low
DSP_CLK High to NWR Low
A0–A13, NCS Setup Before NWR Deasserted
A0–A13, NCS Hold After NWR Deasserted
NWR High to NRD or NWR Low
10 + W
6
12 + W
2
1
3
12 + W
5
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
NOTES
W = wait state x (DSP_CLK period).
AD6439 accesses faster than 20 MHz (DSP_CLK) requires one wait state.
DSP_CLK
A0–A13
NCS
tWRA
NWR
tWWR
tASW
tCWR
tWP
tAW
tDDR
tDH
D
tDW
NRD
Figure 6. Write Operation
REV. 0
–5–
AD6439
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) MQFP . . . . . . . . . . . . . . . .+280°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
128-Lead Plastic MQFP
Package Option
AD6439BS
–40°C to +85°C
S-128B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6439 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
Pin Number
Pin Name
Type
Description
1, 7, 15, 23, 30, 35, 41, 46,
51, 57, 62, 65, 69, 72, 78,
87, 95, 99, 104, 114, 125
VDD
Supply
These pins supply 3.3 V power to the AD6439.
These pins supply ground for the AD6439.
2, 8, 16, 22, 29, 34, 37, 42,
47, 52, 56, 61, 66, 70, 73,
79, 86, 94, 98, 105, 115, 124
GND
Ground
No Connection
Input
3, 39, 71, 74, 100, 101
NC
13
24
25
26
27
28
31
32
33
36
38
40
DSP_CLK
RX_FRM
RX_SDATA
RX_DREQ
RX_BS
Clock for the DSP interface.
Output
Output
Input
Frame pulse for RX serial port.
Serial data for RX serial port.
Data request for RX serial port.
Byte strobe for RX serial port.
Serial clock for TX and RX serial port.
Frame pulse for TX serial port.
Serial data for TX serial port.
Output
Output
Output
Input
TX_RX_SCLK
TX_FRM
TX_SDATA
TX_BS
Input
Byte strobe for TX serial port.
Data request for TX serial port.
Master clock (35.328 MHz).
TX_DREQ
MCLK
Output
Input
TX_CLK
Output
Output clock used to qualify valid transmit data.
43–45, 48–50, 53–55, 58–60,
63, 64, 67, 68
TX_AEC[0:15]
RX_CLK
RX(0:15)
D(0:15)
NRESET
NWR
Outputs
Output
Inputs
I/O
16-bit output for transmit and AEC data stream.
Output clock used to qualify valid receive data.
16-bit input for receive data stream.
16-bit data bus from DSP port.
75
97, 96, 93–88, 85–80, 77, 76
121–116, 113–106, 103, 102
122
Input
Input
Input
Input
Inputs
Reset pin, active low.
123
Write strobe from DSP port, active low.
Rad strobe from DSP port, active low.
Chip set from DSP port, active low.
14-bit address bus for DSP port.
126
NRD
127
NCS
128, 4–6, 9–12, 14, 17–21
A(0:13)
–6–
REV. 0
AD6439
PIN CONFIGURATION
102
101
100
99
98
97
96
95
94
1
VDD
GND
D15
PIN 1
IDENTIFIER
2
NC
3
NC
NC
4
A1
VDD
GND
RX0
5
A2
6
A3
7
VDD
RX1
8
GND
VDD
GND
RX2
9
A4
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A5
A6
RX3
A7
RX4
DSP_CLK
A8
RX5
RX6
VDD
RX7
GND
VDD
GND
RX8
A9
A10
AD6439
A11
RX9
TOP VIEW
(Not to Scale)
A12
RX10
RX11
RX12
RX13
GND
VDD
RX14
RX15
RX_CLK
NC
A13
GND
VDD
RX_FRM
RX_SDATA
RX_DREQ
RX_BS
TX_RX_SCLK
GND
GND
VDD
NC
VDD
TX_FRM
TX_SDATA
TX_BS
GND
GND
VDD
TX_AEC15
TX_AEC14
GND
VDD
VDD
TX_DREQ
GND
MCLK
NC = NO CONNECT
REV. 0
–7–
AD6439
INTRODUCTION
pins as the transmit data stream to minimize the number of pins
required by both the AD6439 and the integrated AFE (AD6440).
The AD6439 can also be connected directly to the AD6437,
however, this does not permit utilization of the analog echo
cancel function.
This data sheet describes the functionality and interfacing of
the AD6439 Discrete Multitone (DMT) Coprocessor IC. The
AD6439 is part of the Analog Devices AD20msp918 ADSL
chipset. Other components include:
• AD6438 ATM Interface and Framer IC
• AD6437 Analog Front-End IC
• AD8016 Driver/Receiver
The receive path begins with data being received by the
AD6439 from the AD6440 or AD6437 AFE. The receive data
stream is processed by the receive path filters, demodulated by
the FFT, decoded, and sent to the AD6435/AD6438. The echo
canceller provides a digital echo cancel stream used by the re-
ceive path filter section.
• ADSP-2183 System Control Processor
Figure 7 illustrates the basic interconnection between system
components.
Encoder/Decoder
The Encode/Decode block handles the QAM or Trellis encod-
ing and decoding of data.
An object code license for all modem software is supplied with
the AD20msp918 chipset.
When used as part of the AD20msp918 ADSL chipset, internal
functionality of the AD6439 is under control of the firmware
supplied with the ADSP-2183 and its MP (Messaging Protocol).
This protocol supplies a hardware-neutral method of controlling
operation of the ADSL chipset that is compatible with various
hardware implementations.
Data received from the AD6435/AD6438 as a 35.328 MHz
serial stream is fed to the encoder buffer. This block handles
encoding, bin allocation and tone reordering operations. Each
subcarrier (from 0 to 255) can handle from 0 to 15 bits, with the
density controlled by the bin allocation. This block also handles
the pilot tone insertion (Bin 64 in CO mode and Bin 16 in the
RT).
The AD6439 is a high performance version of the earlier AD6436
DMT Coprocessor IC and can be used in place of the AD6436
in applications such as the AD20msp910 ADSL chipset.
Enhancements to the AD6439 include:
The decoder is very similar, recovering the data from the
subcarriers and reversing tone ordering and bit allocation opera-
tions. It also operates the same way in CO and RT mode. The
receive serial interface between the decoder and the AD6435/
AD6438 operates at 35.328 MHz.
• Trellis Encoder and Decoder Functions Added
• POTS HPF Block Added
• Mask FIR Added
• Digital Echo Canceller Lengthened
• Analog Echo Canceller Block added (Requires AD6440 Chip)
• Standby operation Mode Added
QAM encoding corresponds to the “Tone Ordering” and “Con-
stellation Encoder and Gain Scaling” blocks in the T1.413
reference model.
• Symmetric FFT and IFFT Operations Performed
IFFT Block
The IFFT block performs a 512-point inverse FFT in CO mode
(transmitting the downstream data) and in RT mode (transmit-
ting the upstream data). It also implements gain-scaling at the
same time.
AD6439
DMT/
COPROCESSOR
AD6438
INTERFACE/
FRAMER
AD6437
AFIC
DATA
TO HYBRID TX
POTS SPLITTER
AD8016
DRIVER
While data is being read out of the IFFT block and into the
digital filter section, the cyclic prefix is added to the transmit
path. The purpose of the cyclic prefix is to make the symbol
appear periodic in nature to the receiver. The IFFT produces
512 real data samples, to which 32 samples are added.
TO RAM
(INTERLEAVE)
ADSP-2183
PROCESSOR
CONTROL
MESSAGES
TO BOOT FLASH
OR P FOR IDMA
Figure 7. Block Diagram AD20msp918 Chipset
FFT Block
On the receive channel, the FFT block performs a 512-point
FFT in CO mode (receiving the upstream duplex data) and in
RT mode (receiving the downstream simplex data). In addition,
carriers can be scaled up to provide full precision for the FDQ
and QAM or Trellis decode operations. After the transform, the
FFT performs the FDQ decode operation in the output buffer.
In addition to performing the FFT, this block also strips off
cyclic prefixes and removes pilot tones from the symbol.
FUNCTIONAL DESCRIPTION
The AD6439 performs encoding and decoding operations,
frequency domain equalization (FDQ), FFT/IFFT operations,
and a number of digital filter functions, including interpolation/
decimation and Time-Domain Equalization (TDQ). It is de-
signed to Category 1 of the ANSI/ETSI standard and relies on
Frequency Division Multiplexing (FDM) to separate upstream
and downstream signals of up to 256 tones.
Digital Filter Block
The AD6439 consists of six major blocks: a serial interface
block, a Trellis/QAM encoder/decoder block, an IFFT block, a
digital filter (DFIC) block, and a DSP interface and control
block (see Figure 8).
This implements a variety of digital filtering operations, includ-
ing Time Domain Equalization (TDQ) and the interpolation/
decimation tasks that connect the digital devices to the analog
stage (AD6437/AD6440).
The transmit path starts with serial data received from the
AD6435/AD6438. This data is encoded (QAM or Trellis),
modulated (IFFT), processed by the digital filter section, and
output to the AD6440 or AD6437. It is also used by the echo
canceller block to produce an Analog Echo Cancel (AEC) data
stream. The AEC data stream is multiplexed on the same output
The echo cancellation filter improves system performance by
easing the task of the FDM separation filter, reducing the effect
of sidelobes in FFT, and reducing the size of the guardband. It
also improves line matching.
–8–
REV. 0
AD6439
TX SERIAL I/F
TX_DREQ
TX_BS
IFFT
TX PATH FILTERS
TX/AEC I/F
TX_SDATA
TX_AEC[15:0]
TX_CLK
TX_FRM
TX_RX_SCLK
TX_FRM
DIGITAL
FILTER
BLOCK
TRELLIS
OR QAM
ECHO
CANCELLER
IF
ENCODER/
DECODER
RX SERIAL I/F
RX_DREQ
RX_BS
ADC I/F
RX[15:0]
RX_CLK
FFT
RX PATH FILTERS
RX_SDATA
A[13:0]
D[15:0]
NRD
NWR
NCS
DSP I/F
AND CONTROL
DSP
PORT
DSP_CLK
MCLK
NRESET
Figure 8. Block Diagram
The AD6439 includes logic for a parallel transmit path to gener-
ate an echo-cancellation signal, which operates with a second
DAC in the AD6440 codec in the analog domain to implement
Category 2 overlapping spectra.
interfaces, and a DSP host port to allow a DSP to monitor sig-
nals and control the data through the device. The analog echo
canceller interface is identical to the DAC interface.
TX Serial Interface
NB Data Width
The TX serial interface between the AD6439 and the AD6435/
AD6438 uses five signals:
The AD6436 uses 16-bit datapaths internally. As such, it can
take full advantage of high resolution analog stages with up to
16-bit resolution. Note: The AD6437/AD6440 (companion part
in the AD20msp918 chipset) is only specified to 12-bit linearity.
TX_RX_SCLK:
TX_DREQ:
TX_FRAME:
TX_BS:
Serial clock provided by AD6439
Data request provided by AD6439
Frame strobe provided by AD6439
Byte strobe provided by AD6435/AD6438
Serial data provided by AD6435/AD6438
INTERFACE TIMING
TX_SDATA:
The AD6439 contains a transmit serial port which accepts a bit
stream from an AD6435/AD6438, a receive serial port that
sends a bit stream to an AD6435/AD6438, ADC and DAC
Figure 9 shows the timing of the TX interface signals.
AD6439 VIEW
TX_RX_SCLK
TX_DREQ
TX_BS
TX_SDATA
B7
T2
B6
T3
B5
B2
B1
B0
T5
B7
T0
T1
T4
AD6435/AD6438 VIEW
TX_RX_SCLK
TX_DREQ
TX_BS
B7
B6
B5
B2
B1
B0
B7
TX_SDATA
NOTE: DATA IS PASSED MSB FIRST
Figure 9. TX Serial Port Timing
–9–
REV. 0
AD6439
This is a byte protocol. The AD6439 raises TX_DREQ on the
falling edge of TX_RX_SCLK to request data (ref T0). The
AD6435/AD6438 samples the TX_DREQ on its rising clock
and when seen, outputs a one clock byte strobe TX_BS (ref T1)
and simultaneously places Bit 7 of the byte on the TX_SDATA
pin. Then, on the next seven rising clocks the AD6435/AD6438
places Bits 6 through 0 on the TX_SDATA pin.
RX Serial Interface
The RX serial interface between the AD6439 and AD6435/
AD6438 uses five signals:
TX_RX_SCLK: Serial clock provided by AD6439
RX_FRAME:
RX_BS:
TX_SDATA:
RX_DREQ:
Frame strobe provided by AD6439
Byte strobe provided by AD6439
Serial data provided by AD6439
On the next rising clock, the TX_DREQ line is again sampled
(ref T5) and, if it is high and another byte is ready to transmit,
outputs the byte strobe coincident with the MSB of the next
byte then proceeds to output the rest of the byte in successive
clock cycles. If TX_DREQ were low, or another byte was not
available yet, the byte strobe would not be output, and TX_DREQ
would continue to be sampled on successive rising clock edges
while waiting for available data. The AD6435/ AD6438 is free
to place Bit 7 of a byte on the TX_SDATA pin even if the
AD6439 will not be taking it, as long as the byte strobe is not
pulsed. Once the byte strobe is pulsed for Bit 7, the TX_DREQ
line is ignored until all 8 bits are sent.
Data request provided by AD6435/AD6438
Figure 10 shows the timing of the RX interface port signals.
This is a byte protocol. The AD6435/AD6438 raises RX_DREQ
on the rising edge of TX_RX_SCLK to request data (ref T0).
The AD6439 samples the RX_DREQ on its rising clock and,
when seen, outputs a one clock byte strobe RX_BS (ref T1),
and at the same time places Bit 7 of the byte on the RX_SDATA
pin. On the next seven rising clocks, the AD6439 places Bits 6
through 0 on the RX_SDATA pin. As the last bit is output, the
RX_DREQ line is again sampled (ref T5), and if high, and
another byte is ready to transmit, outputs the byte strobe coinci-
dent with the MSB of the next byte, then proceeds to output the
remainder of the byte in successive clock cycles.
Once TX_DREQ is raised, the AD6439 leaves TX_DREQ high
and samples TX_BS on successive rising edges of the clock. Once
TX_BS is seen high (ref T2), the AD6439 knows that Bit 7 can
be sampled, followed by the remaining seven bits on the next
seven rising clocks edges (ref T3). If desired, the TX_DREQ can
be dropped at this time.
If RX_DREQ were low, or another byte not yet available, the
byte strobe would not be output, and RX_DREQ would con-
tinue to be sampled on successive rising clock edges while wait-
ing for available data. The AD6439 is free to place Bit 7 of the
next byte on the pin even if RX_DREQ is low, as long the byte
strobe is not pulsed. Once the byte strobe is pulsed for Bit 7, the
RX_DREQ line is ignored until all eight bits are sent.
On the falling edge after Bit 1 has been sampled (ref T4), the
AD6439 must raise or lower the TX_DREQ line depending on
whether it knows it wants another byte immediately following
the current byte. This timing is needed to ensure the AD6435/
AD6438 can detect the TX_DREQ signal as it outputs the last
bit.
Once RX_DREQ is raised, The AD6435/AD6438 leaves
RX_DREQ high and samples RX_BS on successive falling
edges of the clock. Once RX_BS is seen high (ref T2), the
AD6435/AD6438 samples Bit 0 and knows that the data bits
can be sampled on the next 7 falling clocks edges (ref T3). If
desired, the RX_DREQ can be dropped at this time. When Bit
1 is being sampled (ref T4), the AD6435/AD6438 must raise or
lower the RX_DREQ line depending on whether it knows it
wants another byte immediately following the current byte. This
timing is needed to ensure the AD6439 can detect the RX_DREQ
signal on the rising edge after the last bit.
The TX_FRAME signal, which is not shown, is output by the
AD6439 on the rising edge of TX_RX_SCLK to signify the
start of a frame. The AD5435/AD5438 does not respond to
the TX_DREQ line before the start of a frame, or after the
number of data bytes programmed by the DSP has been trans-
ferred within a frame.
AD6439 VIEW
TX_RX_SCLK
RX_DREQ
RX_BS
RX_SDATA
B7
T2
B6
T3
B5
B2
B1
B0
B7
T0
T1
T4
T5
INTERFACE FRAMER VIEW
TX_RX_SCLK
RX_DREQ
RX_BS
B7
B6
B5
B2
B1
B0
B7
RX_SDATA
NOTE: DATA IS PASSED MSB FIRST
Figure 10. RX Serial Port Timing
–10–
REV. 0
AD6439
Because of the direction of the clock skew, this protocol allows
up to one full cycle of skew less some period for settling round
trip timing (AD6439 to AD6435/AD6438 and back, or vice-
versa). The main difference from the TX path is that the data
and RX_BS are sampled by the AD6435/AD6438 on the falling
clock edge because of the known direction of clock skew. The
time from data request to Bit 7 being received is only one clock
(assuming the AD6439 has data ready), so even for the worst
case of 9 clocks per byte, the time to transmit a full frame is less
than 97 µs, which should be within the safe window for the
AD6439.
ADC Interface
The AD6439 includes an interface that accepts 16 bits (RX[15:0])
from an A/D converter (see Figure 8 for the location of this
block). The sample rate is 8.832 MHz, but if the Dec4 block is
bypassed, the rate is only 2.208 MHz. Signal RX_CLK qualifies
when the A/D converter needs to provide valid data. The AD6439
normally assumes that input data is in unsigned binary format,
however, it can also be programmed to received twos comple-
ment binary data.
DSP Port
The AD6439 includes a DSP port consisting of a 14-bit address
bus A[13:0], a 16-bit data bus D[15:0], three bus control pins,
NRD, NWR, NCS, and a clock, DSP_CLK. (See Figure 8 for
the location of this block and Figure 12 for signal details). The
DSP port allows a 2183 DSP to access the AD6439.
The RX_FRAME signal, which is not shown, is output by the
AD6439 on the rising edge of TX_RX_SCLK to indicate the
start of a frame. The AD6435/AD6438 does not raise the
RX_DREQ line before the start of a frame, or after the number
of data bytes programmed by the DSP has been received within
a frame.
ADDR[13:0]
DATA[15:0]
ADDR[13:0]
DATA[15:0]
DAC Interface
The AD6439 provides 16 bits (TX[15:0]) to a Tx A/D con-
verter and 16 bits (AEC[15:0]) to the AEC A/D (see Figure 8
for the location of this block and Figure 11 for signal timing).
These two buses are muxed onto one 16-bit output bus provided
to the analog front end (AD6437, AD6440). The TX_CLK
signal accompanying the 16-bit data bus qualifies TX and AEC
data.
ADSP-2183
AD6439
DSP_CLK
IOMSN
RDN
DSP_CLK
CSN
RDN
WRN
WRN
Figure 12. ADSP-2183 AD6439 Interface
PIN DESCRIPTION
The AD6439 carries 79 signal pins (24 output pins, 39 input
pins, and 16 bidirectional pins) and 43 supply pins. See Figure
13 (Functional Diagram), Pin Configuration and Pin Function
Description) for details.
The output bus always provides valid tx sample data on the
rising edge of TX_CLK and valid AEC sample data on the
falling of TX_CLK. During normal operation, the TX and AEC
output sample rates are 17.664 MHz, therefore, on the output
data bus, the rate is 35.328 MHz and TX_CLK is 17.664 MHz.
TX and AEC data can be down sampled to 8.832 MHz, in
which case the output data bus has a rate of 17.664 MHz and
the TX_CLK signal is 8.832 MHz. The TX Int8 and AEC Int8
blocks can also be bypassed, making the TX and AEC data rate
only 2.208 MHz, the output bus rate 4.416 MHz and the
TX_CLK signal 2.208 MHz. Data sent out is unsigned, how-
ever the AD6439 can be programmed to send out twos comple-
ment binary data.
TX_DREQ
TX_BS
TX_SDATA
TX_FRM
TX_AEC[15:0]
TX_CLK
TX_RX_SCLK
AD6439
RX_DREQ
RX_BS
RX_SDATA
Note that TX and AEC paths must always be in the same mode.
They are either both in normal mode, both in downsample
mode, or both in bypass mode.
RX[15:0]
RX_FRM
RX_CLK
MCLK
NRESET
Figure 13. Functional Pin Diagram
35.328MH
Z
TX_CLK
AEC0
TX0
AEC1
TX1
AEC2
TX2
AEC3
TX3
TX_AEC[15:0]
Figure 11. TX_AEC Mux Bus in Normal Operation
REV. 0
–11–
AD6439
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
128-Lead MQFP Plastic Quad Flatpack
(S-128B)
0.685 (17.40)
0.677 (17.20)
0.669 (17.00)
0.555 (14.10)
0.551 (14.00)
0.547 (13.90)
0.093 (2.35)
MAX
0.041 (1.03)
0.035 (0.88)
0.031 (0.78)
128
1
103
102
SEATING
PLANE
0.791 (20.10)
0.787 (20.00)
0.783 (19.90)
TOP VIEW
(PINS DOWN)
0.921 (23.40)
0.913 (23.20)
0.906 (23.00)
0.003 (0.08)
MAX
38
39
65
64
0.010 (0.25)
MAX
0.011 (0.27)
0.009 (0.22)
0.007 (0.17)
0.020 (0.50)
BSC
0.083 (2.10)
0.079 (2.00)
0.075 (1.90)
–12–
REV. 0
相关型号：
AD644JH
DUAL OP-AMP, 3500uV OFFSET-MAX, 2MHz BAND WIDTH, MBCY8, HERMETIC SEALED, METAL CAN, TO-99, 8 PIN
ROCHESTER
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