AD6630R/PCB [ADI]
Differential, Low Noise IF Gain Block with Output Clamping; 差，低噪声中频增益模块具有输出钳位
| 型号： | AD6630R/PCB |
| 厂家： | 
ADI |
| 描述： | Differential, Low Noise IF Gain Block with Output Clamping |
| 文件： | 总8页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Differential, Low Noise IF Gain
Block with Output Clamping
a
AD6630
FUNCTIONAL BLOCK DIAGRAM
AD6630
FEATURES
24 dB Gain
4 dB Noise Figure
Easy Match to SAW Filters
Output Limiter Adjustable +8.5 dBm to +12 dBm
700 MHz Bandwidth
10 V Single or Dual 5 V Power Supply
300 mW Power Dissipation
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
NC
NC
IP2
IP1
IP1
CD1
OP
+
+
+
V
EE
CMD
OP
IP2
APPLICATIONS
ADC IF Drive Amp
Communications Receivers
PCS/Cellular Base Stations
GSM, CDMA, TDMA
CLLO
CD2
CLHI
V
CC
NC = NO CONNECT
PRODUCT DESCRIPTION
GSM to CDMA to AMPS. The clamping circuitry also main-
tains the phase integrity of an overdriven signal. This allows
phase demodulation of single carrier signals with an overrange
signal.
The AD6630 is an IF gain block designed to interface between
SAW filters and differential input analog-to-digital converters.
The AD6630 has a fixed gain of 24 dB and has been optimized
for use with the AD6600 and AD6620 in digitizing narrowband
IF carriers in the 70 MHz to 250 MHz range.
While the AD6630 is optimized for use with the AD6600 Dual
Channel, Gain Ranging ADC with RSSI, it can also be used in
many other IF applications. The AD6630 is designed with an
input impedance of 200 Ω and an output of 400 Ω. In the typi-
cal application shown below, these values match the real portion
of a typical SAW filter. Other devices can be matched using
standard matching network techniques.
Taking advantage of the differential nature of SAW filters, the
AD6630 has been designed as a differential in/differential out
gain block. This architecture allows 100 dB of adjacent channel
blocking using low cost SAW filters. The AD6630 provides
output limiting for ADC and SAW protection with Ͻ10° phase
variation in recovery from overdrive situations.
The AD6630 is built using Analog Devices’ high speed comple-
mentary bipolar process. Units are available in a 300 mil SOIC
(16 leads) plastic surface mount package and specified to operate
over the industrial temperature range (–40°C to +85°C).
Designed for “narrow-band” cellular/PCS receivers, the high
linearity and low noise performance of the AD6630 allows for
implementation in a wide range of applications ranging from
AD6630
MAIN
LOCAL
OSCILLATOR
AD6600
AD6620
DSP
AD6630
DIVERSITY
Figure 1. Reference Design
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
AD6630–SPECIFICATIONS
NORMAL OPERATING CONDITIONS
Parameter (Conditions)
Min
8.5
Typ
Max
10.5
5.25
–4.25
+85
Units
V
SINGLE SUPPLY VOLTAGE
POSITIVE SUPPLY VOLTAGE
NEGATIVE SUPPLY VOLTAGE
AMBIENT TEMPERATURE
PACKAGE THERMAL RESISTANCE
OPERATING FREQUENCY1
4.25
–5.25
–40
5.0
V
–5.0
V
°C
80
°C/W
MHz
70
250
(TMIN = –40؇C, TMAX = +85؇C. Output dc levels are nominally at VM, where VM = VCC + VEE = [+5 V + (–5 V)] = 0.
Inputs should be AC coupled.)
DC SPECIFICATIONS
Test
Level
Parameter
Temp
Full
Min
Typ
Max
48
Units
mA
SUPPLY CURRENT
OUTPUT DC LEVEL
II
30
Full
II
VM–150
VM+150
mV
(TMIN = –40؇C, TMAX = +85؇C. All AC production tests are performed at 5 MHz. 70 MHz and 250 MHz
performance limits are correlated to 5 MHz testing based on characterization data.)
AC SPECIFICATIONS
Test
Parameter1
Temp
Full
Level
Min
23
Typ
24
Max
25
Units
GAIN (POWER) @ 70 MHz
II
dB
GAIN (POWER) @ 250 MHz
–3 dB BANDWIDTH
OUTPUT REFERRED IP3 @ 70 MHz2
OUTPUT REFERRED IP3 @ 250 MHz2
OUTPUT REFERRED IP2 @ 70 MHz2
OUTPUT REFERRED IP2 @ 250 MHz2
Full
II
22
23
24
dB
+25°C
Full
V
700
22
MHz
dBm
dBm
dBm
dBm
V
Full
V
19
Full
V
45
Full
V
45
OUTPUT REFERRED 1 dB COMPRESSION POINT
@ 70 MHz LOW LEVEL CLAMP3
Full
Full
Full
II
II
II
8.5
7.5
11
9
dBm
dBm
dBm
OUTPUT REFERRED 1 dB COMPRESSION POINT
@ 250 MHz LOW LEVEL CLAMP3
OUTPUT REFERRED 1 dB COMPRESSION POINT
@ 70 MHz HIGH LEVEL CLAMP4
OUTPUT REFERRED 1 dB COMPRESSION POINT
@ 250 MHz HIGH LEVEL CLAMP4
Full
II
V
dBm
V/µs
Ω
OUTPUT SLEW RATE
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
3700
200
2
INPUT IMPEDANCE (REAL)
V
INPUT CAPACITANCE
V
pF
OUTPUT IMPEDANCE (REAL)
V
400
2
Ω
OUTPUT CAPACITANCE
V
pF
NOISE FIGURE
V
4
dB
LOW LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz3, 5
HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 70 MHz4, 5
LOW LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz3, 5
IV
IV
IV
11
12.5
14.3
10.6
dBm
dBm
dBm
Full
13.8
9.25
Full
–2–
REV. 0
AD6630
Test
Level
Parameter
Temp
Full
Min
Typ
11.2
9
Max
12.2
Units
dBm
Degree
dB
HIGH LEVEL CLAMP MAXIMUM OUTPUT @ 250 MHz4, 5
PHASE VARIATION6
CMRR7
IV
V
+25°C
+25°C
+25°C
V
50
PSRR8
V
30
dB
NOTES
1All specifications are valid across the operating frequency range when the source and load impedance are a conjugate match to the amplifier’s input and output
impedance.
2Test is for two tones separated by 1 MHz for IFs at 70 MHz and 250 MHz at –23 dBm per tone input.
3Low Level Clamp is selected by connecting pin CLLO to the negative supply, while pin CLHI is left floating. Clamping can be set at lower levels by connecting pin
CLLO and CLHI to the negative supply through an external resistor.
4High Level Clamp is selected by connecting pin CLHI to the negative supply, while pin CLLO is left floating, this allows the maximum linear range of the device to
be utilized.
5Output clamp levels are measured for hard clamping with a +3 dBm input level. Valid for a maximum input level of +8 dBm/200 Ω = 3.2 V p-p—differential.
6Measured as the change in output phase when the input level is changed from –53 dBm to +8 dBm (i.e., from linear operation to clamping).
7Ratio of the differential output signal (referenced to the input) to the common-mode input signal presented to all input pins.
8Ratio of signal on supply to differential output (<500 kHz).
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
ABSOLUTE MAXIMUM RATINGS
I. 100% production tested.
Parameter
Min
Max
Units
II. 100% production tested at +25°C, and guaranteed by
Single Supply Voltage
Positive Supply Voltage
Negative Supply Voltage
Input Power
Storage Temperature
Junction Temperature
ESD Protection
–0.5
–0.5
–5.75
11.5
5.75
0.5
+8
+150
+150
V
V
V
dBm
°C
°C
kV
design and analysis at temperature extremes.
III. Sample tested only.
IV. Parameter guaranteed by design and analysis.
V. Parameter is typical value only.
–65
1
VI. 100% production tested at +25°C, and sample tested at
temperature extremes.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD6630AR
AD6630AR-REEL
AD6630R/PCB
–40°C to +85°C (Ambient)
–40°C to +85°C (Ambient)
16-Lead Wide Body SOIC
AD6630AR on 1000 PC Reel
Evaluation Board with AD6630AR
R-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6630 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD6630
PIN FUNCTION DESCRIPTION
PIN CONFIGURATION
Pin No
Pin Name
Description
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
NC
IP2
IP1
V
CC
1, 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
IP2
IP1
IP1
No Connect
Input
Input
Input
Input
Clamp Level Low Pin
Clamp Level High Pin
+VCC Supply
Clamp Decoupling
Output
DC Feedback Decoupling
–VEE Supply
Output
CD1
OP
AD6630
TOP VIEW
(Not to Scale)
V
EE
IP2
CMD
IP1
IP2
CLLO
CLHI
VCC
CD2
OP
CMD
VEE
OP
CD1
VCC
OP
CLLO
CLHI
CD2
V
CC
NC = NO CONNECT
Clamp Decoupling
+VCC Supply
Typical Performance Characteristics
13
12
11
10
24
23
22
21
20
19
18
17
16
HIGH CLAMP
LOW CLAMP
9
8
70
100
300
70
100
300
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 2. 3rd Order Intercept (IP3) vs. Frequency
Figure 4. 1 dB Compression Point (Typical)
25
14
13
12
11
10
9
–40؇C
24
HIGH CLAMP
+25؇C
+85؇C
23
LOW CLAMP
22
70
100
300
70
100
300
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 3. Gain vs. Frequency
Figure 5. Clamp Level vs. Frequency
–4–
REV. 0
AD6630
–1dB 15dB –9dB –2dB 15dB –5dB 24dB –5dB
MAIN
9dBm
4dBm
–15dBm
–28dBm –29dBm –14dBm –23dBm–25dBm–10dBm
LOCAL
OSCILLATOR
AD6600
AD6620
DSP
AD6630
SAW
SAW
DIVERSITY
ANTENNA
–104dBm
–43dBm
–28dBm
–16dBm
–15dBm
AD6630 INPUT
–91dBm
–30dBm
–15dBm
–3dBm
AD6630 OUTPUT
–67dBm
–6dBm
AD6600 INPUT
–71dBm
–10dBm
+4dBm
+9dBm
+9dBm
+9dBm
+4dBm
+4dBm
–2dBm
Figure 6. GSM Design Example
This equation is derived from measured data at 170 MHz. Clamp
levels vary with frequency, see Figure 5. Output clamp levels
less than 8.5 dBm will result in damage to the clamp circuitry
unless the absolute maximum input power is derated. Similarly,
the output clamp level cannot be set higher than 12 dBm.
THEORY OF OPERATION
The AD6630 amplifier consists of two stages of gain. The first
stage is differential. This differential amplifier provides good
common-mode rejection to common-mode signals passed by
the SAW filter. The second stage consists of matched current
feedback amplifiers on each side of the differential pair. These
amplifiers provide additional gain as well as output drive capa-
bility. Gain set resistors for these stages are internal to the de-
vice and cannot be changed, allowing fixed compensation for
optimum performance.
R
CLAMP
GENERATOR
V
EE
Figure 7. Clamp Level Resistor
Matching SAW Filters
The AD6630 is designed to easily match to SAW filters. SAW
filters are largely capacitive in nature. Normally a conjugate
match to the load is desired for maximum power transfer.
Clamping levels for the device are normally set by tying CLLO
or CLHI pins to the negative supply. This internally sets bias
points that generate symmetric clamping levels. Clamping is
achieved primarily in the output amplifiers. Additional input
stage clamping is provided for additional protection. Clamping
levels may be adjusted to lower levels as discussed below.
Another way to treat the problem is to make the SAW filter look
purely resistive. If the SAW filter load looks resistive there is no
lead or lag in the current vs. voltage. This may not preserve
maximum power transfer, but maximum voltage swing will
exist. All that is required to make the SAW filter input or output
look real is a single inductor shunted across the input. When the
correct value is used, the impedance of the SAW filter becomes
real.
APPLICATIONS
The AD6630 provides several useful features to meet the needs
of radio designers. The gain and low noise figure of the device
make it perfect for providing interstage gain between differential
SAW filters and/or analog-to-digital converters (ADC). Addi-
tionally, the on-board clamping circuitry provides protection for
sensitive SAW filters or ADCs. The fast recovery of the clamp
circuit permits demodulation of constant envelope modulated
IF signals by preserving the phase response during clamping.
9.7⍀
The following topics provide recommendations for using the
AD6630 in narrowband, single carrier applications.
400⍀
47nH
3pF
15.2pF
Adjusting Output Clamp Levels
Normally, the output clamp level is set by tying either CLLO or
CLHI to ground or VEE. It is possible to set the limit between
8.5 dBm and 12 dBm levels by selecting the appropriate exter-
nal resistor.
Figure 8. Saw Filter Model (170 MHz)
EVALUATION BOARD
To set to a different level, CLLO and CLHI should be tied
together and then through a resistor to ground. The value of the
resistor can be selected using the following equation.
Figures 9, 10 and 12 refer to the schematic and layout of the
AD6630AR as used on Analog Devices’ GSM Diversity Re-
ceiver Reference Design (only the IF section is shown). Figure
14 references the schematic of the stand-alone AD6630 evalua-
tion board and uses a similar layout. The evaluation board uses
center tapped transformers to convert the input to a differential
signal and AD6630 outputs to a single connector to simplify
evaluation. C8, C9 and L2 are optional reactive components to
tune the load for a particular IF frequency if desired.
14.4–OUTPUT
R =
CLAMP (dBm)
0.0014
REV. 0
–5–
AD6630
+10V
U100A
NC1
V
1
CC
SMA
CHNA
NC2
IP2
CD1
OP
L1A
C2
L1
11
12
5
6
V
V
I
O
C100
11
12
5
V
V
V
C1
SAW1
GND
0.1F
I
O
IP1
V
EE
TO
AD6600
L2
L4
L6
IP1B
IP2B
CL1
CL2
CMD
OPB
CD2
SAW2
GND
C101
0.1F
V
V
I
O
6
V
I
O
C104
1
2
3
4
7
8
9
10
0.1F
V
2
1
2 3 4 7 8 9 10
CC
C103
0.1F
AD6630
C102
0.1F
Figure 9. Reference Design Schematic (One Channel)
Figure 10. Reference Design PCB Layout
Figure 12. Reference Design Component Placement (Two
Channels Shown)
OUTPUT
AMP
V
+
CC
+
–
+
DIFF
200⍀
200⍀
200⍀
AMP
IP1
IP1
OUTPUT
AMP
–
TO OUTPUT
AMPLIFIER
TO OUTPUT
AMPLIFIER
BIAS
–
200⍀
IP2
IP2
CLP
CLHI
CLAMP
V
GENERATOR CLN
EE
CLLO
Figure 13. Equivalent Input Circuit
Figure 11. Functional Block Diagram
–6–
REV. 0
AD6630
J1
PCTB3
3
2
1
C13
1F
AGND
J3
C18
1F
1
2
+
–
AGND
+
–
11
2
C16
10nF
AGND
C21
10nF
AGND
C17
R3
10nF
1
R1
200⍀
J6
SMA
TP1
2
1
AGND
TEST P
AD6630
C15
1nF
C10
U1
100nF
16
1
15
1
2
3
4
5
C2
V
NC1
NC2
IP2
CC
10nF
10nF
C5
AGND
CD1
OP
T2
T1
14
13
12
11
10
9
J8
SMA
1
1
J7
SMA
3
2
4
6
C12
10nF
1
3
6
4
2
2
IP1
V
EE
2
L1
470nH
C8
C9
L2
10nF
10nF
C6
C7
IP1B
IP2B
CL1
CL2
CMD
OPB
CD2
C11
10nF
1
6
7
TC4–1W
AT224
TC 8-1
AT224
C1
10nF
AGND
AGND
C3
10nF
8
AGND
V
2
TP2
CC
1
C14
1nF
C4
100nF
TEST P
J2
R2
200⍀
C20
1nF
AGND
C19
100nF
AGND
AGND
Figure 14. Evaluation Board Schematic
Table I. Typical S Parameters
Frequency
(MHz)
S11
S12
S21
S22
70
224.5 –4.52°
–41.0 –3.0°
–31.4 0°
–41.0 –5°
–40.6 –2.3°
24.1 –8.8°
23.5 –22.5°
23.2 –26.4°
22.9 –38.9°
394.3 –8.6°
382.4 –21.9°
353.0 –25.4°
328.9 –29.2°
170
200
250
264.8 –32.9°
227.9 –34.8°
209.5 –36.2°
REV. 0
–7–
AD6630
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Wide Body SOIC
(R-16)
0.4133 (10.50)
0.3977 (10.00)
16
9
1
8
0.1043 (2.65)
0.0926 (2.35)
PIN 1
0.0291 (0.74)
0.0098 (0.25)
x 45؇
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
8؇
0؇
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
–8–
REV. 0
相关型号：
AD6634XBC
IC TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196, 15 X 15 MM, BGA-196, Cellular Telephone Circuit
ADI
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