AD6688-3000EBZ_技术文档

RF Diversity and 1.2 GHz Bandwidth

Observation Receiver

AD6688

Data Sheet

Two Integrated wideband digital processors per channel

FEATURES

48-bit NCO

JESD204B (Subclass 1) coded serial digital outputs

Support for lane rates up to 16 Gbps per lane

1.7 W total power per channel at 3 GSPS (default settings)

Performance at −2 dBFS amplitude, 2.6 GHz input

SFDR = 70 dBFS

NSD = −148.0 dBFS/Hz

Performance at −9 dBFS amplitude, 2.6 GHz input

SFDR = 75 dBFS

4 cascaded half band filters

Phase coherent NCO switching

Up to 4 channels available

Serial port control

Integer clock divide by 2 and divide by 4

Flexible JESD204B lane configurations

On-chip dither

NSD = −151.4 dBFS/Hz

Integrated input buffer

APPLICATIONS

Diversity multiband, multimode digital receivers

3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A

DOCSIS 3.0 CMTS upstream receive paths

HFC digital reverse path receivers

Noise density = −152.0 dBFS/Hz

0.975 V, 1.9 V, and 2.5 V dc supply operation

9 GHz analog input full power bandwidth (−3 dB)

Amplitude detect bits for efficient AGC implementation

FUNCTIONAL BLOCK DIAGRAM

AVDD1

(0.975V)

AVDD2

(1.9V)

AVDD3

(2.5V)

AVDD1_SR

(0.975V)

DVDD

DRVDD1

(0.975V)

DRVDD2

(1.9V)

SPIVDD

(1.9V)

(0.975V)

BUFFER

SIGNAL PROCESSING

VIN+A

VIN–A

ADC

DIGITAL DOWN CONVERSION

SERDOUT0±

SERDOUT1±

SERDOUT2±

SERDOUT3±

SERDOUT4±

SERDOUT5±

SERDOUT6±

SERDOUT7±

DIGITAL DOWN CONVERSION

JESD204B

FAST

SIGNAL

MONITOR

DATA

ROUTER

MUX

DATA

ROUTER

MUX

LINK

AND

8

DETECT

TX

OUTPUTS

PDWN/

STBY

BUFFER

VIN+B

VIN–B

VREF

ADC

GPIO_A0/GPIO_A1 GPIO_B0/GPIO_B1

NCO BAND SELECT

SYNCINB±

FD_A/GPIO_A0

GPIO_A1

CLOCK

DISTRIBUTION

CLK+

CLK–

JESD204B

SUBCLASS1

CONTROL

GPIO MUX

FD_B/GPIO_B0

GPIO_B1

AD6688

SPI CONTROL

÷2

÷4

AGND

SYSREF±

SDIO SCLK CSB

DGND

DRGND

Figure 1.

Rev. 0

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Tel: 781.329.4700

Technical Support

www.analog.com

AD6688

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

DDC Gain Stage ......................................................................... 59

DDC Complex to Real Conversion ......................................... 59

DDC Mixed Decimation Settings ............................................ 60

DDC Example Configurations ................................................. 62

DDC Power Consumption........................................................ 65

Signal Monitor ................................................................................ 66

SPORT Over JESD204B ............................................................ 67

Digital Outputs ............................................................................... 69

Introduction to the JESD204B Interface ................................. 69

JESD204B Overview .................................................................. 69

Functional Overview ................................................................. 70

JESD204B Link Establishment ................................................. 70

Physical Layer (Driver) Outputs .............................................. 72

f_S× 4 Mode................................................................................... 72

Setting Up the AD6688 Digital Interface................................ 74

Deterministic Latency.................................................................... 79

Subclass 0 Operation.................................................................. 79

Subclass 1 Operation.................................................................. 79

Multichip Synchronization............................................................ 81

Normal Mode.............................................................................. 81

Timestamp Mode ....................................................................... 81

SYSREF Input.............................................................................. 82

SYSREF Setup/Hold Window Monitor................................. 85

Latency............................................................................................. 87

End to End Total Latency.......................................................... 87

Example Latency Calculations.................................................. 87

LMFC-Referenced Latency....................................................... 87

Test Modes....................................................................................... 89

ADC Test Modes ........................................................................ 89

JESD204B Block Test Modes .................................................... 90

Serial Port Interface........................................................................ 92

Configuration Using the SPI..................................................... 92

Hardware Interface..................................................................... 92

SPI Accessible Features.............................................................. 92

Memory Map .................................................................................. 93

Reading the Memory Map Register Table............................... 93

Memory Map Register Details.................................................. 94

Applications Information ............................................................ 136

Power Supply Recommendations........................................... 136

Layout GuideLines ................................................................... 137

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

Product Highlights ........................................................................... 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

AC Specifications.......................................................................... 7

Digital Specifications ................................................................... 9

Switching Specifications ............................................................ 10

Timing Specifications ................................................................ 11

Absolute Maximum Ratings.......................................................... 12

Thermal Resistance .................................................................... 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

Typical Performance Characteristics ........................................... 16

Equivalent Circuits ......................................................................... 21

Theory of Operation ...................................................................... 25

ADC Architecture ...................................................................... 25

Analog Input Considerations.................................................... 25

Voltage Reference ....................................................................... 29

DC Offset Calibration................................................................ 30

Clock Input Considerations ...................................................... 30

Power-Down/Standby Mode..................................................... 32

Temperature Diode .................................................................... 32

ADC Overrange and Fast Detect.................................................. 34

ADC Overrange.......................................................................... 34

Fast Threshold Detection (FD_A and FD_B) ........................ 34

ADC Application Modes and JESD204B Tx Converter

Mapping ........................................................................................... 35

Programmable FIR Filters ............................................................. 37

Supported Modes........................................................................ 37

Programming Instructions........................................................ 40

Digital Downconverter (DDC)..................................................... 42

DDC I/Q Input Selection .......................................................... 42

DDC I/Q Output Selection ....................................................... 42

DDC General Description ........................................................ 42

DDC Frequency Translation..................................................... 45

DDC Decimation Filters............................................................ 53

Rev. 0 | Page 2 of 138

Data Sheet

AD6688

AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8)........... 137

Outline Dimensions..................................................................... 138

Ordering Guide .........................................................................138

REVISION HISTORY

4/2017—Revision 0: Initial Version

Rev. 0 | Page 3 of 138

AD6688

Data Sheet

GENERAL DESCRIPTION

The AD6688 is a 1.2 GHz bandwidth, mixed-signal, direct radio

frequency (RF) sampling receiver. It consists of two 14-bit,

3.0 GSPS analog-to-digital converters (ADCs) and various

digital signal processing blocks consisting of four wideband

digital downconverters (DDCs). The AD6688 has an on-chip

buffer and a sample-and-hold circuit designed for low power,

small size, and ease of use. This product is designed to support

communications applications capable of direct sampling wide

bandwidth analog signals of up to 5 GHz. The 3 dB bandwidth

of the ADC input is greater than 9 GHz. The AD6688 is

optimized for wide input bandwidth, high sampling rate,

excellent linearity, and low power in a small package.

threshold indicator has low latency, the user can quickly turn

down the system gain to avoid an overrange condition at the

ADC input. Besides the fast detect outputs, the AD6688 also

offers signal monitoring capability. The signal monitoring block

provides additional information about the signal being digitized

by the ADC.

The user can configure the Subclass 1 JESD204B-based high

speed serialized output in a variety of one-lane, two-lane, four-

lane, six-lane, and eight-lane configurations, depending on the

DDC configuration and the acceptable lane rate of the receiving

logic device. Multidevice synchronization is supported through

the SYSREF and SYNCINB input pins.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations. The analog input and clock signals

are differential inputs. The ADC data outputs are internally

connected to four DDCs through a crossbar mux. Each DDC

consists of up to five cascaded signal processing stages: a 48-bit

numerically controlled oscillator (NCO) and up to four half-

band decimation filters. The NCO has the option to select

preset bands over the general-purpose input/output (GPIO)

pins, which enables selection of up to three bands. Operation of

the AD6688 between the DDC modes is selectable via SPI-

programmable profiles.

The AD6688 has flexible power-down options that allow

significant power savings when desired. All of these features can

be programmed using a 3-wire serial port interface (SPI).

The AD6688 is available in a Pb-free, 196-ball BGA specified

over the −40°C to +85°C ambient temperature range. This

product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

1. Wide full power bandwidth supports IF sampling of signals

up to 9 GHz (−3 dB point).

2. Four integrated wide-band decimation filter and NCO

blocks supporting multiband receivers.

3. Fast NCO switching enabled through GPIO pins.

4. Flexible SPI controls various product features and functions

to meet specific system requirements.

5. Programmable fast overrange detection and signal

monitoring.

6. On-chip temperature diode for system thermal

management.

In addition to the DDC blocks, the AD6688 has several

functions that simplify the automatic gain control (AGC)

function in a communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect control bits in Register 0x0245 of the

ADC. If the input signal level exceeds the programmable

threshold, the fast detect indicator goes high. Because this

7. 12 mm × 12 mm, 196-ball BGA.

Rev. 0 | Page 4 of 138

Data Sheet

AD6688

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,

SPIVDD = 1.9 V, sampling rate = 3000 MHz, 1.7 V p-p full-scale differential input, input amplitude (A_IN) = −2.0 dBFS, L = 8, M = 2, F = 1,

−10°C ≤ T_J≤ +120°C¹, unless otherwise noted. Typical specifications represent performance at T_J= 70°C (T_A= 25°C).

Table 1.

Parameter

Min

Typ

Max

Unit

RESOLUTION

14

Bits

ACCURACY

No Missing Codes

Offset Error

Offset Matching

Gain Error

Gain Matching

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Guaranteed

0

%FSR

LSB

−5.89

−2.9

−0.63

−26

1

+5.89

+2.9

+0.74

+21

0.2

0.4

6

LSB

15

440

0.5

ppm/°C

V

Gain Error

INTERNAL VOLTAGE REFERENCE

ANALOG INPUTS

Differential Input Voltage Range

Common-Mode Voltage (V_CM

Differential Input Resistance

1.7

1.35

200

0.25

−7

V p-p

V

Ω

pF

dB

)

1.32

1.52

Differential Input Capacitance

Differential Input Return Loss at 2.1 GHz²

−3 dB Bandwidth

POWER SUPPLY

AVDD1

AVDD2

AVDD3

AVDD1_SR

DVDD

DRVDD1

DRVDD2

SPIVDD

I_AVDD1

9

GHz

0.95

1.85

2.44

0.95

1.85

0.975

1.9

2.5

0.975

1.9

1.0

V

mA

1.95

2.56

1.0

1.95

765

885

120

50

1020

590

35

1.9

640

790

110

24

480

320

30

I_AVDD2

I_AVDD3

I_{AVDD1_SR}

I_DVDD

I_DRVDD1

3

I_DRVDD2

I_SPIVDD

1

5

Rev. 0 | Page 5 of 138

AD6688

Data Sheet

Parameter

Min

Typ

Max

Unit

POWER CONSUMPTION

Total Power Dissipation (Including Output Drivers)⁴

Power-Down Dissipation

Standby⁵

3.3

300

1.65

W

mW

¹Junction temperature (T_J) range of −10°C to +120°C translates to an ambient temperature range of −40°C to+85°C.

²For more information, see the Analog Input Considerations section.

³All lanes running. Power dissipation on DRVDD1 changes with lane rate and number of lanes used.

⁴Default mode. No DDCs used.

⁵Can be controlled by SPI.

Rev. 0 | Page 6 of 138

Data Sheet

AD6688

AC SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,

SPIVDD = 1.9 V, sampling rate = 3000 MHz, 1.7 V p-p full-scale differential input, DDC decimation ratio = 8, −10°C ≤ T_J≤ +120°C¹,

unless otherwise noted. Typical specifications represent performance at T_J= 70°C (T_A= 25°C).

Table 2.

A_IN= −2 dBFS

A_IN= −9 dBFS

Parameter²

Min

Typ

1.7

Max

Min

Typ

1.7

Max

2.04

Unit

V p-p

dB

ANALOG INPUT FULL SCALE (DIFFERENTIAL)

NOISE FIGURE

1.1

2.04

1.1

24.5

NOISE SPECTRAL DENSITY (NSD)

Input Frequency (f_IN) = 10 MHz, A_IN= −30 dBFS (2.04 V p-p)

f_IN= 10 MHz, A_IN= −30 dBFS

f_IN= 255 MHz

f_IN= 950 MHz

f_IN= 1870 MHz

−153.6

−152.0

−151.5

−150.5

−149.9

−149.7

−148.0

−153.6

−152.0

−151.9

−151.8

−151.4

dBFS/Hz

f_IN= 2170 MHz

f_IN= 2600 MHz

−143.9

IN-BAND SIGNAL-TO-NOISE RATIO (SNR)³

f_IN= 950 MHz, NCO Tuning Frequency = 942.5 MHz

f_IN= 1870 MHz, NCO Tuning Frequency = 1842.0 MHz

f_IN= 2170 MHz, NCO Tuning Frequency = 2140.0 MHz

f_IN= 2600 MHz, NCO Tuning Frequency = 2655.0 MHz

IN-BAND SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)³

f_IN= 950 MHz, NCO Tuning Frequency = 942.5 MHz

f_IN= 1870 MHz, NCO Tuning Frequency = 1842.0 MHz

f_IN= 2170 MHz, NCO Tuning Frequency = 2140.0 MHz

f_IN= 2600 MHz, NCO Tuning Frequency = 2655.0 MHz

65.8

65.2

65.0

63.4

67.7

67.2

67.1

66.7

dBFS

65.6

65.1

64.8

63.2

67.7

67.1

67.0

66.5

dBFS

SPURIOUS FREE DYNAMIC RANGE (SFDR), SECOND OR

THIRD HARMONIC⁴

f_IN= 950 MHz

f_IN= 1870 MHz

f_IN= 2170 MHz

f_IN= 2600 MHz

71

69

67

70

78

76

73

75

dBFS

51

IN-BAND SPURIOUS FREE DYNAMIC RANGE (SFDR),

WORST HARMONIC⁵

f_IN= 950 MHz, NCO Tuning Frequency = 942.5 MHz

f_IN= 1870 MHz, NCO Tuning Frequency = 1842.0 MHz

f_IN= 2170 MHz, NCO Tuning Frequency = 2140.0 MHz

f_IN= 2600 MHz, NCO Tuning Frequency = 2655.0 MHz

WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC⁶

f_IN= 950 MHz

71

90

88

89

91

96

92

dBFS

−86

−84

−83

−79

−95

−94

−90

dBFS

f_IN= 1870 MHz

f_IN= 2170 MHz

f_IN= 2600 MHz

−66

Rev. 0 | Page 7 of 138

AD6688

Data Sheet

A_IN= −2 dBFS

Typ

A_IN= −9 dBFS

Parameter²

Min

Max

Min

Typ

Max

Unit

TWO-TONE INTERMODULATION DISTORTION (IMD),

A

_IN1AND A_IN2= −15.0 dBFS

f_IN1= 1.841 GHz, f_IN2= 1.846 GHz;

NCO Frequency = 1874.28 MHz

N/A⁷

96

dBFS

CROSSTALK⁸

ANALOG INPUT BANDWIDTH, FULL POWER⁹

>90

5

>90

5

dB

GHz

¹Junction temperature (T_J) range of −10°C to +120°C translates to an ambient temperature range of −40°C to +85°C.

²See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

³In-band SNR is dependent on the DDC decimation ratio (DCM) and is calculated by |NSD| = |SNR| + 10 × log(f_S/(2 × DCM)), where f_S= ADC sample clock rate.

⁴SFDR is specified with DDCs bypassed.

⁵In-band SFDR is defined as the worst spur within the alias protected bandwidth of the DDC outputs. When DDCs are enabled, SFDR changes with DDC decimation

settings, NCO frequency, and overall frequency plan.

⁶Worst other harmonic is specified with DDCs bypassed.

⁷N/A means not applicable.

⁸Crosstalk is measured at 950 MHz with a −2.0 dBFS analog input on one channel, and no input on the adjacent channel.

⁹Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.

Rev. 0 | Page 8 of 138

Data Sheet

AD6688

DIGITAL SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,

SPIVDD = 1.9 V, sampling rate = 3000 MHz, 1.7 V p-p full-scale differential input, A_IN= −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ T_J≤ +120°C¹,

unless otherwise noted. Typical specifications represent performance at T_J= 70°C (T_A= 25°C).

Table 3.

Parameter

Min

Typ

LVDS/LVPECL

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Differential Input Return Loss at 3 GHz²

SYSREF INPUTS (SYSREF+, SYSREF−)

Logic Compliance

300

800

0.675

106

0.9

1800

mV p-p

V

Ω

pF

dB

−9.4

LVDS/LVPECL

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance (Differential)

400

800

0.675

18

1800

2.0

mV p-p

V

kΩ

pF

1

LOGIC INPUT (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0,

FD_B/GPIO_B0, GPIO_A1, GPIO_B1)

Logic Compliance

CMOS

Logic 1 Voltage

Logic 0 Voltage

0.65 × SPIVDD

0

V

0.35 × SPIVDD

Input Resistance

30

kΩ

LOGIC OUTPUT (SDIO, FD_A, FD_B)

Logic Compliance

CMOS

Logic 1 Voltage (I_OH= 4 mA)

Logic 0 Voltage (I_OL= 4 mA)

SYNCIN INPUT (SYNCINB+/SYNCINB−)

Logic Compliance

SPIVDD − 0.45V

0

V

0.45

LVDS/LVPECL

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

400

800

0.675

18

1800

2.0

mV p-p

V

kΩ

pF

1

SYNCINB+ INPUT

Logic Compliance

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

CMOS

2.6

0.9 × DRVDD1

2 × DRVDD1

V

0.1 × DRVDD1

V

kΩ

DIGITAL OUTPUTS (SERDOUTx , x = 0 TO 7)

Logic Compliance

Differential Output Voltage

Differential Termination Impedance

SST

560

100

360

80

770

120

mV p-p

Ω

¹Junction temperature (T_J) range of −10°C to +120°C translates to an ambient temperature range of −40°C to+85°C.

²Reference impedance = 100 Ω.

Rev. 0 | Page 9 of 138

AD6688

Data Sheet

SWITCHING SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,

SPIVDD = 1.9 V, sampling rate = 3000 MHz, 1.7 V p-p full-scale differential input, A_IN= −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ T_J≤ +120°C¹,

unless otherwise noted. Typical specifications represent performance at T_J= 70°C (T_A= 25°C).

Table 4.

Parameter

Min

Typ

Max

Unit

CLOCK

Clock Rate (at CLK+/CLK− Pins)

Sample Rate²

Clock Pulse Width High

Clock Pulse Width Low

OUTPUT PARAMETERS

Unit Interval (UI)³

Rise Time (t_R) (20% to 80% into 100 Ω Load)

Fall Time (t_F) (20% to 80% into 100 Ω Load)

Phase-Locked Loop (PLL) Lock Time

Data Rate per Channel (NRZ)⁴

LATENCY⁵

3

6

GHz

MSPS

ps

2500

161.29

3000

166.67

3100

192.31

ps

62.5

66.67

26

5

15

592.6

ps

ms

Gbps

1.6875

16

Pipeline Latency

Fast Detect Latency

75

26

Clock cycles

WAKE-UP TIME

Standby

Power-Down

400

15

µs

ms

NCO CHANNEL SELCTION TO OUTPUT

APERTURE

8

Clock cycles

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

Out of Range Recovery Time

250

55

1

ps

fs rms

Clock cycles

¹Junction temperature (T_J) range of −10°C to +120°C translates to an ambient temperature range of −40°C to+85°C.

²The maximum sample rate is the clock rate after the divider.

³Baud rate = 1/UI. A subset of this range can be supported.

⁴Default L = 8. This number can be changed based on the sample rate and decimation ratio.

⁵No DDCs used. L = 8, M = 2, F = 1.

Rev. 0 | Page 10 of 138

Data Sheet

AD6688

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Min

Typ

Max

Unit

CLK+ to SYSREF+ TIMING REQUIREMENTS

t_{SU_SR}

t_{H_SR}

Device clock to SYSREF+ setup time

Device clock to SYSREF+ hold time

−65

95

ps

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_ACCESS

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

Minimum period that SCLK must be in a logic high state

Minimum period that SCLK must be in a logic low state

Maximum time delay between falling edge of SCLK and

output data valid for a read operation

2

40

2

ns

10

6

10

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to 10

an input relative to the SCLK rising edge

ns

Timing Diagrams

CLK–

CLK+

t_{SU_SR}

t_{H_SR}

SYSREF–

SYSREF+

Figure 2. SYSREF Setup and Hold Timing

t_DS

t_HIGH

t_CLK

t_ACCESS

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

DON’T CARE

R/W

A14

A13

A12

A11

A10

A9

A8

A7

DON’T CARE

SDIO DON’T CARE

D5

D4

D3

D2

D1

D0

Figure 3. SPI Timing Diagram

Rev. 0 | Page 11 of 138

AD6688

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 6.

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to

PCB thermal design is required.

Parameter

Rating

Electrical

AVDD1 to AGND

AVDD1_SR to AGND

AVDD2 to AGND

AVDD3 to AGND

DVDD to DGND

DRVDD1 to DRGND

DRVDD2 to DRGND

SPIVDD to DGND

AGND to DRGND

AGND to DGND

DGND to DRGND

VIN x to AGND

1.05 V

2.0 V

2.70 V

1.05 V

2.0 V

Table 7. Thermal Resistance

Package Type

BP-196-4¹

θ_JA

θ_{JC_TOP}Ψ_JB

5.44

Ψ_JT

Unit

16.26 1.4

1.68

°C/W

¹Test Condition 1: Thermal impedance simulated values are based on JEDEC

2S2P thermal test board with 190 thermal vias. See JEDEC JESD51.

ESD CAUTION

−0.3 V to +0.3 V

AGND − 0.3 V to AVDD3 + 0.3 V

AGND − 0.3 V to AVDD1 + 0.3 V

DGND − 0.3 V to SPIVDD + 0.3 V

2.5 V

CLK to AGND

SCLK, SDIO, CSB to DGND

PDWN/STBY to DGND

SYSREF to AGND

SYNCINB to DRGND

2.5 V

Junction Temperature Range (T_J) −40°C to +125°C

Storage Temperature Range,

Ambient (T_A)

−65°C to +150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. 0 | Page 12 of 138

Data Sheet

AD6688

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

1

AVDD2

AVDD1

AGND

CLK+

CLK–

AGND

AVDD1

AVDD2

A

B

C

D

E

F

1

AVDD2

AVDD3

VIN–B

VIN+B

AVDD3

AGND

AVDD2

AGND

AVDD1

AGND

AVDD1

AGND

VREF

AGND

AVDD1

AGND

AVDD1

AGND

AVDD2

AGND

AVDD2

AVDD3

VIN–A

VIN+A

AVDD3

AGND

1

2

AGND

2

AVDD1_SR

AGND

SYSREF+ SYSREF–

AGND

G

H

J

3

AGND

CSB

AGND

SDIO

AGND

K

L

FD_B/

PDWN/

STBY

FD_A/

GPIO_A0

DGND

GPIO_B1

SPIVDD

SCLK

SPIVDD

DRGND

GPIO_A1

DRVDD1

DGND

GPIO_B0

DRGND

DGND

DVDD

DGND

DVDD

DRGND

DRVDD1

DRGND

DRVDD2

DVDD

M

N

SERDOUT7+ SERDOUT6+ SERDOUT5+ SERDOUT4+ SERDOUT3+ SERDOUT2+ SERDOUT1+ SERDOUT0+

SERDOUT7– SERDOUT6– SERDOUT5– SERDOUT4– SERDOUT3– SERDOUT2– SERDOUT1– SERDOUT0–

DRGND SYNCINB+

SYNCINB–

DVDD

DRGND

DVDD

P

1

DENOTES CLOCK DOMAIN.

DENOTES SYSREF± DOMAIN.

DENOTES ISOLATION DOMAIN.

2

3

Figure 4. Pin Configuration (Top View)

Rev. 0 | Page 13 of 138

AD6688

Data Sheet

Table 8. Pin Function Descriptions¹

Pin No.

Mnemonic

Type

Description

Power Supplies

A3, A12, B3, B12, C3, C12

A4, A5, A10, A11, B4, B11

AVDD1

AVDD1²

Power

Analog Power Supply (0.975 V Nominal).

Analog Power Supply for the Clock Domain (0.975 V

Nominal).

A1, A2, A13, A14, B1, B2, B13, B14,

C1, C2, C13, C14

AVDD2

Power

Analog Power Supply (1.9 V Nominal).

D1, D14, G1, G14

E7

L3, L10

M14, N1, N2, N14, P1, P2, P14

M5 to M8, M11

M13

B5, B10, C4, C5, C10, C11, D2 to D6,

D9 to D13, E2 to E5, E9 to E13,

F2 to F6, F9 to F13, G2 to G13,

H1 to H9, H11 to H14, J1 to J14

AVDD3

Power

Ground

Analog Power Supply (2.5 V Nominal).

AVDD1_SR

SPIVDD

DVDD

DRVDD1

DRVDD2

AGND

Analog Power Supply for SYSREF (0.975 V Nominal).

Digital Power Supply for SPI (1.9 V Nominal).

Digital Power Supply (0.975 V Nominal).

Digital Driver Power Supply (0.975 V Nominal).

Digital Driver Power Supply (1.9 V Nominal).

Analog Ground. These pins connect to the analog

ground plane.

A6, A9, B6 to B9, C6 to C9, D7, D8

E6, E8

K1 to K14

AGND²

AGND³

AGND⁴

DGND

Ground

Ground Reference for Clock Domain.

Ground Reference for SYSREF .

Isolation Ground.

Digital Control Ground Supply. These pins connect to

the digital ground plane.

L1, L12 to L14, M1, M2

M3, M4, M9, M10, M12, N3, N12,

P3, P12

DRGND

Ground

Digital Driver Ground Supply. These pins connect to

the digital driver ground plane.

Analog

E1, F1

E14, F14

A7, A8

H10

VIN−B, VIN+B

VIN−A, VIN+A

CLK+, CLK−

VREF

Input

Input/DNC

ADC B Analog Input Complement/True.

ADC A Analog Input Complement/True.

Clock Input True/Complement.

0.50 V Reference Voltage Input/Do Not Connect. This

pin is configurable through the SPI as a no connect or

an input. Do not connect this pin if using the internal

reference. This pin requires a 0.50 V reference voltage

input if using an external voltage reference source.

CMOS Inputs/Outputs

L2

L4

L9

L11

GPIO_B1

Input/Output

GPIO B1.

FD_B/GPIO_B0

FD_A/GPIO_A0

GPIO_A1

Fast Detect Outputs for Channel B/GPIO B0.

Fast Detect Outputs for Channel A/GPIO A0.

GPIO A1.

Digital Inputs

F7, F8

SYSREF+, SYSREF−

Input

Active High JESD204B LVDS System Reference Input

True/Complement.

N13

P13

SYNCINB+

SYNCINB−

Input

Active Low JESD204B LVDS/CMOS Sync Input True.

Active Low JESD204B LVDS Sync Input Complement.

Data Outputs

N4, P4

N5, P5

N6, P6

N7, P7

N8, P8

N9, P9

N10, P10

N11, P11

SERDOUT7+, SERDOUT7− Output

SERDOUT6+, SERDOUT6− Output

SERDOUT5+, SERDOUT5− Output

SERDOUT4+, SERDOUT4− Output

SERDOUT3+, SERDOUT3− Output

SERDOUT2+, SERDOUT2− Output

SERDOUT1+, SERDOUT1− Output

SERDOUT0+, SERDOUT0− Output

Lane 7 Output Data True/Complement.

Lane 6 Output Data True/Complement.

Lane 5 Output Data True/Complement.

Lane 4 Output Data True/Complement.

Lane 3 Output Data True/Complement.

Lane 2 Output Data True/Complement.

Lane 1 Output Data True/Complement.

Lane 0 Output Data True/Complement.

Rev. 0 | Page 14 of 138

Data Sheet

AD6688

Pin No.

Mnemonic

Type

Description

Digital Controls

L8

PDWN/STBY

Input

Power-Down Input (Active High). The operation of

this pin depends on the SPI mode and can be

configured as power-down or standby.

L5

L6

L7

CSB

SCLK

SDIO

Input

Input/Output

SPI Chip Select (Active Low).

SPI Serial Clock.

SPI Serial Data Input/Output.

¹See the Theory of Operation section and Applications Information section for more information on isolating the planes for optimal performance.

²Denotes clock domain.

³Denotes SYSREF domain.

⁴Denotes isolation domain.

Rev. 0 | Page 15 of 138

AD6688

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,

SPIVDD = 1.9 V, sampling rate = 3000 MHz, 1.7 V p-p full-scale differential input, DDC decimation rate = 8, default buffer current settings,

T_A= 25°C, 128,000 FFT sample, unless otherwise noted. See Table 10 for the recommended settings.

0

A

= –2dBFS

A

= –9dBFS

IN

NSD = –150.4dBFS/Hz

NSD = –151.9dBFS/Hz

–15

IN-BAND SNR = 65.8dBFS

IN-BAND SFDR = 71dBFS

BUFFER CURRENT = 500µA

IN-BAND SNR = 67.2dBFS

IN-BAND SFDR = 96dBFS

BUFFER CURRENT = 500µA

–30

–45

–60

–75

–90

–105

–120

–135

–105

–120

–135

–184.32 –138.24 –92.16 –46.08

0

46.08

92.16

138.24 184.32

–184.32 –138.24 –92.16 –46.08

0

46.08

92.16

138.24 184.32

FREQUENCY (MHz)

Figure 5. Single-Tone FFT at f_IN= 960 MHz, NCO Frequency = 942.5 MHz,

_IN= −2 dBFS, f_S= 2.94912 GHz

Figure 8. Single-Tone FFT at f_IN= 1870 MHz, NCO Frequency = 1842 MHz,

_IN= −9 dBFS; f_S= 2.94912 GHz

A

0

–15

0

–15

A

= –9dBFS

A

= –2dBFS

IN

NSD = –152.3dBFS/Hz

NSD = –149.7dBFS/Hz

IN-BAND SNR = 67.7dBFS

IN-BAND SFDR = 95dBFS

BUFFER CURRENT = 500µA

IN-BAND SNR = 65.1dBFS

IN-BAND SFDR = 88dBFS

BUFFER CURRENT = 500µA

–30

–45

–60

–75

–90

–105

–120

–135

–105

–120

–135

–138.24 –92.16 –46.08

0

46.08

92.16

138.24 184.32

–184.32

–184.32 –138.24 –92.16 –46.08

0

46.08

92.16

138.24 184.32

FREQUENCY (MHz)

Figure 9. Single-Tone FFT at f_IN= 2170 MHz, NCO Frequency = 2140 MHz,

_IN= −2 dBFS; f_S= 2.94912 GHz

Figure 6. Single-Tone FFT at f_IN= 960 MHz, NCO Frequency = 942.5 MHz,

_IN= −9 dBFS; f_S= 2.94912 GHz

A

0

–15

0

–15

A

= –9dBFS

A

= –2dBFS

IN

NSD = –151.8dBFS/Hz

NSD = –149.9dBFS/Hz

IN-BAND SNR = 67.1dBFS

IN-BAND SFDR = 89dBFS

BUFFER CURRENT = 500µA

IN-BAND SNR = 65.2dBFS

IN-BAND SFDR = 90dBFS

BUFFER CURRENT = 500µA

–30

–45

–60

–75

–90

–105

–120

–135

–105

–120

–135

–184.32 –138.24 –92.16 –46.08

0

46.08

92.16

138.24 184.32

–184.32 –138.24 –92.16 –46.08

0

46.08

92.16

138.24 184.32

FREQUENCY (MHz)

Figure 10. Single-Tone FFT at f_IN= 2170 MHz, NCO Frequency = 2140 MHz,

_IN= −9 dBFS; f_S= 2.94912 GHz

Figure 7. Single-Tone FFT at f_IN= 1870 MHz, NCO Frequency = 1842 MHz,

_IN= −2 dBFS; f_S= 2.94912 GHz

A

Rev. 0 | Page 16 of 138

Data Sheet

AD6688

0

90

80

70

60

50

40

30

20

10

0

A

= –2dBFS

IN

NSD = –148.0dBFS/Hz

–15

–30

IN-BAND SNR = 63.4dBFS

IN-BAND SFDR = 89dBFS

BUFFER CURRENT = 500µA

–45

–60

–75

–90

–105

–120

–135

–9dBFS

–2dBFS

155 455 755 1055 1355 1655 1955 2255 2555 2855 3205 3505 3805

–184.32 –138.24 –92.16 –46.08

0

46.08

92.16

138.24 184.32

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

Figure 11. Single-Tone FFT at f_IN= 2690 MHz, NCO Frequency = 2655 MHz,

_IN= −2 dBFS; f_S= 2.94912 GHz

Figure 14. SFDR vs. f_IN; A_IN= −2 dBFS and −9 dBFS

A

0

–15

0

A

= –2dBFS

–9dBFS

–2dBFS

IN

NSD = –148.0dBFS/Hz

IN-BAND SNR = 63.4dBFS

IN-BAND SFDR = 89dBFS

BUFFER CURRENT = 500µA

–10

–20

–30

–40

–50

–60

–70

–80

–30

–45

–60

–75

–90

–105

–120

–135

155 455 755 1055 1355 1655 1955 2255 2555 2855 3205 3505 3805

–184.32 –138.24 –92.16 –46.08

0

46.08

92.16

138.24 184.32

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

Figure 12. Single-Tone FFT at f_IN= 2690 MHz, NCO Frequency = 2655 MHz,

_IN= −2 dBFS; f_S= 2.94912 GHz

Figure 15. Second Harmonic Distortion (HD2) vs. f_IN

_IN= −2 dBFS and −9 dBFS

;

A

–150.0

–150.2

–150.4

–150.6

–150.8

–151

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–9dBFS

–2dBFS

–151.2

–151.4

–151.6

–151.8

–152.0

155 455 755 1055 1355 1655 1955 2255 2555 2855 3205 3505 3805

155 455 755 1055 1355 1655 1955 2255 2555 2855 3155 3455 3755

INPUT FREQUENCY (MHz)

Figure 13. NSD vs. f_IN; A_IN= −9 dBFS

Figure 16. Third Harmonic Distortion (HD3) vs. f_IN

_IN= −2 dBFS and −9 dBFS

;

A

Rev. 0 | Page 17 of 138

AD6688

Data Sheet

A

AND A

= –15dBFS

A

AND A

= –15dBFS

IN2

IN1

IN2

IN1

–10

–30

–10

–30

NCO FREQUENCY = 2176.9MHz

SFDR = 94dBFS

SFDR = 96dBFS

IMD2 = 115dBFS

IMD3 = 96dBFS

–50

–70

–90

–110

–130

–187.5 –150.0 –112.5 –75.0 –37.5

0

37.5

75.0 112.5 150.0 187.5

–187.5 –150.0 –112.5 –75.0 –37.5

0

37.5

75.0 112.5 150.0 187.5

FREQUENCY (MHz)

Figure 17. Two-Tone FFT; f_IN1= 1841.5 MHz, f_IN2= 1846.5 MHz;

NCO Frequency = 1874.28 MHz; f_S= 3 GHz

Figure 20. Two-Tone FFT; f_IN1= 1800 MHz, f_IN2= 2100 MHz

NCO Frequency = 2176.92 MHz; f_S= 2.94912 GHz

0

A

AND A = –15dBFS

IN2

IN1

IMD3 (dBFS)

IMD3 (dBc)

SFDR (dBFS)

SFDR (dBc)

–10

–30

SFDR = 94dBFS

IMD2 = 115dBFS

IMD3 = 94dBFS

–20

–40

–50

–60

–70

–80

–90

–110

–130

–100

–120

–187.5 –150.0 –112.5 –75.0 –37.5

0

37.5

75.0 112.5 150.0 187.5

–95 –89 –83 –77 –71 –65 –59 –53 –47 –41 –35 –29 –23 –17 –11 –7

INPUT AMPLITUDE (dBFS)

FREQUENCY (MHz)

Figure 18. Two-Tone FFT; f_IN1= 2137.5 MHz, f_IN2= 2142.5 MHz

NCO Frequency = 2176.92 MHz; f_S= 3 GHz

Figure 21. Two-Tone SFDR/IMD3 vs. Input Amplitude with

f

_IN1= 1841.5 MHz, f_IN2= 1846.5 MHz

A

AND A

= –15dBFS

0

–20

IN1

IN2

–10

–30

IMD3 (dBFS)

NCO FREQUENCY = 1874.28MHz

SFDR = 80dBFS

IMD3 (dBc)

SFDR (dBFS)

SFDR (dBC)

–40

–50

–70

–60

–90

–80

–110

–130

–100

–120

–187.5 –150.0 –112.5 –75.0 –37.5

0

37.5

75.0 112.5 150.0 187.5

–11 –7

–95 –89 –83 –77 –71 –65 –59 –53 –47 –41 –35 –29 –23 –17

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 19. Two-Tone FFT; f_IN1= 1800 MHz, f_IN2= 2100 MHz

NCO Frequency = 1874.28 MHz; f_S= 2.94912 GHz

Figure 22. Two-Tone SFDR/IMD3 vs. Input Amplitude with

_IN1= 2137.5 MHz, f_IN2= 2142.5 MHz

f

Rev. 0 | Page 18 of 138

Data Sheet

AD6688

110

100

90

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

80

70

60

50

40

30

TOTAL POWER (W)

AVDD1 + AVDD2 + AVDD3 POWER (W)

DVDD + SPIVDD POWER (W)

DRVDD1 + DRVDD2 POWER (W)

20

10

0

–10

–20

–30

–40

SNR (dBc)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

–95 –89 –83 –77 –71 –65 –59 –53 –47 –41 –35 –29 –23 –17 –11 –5 –1

INPUT AMPLITUDE (dBFS)

–10

0

10 20 30 40 50 60 70 80 90 100 110 120

(°C)

T

J

Figure 23. SNR/SFDR vs. Input Amplitude, f_IN= 950 MHz

Figure 26. Power vs. Junction Temperature, f_IN= 950 MHz

110

–148.0

–148.5

–149.0

–149.5

–150.0

–150.5

–151.0

–151.5

–152.0

200mV p-p

500mV p-p

1000mV p-p

1200mV p-p

1500mV p-p

1800mV p-p

2000mV p-p

100

90

80

70

60

50

40

30

20

10

0

–10

–20

–30

–40

SNR (dBc)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

–95 –89 –83 –77 –71 –65 –59 –53 –47 –41 –35 –29 –23 –17 –11 –5 –1

255

655 1055 1455 1855 2255 2655 3055 3455 3855

ANALOG INPUT FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 24. SNR/SFDR vs. Input Amplitude, f_IN= 1800 MHz

Figure 27. NSD vs. Analog Input Frequency vs. Various Clock Amplitude in

Differential Voltages, A_IN= −9 dBFS

80

–146.5

SNR (dBFS)

SFDR (dBFS)

AIN = –9dBFS

AIN = –2dBFS

–147.0

–147.5

–148.0

–148.5

–149.0

–149.5

–150.0

–150.5

–151.0

–151.5

–152.0

75

70

65

60

55

50

–10

0

10 20 30 40 50 60 70 80 90 100 110 120

(°C)

2400

2500

2600

2700

2800

2900

3000

3100

T

SAMPLE FREQUENCY (MHz)

J

Figure 25. SNR/SFDR vs. Junction Temperature, f_IN= 950 MHz, A_IN= −9 dBFS

Figure 28. NSD vs. Sample Frequency (f_S)

_IN= 1.8 GHz; A_IN= −2 dBFS

f

Rev. 0 | Page 19 of 138

AD6688

Data Sheet

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

80000

70000

60000

50000

40000

30000

20000

10000

0

5.6LSBRMS

AVDD1 + AVDD2 + AVDD3 POWER

DVDD + SPIVDD POWER

DRVDD1 + DRVDD2 POWER

TOTAL POWER

0

2400

2500

2600

2700

2800

2900

3000

3100

SAMPLE FREQUENCY (MHz)

OUTPUT CODE

Figure 31. Input Referred Noise Histogram

Figure 29. Power Dissipation vs. Sample Frequency (f_S)

_IN= 1.8 GHz; A_IN= −2 dBFS

f

–3

–4

–5

–6

–7

–8

–9

–10

–11

–12

–13

–14

–15

100

2100

4100

6100

8100

10100

12100

FREQUENCY (MHz)

Figure 30. Input Bandwidth (see Figure 46 for Input Configuration)

Rev. 0 | Page 20 of 138

Data Sheet

AD6688

EQUIVALENT CIRCUITS

AVDD3

VIN+x

0.3pF

AVDD3

100Ω

V

CM

BUFFER

AVDD3

VIN–x

A

IN

CONTROL

(SPI)

0.3pF

Figure 32. Analog Inputs

AVDD1

CLK+

106Ω

AVDD1

CLK–

16kΩ

V

= 0.65V

CM

Figure 33. Clock Inputs

Rev. 0 | Page 21 of 138

AD6688

Data Sheet

AVDD1_SR

100Ω

10kΩ

SYSREF+

1.9pF

130kΩ

LEVEL

TRANSLATOR

V

= 0.65V

CM

AVDD1_SR

100Ω

10kΩ

SYSREF–

1.9pF

Figure 34. SYSREF Inputs

EMPHASIS/SWING

CONTROL (SPI)

DRVDD1

SERDOUTx+

DATA+

x = 0, 1, 2, 3, 4, 5, 6, 7

DRGND

OUTPUT

DRIVER

DRVDD1

SERDOUTx–

DATA–

x = 0, 1, 2, 3, 4, 5, 6, 7

DRGND

Figure 35. Digital Outputs

DRVDD1

CMOS PATH

SYNCINB± PIN

CONTROL (SPI)

DRGND

DRVDD1

2.6kΩ

100Ω

10kΩ

SYNCINB+

1.9pF

DRGND

130kΩ

DRGND

LEVEL

TRANSLATOR

V

= 0.65V

CM

130kΩ

DRVDD1

10kΩ

100Ω

SYNCINB–

1.9pF

DRGND

Figure 36. SYNCINB Inputs

Rev. 0 | Page 22 of 138

Data Sheet

AD6688

SPIVDD

ESD

PROTECTED

SPIVDD

SCLK

56kΩ

DGND

ESD

PROTECTED

DGND

Figure 37. SCLK Input

SPIVDD

ESD

PROTECTED

56kΩ

CSB

DGND

ESD

PROTECTED

DGND

Figure 38. CSB Input

SPIVDD

SDI

ESD

PROTECTED

DGND

SPIVDD

SDIO

ESD

PROTECTED

56kΩ

SDO

DGND

Figure 39. SDIO Input

SPIVDD

NCO BAND SELECT

ESD

PROTECTED

DGND

SPIVDD

FD_A/GPIO_A0

FD

56kΩ

ESD

PROTECTED

JESD LMFC

DGND

FD_x PIN CONTROL (SPI)

Figure 40. FD_A/GPIO_A0, FD_B/GPIO_B0, Input/Outputs

Rev. 0 | Page 23 of 138

AD6688

Data Sheet

SPIVDD

ESD

SPIVDD

PROTECTED

NCO BAND SELECT

CHIP TRANSFER

SDI

GPIO_A1/GPIO_B1

ESD

PROTECTED

DGND

56kΩ

DGND

GPIO_A1/GPIO_B1

PIN CONTROL (SPI)

Figure 41. GPIO_A1/GPIO_B1

SPIVDD

ESD

PROTECTED

PDWN/

STBY

DGND

56kΩ

ESD

PROTECTED

PDWN

CONTROL (SPI)

DGND

Figure 42. PDWN/STBY Input

V

OUTPUT

CM

AVDD2

TEMPERATURE DIODE

VOLTAGE OUTPUT

EXTERNAL REFERENCE

VOLTAGE INPUT

VREF

VREF PIN

CONTROL (SPI)

AGND

Figure 43. VREF Input/Output

Rev. 0 | Page 24 of 138

Data Sheet

AD6688

THEORY OF OPERATION

The AD6688 has two analog input channels and up to eight

JESD204B output lane pairs. The ADC samples wide bandwidth

analog signals of up to 5 GHz. The actual 3 dB roll-off of the analog

inputs is greater than 9 GHz. The AD6688 is optimized for wide

input bandwidth, high sampling rate, excellent linearity, and

low power in a small package.

Either a differential capacitor or two single-ended capacitors (or

a combination of both) can be placed on the inputs to provide a

matching passive network. These capacitors ultimately create a

low-pass filter that limits unwanted broadband noise. For more

information, refer to the Analog Dialogue article “Transformer-

Coupled Front-End for Wideband A/D Converters”

(Volume 39, April 2005). In general, the precise front-end

network component values depend on the application.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations.

Figure 44 shows the differential input return loss curve for the

analog inputs across a frequency range of 100 MHz to 10 GHz.

The reference impedance is 100 Ω.

1.0

The AD6688 has several functions that simplify the AGC

function in a communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect output bits of the ADC. If the input

signal level exceeds the programmable threshold, the fast detect

indicator goes high. Because this threshold indicator has low

latency, the user can quickly turn down the system gain to avoid

an overrange condition at the ADC input.

2.0

0.5

m5

m4

0.2

5.0

m1

m3

0

The Subclass 1 JESD204B-based high speed serialized output data

lanes can be configured in one lane (L = 1), two lane (L = 2), four

lane (L = 4), and eight lane (L = 8) configurations, depending

on the sample rate and the decimation ratio. Multiple device

synchronization is supported through the SYSREF and

SYNCINB input pins. The SYSREF pin in the AD6688 can

also be used as a timestamp of data as it passes through the

ADC and out the JESD204B interface.

m2

–0.2

–5.0

–0.5

–2.0

–1.0

FREQUENCY (100MHz TO 10GHz)

ADC ARCHITECTURE

The architecture of the AD6688 consists of an input buffered

pipelined ADC. The input buffer provides a termination

impedance to the analog input signal. This termination

impedance is set to 200 Ω. The equivalent circuit diagram of the

analog input termination is shown in Figure 32. The input

buffer is optimized for high linearity, low noise, and low power

across a wide bandwidth.

m1

m4

FREQUENCY = 100MHz

SDD11 = 0.301/–8.069

IMPEDANCE= Z0 × (1.838 – j0.171)

FREQUENCY = 4GHz

SDD11 = 0.500/136.667

IMPEDANCE = Z0 × (0.379 – j0.347)

m2

m5

FREQUENCY = 1GHz

SDD11 = 0.352/–73.534

IMPEDANCE= Z0 × (0.947 – j0.731)

FREQUENCY = 5GHz

SDD11 = 0.475/79.360

IMPEDANCE= Z0 × (0.737 – j0.889)

m3

FREQUENCY = 3GHz

SDD11 = 0.496/175.045

IMPEDANCE= Z0 × (0.337 – j0.038)

Figure 44. Differential Input Return Loss

The input buffer provides a linear high input impedance (for

ease of drive) and reduces kickback from the ADC. The

quantized outputs from each stage are combined into a final

14-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate with a new input

sample; at the same time, the remaining stages operate with the

preceding samples. Sampling occurs on the rising edge of the clock.

For best dynamic performance, the source impedances driving

VIN+x and VIN−x must be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference

buffer creates a differential reference that defines the span of the

ADC core.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. For the AD6688,

the available span is programmable through the SPI port from

1.1 V p-p to 2.04 V p-p differential, with 1.7 V p-p differential

being the default.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD6688 is a differential buffer. The

internal common-mode voltage of the buffer is 1.35 V. The

clock signal alternately switches the input circuit between

sample mode and hold mode.

Rev. 0 | Page 25 of 138

AD6688

Data Sheet

Differential Input Configurations

For low to midrange frequencies, a double balun or double

transformer network (see Figure 45 and Table 9) is recommended

for optimum performance of the AD6688. For higher frequencies

in the second or third Nyquist zones, it is recommended to

remove some of the front-end passive components to ensure

wideband operation (see Figure 45 and Table 9).

There are several ways to drive the AD6688, either actively or

passively. Optimum performance is achieved by driving the

analog input differentially.

For applications where SNR and SFDR are key parameters,

differential transformer coupling is the recommended input

configuration (see Figure 45 and Table 9) because the noise

performance of most amplifiers is not adequate to achieve the

true performance of the AD6688.

C2

R1

R3

C3

R2

MARKI

BAL-0006

200Ω

C4

ADC

C1

R2

R1

R3

C2

C3

NOTES

1. SEE TABLE 9 FOR COMPONENT VALUES.

Figure 45. Differential Transformer-Coupled Configuration for AD6688

0.1µF

25Ω

10Ω

25Ω

MARKI

BAL-0009

200Ω

ADC

0.1µF

10Ω

0.1µF

Figure 46. Input Network Configuration for Frequencies >5 GHz

Table 9. Differential Transformer-Coupled Input Configuration Component Values

Device

Frequency Range

Transformer

R1

R2

R3

C1

0.1 µF

C2

C3

C4

AD6688

<5000 MHz

BAL-0006

25 Ω

10 Ω

0.1 µF

0.4 pF

Rev. 0 | Page 26 of 138

Data Sheet

AD6688

Input Common Mode

When performing SPI writes for dc coupling operation, use the

following register settings in order:

The analog inputs of the AD6688 are internally biased to the

common-mode voltage, as shown in Figure 48. The common-

mode buffer has a limited range in that the performance suffers

greatly if the common-mode voltage drops by more than 50 mV on

either side of the nominal value.

1. Set Register 0x1908, Bit 2 to disconnect the internal

common-mode buffer from the analog input. Note that

this is a local register.

2. Set Register 0x18A6 to 0x00 to turn off the voltage

reference.

3. Set Register 0x18E6 to 0x00 to turn off the temperature

diode export.

4. Set Register 0x18E3, Bit 6 to 1 to turn on the V_CMexport.

5. Set Register 0x18E3, Bit[5:0] to the buffer current setting

(Register 0x1A4C and Register 0x1A4D) to improve the

accuracy of the common-mode export.

For dc-coupled applications, the recommended operation

procedure is to export the common-mode voltage to the VREF pin

using the SPI writes listed in this section. The common-mode

voltage must be set by the exported value to ensure proper ADC

operation. Disconnect the internal common-mode buffer from

the analog input using Register 0x1908.

Figure 47 shows the block diagram representation of a dc-coupled

application.

ADC

+

ADC

A

AMP A

–

VOCM

VREF

VOCM

+

V

EXPORT SELECT

CM

SPI REGISTERS

0x1908, 0x18A6,

0x18E3, 0x18E6

ADC

B

AMP B

–

Figure 47. DC-Coupled Application Using AD6688

Rev. 0 | Page 27 of 138

AD6688

Data Sheet

Analog Input Buffer Controls and SFDR Optimization

AVDD3

VIN+

0.3pF

100Ω

AVDD3

V

CM

BUFFER

REG

(0x0008,

0x1908)

AVDD3

VIN–

0.3pF

REG (0x0008, 0x1A4C,

0x1A4D, 0x1910)

Figure 48. Analog Input Controls

The AD6688 input buffer offers flexible controls for the analog

inputs, such as buffer current, dc coupling, and input full-scale

adjustment. All the available controls are shown in Figure 48.

Table 10 shows the recommended values for the buffer current

for various Nyquist zones.

Table 10. SFDR Optimization for Input Frequencies

Using the 0x1A4C and 0x1A4D registers, the buffer behavior on

each channel can be adjusted to optimize the SFDR over various

input frequencies and bandwidths of interest. Register 0x1910 can

be used to change the internal reference voltage. Changing the

internal reference voltage results in a change in the input full-

scale voltage.

Product

Frequency

0x1A4C and 0x1A4D

400 µA/500 µA

500 µA

AD6688

DC to 1500 MHz

1500 MHz to 3000 MHz

>3000 MHz

500 µA/700 µA

Dither

When the input buffer current in Register 0x1A4C and

Register 0x1A4D is set, the amount of current required by the

AVDD3 supply changes. This relationship is shown in Figure 49.

For a complete list of buffer current settings, see Table 46.

0.26

The AD6688 has internal on-chip dither circuitry that improves

the ADC linearity and SFDR, particularly at smaller signal

levels. A known but random amount of white noise is injected

into the input of the AD6688. This dither improves the small

signal linearity within the ADC transfer function and is

precisely subtracted out digitally. The dither is turned on by

default and does not reduce the ADC input dynamic range. The

data sheet specifications and limits are obtained with the dither

turned on.

0.25

0.24

0.23

0.22

0.21

0.2

The dither is on by default. It is not recommended to turn it off.

Absolute Maximum Input Swing

The absolute maximum input swing allowed at the inputs of the

AD6688 is 5.8 V p-p differential. Signals operating near or at

this level can cause permanent damage to the ADC. See Table 6

for more information.

0.19

0.18

0.17

400

500

600

700

BUFFER CURRENT SETTING (µA)

Figure 49. AVDD3 Current (I_AVDD3) vs. Buffer Control 1 Setting in

Register 0x1A4C and Register 0x1A4D

Rev. 0 | Page 28 of 138

Data Sheet

AD6688

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the

AD6688. This internal 0.5 V reference sets the full-scale input

range of the ADC. The full-scale input range can be adjusted via

the ADC input full-scale control register (Register 0x1910). For

more information on adjusting the input swing, see Table 46.

Figure 51 shows the block diagram of the internal 0.5 V reference

controls.

improve thermal drift characteristics. Figure 50 shows the

typical drift characteristics of the internal 0.5 V reference.

0.5060

0.5055

0.5050

0.5045

0.5040

0.5035

0.5030

The SPI Register 0x18A6 enables the user to either use this

internal 0.5 V reference or to provide an external 0.5 V

reference. When using an external voltage reference, provide a

0.5 V reference. The full-scale adjustment is made using the SPI,

irrespective of the reference voltage. For more information on

adjusting the full-scale level of the AD6688, refer to the

Memory Map section.

–10

10

30

50

70

90

110

130

The SPI writes required to use the external voltage reference, in

order, are as follows:

JUNCTION TEMPERATURE (°C)

Figure 50. Typical V_REFDrift

1. Set Register 0x18E3 to 0x00 to turn off the V_CMexport.

2. Set Register 0x18E6 to 0x00 to turn off the temperature

diode export.

3. Set Register 0x18A6 to 0x01 to turn on the external voltage

reference.

The external reference must be a stable 0.5 V reference. The

ADR130 is a good option for providing the 0.5 V reference.

Figure 52 shows how the ADR130 can be used to provide the

external 0.5 V reference to the AD6688. The grayed out areas

show unused blocks within the AD6688 while using the

ADR130 to provide the external reference.

The use of an external reference may be necessary in some

applications to enhance the gain accuracy of the ADC or to

VIN+A/VIN+B

VIN–A/VIN–B

ADC

CORE

INTERNAL

0.5V

REFERENCE

GENERATOR

VFS

ADJUST

INPUT FULL-SCALE

CONTROL

SPI REGISTER

(0x1910)

VREF

CONTROL SPI

REGISTER

(0x18A6)

Figure 51. Internal Reference Configuration and Controls

INTERNAL

0.5V

REFERENCE

GENERATOR

VFS

ADJUST

ADR130

1

2

3

NC

6

ADC

5

GND SET

VREF

4

INPUT

V

OUT

IN

0.1µF

VREF PIN AND VFS

CONTROL

Figure 52. External Reference Using ADR130

Rev. 0 | Page 29 of 138

AD6688

Data Sheet

Figure 54 shows a preferred method for clocking the AD6688.

The low jitter clock source is converted from a single-ended

signal to a differential signal using an RF transformer.

DC OFFSET CALIBRATION

The AD6688 contains a digital filter to remove the dc offset from

the output of the ADC. For ac-coupled applications, this filter

can be enabled by writing 0x86 to Register 0x0701. The filter

computes the average dc signal and it is digitally subtracted

from the ADC output. As a result, the dc offset is improved to

better than 70 dBFS at the output. Since the filter does not

distinguish between the source of dc signals, this feature can be

used when the signal content at dc is not of interest. The filter

corrects dc up to 512 codes and saturates beyond that.

CLK+

CLOCK

INPUT

ADC

1:2Z

CLK–

Figure 54. Transformer-Coupled Differential Clock

CLOCK INPUT CONSIDERATIONS

Another option is to ac couple a differential CML or LVDS

signal to the sample clock input pins, as shown in Figure 55.

For optimum performance, drive the AD6688 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal is

ac-coupled to the CLK+ and CLK− pins via a transformer or clock

drivers. These pins are biased internally and require no

additional biasing.

ADC

CLK+

Figure 53 shows the differential input return loss curve for the

clock inputs across a frequency range of 100 MHz to 6 GHz.

The reference impedance is 100 Ω.

LVPECL

DRIVER

ADC

CLOCK INPUT

100Ω

DIFFERENTIAL

TRACE

CLK–

1.0

150Ω

2.0

0.5

Figure 55. Differential LVPECL Sample Clock

Clock Duty Cycle Considerations

0.2

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. The AD6688 contains an

internal clock divider and a duty cycle stabilizer (DCS). In the

AD6688, the DCS is enabled by default. In applications where

the clock duty cycle cannot be guaranteed to be 50%, a higher

multiple frequency clock along with the usage of the clock

divider is recommended.

5.0

m4

m3

m2

0

m1

–0.2

–5.0

When it is not possible to provide a higher frequency clock, it is

recommended to turn on the DCS using Register 0x011C and

Register 0x011E. Figure 56 shows a block diagram representation

showing the different controls to the AD6688 clock inputs. The

output of the divider offers a 50% duty cycle, high slew rate (fast

edge) clock signal to the internal ADC. See the Memory Map

section for more details on using this feature.

–0.5

–2.0

–1.0

FREQUENCY (100MHz TO 6GHz)

m1

m3

FREQUENCY = 2.503GHz

FREQUENCY = 3.104GHz

SDD11 = 0.313/–173.307

SDD11 = 0.332/165.502

IMPEDANCE = Z0 × (0.524 – j0.042)

IMPEDANCE = Z0 × (0.508 – j0.095)

m2

m4

FREQUENCY = 2.996GHz

SDD11 = 0.337/169.383

IMPEDANCE = Z0 × (0.499 – j0.070)

FREQUENCY = 6GHz

SDD11 = 0.271/54.790

IMPEDANCE = Z0 × (1.218 – j0.581)

Figure 53. Differential Input Return Loss for the CLK Inputs

Rev. 0 | Page 30 of 138

Data Sheet

AD6688

Input Clock Divider

CHANNEL A

The AD6688 contains an input clock divider with the ability to

divide the input clock by 1, 2, or 4. The divider ratios can be

selected using Register 0x0108, as shown in Figure 56.

PHASE

The maximum frequency at the CLK inputs is 6 GHz, which is

the limit of the divider. In applications where the clock input is a

multiple of the sample clock, take care to program the appropriate

divider ratio into the clock divider before applying the clock

signal. This ensures that the current transients during device

startup are controlled.

τ

CHANNEL A

CLK_DIV

0x0108

CLK INPUT

PHASE

CHANNEL A

REGISTER 0x011C,

REGISTER 0x011E

FINE DELAY

0x0110,

0x0109

CLK+

0x0111,

0x0112

÷2

CLK–

CHANNEL B

÷4

Figure 57. Clock Divider Phase and Delay Controls

The clock delay adjust takes effect immediately when it is

enabled via SPI writes. Enabling the clock fine delay adjust in

Register 0x0110 causes a datapath reset. However, the contents

of Register 0x0111 and Register 0x0112 can be changed without

affecting the stability of the JESD204B link.

REGISTER 0x0108

Figure 56. Clock Divider Circuit

The AD6688 clock divider can be synchronized using the

external SYSREF input. A valid SYSREF causes the clock

divider to reset to a programmable state. This synchronization

feature allows multiple devices to have their clock dividers

aligned to guarantee simultaneous input sampling. See the

Memory Map Register Details section for more information.

Clock Coupling Considerations

The AD6688 has many different domains within the analog

supply that control various aspects of the data conversion. The

clock domain is supplied by the A4, A5, A10, A11, B4, and B11

pins on the analog supply, AVDD1 (0.975 V), and the A6, A9,

B6, B7, B8, B9, C6, C7, C8, C9, D7, and D8 pins on the ground

(AGND) side. To minimize coupling between the clock supply

domain and the other analog domains, it is recommended to

add a supply Q factor reduction circuitry for the A4/A11 and

B4/B11 pins, as shown in Figure 58.

Input Clock Divider ½ Period Delay Adjust

The input clock divider inside the AD6688 provides phase delay

in increments of ½ the input clock cycle. Register 0x0109 can be

programmed to enable this delay independently for each channel.

Changing this register does not affect the stability of the

JESD204B link.

FERRITE BEAD

Clock Fine Delay and Super Fine Delay Adjust

220Ω AT

100MHz

The AD6688 sampling edge instant can be adjusted by writing to

Register 0x0110, Register 0x0111, and Register 0x0112. Bits[2:0] of

Register 0x0110 enable the selection of the fine delay, or the fine

delay with super fine delay. The fine delay allows the user to delay

the clock edges with 16 step or 192 step delay options. The super

fine delay is an unsigned control to adjust the clock delay in super

fine steps of 0.25 ps each.

A4

B4

DCR ≤ 0.5Ω

100nF

10Ω

AVDD1

PLANE

FERRITE BEAD

220Ω AT

100MHz

Register 0x0112, Bits[7:0] offer the user the option to delay the

clock in 192 delay steps. Register 0x0111, Bits[7:0] offer the user the

option to delay the clock in 128 super-fine steps. These values can

be programmed individually for each channel. To utilize the

super fine delay option, the user must set the clock delay control,

Register 0x0110, Bits[2:0], to 0x2 or 0x6. Figure 57 shows the

controls available to the clock dividers within the AD6688. It is

recommended to apply the same delay settings to the digital

delay circuits as are applied to the analog delay circuits to

maintain sample accuracy through the pipe.

DCR ≤ 0.5Ω

A11

B11

100nF

10Ω

Figure 58. De-Q Network Recommendation for Clock Domain Supply

Rev. 0 | Page 31 of 138

AD6688

Data Sheet

Clock Jitter Considerations

ADC

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR at a given input

frequency (f_A) due only to aperture jitter (t_J) can be calculated by

ADC

A

ADC

B

TEMPERATURE DIODE

VREF

LOCATIONS

CHANNEL A, CENTRAL,

CHANNEL B

SNR_JITTER= −20 × log₁₀(2 × π × f_A× t_J)

DIGITAL

In this equation, the rms aperture jitter represents the root

mean square of all jitter sources, including the clock input,

analog input signal, and ADC aperture jitter specifications.

JESD204B DRIVER

Figure 59. Temperature Diode Locations in the Die

Treat the clock input as an analog signal in cases where aperture

jitter can affect the dynamic range of the AD6688. Separate

power supplies for clock drivers from the ADC output driver

supplies to avoid modulating the clock signal with digital noise.

If the clock is generated from another type of source (by gating,

dividing, or other methods), retime the clock by the original clock

at the last step. Refer to the AN-501 Application Note and the

AN-756 Application Note for more in-depth information about

jitter performance as it relates to ADCs.

The temperature diode voltages can be exported to the VREF

pin using the SPI. Use Register 0x18E6 to enable or disable the

diodes. It is important to note that other voltages can be

exported to the VREF pin at the same time, which can result in

undefined behavior. To ensure a proper readout, switch off all

other voltage exporting circuits as detailed in this section.

Figure 60 shows the block diagram representation of the

controls that are required to enable the diode voltage readout.

VREF

CONTROL

SPI REGISTER

(0x18A6)

The SNR can be estimated by using the following equation:

−SNR





¹⁰

_^

−SNR

10

JITTER









ADC



10





SNR(dBFS) = −10log 10

+10^





CHANNEL A







CENTRAL

VREF

POWER-DOWN/STANDBY MODE

The AD6688 has a PDWN/STBY pin that can configure the device

in power-down or standby mode. The default operation is PDWN.

The PDWN/STBY pin is a logic high pin. When in power-down

mode, the JESD204B link is disrupted. The power-down option

can also be set via Register 0x003F and Register 0x0040.

CHANNEL B

TEMPERATURE DIODE

LOCATION SELECT

SPI REGISTER (0x18E6)

Figure 60. Register Controls to Output Temperature Diode Voltage on VREF Pin

In standby mode, the JESD204B link is not disrupted and

transmits zeros for all converter samples. This can be changed

using Register 0x0571, Bit 7 to select /K/ characters.

The SPI writes required to export the central temperature diode

are as follows (see the Memory Map Register Details for more

information):

TEMPERATURE DIODE

1. Set Register 0x0008 to 0x03 to select both channels.

2. Set Register 0x18E3 to 0x00 to turn off the V_CMexport.

3. Set Register 0x18A6 to 0x00 to turn off the voltage

reference export.

4. Set Register 0x18E6 to 0x01 to turn on voltage export of

the central 1× temperature diode. The typical voltage

response of the temperature diode is shown in Figure 61.

Even though this voltage does represent the die

temperature, it is recommended to take measurements

from a pair of diodes for improved accuracy. The following

step explains how to enable the 20× diode.

5. Set Register 0x18E6 to 0x02 to turn on the second central

temperature diode of the pair, which is 20× the size of the

first. For the method utilizing two diodes simultaneously

giving a more accurate result, see the AN-1432 Application

Note, Practical Thermal Modeling and Measurements in

High Power ICs.

The AD6688 contains diode-based temperature sensors. The

diodes output voltages commensurate to the temperature of the

silicon. There are multiple diodes on the die; however, the

results established using the temperature diode at the central

location of the die can be regarded as representative of the

entire die. However, in applications where only one channel is

used (the other being in the power-down state), it is recommended

to read the temperature diode corresponding to the channel

that is on. Figure 59 shows the locations of the diodes inside the

AD6688 whose voltages can be output to the VREF pin. In each

location, there is a pair of diodes, one of which is 20× the size of

the other. It is recommended to use both diodes in a location to

obtain an accurate estimate of the die temperature. For more

information, see the AN-1432 Application Note, Practical Thermal

Modeling and Measurements in High Power ICs.

The relationship between the measured ΔV and the junction

temperature in degrees Celsius is shown in Figure 62.

Rev. 0 | Page 32 of 138

Data Sheet

AD6688

150

140

130

120

110

100

90

80

70

60

50

0.80

0.75

0.70

0.65

0.60

0.55

0.50

40

30

20

10

0

–10

–20

–30

–40

60

65

70

75

80

85

90

95

100 105 110

–40

–20

0

20

40

60

80

100

DELTA VOLTAGE (mV)

JUNCTION TEMPERATURE (°C)

Figure 61. Typical Voltage Response of 1× Temperature Diode

Figure 62. Junction Temperature (°C) vs. ΔV (mV)

Rev. 0 | Page 33 of 138

AD6688

Data Sheet

ADC OVERRANGE AND FAST DETECT

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be clipped.

The standard overrange bit in the JESD204B outputs provides

information on the state of the analog input that is of limited

usefulness. Therefore, it is helpful to have a programmable

threshold below full scale that allows time to reduce the gain

before the clip actually occurs. In addition, because input

signals can have significant slew rates, the latency of this

function is of major concern. Highly pipelined converters can

have significant latency. The AD6688 contains fast detect

circuitry for individual channels to monitor the threshold and

assert the FD_A and FD_B pins.

The operation of the upper threshold and lower threshold

registers, along with the dwell time registers, is shown in

Figure 63.

The FD indicator is asserted if the input magnitude exceeds the

value programmed in the fast detect upper threshold registers,

located at Register 0x0247 and Register 0x0248. The selected

threshold register is compared with the signal magnitude at the

output of the ADC. The fast upper threshold detection has a

latency of 28 clock cycles (maximum). The approximate upper

threshold magnitude is defined by

Upper Threshold Magnitude (dBFS)

= 20log(Threshold Magnitude/2¹³)

ADC OVERRANGE

The FD indicators are not cleared until the signal drops below

the lower threshold for the programmed dwell time. The lower

threshold is programmed in the fast detect lower threshold

registers, located at Register 0x0249 and Register 0x024A. The

fast detect lower threshold register is a 13-bit register that is

compared with the signal magnitude at the output of the ADC.

This comparison is subject to the ADC pipeline latency, but is

accurate in terms of converter resolution. The lower threshold

magnitude is defined by

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange indicator can

be embedded within the JESD204B link as a control bit (when

CSB > 0). The latency of this overrange indicator matches the

sample latency.

The AD6688 also records any overrange condition in any of the

eight virtual converters. For more information on the virtual

converters, refer to Figure 71. The overrange status of each

virtual converter is registered as a sticky bit in Register 0x0563. The

contents of Register 0x0563 can be cleared using Register 0x0562,

by toggling the bits corresponding to the virtual converter to

the set and reset positions.

Lower Threshold Magnitude (dBFS)

= 20log(Threshold Magnitude/2¹³)

For example, to set an upper threshold of −6 dBFS, write 0xFFF

to Register 0x0247 and Register 0x0248. To set a lower threshold

of −10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.

FAST THRESHOLD DETECTION (FD_A AND FD_B)

The FD_A or FD_B pin is immediately set whenever the

absolute value of the input signal exceeds the programmable

upper threshold level. The FD bit is only cleared when the

absolute value of the input signal drops below the lower

threshold level for greater than the programmable dwell time.

This feature provides hysteresis and prevents the FD bit from

excessively toggling.

The dwell time can be programmed from 1 to 65,535 sample clock

cycles by placing the desired value in the fast detect dwell time

registers, located at Register 0x024B and Register 0x024C. See

the Memory Map section (Register 0x0040, and Register 0x0245

to Register 0x024C in Table 46) for more details.

UPPER THRESHOLD

DWELL TIME

TIMER RESET BY

RISE ABOVE

LOWER

THRESHOLD

LOWER THRESHOLD

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE

LOWER THRESHOLD

DWELL TIME

FD_A OR FD_B

Figure 63. Threshold Settings for FD_A and FD_B Signals

Rev. 0 | Page 34 of 138

Data Sheet

AD6688

ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING

The AD6688 contains a configurable signal path that allows

different features to be enabled for different applications. These

features are controlled through the chip application mode

register (0x0200). The chip operating mode is controlled by

Bits[3:0] and the chip Q ignore is controlled by Bit 5.

converters and their relationship to the DDC outputs when

using complex outputs.

Each DDC channel outputs either two sample streams (I/Q)

for the complex data components (real and imaginary) or one

sample stream for real (I) data. The AD6688 can be configured

to use up to eight virtual converters depending on the DDC

configuration.

The AD6688 contains the following modes:

•

Full bandwidth mode: two 7-bit ADC cores running at full

sample rate.

The I/Q samples are always mapped in pairs with the I samples

mapped to the first virtual converter and the Q samples mapped

to the second virtual converter. With this transport layer mapping,

the number of virtual converters are the same whether

•

DDC mode: up to four DDC channels.

When the chip application mode has been selected, the output

decimation ratio is set using the chip decimation ratio in

Register 0x0201, Bits[3:0]. The output sample rate = ADC

sample rate/the chip decimation ratio.

•

A single real converter is used along with a digital

downconverter block producing I/Q outputs, or

An analog downconversion is used with two real

converters producing I/Q outputs.

•

To support the different application layer modes, the AD6688

treats each sample stream (real or I or Q) as originating from

separate virtual converters. Table 11 shows the number of

virtual converters required and the transport layer mapping

when channel swapping is disabled. Figure 64 shows the virtual

Figure 65 shows a block diagram of the two scenarios described

for I/Q transport layer mapping.

Table 11. Virtual Converter Mapping

Number of

Virtual

Converters

Supported

Chip

Virtual Converter Mapping

Application

Mode (0x0200,

Bits[3:0])

Chip Q Ignore

(0x0200, Bit 5)

0

1

2

3

4

5

6

7

1 to 2

Full bandwidth

mode (0x0)

Real or complex ADC A

ADC B

samples

Unused

(0x0)

samples

1

2

4

8

One DDC mode

(0x1)

One DDC mode

(0x1)

Two DDC mode

(0x2)

Two DDC mode

(0x2)

Four DDC mode

(0x3)

Four DDC mode

(0x3)

Real (I only)

(0x1)

Complex (I/Q)

(0x0)

Real (I only)

(0x1)

Complex (I/Q)

(0x0)

Real (I only)

(0x1)

Complex (I/Q)

(0x0)

DDC0 I

samples

DDC0 I

samples

DDC0 I

samples

DDC0 I

samples

DDC0 I

samples

DDC0 I

samples

Unused

DDC0 Q

samples

DDC1 I

samples

DDC0 Q

samples

DDC1 I

samples

DDC0 Q

samples

DDC1 I

samples

DDC2 I

samples

DDC1 I

samples

DDC1 Q

samples

DDC3 I

samples

DDC1 Q

samples

DDC2 I

samples

DDC2 Q

samples

DDC3 I

samples

DDC3 Q

samples

Rev. 0 | Page 35 of 138

AD6688

Data Sheet

DDC 0

DDC 1

DDC 2

DDC 3

ADC A

SAMPLING

AT f_S

REAL/I

CONVERTER 0

Q

REAL/I

I

REAL/Q

Q

CONVERTER 1

REAL/I

CONVERTER 2

Q

I

REAL/Q

Q

I/Q

CROSSBAR

MUX

CONVERTER 3

OUTPUT

INTERFACE

REAL/I

CONVERTER 4

Q

I

REAL/Q

Q

CONVERTER 5

ADC B

SAMPLING

AT f_S

REAL/I

CONVERTER 6

Q

REAL/Q

I

REAL/Q

Q

CONVERTER 7

Figure 64. DDCs and Virtual Converter Mapping

DIGITAL DOWNCONVERSION

M = 2

I

CONVERTER 0

DIGITAL

JESD204B

Tx

REAL

DOWN

L LANES

ADC

CONVERSION

Q

CONVERTER 1

I/Q ANALOG MIXING

M = 2

I

CONVERTER 0

ADC

REAL

90°

PHASE

JESD204B

Tx

L LANES

Q

CONVERTER 1

ADC

Figure 65. I/Q Transport Layer Mapping

Rev. 0 | Page 36 of 138

Data Sheet

AD6688

PROGRAMMABLE FIR FILTERS

SUPPORTED MODES

The AD6688 supports the following modes of operation:

•

Half complex filter using two real 48-tap filters for the I/Q

channels (see Figure 69)

•

dout_i[n] = din_i[n]

dout_q[n] = din_q[n] * xy_q[n] + din_i[n] * xy_i[n]

•

Real 48-tap filter for each I/Q channel (see Figure 66)

•

dout_i[n] = din_i[n] * xy_i[n]

dout_q[n] = din_q[n] * xy_q[n]

Full complex filter using four real 24-tap filters for the I/Q

channels (see Figure 70)

Real 96-tap filter for on either I or Q channel (see Figure 67)

•

dout_i[n] = din_i[n] * x_i[n] + din_q[n] * y_q[n]

dout_q[n] = din_q[n] * x_q[n] + din_i[n] * y_i[n]

•

dout_i[n] = din_i[n] * xy_i[n]

dout_q[n] = din_q[n] * xy_q[n]

The asterisk symbol (*) denotes convolution.

Real set of two cascaded 24-tap filters for each I/Q channel

(see Figure 68)

•

dout_i[n] = din_i[n] * x_i[n] * y_i[n]

dout_q[n] = din_q[n] * x_q[n] * y_q[n]

PROGRAMMABLE FILTER (PFILT)

48-TAP FIR

FILTER

xy_i[n]

din_i[n]

dout_i[n]

I' (REAL)

I (REAL)

ADC A

CORE

SIGNAL

JESD

PROCESSING

INTERFACE

BLOCKS

48-TAP FIR

FILTER

xy_q[n]

Q (IMAG)

din_q[n]

dout_q[n]

Q' (IMAG)

ADC B

CORE

Figure 66. Real 48-Tap Filter Configuration

Rev. 0 | Page 37 of 138

AD6688

Data Sheet

PROGRAMMABLE FILTER (PFILT)

96-TAP FIR

FILTER

din_i[n]

dout_i[n]

I (REAL)

ADC A

CORE

I' (REAL)

X Y X

Y [n]

I

Q

SIGNAL

PROCESSING

BLOCKS

JESD

INTERFACE

din_q[n]

dout_q[n]

Q (IMAG)

ADC B

CORE

Q' (IMAG)

Figure 67. Real 96-Tap Filter Configuration

PROGRAMMABLE FILTER (PFILT)

24-TAP FIR

FILTER

x_i[n]

din_i[n]

dout_i[n]

I (REAL)

ADC A

CORE

I' (REAL)

24-TAP FIR

FILTER

y_i[n]

SIGNAL

PROCESSING

BLOCKS

JESD

INTERFACE

24-TAP FIR

FILTER

y_q[n]

24-TAP FIR

FILTER

x_q[n]

din_q[n]

Q (IMAG)

ADC B

CORE

dout_q[n]

Q' (IMAG)

Figure 68. Real Two Cascaded 24-Tap Filter Configuration

Rev. 0 | Page 38 of 138

Data Sheet

AD6688

PROGRAMMABLE FILTER (PFILT)

din_i[n]

dout_i[n]

I (REAL)

0 TO 47

DELAY TAPS

ADC A

CORE

I' (REAL)

48-TAP FIR

FILTER

xy_i[n]

SIGNAL

PROCESSING

BLOCKS

JESD

INTERFACE

+

48-TAP FIR

+

dout_q[n]

din_q[n]

Q (IMAG)

ADC B

CORE

FILTER

xy_q[n]

Q' (IMAG)

Figure 69. 48 Half Complex Filter Configuration

PROGRAMMABLE FILTER (PFILT)

24-TAP FIR

FILTER

x_i[n]

dout_i[n]

din_i[n]

+

I (REAL)

ADC A

CORE

I' (REAL)

+

24-TAP FIR

FILTER

y_i[n]

SIGNAL

PROCESSING

BLOCKS

JESD

INTERFACE

24-TAP FIR

FILTER

y_q[n]

+

24-TAP FIR

FILTER

x_q[n]

+

dout_q[n]

din_q[n]

Q (IMAG)

ADC B

CORE

Q' (IMAG)

Figure 70. 24-Tap Full Complex Filter Configuration

Rev. 0 | Page 39 of 138

AD6688

Data Sheet

Table 12. Register 0x0DF8 Definition

PROGRAMMING INSTRUCTIONS

Bit(s)

[7:3]

[2:0]

Description

Follow this sequence to set up the programmable finite impulse

response (FIR) filter:

Reserved

Filter mode (IMODE or QMODE)

000: filters bypassed

001: real 24-tap filter (X only)

1. Enable sample CLK to the device.

2. Configure the mode registers.

a. Set device index to Channel A (I path)

(Register 0x0008 = 0x01).

b. Set I path mode (IMODE) and gain in Register 0x0DF8

and Register 0x0DF9 (see Table 12 and Table 13).

c. Set device index to Channel B (Q path)

(Register 0x0008 = 0x02).

010: real 48-tap filter (X and Y together)

100: real set of two cascaded 24-tap filters (X then Y

cascaded)

101: full complex filter using four real 24-tap filters for

the A and B channels (opposite channel must also be

set to 101)

d. Set Q path mode (QMODE) and gain in Register 0x0DF8

and Register 0x0DF9.

3. Wait for at least 5 µs to allow the programmable filter to

power up.

4. Program the I path coefficients to the internal shadow

registers.

110: half complex filter using two real 48-tap filters +

48-tap delay line (X and Y together) (opposite channel

must also be set to 010)

111: real 96-tap filter (XI, YI, XQ, and YQ together)

(opposite channel must be set to 000)

Table 13. Register 0x0DF9 Definition

a. Set device index to Channel A (I path)

(Register 0x0008 = 0x01).

Bit(s)

Description

b. Program the I path X coefficients (XI) in

Register 0x0E00 to Register 0x0E2F (see Table 14 and

Table 15).

c. Program the I path Y coefficients (YI) in

Register 0x0F00 to Register 0x0F7F (see Table 14 and

Table 15).

7

Reserved

[6:4]

Y filter gain

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

Reserved

d. Program tapped delay in Register 0x0F30 (optional).

5. Program the Q path coefficients to the internal shadow

registers:

3

[2:0]

X filter gain

a. Set device index to Channel B (Q path)

(Register 0x0008 = 0x02).

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

b. Set Q path mode and gain in Register 0x0DF8 and

Register 0x0DF9 (see Table 12 and Table 13).

c. Program the Q path X coefficients (XQ) in

Register 0x0E00 to Register 0x0E2F (see Table 14 and

Table 15).

d. Program Q path Y coefficients (YQ) in Register 0x0F00

to Register 0x0F7F (see Table 14 and Table 15).

e. Program tapped delay in Register 0x0F30 (see Table 14

and Table 15) (optional).

Table 14 and Table 15 show the coefficient tables in Register 0x0E00

to Register 0x0F30. All coefficients are Q1.15 format (sign bit + 15

fractional bits).

6. Set the chip transfer bit using one of the following methods

(note that setting the chip transfer bit applies the programmed

shadow coefficients to the filter).

•

Register map.

Write the chip transfer bit (Register 0x000F = 0x01).

GPIO pin.

i.

Configure one of the GPIO pins as the chip

transfer bit in Register 0x0040 to Register 0x0042.

Toggle the GPIO pin to initiate the chip transfer

(rising edge triggered).

ii.

7. Whenever the I or Q path mode register changes in

Register 0x0DF8, all coefficients must be reprogrammed.

Rev. 0 | Page 40 of 138

Data Sheet

AD6688

Table 14. I Coefficient Table (Device Selection = 0x1)¹

Full Complex

24-Tap Filters

(IMODE[2:0] = 0x5

and

Half Complex

48-Tap Filters

(IMODE[2:0] = 0x6

and

Q Path 96-Tap

Filter

Filter (IMODE[2:0] = (IMODE[2:0] = 0x0

0x7 and and

I Path 96-Tap

Single 24-Tap

Filter

Single 48-Tap

Filter

Two Cascaded

24-Tap Filters

Addr.

(IMODE[2:0] = 0x1) (IMODE[2:0] = 0x2) (IMODE[2:0] = 0x4) QMODE[2:0] = 0x5) QMODE[2:0] = 0x2)²QMODE[2:0] = 0x0)³QMODE[2:0] = 0x7)³

0x0E00 XI C0 [7:0]

0x0E01 XI C0 [15:8]

0x0E02 XI C1 [7:0]

0x0E03 XI C1 [15:8]

XI C0 [7:0]

XI C0 [15:8]

XI C1 [7:0]

XI C1 [15:8]

...

XI C0 [7:0]

XI C0 [15:8]

XI C1 [7:0]

XI C1 [15:8]

...

XI C0 [7:0]

XI C0 [15:8]

XI C1 [7:0]

XI C1 [15:8]

...

XI C0 [7:0]

XI C0 [15:8]

XI C1 [7:0]

XI C1 [15:8]

...

XI C0 [7:0]

XI C0 [15:8]

XI C1 [7:0]

XI C1 [15:8]

...

XQ C48 [7:0]

XQ C48 [15:8]

XQ C49 [7:0]

XQ C49 [15:8]

...

0x0E2E XI C23 [7:0]

0x0E2F XI C23 [15:0]

0x0F00 Unused

0x0F01 Unused

0x0F02 Unused

0x0F03 Unused

XI C23 [7:0]

XI C23 [15:0]

YI C24 [7:0]

YI C24 [15:8]

YI C25 [7:0]

YI C25 [15:8]

...

XI C23 [7:0]

XI C23 [15:0]

YI C0 [7:0]

YI C0 [15:8]

YI C1 [7:0]

YI C1 [15:8]

...

XI C23 [7:0]

XI C23 [15:0]

YI C0 [7:0]

YI C0 [15:8]

YI C1 [7:0]

YI C1 [15:8]

...

XI C23 [7:0]

XI C23 [15:0]

YI C24 [7:0]

YI C24 [15:8]

YI C25 [7:0]

YI C25 [15:8]

...

XI C23 [7:0]

XI C23 [15:0]

YI C24 [7:0]

YI C24 [15:8]

YI C25 [7:0]

YI C25 [15:8]

...

XQ C71 [7:0]

XQ C71 [15:0]

YQ C72 [7:0]

YQ C72 [15:8]

YQ C73 [7:0]

YQ C73 [15:8]

...

Unused

0x0F2E Unused

0x0F2F Unused

0x0F30 Unused

YI C47 [7:0]

YI C47 [15:0]

Unused

YI C23 [7:0]

YI C23 [15:0]

Unused

YI C23 [7:0]

YI C23 [15:0]

Unused

YI C47 [7:0]

YI C47 [15:0]

I path tapped delay

YI C47 [7:0]

YI C47 [15:0]

Unused

YQ C95 [7:0]

YQ C95 [15:0]

Unused

0: 0 tapped delay

(matches C0 in the

filter)

1: 1 tapped delays

…

47: 47 tapped delays

¹XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n.

²When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode.

³When using the I path in 96-tap filter mode, the Q path must be in bypass mode.

Table 15. Q Coefficient Table (Device Selection = 0x2)¹

Full Complex

24-Tap Filters

Half Complex

48-Tap Filters

I Path 96-Tap

Filter

Q Path 96-Tap

Filter

Single 24-Tap

Filter

Single 48-Tap

Filter

Two Cascaded

24-Tap Filters

(QMODE[2:0] = 0x5 (QMODE[2:0] = 0x6 (QMODE[2:0] = 0x0 (QMODE[2:0] = 0x7

and

Addr.

(QMODE[2:0] = 0x1) (QMODE[2:0] = 0x2) (QMODE[2:0] = 0x4) IMODE[2:0] = 0x5)

IMODE[2:0] = 0x2)²

IMODE[2:0] = 0x7)³

IMODE[2:0] = 0x0)³

0x0E00 XQ C0 [7:0]

0x0E01 XQ C0 [15:8]

0x0E02 XQ C1 [7:0]

0x0E03 XQ C1 [15:8]

XQ C0 [7:0]

XQ C0 [15:8]

XQ C1 [7:0]

XQ C1 [15:8]

...

XQ C0 [7:0]

XQ C0 [15:8]

XQ C1 [7:0]

XQ C1 [15:8]

...

XQ C0 [7:0]

XQ C0 [15:8]

XQ C1 [7:0]

XQ C1 [15:8]

...

XQ C0 [7:0]

XQ C0 [15:8]

XQ C1 [7:0]

XQ C1 [15:8]

...

XI C48 [7:0]

XI C48 [15:8]

XI C49 [7:0]

XI C49 [15:8]

...

XQ C0 [7:0]

XQ C0 [15:8]

XQ C1 [7:0]

XQ C1 [15:8]

...

0x0E2E XQ C23 [7:0]

0x0E2F XQ C23 [15:0]

0x0F00 Unused

0x0F01 Unused

0x0F02 Unused

0x0F03 Unused

XQ C23 [7:0]

XQ C23 [15:0]

YQ C24 [7:0]

YQ C24 [15:8]

YQ C25 [7:0]

YQ C25 [15:8]

...

XQ C23 [7:0]

XQ C23 [15:0]

YQ C0 [7:0]

YQ C0 [15:8]

YQ C1 [7:0]

YQ C1 [15:8]

...

XQ C23 [7:0]

XQ C23 [15:0]

YQ C0 [7:0]

YQ C0 [15:8]

YQ C1 [7:0]

YQ C1 [15:8]

...

XQ C23 [7:0]

XQ C23 [15:0]

YQ C24 [7:0]

YQ C24 [15:8]

YQ C25 [7:0]

YQ C25 [15:8]

...

XI C71 [7:0]

XI C71 [15:0]

YI C72 [7:0]

YI C72 [15:8]

YI C73 [7:0]

YI C73 [15:8]

...

XQ C23 [7:0]

XQ C23 [15:0]

YQ C24 [7:0]

YQ C24 [15:8]

YQ C25 [7:0]

YQ C25 [15:8]

...

Unused

0x0F2E Unused

0x0F2F Unused

0x0F30 Unused

YQ C47 [7:0]

YQ C47 [15:0]

Unused

YQ C23 [7:0]

YQ C23 [15:0]

Unused

YQ C23 [7:0]

YQ C23 [15:0]

Unused

YQ C47 [7:0]

YQ C47 [15:0]

YI C95 [7:0]

YI C95 [15:0]

Unused

YQ C47 [7:0]

YQ C47 [15:0]

Unused

Q Path Tapped

Delay

0: 0 tapped delay

(matches C0 in the

filter)

1: 1 tapped delays

…

47: 47 tapped

delays

¹XQ Cn means Q Path X Coefficient n. YQ Cn means Q Path Y Coefficient n.

²When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode.

³When using the I path in 96-tap filter mode, the Q path must be in bypass mode.

Rev. 0 | Page 41 of 138

AD6688

Data Sheet

DIGITAL DOWNCONVERTER (DDC)

The AD6688 includes four digital downconverters (DDC0 to

DDC3) that provide filtering and reduce the output data rate.

This digital processing section includes an NCO, multiple

decimating FIR filters, a gain stage, and a complex to real

conversion stage. Each of these processing blocks has control lines

that allow it to be independently enabled and disabled to provide

the desired processing function. The digital downconverter can be

configured to output either real data or complex output data.

DDC GENERAL DESCRIPTION

The four DDC blocks are used to extract a portion of the full

digital spectrum captured by the ADC(s). They are intended for

IF sampling or oversampled baseband radios requiring wide

bandwidth input signals.

Each DDC block contains the following signal processing

stages:

•

Frequency translation stage (optional)

Filtering stage

Gain stage (optional)

The DDCs output a 16-bit stream. To enable this operation, the

converter number of bits, N, is set to a default value of 16, even

though the analog core only outputs 14 bits. In full bandwidth

operation, the ADC outputs are the 14-bit word followed by two

zeros, unless the tail bits are enabled.

Complex to real conversion stage (optional)

Frequency Translation Stage (Optional)

DDC I/Q INPUT SELECTION

This stage consists of a phase coherent, numerically controlled

oscillator (NCO) and quadrature mixers that can be used for

frequency translation of both real or complex input signals. The

phase-coherent NCO allows an infinite number of frequency

hops that are all referenced back to a single synchronization

event. It also includes 16 shadow registers for fast-switching

applications. This stage shifts a portion of the available digital

spectrum down to baseband.

The AD6688 has two ADC channels and four DDC channels.

Each DDC channel has two input ports that can be paired to

support both real and complex inputs through the I/Q crossbar

mux. For real signals, both DDC input ports must select the

same ADC channel (that is, DDC Input Port I = ADC Channel A

and DDC Input Port Q = ADC Channel A). For complex

signals, each DDC input port must select different ADC

channels (that is, DDC Input Port I = ADC Channel A and

DDC Input Port Q = ADC Channel B).

Filtering Stage

After shifting down to baseband, this stage decimates the

frequency spectrum using multiple low pass FIR filters for rate

conversion. The decimation process lowers the output data rate,

which in turn reduces the output interface rate.

The inputs to each DDC are controlled by the DDC input selec-

tion registers (Register 0x0311, Register 0x0331, Register 0x0351,

and Register 0x0371). See Table 46 for information on how to

configure the DDCs.

Gain Stage (Optional)

DDC I/Q OUTPUT SELECTION

Because of losses associated with mixing a real input signal

down to baseband, this stage compensates by adding an

additional 0 dB or 6 dB of gain.

Each DDC channel has two output ports that can be paired to

support both real and complex outputs. For real output signals,

only the DDC Output Port I is used (the DDC Output Port Q is

invalid). For complex I/Q output signals, both DDC Output

Port I and DDC Output Port Q are used.

Complex to Real Conversion Stage (Optional)

When real outputs are necessary, this stage converts the

complex outputs back to real by performing an f_S/4 mixing

operation plus a filter to remove the complex component of the

signal.

The I/Q outputs to each DDC channel are controlled by the

DDC complex to real enable bit, Bit 3, in the DDC control

registers (Register 0x0310, Register 0x0330, Register 0x0350,

and Register 0x0370).

Figure 71 shows the detailed block diagram of the DDCs

implemented in the AD6688.

The chip Q ignore bit in the chip mode register (Register 0x0200,

Bit 5) controls the chip output muxing of all the DDC channels.

When all DDC channels use real outputs, set this bit high to

ignore all DDC Q output ports. When any of the DDC channels

are set to use complex I/Q outputs, the user must clear this bit

to use both DDC Output Port I and DDC Output Port Q. For

more information, see Figure 88.

Figure 72 shows an example usage of one of the four DDC

channels with a real input signal and four half-band filters

(HB4 + HB3 + HB2 + HB1) used. It shows both complex

(decimate by 16) and real (decimate by 8) output options.

Rev. 0 | Page 42 of 138

Data Sheet

AD6688

DDC 0

REAL/I

CONVERTER 0

NCO

AND

DECIMATION

FILTERS

MIXER

(OPTIONAL)

REAL/Q

REAL/I

Q CONVERTER 1

ADC A

SAMPLING

AT f_S

REAL/I

DDC 1

REAL/I

CONVERTER 2

NCO

AND

DECIMATION

FILTERS

MIXER

(OPTIONAL)

Q CONVERTER 3

REAL/Q

REAL/I

L

JESD204B LANES

AT UP TO

16Gbps

DDC 2

REAL/I

CONVERTER 4

NCO

AND

DECIMATION

FILTERS

MIXER

(OPTIONAL)

Q CONVERTER 5

REAL/Q

REAL/I

ADC B

SAMPLING

AT f_S

REAL/Q

DDC 3

REAL/I

CONVERTER 6

NCO

AND

DECIMATION

FILTERS

MIXER

(OPTIONAL)

REAL/Q

SYSREF

Q CONVERTER 7

SYSREF

SYNCHRONIZATION

CONTROL

SYSREF

CIRCUITS

DCM = DECIMATION

REGISTER MAP

CONTROLS

NCO CHANNEL

SELECTION

NCO CHANNEL

SELECTION

CIRCUITS

GPIO

PINS

Figure 71. DDC Detailed Block Diagram

Rev. 0 | Page 43 of 138

AD6688

Data Sheet

ADC

SAMPLING

AT f_S

ADC

REAL

REAL INPUT—SAMPLED AT f_S

BANDWIDTH OF

INTEREST

BANDWIDTH OF

INTEREST IMAGE

–

f_S/32

DC

–f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

FREQUENCY TRANSLATION STAGE (OPTIONAL)

I

DIGITAL MIXER + NCO

NCO TUNES CENTER OF

BANDWIDTH OF INTEREST

TO BASEBAND

FOR f_S/3 TUNING, THE FREQUENCY TUNING WORD = ROUND

48

13

((f_S/3)/f_S× 2 ) = +9.3825

cos(ωt)

(0x5555_5555_5555)

REAL

48-BIT

NCO

90°

0°

–sin(ωt)

Q

BANDWIDTH OF

INTEREST IMAGE

(–6dB LOSS DUE TO

NCO + MIXER)

DIGITAL FILTER

RESPONSE

BANDWIDTH OF INTEREST

(–6dB LOSS DUE TO

NCO + MIXER)

–

f_S/32

DC

–f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

FILTERING STAGE

4 DIGITAL HALF-BAND FILTERS

(HB4 + HB3 + HB2 + HB1)

HB4 FIR

HB3 FIR

HB2 FIR

HB1 FIR

I

Q

6dB GAIN TO

COMPENSATE FOR

NCO + MIXER LOSS

COMPLEX (I/Q) OUTPUTS

DECIMATE BY 16

GAIN STAGE (OPTIONAL)

0dB OR 6dB GAIN

DIGITAL FILTER

RESPONSE

I

2

GAIN STAGE (OPTIONAL)

0dB OR 6dB GAIN

Q

–

f_S/32

–

f_S/32

COMPLEX TO REAL

CONVERSION STAGE (OPTIONAL)

DC

–

f_S/8

–

f_S/16

f_S/8

–

f_S/16

f_S/4 MIXING + COMPLEX FILTER TO REMOVE Q

DOWNSAMPLE BY 2

I

REAL (I) OUTPUTS

DECIMATE BY 8

COMPLEX

TO

REAL

REAL/I

Q

6dB GAIN TO

COMPENSATE FOR

NCO + MIXER LOSS

–

f_S/32

DC

–

f_S/8

–

f_S/16

f_S/8

Figure 72. DDC Theory of Operation Example (Real Input)

Rev. 0 | Page 44 of 138

Data Sheet

AD6688

Variable IF Mode

DDC FREQUENCY TRANSLATION

In this mode, the NCO and mixers are enabled. NCO output

frequency can be used to digitally tune the IF frequency.

DDC Frequency Translation General Description

Frequency translation is accomplished by using a 48-bit

complex NCO with a digital quadrature mixer. This stage

translates either a real or complex input signal from an IF to a

baseband complex digital output (carrier frequency = 0 Hz).

0 Hz IF (ZIF) Mode

In this mode, the mixers are bypassed, and the NCO is disabled.

f_S/4 Hz IF Mode

The frequency translation stage of each DDC can be controlled

individually and supports four different IF modes using Bits[5:4]

of the DDC control registers (Register 0x0310, Register 0x0330,

Register 0x0350, and Register 0x0370). These IF modes are

In this mode, the mixers and the NCO are enabled in special

downmixing by f_S/4 mode to save power.

Test Mode

In this mode, input samples are forced to 0.999 to positive full

scale. The NCO is enabled. This test mode allows the NCOs to

directly drive the decimation filters.

•

Variable IF mode

0 Hz IF or zero IF (ZIF) mode

f_S/4 Hz IF mode

Figure 73 and Figure 74 show examples of the frequency

translation stage for both real and complex inputs.

Test mode

NCO FREQUENCY TUNING WORD (FTW) SELECTION

48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096

I

cos(ωt)

ADC

SAMPLING

AT f_S

ADC + DIGITAL MIXER + NCO

REAL INPUT—SAMPLED AT f_S

REAL

48-BIT

NCO

90°

0°

COMPLEX

–sin(ωt)

Q

BANDWIDTH OF

INTEREST IMAGE

BANDWIDTH OF

INTEREST

–

f_S/32

DC

–f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

–6dB LOSS DUE TO

NCO + MIXER

48-BIT NCO FTW =

48

POSITIVE FTW VALUES

13

ROUND ((f_S/3)/f_S× 2 ) = +9.3825

(0x5555_5555_5555)

–f_S/32

f_S/32

DC

48-BIT NCO FTW =

48

13

ROUND ((f_S/3)/f_S× 2 ) = –9.3825

NEGATIVE FTW VALUES

(0xAAAA_AAAA_AAAB)

–f_S/32

f_S/32

DC

Figure 73. DDC NCO Frequency Tuning Word Selection—Real Inputs

Rev. 0 | Page 45 of 138

AD6688

Data Sheet

NCO FREQUENCY TUNING WORD (FTW) SELECTION

48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 2

48

QUADRATURE MIXER

ADC

SAMPLING

AT f_S

I

+

I

–

I

Q

QUADRATURE ANALOG MIXER +

Q

2 ADCs + QUADRATURE DIGITAL

MIXER + NCO

REAL

90°

PHASE

48-BIT

NCO

90°

0°

COMPLEX

Q

COMPLEX INPUT—SAMPLED AT f_S

I

+

ADC

SAMPLING

AT f_S

Q

+

BANDWIDTH OF

INTEREST

IMAGE DUE TO

ANALOG I/Q

MISMATCH

–

f_S/32

f_S/16

–f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

DC

48-BIT NCO FTW =

48

13

ROUND ((f_S/3)/f_S× 2 ) = +9.3825

(0x5555_5555_5555)

POSITIVE FTW VALUES

–f_S/32

f_S/32

DC

Figure 74. DDC NCO Frequency Tuning Word Selection—Complex Inputs

Rev. 0 | Page 46 of 138

Data Sheet

AD6688

DDC NCO Description

DDC NCO Coherent Mode

Each DDC contains one NCO. Each NCO enables the

frequency translation process by creating a complex exponential

frequency (e^-jωct), which can be mixed with the input spectrum

to translate the desired frequency band of interest to dc, where

it can be filtered by the subsequent low-pass filter blocks to

prevent aliasing.

This mode allows an infinite number of frequency hops where the

phase is referenced to a single synchronization event at Time 0.

This mode is useful when phase coherency must be maintained

when switching between different frequency bands. In this mode,

the user can switch to any tuning frequency without the need to

reset the NCO. Although only one FTW is required, the NCO

contains 16 shadow registers for fast switching applications.

Selection of the shadow registers is controlled by the CMOS

GPIO pins or through the register map of the SPI. In this mode,

the NCO can be set up by providing the following:

When placed in variable IF mode, the NCO supports two

different additional modes.

DDC NCO Programmable Modulus Mode

This mode supports >48-bit frequency tuning accuracy for

applications that require exact rational (M/N) frequency

synthesis at a single carrier frequency. In this mode, the NCO is

set up by providing the following:

•

Up to 16, 48-bit FTWs.

Up to 16, 48-bit POWs.

The 48-bit MAW must be set to 0 in coherent mode.

Figure 75 shows a block diagram of one NCO and its

connection to the rest of the design. The coherent phase

accumulator block contains the logic that allows an infinite

number of frequency hops. The gray lines in Figure 75 represent

SPI control lines.

•

48-bit frequency tuning word (FTW)

48-bit Modulus A word (MAW)

48-bit Modulus B word (MBW)

48-bit phase offset word (POW)

NCO

CHANNEL

SELECTION

CIRCUITS

NCO CHANNEL

SELECTION

MAW/MBW

48-BIT

MAW/MBW

MODULUS

ERROR

48-BIT

0

1

0

1

FTW/POW

48-BIT

FTW/POW

COHERENT

PHASE

ACCUMULATOR

BLOCK

FTW/POW

REGISTER

MAP

COS/SIN

GENERATOR

15

48-BIT

FTW/POW

15

FTW/POW

WRITE INDEX

SYSREF

SYNCHRONIZATION

CONTROL CIRCUITS

I

I/O

CROSSBAR

MUX

DECIMATION

FILTERS

Q

DIGITAL

QUADRATURE

MIXER

FTW = FREQUENCY TUNING WORD

POW = PHASE OFFSET WORD

MAW = MODULUS A WORD (NUMERATOR)

MBW = MODULUS B WORD (DENOMINATOR)

Figure 75. NCO + Mixer Block Diagram

Rev. 0 | Page 47 of 138

AD6688

Data Sheet

NCO FTW/POW/MAW/MAB Description

Note that Equation 1 to Equation 4 apply to the aliasing of

signals in the digital domain (that is, aliasing introduced when

digitizing analog signals).

The NCO frequency value is determined by the following settings:

•

A 48-bit twos complement number entered in the FTW.

A 48-bit unsigned number entered in the MAW.

A 48-bit unsigned number entered in the MBW.

M and N are integers reduced to their lowest terms. MAW and

MBW are integers reduced to their lowest terms. When MAW is

set to zero, the programmable modulus logic is automatically

disabled.

Frequencies between −f_S/2 and +f_S/2 (f_S/2 excluded) are

represented using the following values:

For example, if the ADC sampling frequency (f_S) is 3000 MSPS

and the carrier frequency (f_C) is 1001.5 MHz, then,

•

FTW = 0x8000_0000_0000 and MAW = 0x0000_0000_0000

represents a frequency of –f_S/2.

FTW = 0x0000_0000_0000 and MAW = 0x0000_0000_0000

represents dc (frequency is 0 Hz).

FTW = 0x7FFF_FFFF_FFFF and MAW = 0x0000_0000_0000

represents a frequency of +f_S/2.

mod(1001.5, 3000)

3000

M

N

2003

6000

=

mod(1001.5, 3000)

3000

FTW = floor(2⁴⁸

)

= 0x5576_19F0_FB38

NCO FTW/POW/MAW/MAB Programmable Modulus

Mode

MAW = mod(2⁴⁸× 2003, 6000) = 0x0000_0000_0F80

MBW = 0x0000_0000_1770

For programmable modulus mode, the MAW must be set to a

nonzero value (not equal to 0x0000_0000_0000). This mode is

only needed when frequency accuracy of >48 bits is required. One

example of a rational frequency synthesis requirement that requires

>48 bits of accuracy is a carrier frequency of 1/3 the sample

rate. When frequency accuracy of ≤48 bits is required, coherent

mode must be used (see the NCO FTW/POW/MAW/MAB

Coherent Mode section).

The actual carrier frequency can be calculated based on the

following equation:

MAW

FTW +

× f_S

MBW

f_{C _ ACTUAL}

=

2⁴⁸

For the previous example, the actual carrier frequency (f_{C_ACTUAL}

)

is

In programmable modulus mode, the FTW, MAW, and MBW

must satisfy the following four equations (for a detailed

description of the programmable modulus feature, see the DDS

architecture described in the AN-953 Application Note):

f_{C _ ACTUAL}

0x0000_0000_0F80

0x0000_0000_1770

0x5576_19F0_FB38 ×

=

2⁴⁸

MAW

MBW

FTW +

mod( f_c, f_s)

M

N

=1001.5 MHz

(1)

(2)

=

f_s

2⁴⁸

A 48-bit POW is available for each NCO to create a known

phase relationship between multiple chips or individual DDC

channels inside the chip.

mod( f_c, f_s)

FTW = floor(2⁴⁸

)

f_s

MAW = mod(2⁴⁸× M,N)

(3)

(4)

While in programmable modulus mode, the FTW and POW

registers can be updated at any time while still maintaining

deterministic phase results in the NCO. However, the following

procedure must be followed to update the MAW and/or MBW

registers to ensure proper operation of the NCO:

MBW = N

where:

f_Cis the desired carrier frequency.

f_Sis the ADC sampling frequency.

M is the integer representing the rational numerator of the

frequency ratio.

N is the integer representing the rational denominator of the

frequency ratio.

1. Write to the MAW and MBW registers for all the DDCs.

2. Synchronize the NCOs either through the DDC soft reset

bit accessible through the SPI or through the assertion of

the SYSREF pin (see the Memory Map section).

FTW is the 48-bit twos complement number representing the

NCO FTW.

MAW is the 48-bit unsigned number representing the NCO

MAW (must be <2⁴⁷).

MBW is the 48-bit unsigned number representing the NC O M BW.

mod(x) is a remainder function. For example mod(110,100) =

10 and for negative numbers, mod(–32,10)= –2.

floor(x) is defined as the largest integer less than or equal to x.

For example, floor(3.6) = 3.

Rev. 0 | Page 48 of 138

Data Sheet

AD6688

For the previous example, the actual carrier frequency (f_{C_ACTUAL}) is

NCO FTW/POW/MAW/MAB Coherent Mode

416.6673000

For coherent mode, the NCO MAW must be set to zero

(0x0000_0000_0000). In this mode, the NCO FTW can be

calculated by the following equation:

f

_{C _ ACTUAL}

 416.66699MHz

2⁴⁸

A 48-bit POW is available for each NCO to create a known

phase relationship between multiple chips or individual DDC

channels inside the chip.

mod(f_c, f_s)

FTW  round(2⁴⁸

)

(5)

f_s

While in coherent mode, the FTW and POW registers can be

updated at any time while still maintaining deterministic phase

results in the NCO.

where:

FTW is the 48-bit twos complement number representing the

NCO FTW.

f_Sis the ADC sampling frequency.

f_Cis the desired carrier frequency.

mod(x) is a remainder function. For example mod(110,100) =

10 and for negative numbers, mod(–32,10) = –2.

round(x) is a rounding function. For example round(3.6) = 4

and for negative numbers, round(–3.4)= –3.

NCO Channel Selection

When configured in coherent mode, only one FTW is required

in the NCO. In this mode, the user can switch to any tuning

frequency without the need to reset the NCO by writing to the

FTW directly. However, for fast switching applications, where

either all FTWs are known beforehand or it is possible to queue

up the next set of FTWs, the NCO contains 16 additional

shadow registers (see Figure 75). These shadow registers are

hereafter referred to as the NCO channels.

Note that Equation 5 applies to the aliasing of signals in the

digital domain (that is, aliasing introduced when digitizing

analog signals). The MAW must be set to zero to use coherent

mode. When MAW is zero, the programmable modulus logic is

automatically disabled.

Figure 76 shows a simplified block diagram of the NCO channel

selection block. The gray lines in Figure 76 represent SPI

control lines.

For example, if the ADC sampling frequency (f_S) is 3000 MSPS

and the carrier frequency (f_C) is 416.667 MHz, then,

Only one NCO channel is active at a time, and NCO channel

selection is controlled either by the CMOS GPIO pins or

through the register map.

NCO _ FTW

mod(416.667,3000)

3000

 0x2EC6_C03A_8E23

 round(2⁴⁸

)

Each NCO channel selector supports three different modes, as

described in the following sections.

The actual carrier frequency can be calculated based on the

following equation:

FTW  f_S

f_{C _ ACTUAL}



2⁴⁸

NCO CHANNEL

SELECTION

IN

GPIO

CMOS

PINS

[3:0]

GPIO

SELECTION

[0]

NCO CHANNEL SELECTION

NCO

MUX

COUNTER

INC

REGISTER MAP NCO

CHANNEL SELECTION

0x0314, 0x0334, 0x0354, 0x0374

REGISTER

MAP

NCO CHANNEL MODE

Figure 76. NCO Channel Selection Block

Rev. 0 | Page 49 of 138

AD6688

Data Sheet

GPIO Level Control Mode

The following procedure must be followed to use GPIO edge

control for NCO channel selection:

The GPIO pins determine the exact NCO channel selected.

1. Configure one or more GPIO pins as NCO channel

selection inputs.

The following procedure must be followed to use GPIO level

control for NCO channel selection:

a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to

0x6 and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to

0x6 and Bits[7:4] in Register 0x0041 to 0x0.

c. To use GPIO_A1, write Bits[3:0] in Register 0x0042 to

0x0.

1. Configure one or more GPIO pins as NCO channel

selection inputs. GPIO pins not configured as NCO

channel selection are internally tied low.

a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to

0x6 and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to

0x6 and Bits[7:4] in Register 0x0041 to 0x0.

c. To use GPIO_A1, write Bits[3:0] in Register 0x0042 to

0x0.

d. To use GPIO_B1, write Bits[7:4] in Register 0x0042 to

0x0.

2. Configure the NCO channel selector in GPIO edge control

mode by setting Bits[7:4] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

Register 0x0374) to 0x8 through 0xB, depending on the

desired GPIO Pin.

3. Configure the wrap point for the NCO channel selection

by setting Bits[3:0] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

Register 0x0374). A value of 4 causes the channel selection

to wrap at Channel 4 (0, 1, 2, 3, 4, 0, 1, 2, 3, 4, and so on).

4. Transition the selected GPIO pin from low to high to

increment the NCO channel selection.

d. To use GPIO_B1, write Bits[7:4] in Register 0x0042 to

0x0.

2. Configure the NCO channel selector in GPIO level control

mode by setting Bits[7:4] in the NCO control registers

(Register 0x0314, Register 0x0334, Register 0x0354, and

Register 0x0374) to 0x1 through 0x6, depending on the

desired GPIO pin ordering.

3. Select the desired NCO channel through the GPIO pins.

GPIO Edge Control Mode

Low to high transition on a single GPIO pin determines the

exact NCO channel selected. The internal channel selection

counter is reset by either SYSREF or the DDC soft reset.

Register Map Mode

NCO channel selection is controlled directly through the

register map.

Rev. 0 | Page 50 of 138

Data Sheet

AD6688

f₀

f₁

f₂

ACTIVE

DDC

B2

B1

B0

NCO CHANNEL 0

CARRIER FREQUENCY 0

(ACTIVE)

NCO CHANNEL 1

CARRIER FREQUENCY 1

(STANDBY)

NCO CHANNEL 2

CARRIER FREQUENCY 2

(STANDBY)

DC

f_S/2

Figure 77. NCO Coherent Mode with Three NCO Channels (B0 Selected)

Figure 77 shows an example use case for coherent mode

utilizing three NCO channels. In this example, NCO Channel 0 is

actively downconverting bandwidth 0 (B0) while NCO Channel 1

and Channel 2 are in standby and tuned to Bandwidth 1 and

Bandwidth 2 (B1 and B2), respectively.

The following sequence describes the method for selecting the

active NCO channel using GPIO CMOS pins.

1. Set NCO channel selection mode (Bits[7:4]) in

Register 0x0314, Register 0x0334, Register 0x0354, and

Register 0x0374 to a nonzero value to enable GPIO pin

selection.

2. Configure the GPIO pins as NCO channel selection inputs

by writing to Register 0x0040, Register 0x0041, and

Register 0x0042.

The phase coherent NCO switching feature allows infinite number

of frequency hops that are all phase coherent. The initial phase of

the NCO is established at Time t₀from SYSREF synchronization.

Switching the NCO FTW does not affect the phase. With this

feature, only one FTW is required; however, the user may want

to use all 16 channels to queue up the next hop.

3. NCO switching is done by externally controlling the GPIO

CMOS pins.

After SYSREF synchronization at start-up, all NCOs across

multiple chips are inherently synchronized.

NCO Synchronization

Each NCO contains a separate phase accumulator word (PAW).

The initial reset value of each PAW is set to zero and incremented

every clock cycle. The instantaneous phase of the NCO is

calculated using the PAW, FTW, MAW, MBW, and POW.

Because of this architecture, the FTW and POW registers can

be updated at any time while still maintaining deterministic

phase results in the PAW of the NCO.

Setting Up the Multichannel NCO Feature

The first step to configure the multichannel NCO is to program

the FTWs. The AD6688 memory map has a FTW index register

for each DDC. This index determines which NCO channel

receives the FTW from the register map. The following

sequence describes the method for programming the FTWs.

Two methods can be used to synchronize multiple PAWs within

the chip:

1. Write the FTW index register with the desired DDC

channel.

2. Write the FTW with the desired value. This value is applied

to the NCO channel index mentioned in Step 1.

3. Repeat Step 1 and Step 2 for other NCO channels.

•

Using the SPI. Use The DDC soft reset bit in the DDC

synchronization control register (Register 0x0300, Bit 4) to

reset all the PAWs in the chip. This is accomplished by

setting the DDC soft reset high and then setting this bit

low. Note that this method can only be used to synchronize

DDC channels within the same chip.

Using the SYSREF pin. When the SYSREF pin is enabled

in the SYSREF control registers (Register 0x0120 and

Register 0x0121) and the DDC synchronization is enabled in

the DDC synchronization control register (Register 0x0300,

Bits[1:0]); any subsequent SYSREF event resets all the PAWs

in the chip. Note that this method can be used to synchronize

DDC channels within the same chip or DDC channels within

separate chips.

After setting the FTWs, the user must then select an active

NCO channel. This selection can be done either through the

SPI registers or through the external GPIO pins. The following

sequence describes the method for selecting the active NCO

channel using SPI.

•

1. Set the NCO channel selection mode (Bits[7:4]) in

Register 0x0314, Register 0x0334, Register 0x0354, and

Register 0x0374 to 0x0 to enable SPI selection.

2. Choose the active NCO channel (Bits[3:0]) in Register 0x0314,

Register 0x0334, Register 0x0354, and Register 0x0374.

Rev. 0 | Page 51 of 138

AD6688

Data Sheet

1 LINK,

L LANES

NCO Multichip Synchronization

MNTO

ADC DEVICE 0

(MASTER)

In some applications, it is necessary to synchronize all the

NCOs and LMFCs within multiple devices in a system. For

applications needing multiple NCO tuning frequencies in the

system, a designer likely needs to generate a single SYSREF

pulse at all devices simultaneously. For many systems,

generating/receiving a single-shot SYSREF at all devices is

challenging because enabling/disabling the SYSREF is often an

asynchronous event, and not all clock generation chips support

this feature.

1 LINK,

SNTI

L LANES

ADC DEVICE 1

(SLAVE)

1 LINK,

L LANES

ADC DEVICE 2

(SLAVE)

For this reason, the AD6688 contains a synchronization

triggering mechanism that allows the following:

1 LINK,

L LANES

ADC DEVICE 3

(SLAVE)

•

At system startup, multichip synchronization of all NCOs

and LMFCs.

SYSREF±

•

During normal operation, multichip synchronization of all

NCOs after applying new tuning frequencies.

CLOCK

GENERATION

DEVICE_CLOCK±

The synchronization triggering mechanism uses a master/slave

arrangement, as shown in Figure 78.

MNTO = MASTER NEXT TRIGGER OUTPUT (CMOS)

SNTI = SLAVE NEXT TRIGGER INPUT (CMOS)

Figure 78. System using Master/Slave Synchronization Triggering

Each device has an internal next synchronization trigger enable

(NSTE) signal that controls whether the next SYSREF causes a

synchronization event. Slave ADC devices must source their

NSTE from an external slave next trigger input (SNTI) pin.

Master devices can either use their external master next trigger

output (MNTO) pin (default setting) or use an external

SNTI pin.

NCO Multichip Synchronization at Startup

Figure 79 shows a timing diagram along with the required

sequence of events for NCO multichip synchronization using

triggering and SYSREF at startup. Using this startup sequence

synchronizes all the NCOs and LMFCs in the system at once.

NCO Multichip Synchronization During Normal Operation

See Register 0x0041 and Register 0x0042 in Table 46 to

configure the FD/GPIO pins for this operation.

See the Setting Up the Multichannel NCO Feature section.

CONFIGURE MASTER AND SLAVE DEVICES

ENABLE TRIGGER IN MASTER DEVICES

SYSTEM

SYNCHRONIZATION

ACHIEVED

SYSREF

IGNORED

MNTO SET HIGH

SNTI SET HIGH

DEVICE

CLOCK

SYSREF

MNTO

SNTI

BOARD PROPAGATION

DELAY

INPUT DELAY

NSTE

LMFC

SYNCHRONIZED

LMFCS

DON’T CARE

NCOS

DON’T CARE

NCO

SYNCHRONIZED

LEGEND

MNTO = MASTER NEXT TRIGGER OUTPUT (CMOS)

SNTI = SLAVE NEXT TRIGGER INPUT (CMOS)

NSTE = NEXT SYNCHRONIZATION TRIGGER ENABLE

LMFC = LOCAL MULTIFRAME CLOCK

NCO = NUMERICALLY CONTROLLED OSCILLATOR

Figure 79. NCO Multichip Synchronization at Startup (Using Triggering and SYSREF)

Rev. 0 | Page 52 of 138

Data Sheet

AD6688

maximum value each I/Q sample can reach is 1.414 × full-scale

after it passes through the complex mixer. To avoid overrange of

the I/Q samples and to keep the data bit widths aligned with

real mixing, −3.06 dB of loss is introduced in the mixer for

complex signals. An additional −0.05 dB of loss is introduced by

the NCO. The total loss of a complex input signal mixed down

to baseband is −3.11 dB.

DDC Mixer Description

When not bypassed (Register 0x0200 ≠ 0x00), the digital

quadrature mixer performs a similar operation to an analog

quadrature mixer. It performs the downconversion of input

signals (real or complex) by using the NCO frequency as a local

oscillator. For real input signals, a real mixer operation (with

two multipliers) is performed. For complex input signals, a

complex mixer operation (with four multipliers and two adders)

is performed. The selection of real or complex inputs can be

controlled individually for each DDC block using Bit 7 of the

DDC control registers (Register 0x0310, Register 0x0330,

Register 0x0350, and Register 0x0370).

The worst case spurious signal from the NCO is greater than

102 dBc SFDR for all output frequencies.

DDC DECIMATION FILTERS

After the frequency translation stage, there are multiple

decimation filter stages used to reduce the output data rate.

After the carrier of interest is tuned down to dc (carrier

frequency = 0 Hz), these filters efficiently lower the sample rate,

while providing sufficient alias rejection from unwanted

adjacent carriers around the bandwidth of interest.

DDC NCO + Mixer Loss and SFDR

When mixing a real input signal down to baseband, −6 dB of

loss is introduced in the signal due to filtering of the negative

image. An additional −0.05 dB of loss is introduced by the

NCO. The total loss of a real input signal mixed down to

baseband is −6.05 dB. For this reason, it is recommended that

the user compensate for this loss by enabling the 6 dB of gain in

the gain stage of the DDC to recenter the dynamic range of the

signal within the full scale of the output bits (see the DDC Gain

Stage section for more information).

Figure 80 shows a simplified block diagram of the decimation

filter stage, and Table 16 describes the filter characteristics of

the different finite impulse response (FIR) filter blocks.

Table 17 and Table 18 show the different filter configurations

selectable by including different filters. In all cases, the DDC

filtering stage provides 80% of the available output bandwidth,

< 0.005 dB of passband ripple, and >100 dB of stop band alias

rejection.

When mixing a complex input signal (where I and Q DDC

inputs come from the different ADCs) down to baseband, the

DCM = 3

TB1

DECIMATION FILTERS

I

FIR

I

DCM = 2

HB4

FIR

HB3

FIR

HB2

FIR

HB1

FIR

DCM = 3

TB2

FIR

DCM = 5

FB2

FIR

I

NCO

AND

MIXERS

(OPTIONAL)

DCM = 5

Q

FB2

FIR

TB2

FIR

DCM = 3

HB3

FIR

HB2

FIR

HB4

FIR

HB1

FIR

Q

DCM = 2

TB1

FIR

Q

DCM = 3

FIR = FINITE IMPULSE RESPONSE FILTER

DCM = DECIMATION

NOTES

1. TB1 IS ONLY SUPPORTED IN DDC0 AND DDC1

Figure 80. DDC Decimation Filter Block Diagram

Rev. 0 | Page 53 of 138

AD6688

Data Sheet

Table 16. DDC Decimation Filter Characteristics

Decimation

Ratio

Pass Band

(rad/sec)

Stop Band

(rad/sec)

Pass-Band

Ripple (dB)

Stop-Band

Attenuation (dB)

Filter Name

HB4

HB3

HB2

HB1

TB2

TB1¹

FB2

Filter Type

FIR low-pass

2

3

5

0.1 x π/2

0.2 x π/2

0.4 x π/2

0.8 x π/2

0.4 x π/3

0.8 x π/3

0.4 x π/5

1.9 x π/2

1.8 x π/2

1.6 x π/2

1.2 x π/2

1.6 x π/3

1.2 x π/3

1.6 x π/5

< 0.001

< 0.002

< 0.005

< 0.001

>100

¹TB1 is only supported in DDC0 and DDC1.

Table 17. DDC Filter Configurations¹

Real (I) Output

Decimation Sample

Complex (I/Q) Outputs

Decimation

ADC

Sample

Rate

Alias-

Protected

Bandwidth

Ideal SNR

Improvement

DDC Filter Configuration

HB1

Ratio

Rate

Ratio

Sample Rate

(dB)²

f_S

1

f_S

2

3

4

6

f_S/2 (I) + f_S/2 (Q)

f f_S/3 (I) + f_S/3 (Q)

f_S/4 (I) + f_S/4 (Q)

f_S/6 (I) + f_S/6 (Q)

f_S/8 (I) + f_S/8 (Q)

f_S/10 (I) + f_S/10 (Q)

f_S/12 (I) + f_S/12 (Q)

f_S/15 (I) + f_S/15 (Q)

f_S/16 (I) + f_S/16 (Q)

f_S/20 (I) + f_S/20 (Q)

f_S/24 (I) + f_S/24 (Q)

f_S/30 (I) + f_S/30 (Q)

f_S/40 (I) + f_S/40 (Q)

f_S/48 (I) + f_S/48 (Q)

f_S/2 × 80%

f_S/3 × 80%

f_S/4 × 80%

f_S/6 × 80%

f_S/8 × 80%

f_S/10 × 80%

f_S/12 × 80%

f_S/15 × 80%

f_S/16 × 80%

f_S/20 × 80%

f_S/24 × 80%

f_S/30 × 80%

f_S/40 × 80%

f_S/48 × 80%

1

2.7

4

5.7

7

8

8.8

9.7

10

11

11.8

12.7

14

14.8

TB1³

N/A

2

3

4

5

6

N/A

8

10

12

N/A

20

N/A

f_S/2

f_S/3

f_S/4

f_S/5

f_S/6

N/A

f_S/8

f_S/10

f_S/12

N/A

f_S/20

f_S/24

HB2 + HB1

TB2 + HB1

HB3 + HB2 + HB1

FB2 + HB1

TB2 + HB2 + HB1

FB2 + TB1³

HB4 + HB3 + HB2 + HB1

FB2 + HB2 + HB1

TB2 + HB3 + HB2 + HB1

HB2 + FB2 + TB1³

FB2 + HB3 + HB2 + HB1

8

10

12

15

16

20

24

30

40

48

TB2 + HB4 + HB3 + HB2 + HB1 24

¹N/A means not applicable.

²Ideal SNR improvement due to oversampling + filtering > 10log(bandwidth/f_S/2).

³TB1 is only supported in DDC0 and DDC1.

Table 18. DDC Filter Configurations (f_S= 3000 MSPS)¹

Real (I) Output

Complex (I/Q) Outputs

Alias-Protected

Bandwidth

(MHz)

ADC Sample

Rate (MSPS)

Decimation Sample Rate Decimation Sample Rate

DDC Filter Configuration

HB1

Ratio

1

N/A

2

3

4

5

6

N/A

8

10

12

N/A

20

24

(MSPS)

3000

N/A

1500

1000

750

600

500

N/A

375

300

Ratio

2

3

4

6

(MSPS)

3000

1500 (I) + 1500 (Q)

1000 (I) + 1000 (Q)

750 (I) + 750 (Q)

500 (I) + 500 (Q)

375 (I) + 375 (Q)

300 (I) + 300 (Q)

250 (I) + 250 (Q)

200 (I) + 200 (Q)

187.5 (I) + 187.5 (Q)

150 (I) + 150 (Q)

125 (I) + 125 (Q)

100 (I) + 100 (Q)

75 (I) + 75 (Q)

1200

800

600

400

300

240

200

160

150

120

100

80

TB1²

HB2 + HB1

TB2 + HB1

HB3 + HB2 + HB1

FB2 + HB1

TB2 + HB2 + HB1

FB2 + TB12

HB4 + HB3 + HB2 + HB1

FB2 + HB2 + HB1

TB2 + HB3 + HB2 + HB1

HB2 + FB2 + TB12

FB2 + HB3 + HB2 + HB1

TB2 + HB4 + HB3 + HB2 + HB1

8

10

12

15

16

20

24

30

40

48

250

N/A

150

60

50

125

62.5 (I) + 62.5 (Q)

¹N/A means not applicable.

²TB1 is only supported in DDC0 and DDC1.

Rev. 0 | Page 54 of 138

Data Sheet

AD6688

20

0

HB4 Filter Description

The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses

an 11-tap, symmetrical, fixed coefficient filter implementation

that is optimized for low power consumption. The HB4 filter is

only used when complex outputs (decimate by 16) or real

outputs (decimate by 8) are enabled; otherwise, it is bypassed.

Table 19 and Figure 81 show the coefficients and response of

the HB4 filter.

–20

–40

–60

–80

–100

–120

–140

–160

Table 19. HB4 Filter Coefficients

HB4 Coefficient

Number

Normalized

Coefficient

Decimal

Coefficient (15-Bit)

C1, C11

C2, C10

C3, C9

C4, C8

C5, C7

C6

0.006042

0

−0.049377

0

0.293304

0.5

99

0

−809

0

4806

8192

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NORMALIZED FREQUENCY (× Π RAD/s)

Figure 82. HB3 Filter Response

HB2 Filter Description

The third decimate by 2, half-band, low-pass, FIR filter (HB2)

uses a 19-tap, symmetrical, fixed coefficient filter implementa-

tion that is optimized for low power consumption.

20

0

The HB2 filter is only used when complex or real outputs

(decimate by 4, 8, or 16) is enabled; otherwise, it is bypassed.

–20

Table 21 and Figure 83 show the coefficients and response of

the HB2 filter.

–40

–60

Table 21. HB2 Filter Coefficients

–80

HB2 Coefficient

Number

Normalized

Coefficient

Decimal

Coefficient (18-Bit)

–100

–120

–140

–160

C1, C19

C2, C18

C3, C17

C4, C16

C5, C15

C6, C14

C7, C13

C8, C12

C9, C11

C10

0.000671

0

−0.005325

0

0.022743

0

−0.074180

0

88

0

−698

0

2981

0

−9723

0

40120

65536

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NORMALIZED FREQUENCY (× Π RAD/s)

Figure 81. HB4 Filter Response

HB3 Filter Description

The second decimate by 2, half-band, low-pass, FIR filter (HB3)

uses an 11-tap, symmetrical, fixed coefficient filter implementa-

tion that is optimized for low power consumption. The HB3

filter is only used when complex outputs (decimate by 8 or 16)

or real outputs (decimate by 4 or 8) are enabled; otherwise, it is

bypassed. Table 20 and Figure 82 show the coefficients and

response of the HB3 filter.

0.306091

0.5

20

0

–20

–40

Table 20. HB3 Filter Coefficients

–60

HB3 Coefficient

Number

Normalized

Coefficient

Decimal Coefficient

(17-Bit)

–80

C1, C11

C2, C10

C3, C9

C4, C8

C5, C7

C6

0.006637

0

−0.051055

0

0.294418

0.500000

435

0

−3346

0

19295

65,536

–100

–120

–140

–160

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NORMALIZED FREQUENCY (× Π RAD/s)

Figure 83. HB2 Filter Response

Rev. 0 | Page 55 of 138

AD6688

Data Sheet

20

0

HB1 Filter Description

The fourth and final decimate by 2, half-band, low-pass, FIR

filter (HB1) uses a 63-tap, symmetrical, fixed coefficient filter

implementation that is optimized for low power consumption. The

HB1 filter is always enabled and cannot be bypassed. Table 22 and

Figure 84 show the coefficients and response of the HB1 filter.

–20

–40

–60

–80

Table 22. HB1 Filter Coefficients

–100

–120

–140

–160

HB1 Coefficient

Number

Normalized

Coefficient

Decimal

Coefficient (20-Bit)

C1, C63

C2, C62

C3, C61

C4, C60

C5, C59

C6, C58

C7, C57

C8, C56

C9, C55

C10, C54

C11, C53

C12, C52

C13, C51

C14, C50

C15, C49

C16, C48

C17, C47

C18, C46

C19, C45

C20, C44

C21, C43

C22, C42

C23, C41

C24, C40

C25, C39

C26, C38

C27, C37

C28, C36

C29, C35

C30, C34

C31, C33

C32

−0.000019

0

0.000072

0

−0.000195

0

0.000443

0

−0.000891

0

0.001644

0

−0.00284

0

0.004654

0

−0.007311

0

0.011122

0

−0.016554

0

0.02442

0

−0.036404

0

0.056866

0

−0.101892

0

0.316883

0.5

−10

0

38

0

−102

0

232

0

−467

0

862

0

−1489

0

2440

0

−3833

0

5831

0

−8679

0

12803

0

−19086

0

29814

0

−53421

0

166138

262144

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NORMALIZED FREQUENCY (× Π RAD/s)

Figure 84. HB1 Filter Response

TB2 Filter Description

The TB2 uses a 26-tap, symmetrical, fixed coefficient filter

implementation that is optimized for low power consumption.

The TB2 filter is only used when decimation ratios of 6, 12, or 24

are required. Table 23 and Figure 85 show the coefficients and

response of the TB2 filter.

Table 23. TB2 Filter Coefficients

TB2 Coefficient

Number

Normalized

Coefficient

Decimal

Coefficient (19-Bit)

C1, C26

C2, C25

C3, C24

C4, C23

C5, C22

C6, C21

C7, C20

C8, C19

C9, C18

C10, C17

C11, C16

C12, C15

C13, C14

−0.000190

−0.000793

−0.00113

0.000915

0.006290

0.009822

0.000915

−0.023483

−0.043151

−0.019317

0.071327

0.201171

0.297756

−50

−208

−298

240

1649

2575

240

−6156

−11312

−5064

18698

52736

78055

20

0

–20

–40

–60

–80

–100

–120

–140

–160

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NORMALIZED FREQUENCY (× Π RAD/s)

Figure 85. TB2 Filter Response

Rev. 0 | Page 56 of 138

Data Sheet

AD6688

20

0

TB1 Filter Description

The TB1 decimate by 3, low-pass, FIR filter uses a 76-tap,

symmetrical, fixed-coefficient filter implementation. Table 24

shows the TB1 filter coefficients and Figure 86 shows the TB1

filter response. TB1 is only supported in DDC0 and DDC1.

–20

–40

–60

Table 24. TB1 Filter Coefficients

–80

TB1 Coefficient Decimal

Quantized Coefficient

(22-Bit)

–100

–120

–140

–160

Number

Coefficient

1, 96

2, 75

3, 74

4, 73

5, 72

6, 71

7, 70

8, 69

−0.000023

−0.000053

−0.000037

0.000090

0.000291

0.000366

0.000095

−0.000463

−0.000822

−0.000412

0.000739

0.001665

0.001132

−0.000981

−0.002961

−0.002438

0.001087

0.004833

0.004614

−0.000871

−0.007410

−0.008039

0.000053

0.010874

0.013313

0.001817

−0.015579

−0.021590

−0.005603

0.022451

0.035774

0.013541

−0.034655

−0.066549

−0.035213

0.071220

0.210777

0.309200

−96

−224

−156

379

1220

1534

398

−1940

−3448

−1729

3100

6984

4748

−4114

−12418

−10226

4560

20272

19352

−3652

−31080

−33718

222

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NORMALIZED FREQUENCY (× Π RAD/s)

Figure 86. TB1 Filter Response

9, 68

10, 67

11, 66

12, 65

13, 64

14, 63

15, 62

16, 61

17, 60

18, 59

19, 58

20, 57

21, 56

22, 55

23, 54

24, 53

25, 52

26, 51

27, 50

28, 49

29, 48

30, 47

31, 46

32, 45

33, 44

34, 43

35, 42

36, 41

37, 40

38, 39

45608

55840

7620

−65344

−90556

−23502

94167

150046

56796

−145352

−279128

−147694

298720

884064

1296880

Rev. 0 | Page 57 of 138

AD6688

Data Sheet

20

0

FB2 Filter Description

The FB2 decimate by 5, low-pass, FIR filter uses a 48-tap,

symmetrical, fixed coefficient filter implementation. Table 25

shows the FB2 filter coefficients and Figure 87 shows the FB2

filter response.

–20

–40

–60

–80

–100

–120

–140

–160

Table 25. FB2 Filter Coefficients

FB2 Coefficient

Number

Decimal

Coefficient

Quantized

Coefficient (21-Bit)

1, 48

2, 47

3, 46

4, 45

5, 44

6, 43

7, 42

8, 41

0.000007

−0.000004

−0.000069

−0.000244

−0.000544

−0.000870

−0.000962

−0.000448

0.000977

0.003237

0.005614

0.006714

0.004871

−0.001011

−0.010456

−0.020729

−0.026978

−0.023453

−0.005608

0.027681

0.072720

0.121223

0.162346

0.185959

7

−4

−72

−256

−570

−912

−1009

−470

1024

3394

5887

7040

5108

−1060

−10964

−21736

−28288

−24592

−5880

29026

76252

127112

170232

194992

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

NORMALIZED FREQUENCY (× Π RAD/s)

Figure 87. FB2 Filter Response

9, 40

10, 39

11, 38

12, 37

13, 36

14, 35

15, 34

16, 33

17, 32

18, 31

19, 30

20, 29

21, 28

22, 27

23, 26

24, 25

Rev. 0 | Page 58 of 138

Data Sheet

AD6688

DDC GAIN STAGE

DDC COMPLEX TO REAL CONVERSION

Each DDC contains an independently controlled gain stage.

The gain is selectable as either 0 dB or 6 dB. When mixing a real

input signal down to baseband, it is recommended that the user

enable the 6 dB of gain to recenter the dynamic range of the

signal within the full scale of the output bits.

Each DDC contains an independently controlled complex to

real conversion block. The complex to real conversion block

reuses the last filter (HB1 FIR) in the filtering stage along with

an f_S/4 complex mixer to upconvert the signal. After

upconverting the signal, the Q portion of the complex mixer is

no longer needed and is dropped. The TB1 filter does not

support complex to real conversion.

When mixing a complex input signal down to baseband, the

mixer has already recentered the dynamic range of the signal

within the full scale of the output bits, and no additional gain is

necessary. However, the optional 6 dB gain compensates for low

signal strengths. The downsample by 2 portion of the HB1 FIR

filter is bypassed when using the complex to real conversion

stage. The TB1 filter does not have the 6 dB gain stage.

Figure 88 shows a simplified block diagram of the complex to

real conversion.

HB1 FIR

GAIN STAGE

COMPLEX TO

REAL ENABLE

LOW-PASS

FILTER

I

0dB

OR

I

2

0

1

I/REAL

6dB

COMPLEX TO REAL CONVERSION

0dB

OR

6dB

cos(wt)

+

REAL

90°

f_S/4

0°

–

sin(wt)

0dB

OR

6dB

Q

LOW-PASS

FILTER

Q

0dB

OR

6dB

Q

2

HB1 FIR

Figure 88. Complex to Real Conversion Block

Rev. 0 | Page 59 of 138

AD6688

Data Sheet

Table 26 shows the DDC sample mapping when the chip

decimation ratio is different than the DDC decimation ratio.

DDC MIXED DECIMATION SETTINGS

The AD6688 also supports DDCs with different decimation

rates. In this scenario, the chip decimation ratio must be set to

the lowest decimation ratio of all the DDC channels. Samples of

higher decimation ratio DDCs are repeated to match the chip

decimation ratio sample rate. Only mixed decimation ratios that

are integer multiples of 2 are supported. For example, decimate

by 1, 2, 4, 8, or 16 can be mixed together, decimate by 3, 6, 12,

24, or 48 can be mixed together, or decimate by 5, 10, 20, or 40

can be mixed together.

For example, if the chip decimation ratio is set to decimate by 4,

DDC0 is set to use the HB2 + HB1 filters (complex outputs,

decimate by 4) and DDC1 is set to use the HB4 + HB3 + HB2 +

HB1 filters (real outputs, decimate by 8), then DDC1 repeats its

output data 2 times for every one DDC0 output. The resulting

output samples are shown in Table 27.

Table 26. Sample Mapping when Chip Decimation Ratio (DCM) Does Not Match DDC DCM

Sample Index

DDC DCM = Chip DCM

DDC DCM = 2 × Chip DCM

DDC DCM = 4 × Chip DCM

DDC DCM = 8 × Chip DCM

0

N

1

N + 1

N

2

N + 2

N + 1

N

3

N + 3

N + 1

N

4

5

6

7

8

9

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N

N + 1

N + 2

N + 3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 16

N + 17

N + 18

N + 19

N + 20

N + 21

N + 22

N + 23

N + 24

N + 25

N + 26

N + 27

N + 28

N + 29

N + 30

N + 31

Rev. 0 | Page 60 of 138

Data Sheet

AD6688

Table 27. Chip DCM = 4, DDC0 DCM = 4 (Complex), and DDC1 DCM = 8 (Real)¹

DDC0

DDC1

Output Port Q

DDC Input Samples

N

Output Port I

I0[N]

Output Port Q

Q0[N]

Q0[N + 1]

Q0[N + 2]

Q0[N + 3]

Output Port I

I1[N]

I1[N + 1]

Not applicable

N + 1

I0[N]

N + 2

I0[N]

N + 3

I0[N]

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

I0[N + 1]

I0[N + 2]

I0[N + 3]

¹DCM means decimation.

Rev. 0 | Page 61 of 138

AD6688

Data Sheet

DDC EXAMPLE CONFIGURATIONS

Table 28 describes the register settings for multiple DDC example configurations. Bandwidths listed are with <−0.005 dB of pass-band

ripple and >100 dB of stop band alias rejection.

Table 28. DDC Example Configurations (per ADC Channel Pair)

Chip

DDC

No. of Virtual

Application Decimation Input

Output

Type

Bandwidth Converters

Layer

Ratio

Type

Per DDC¹

Required

Register Settings

One DDC

2

Complex Complex 40% × f_S

2

0x0200 = 0x01 (one DDC; I/Q selected)

0x0201 = 0x01 (chip decimate by 2)

0x0310 = 0x83 (complex mixer; 0 dB gain; variable IF;

complex outputs; HB1 filter)

0x0311 = 0x04 (DDC I Input = ADC Channel A; DDC Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

Two DDCs

4

Complex Complex 20% × f_S

4

2

0x0200 = 0x02 (two DDCs; I/Q selected)

0x0201 = 0x02 (chip decimate by 4)

0x0310, 0x0330 = 0x80 (complex mixer; 0 dB gain;

variable IF; complex outputs; HB2+HB1 filters)

0x0311,0x0331 = 0x04 (DDC I input = ADC Channel A;

DDC Q input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

Complex Real

10% × f_S

0x0200 = 0x22 (two DDCs; I only selected)

0x0201 = 0x02 (chip decimate by 4)

0x0310, 0x0330 = 0x89 (complex mixer; 0 dB gain;

variable IF; real output; HB3 + HB2 + HB1 filters)

0x0311,0x0331 = 0x04 (DDC I Input = ADC Channel A;

DDC Q input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

Real

10% × f_S

0x0200 = 0x22 (two DDCs; I only selected)

0x0201 = 0x02 (chip decimate by 4)

0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain; variable IF;

real output; HB3 + HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q

input = ADC Channel A)

0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

Rev. 0 | Page 62 of 138

Data Sheet

AD6688

Chip

Application Decimation Input

Chip

DDC

Output

Type

No. of Virtual

Bandwidth Converters

Layer

Ratio

Type

Per DDC¹

Required

Register Settings

Two DDCs

4

Real

Complex 20% × f_S

4

0x0200 = 0x02 (two DDCs; I/Q selected)

0x0201 = 0x02 (chip decimate by 4)

0x0310, 0x0330 = 0x40 (real mixer; 6 dB gain; variable IF;

complex output; HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q

input = ADC Channel A)

0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

Two DDCs

8

Real

5% × f_S

2

0x0200 = 0x22 (two DDCs; I only selected)

0x0201 = 0x03 (chip decimate by 8)

0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain; variable

IF; real output; HB4 + HB3 + HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q

input = ADC Channel A)

0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

Four DDCs

8

Real

Complex 10% × f_S

8

0x0200 = 0x03 (four DDCs; I/Q selected)

0x0201 = 0x03 (chip decimate by 8)

0x0310, 0x0330, 0x0350, 0x0370 = 0x41 (real mixer; 6 dB

gain; variable IF; complex output; HB3 + HB2 + HB1

filters)

0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q

input = ADC Channel A)

0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q

input = ADC Channel A)

0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q

input = ADC Channel B)

0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,

0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW

and POW set as required by application for DDC2

0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,

0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW

and POW set as required by application for DDC3

Rev. 0 | Page 63 of 138

AD6688

Data Sheet

Chip

DDC

No. of Virtual

Application Decimation Input

Output

Type

Bandwidth Converters

Layer

Ratio

Type

Per DDC¹

Required

Register Settings

Four DDCs

8

Real

5% × f_S

4

0x0200 = 0x23 (four DDCs; I only selected)

0x0201 = 0x03 (chip decimate by 8)

0x0310, 0x0330, 0x0350, 0x0370 = 0x4A (real mixer;

6 dB gain; variable IF; real output; HB4 + HB3 + HB2 +

HB1 filters)

0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q

input = ADC Channel A)

0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q

input = ADC Channel A)

0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q

input = ADC Channel B)

0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,

0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW

and POW set as required by application for DDC2

0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,

0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW

and POW set as required by application for DDC3

Four DDCs

16

Real

Complex 5% × f_S

8

0x0200 = 0x03 (four DDCs; I/Q selected)

0x0201 = 0x04 (chip decimate by 16)

0x0310, 0x0330, 0x0350, 0x0370 = 0x42 (real mixer; 6 dB

gain; variable IF; complex output; HB4 + HB3 + HB2 +

HB1 filters)

0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q

input = ADC Channel A)

0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q

input = ADC Channel A)

0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q

input = ADC Channel B)

0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,

0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW

and POW set as required by application for DDC2

0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,

0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW

and POW set as required by application for DDC3

¹f_Sis the ADC sample rate.

Rev. 0 | Page 64 of 138

Data Sheet

AD6688

DDC POWER CONSUMPTION

Table 28 describes the typical and maximum DVDD and DRVDD1 power for certain DDC modes. f_S= 3 GHz in all cases.

Table 29. DDC Power Consumption for Example Configurations

DVDD Power (mW)

DRVDD1 Power (mW)

Number of DDC Decimation

DDCs

Number of Number of Virtual

Number of Octets

per frame (F)

Ratio¹

Lanes (L)

Converters (M)

Typ

615

675

585

590

570

585

745

755

715

Max

1190

1250

1150

1145

1120

1135

1350

1365

1320

Typ

415

310

250

175

145

105

415

305

250

Max

565

435

370

275

245

205

570

440

370

2

4

2

3

4

6

8

12

4

6

8

4

2

8

4

8

1

2

4

2

¹See Table 17 and Table 18 for details on decimation filter selection and associated alias protected bandwidths and SNR improvements.

Rev. 0 | Page 65 of 138

AD6688

Data Sheet

SIGNAL MONITOR

The signal monitor block provides additional information about

the signal being digitized by the ADC. The signal monitor

computes the peak magnitude of the digitized signal. This

information can be used to drive an AGC loop to optimize the

range of the ADC in the presence of real-world signals.

converter output samples. The peak magnitude can be derived

by using the following equation:

Peak Magnitude (dBFS) = 20log(Peak Detector Value/2¹³)

The magnitude of the input port signal is monitored over a

programmable time period, which is determined by the signal

monitor period register (SMPR). The peak detector function is

enabled by setting Bit 1 of Register 0x0270 in the signal monitor

control register. The 24-bit SMPR must be programmed before

activating this mode.

The results of the signal monitor block can be obtained either

by reading back the internal values from the SPI port or by

embedding the signal monitoring information into the

JESD204B interface as special control bits. A global, 24-bit

programmable period controls the duration of the

measurement. Figure 89 shows the simplified block diagram

of the signal monitor block.

After enabling peak detection mode, the value in the SMPR is

loaded into a monitor period timer, which decrements at the

decimated clock rate. The magnitude of the input signal is

compared with the value in the internal magnitude storage

register (not accessible to the user), and the greater of the two

is updated as the current peak level. The initial value of the

magnitude storage register is set to the current ADC input signal

magnitude. This comparison continues until the monitor period

timer reaches a count of 1.

SIGNAL MONITOR

FROM

MEMORY

MAP

DOWN

COUNTER

IS

PERIOD REGISTER

(SMPR)

COUNT = 1?

0x0271, 0x0272, 0x0273

LOAD

CLEAR

LOAD

MAGNITUDE

STORAGE

REGISTER

SIGNAL

MONITOR

HOLDING

REGISTER

TO SPORT OVER

JESD204B AND

MEMORY MAP

FROM

INPUT

LOAD

When the monitor period timer reaches a count of 1, the 13-bit

peak level value is transferred to the signal monitor holding

register, which can be read through the memory map or output

through the SPORT over the JESD204B interface. The monitor

period timer is reloaded with the value in the SMPR, and the

countdown restarts. In addition, the magnitude of the first

input sample is updated in the magnitude storage register, and

the comparison and update procedure, as explained previously,

continues.

COMPARE

A > B

Figure 89. Signal Monitor Block

The peak detector captures the largest signal within the

observation period. The detector only observes the magnitude

of the signal. The resolution of the peak detector is a 13-bit

value, and the observation period is 24 bits and represents

Rev. 0 | Page 66 of 138

Data Sheet

AD6688

significant control bit is used (see Example Configuration 1 and

SPORT OVER JESD204B

Example Configuration 2 in Figure 90). To select the SPORT

over JESD204B option, program Register 0x0559, Register 0x055A,

and Register 0x058F. See Table 46 for more information on setting

these bits.

The signal monitor data can also be serialized and sent over the

JESD204B interface as control bits. These control bits must be

deserialized from the samples to reconstruct the statistical data.

The signal control monitor function is enabled by setting Bits[1:0]

of Register 0x0279 and Bit 1 of Register 0x027A. Figure 90

shows two different example configurations for the signal

monitor control bit locations inside the JESD204B samples.

A maximum of three control bits can be inserted into the

JESD204B samples; however, only one control bit is required for

the signal monitor. Control bits are inserted from MSB to LSB. If

only one control bit is to be inserted (CS = 1), only the most

Figure 91 shows the 25-bit frame data that encapsulates the

peak detector value. The frame data is transmitted MSB first

with five 5-bit subframes. Each subframe contains a start bit

that can be used by a receiver to validate the deserialized data.

Figure 92 shows the SPORT over JESD204B signal monitor data

with a monitor period timer set to 80 samples.

16-BIT JESD204B SAMPLE SIZE (N' = 16)

1-BIT

CONTROL

BIT

15-BIT CONVERTER RESOLUTION (N = 15)

(CS = 1)

EXAMPLE

CONFIGURATION 1

(N' = 16, N = 15, CS = 1)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CTRL

[BIT 2]

X

S[14] S[13] S[12] S[11] S[10]

S[9]

X

S[8]

X

S[7]

X

S[6]

X

S[5]

X

S[4]

X

S[3]

X

S[2]

X

S[1]

X

S[0]

X

SERIALIZED SIGNAL MONITOR

FRAME DATA

16-BIT JESD204B SAMPLE SIZE (N' = 16)

14-BIT CONVERTER RESOLUTION (N = 14)

1

CONTROL

BIT

(CS = 1)

1 TAIL

BIT

EXAMPLE

CONFIGURATION 2

(N' = 16, N = 14, CS = 1)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CTRL

[BIT 2]

X

S[13] S[12] S[11] S[10]

S[9]

X

S[8]

X

S[7]

X

S[6]

X

S[5]

X

S[4]

X

S[3]

X

S[2]

X

S[1]

X

S[0]

X

TAIL

X

SERIALIZED SIGNAL MONITOR

FRAME DATA

Figure 90. Signal Monitor Control Bit Locations

5-BIT SUBFRAMES

5-BIT IDLE

SUBFRAME

(OPTIONAL)

IDLE IDLE IDLE IDLE IDLE

1

5-BIT IDENTIFIER START ID[3]

ID[2]

0

ID[1]

0

ID[0]

1

0

SUBFRAME

5-BIT DATA

MSB

START

0

P[12]

P[11]

P[7]

P[10]

P[6]

P[9]

P[5]

SUBFRAME

25-BIT

FRAME

5-BIT DATA

SUBFRAME

START

0

P[8]

P[4]

P[0]

5-BIT DATA

SUBFRAME

START

0

P[3]

0

P[2]

0

P[1]

0

5-BIT DATA

LSB

SUBFRAME

START

0

P[] = PEAK MAGNITUDE VALUE

Figure 91. SPORT over JESD204B Signal Monitor Frame Data

Rev. 0 | Page 67 of 138

AD6688

Data Sheet

SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00)

80 SAMPLE PERIOD

PAYLOAD 3

25-BIT FRAME (N)

DATA

MSB

DATA

LSB

IDENT.

DATA DATA

IDLE

80 SAMPLE PERIOD

PAYLOAD 3

25-BIT FRAME (N + 1)

DATA

LSB

DATA DATA

MSB

IDLE

80 SAMPLE PERIOD

PAYLOAD 3

25-BIT FRAME (N + 2)

DATA

LSB

DATA DATA

MSB

IDLE

Figure 92. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples

Rev. 0 | Page 68 of 138

Data Sheet

AD6688

DIGITAL OUTPUTS

•

K is the number of frames per multiframe;

AD6688 value = 4, 8, 12, 16, 20, 24, 28, or 32.

S is the samples transmitted per single converter per frame

cycle; AD6688 value is set automatically based on L, M, F,

and N΄.

HD is the high density mode; the AD6688 is set

automatically based on L, M, F, and N΄.

CF is the number of control words per frame clock cycle

per converter device; AD6688 value = 0.

INTRODUCTION TO THE JESD204B INTERFACE

The AD6688 digital outputs are designed to the JEDEC standard

JESD204B, serial interface for data converters. JESD204B is a

protocol to link the AD6688 to a digital processing device over

a serial interface with lane rates of up to 16 Gbps. The benefits

of the JESD204B interface over LVDS include a reduction in

required board area for data interface routing, and an ability to

enable smaller packages for converter and logic devices.

•

JESD204B OVERVIEW

Figure 93 shows a simplified block diagram of the AD6688

JESD204B link. By default, the AD6688 is configured to use

two converters and four lanes. Converter A data is output to

SERDOUT0 and/or SERDOUT1 , and Converter B is output

to SERDOUT2 and/or SERDOUT3 . The AD6688 allows

other configurations such as combining the outputs of both

converters onto a single lane, or changing the mapping of the

A and B digital output paths. These modes are set up via a quick

configuration register in the SPI register map, along with

additional customizable options.

The JESD204B data transmit block assembles the parallel data

from the ADC into frames and uses 8-bit/10-bit encoding as

well as optional scrambling to form serial output data. Lane

synchronization is supported through the use of special control

characters during the initial establishment of the link. Additional

control characters are embedded in the data stream to maintain

synchronization thereafter. A JESD204B receiver is required to

complete the serial link. For additional details on the JESD204B

interface, refer to the JESD204B standard.

The AD6688 JESD204B data transmit block maps up to two

physical ADCs or up to eight virtual converters (when DDCs are

enabled) over a link. A link can be configured to use one, two,

four, or eight JESD204B lanes. The JESD204B specification refers

to a number of parameters to define the link, and these parameters

must match between the JESD204B transmitter (the AD6688

output) and the JESD204B receiver (the logic device input).

By default in the AD6688, the 14-bit converter word from each

converter is broken into two octets (eight bits of data). Bit 13

(MSB) through Bit 6 are in the first octet. The second octet

contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits

can be configured as zeros or as a pseudorandom number

sequence. The tail bits can also be replaced with control bits

indicating overrange, SYSREF , or fast detect output.

The JESD204B link is described according to the following

parameters:

The two resulting octets can be scrambled. Scrambling is

optional; however, it is recommended to avoid spectral peaks

when transmitting similar digital data patterns. The scrambler

uses a self synchronizing, polynomial-based algorithm defined

•

L is the number of lanes per converter device (lanes per

link); AD6688 value = 1, 2, 4, or 8.

¹⁴+ x¹⁵. The descrambler in the receiver is

•

M is the number of converters per converter device (virtual

converters per link); AD6688 value = 1, 2, 4, or 8.

F is the octets per frame; AD6688 value = 1, 2, 4, 8, or 16.

N΄ is the number of bits per sample (JESD204B word size);

AD6688 value = 8 or 16.

by the equation 1 + x

a self synchronizing version of the scrambler polynomial.

•

The two octets are then encoded with an 8-bit/10-bit encoder. The

8-bit/10-bit encoder works by taking eight bits of data (an octet)

and encoding them into a 10-bit symbol. Figure 94 shows how

the 14-bit data is taken from the ADC, how the tail bits are added,

how the two octets are scrambled, and how the octets are encoded

into two 10-bit symbols. Figure 94 shows the default data format.

•

N is the converter resolution; AD6688 value = 7 to 16.

CS is the number of control bits per sample;

AD6688 value = 0, 1, 2, or 3.

CONVERTER 0

CONVERTER A

ADC

A

INPUT

SERDOUT0±

SERDOUT1±

MUX/

JESD204B LINK

LANE MUX

AND MAPPING

(SPI

REG 0x05B0,

REG 0x05B2,

REG 0x05B3,

REG 0x05B5,

REG 0x05B6)

FORMAT

(SPI

CONTROL

SERDOUT2±

SERDOUT3±

SERDOUT4±

SERDOUT5±

SERDOUT6±

SERDOUT7±

(L, M, F)

SPI REG 0x058B,

0x058E, 0x058C

REG 0x0561,

REG 0x0564)

CONVERTER B

INPUT

ADC

B

CONVERTER 1

SYSREF±

SYNCINB±

Figure 93. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00)

Rev. 0 | Page 69 of 138

AD6688

Data Sheet

JESD204B

INTERFACE

TEST PATTERN

(REG 0x0573,

REG 0x0551 TO

REG 0x0558)

JESD204B DATA

LINK LAYER TEST

PATTERNS

JESD204B

LONG TRANSPORT

TEST PATTERN

REG 0x0571[5]

REG 0x0574[2:0]

SERDOUT0±

SERDOUT1±

SERDOUT2±

SERDOUT3±

SERIALIZER

ADC TEST PATTERNS

SCRAMBLER

1 + x + x

(OPTIONAL)

(REG 0x0550,

REG 0x0551 TO

REG 0x0558)

FRAME

CONSTRUCTION

8-BIT/10-BIT

ENCODER

14

15

a

b

i

j

a

b

i j

JESD204B SAMPLE

CONSTRUCTION

MSB A13

SYMBOL 0

SYMBOL 1

a

b

c

d

e

f

g

h

i

j

A12

A11

A10

A9

MSB S7 S7

MSB A13 A5

A12 A4

A11 A3

A10 A2

A9 A1

ADC

S6 S6

S5 S5

A8

TAIL BITS

0x0571[6]

A7

S4 S4

A6

S3 S3

A5

S2 S2

A8 A0

A4

S1 S1

A7 C2

A3

LSB S0 S0

LSB

A6

T

A2

A1

LSB A0

C2

C1

C0

CONTROL BITS

Figure 94. ADC Output Datapath Showing Data Framing

TRANSPORT

LAYER

DATA LINK

LAYER

PHYSICAL

LAYER

PROCESSED

ALIGNMENT

CHARACTER

GENERATION

SAMPLE

CONSTRUCTION

FRAME

CONSTRUCTION

8-BIT/10-BIT

ENCODER

CROSSBAR

MUX

SAMPLES

SCRAMBLER

SERIALIZER

Tx

OUTPUT

FROM ADC

SYSREF±

SYNCINB±

Figure 95. Data Flow

Physical Layer

FUNCTIONAL OVERVIEW

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. In this layer, parallel data is converted into

one, two, four, or eight lanes of high speed differential serial data.

The block diagram in Figure 95 shows the flow of data through

the JESD204B hardware from the sample input to the physical

output. The processing can be divided into layers that are

derived from the open source initiative (OSI) model widely

used to describe the abstraction layers of communications

systems. These layers are the transport layer, data link layer,

and physical layer (serializer and output driver).

JESD204B LINK ESTABLISHMENT

The AD6688 JESD204B transmitter (Tx) interface operates in

Subclass 1 as defined in the JEDEC Standard JESD204B (July

2011 specification). The link establishment process is divided

into the following steps: code group synchronization and

SYNCINB , initial lane alignment sequence, and user data and

error correction.

Transport Layer

The transport layer handles packing the data (consisting of

samples and optional control bits) into JESD204B frames that

are mapped to 8-bit octets. These octets are sent to the data link

layer. The transport layer mapping is controlled by rules derived

from the link parameters. Tail bits are added to fill gaps where

required. The following equation can be used to determine the

number of tail bits within a sample (JESD204B word):

Code Group Synchronization (CGS) and SYNCINB

The CGS is the process by which the JESD204B receiver finds

the boundaries between the 10-bit symbols in the stream of

data. During the CGS phase, the JESD204B transmit block

transmits /K28.5/ characters. The receiver must locate /K28.5/

characters in its input data stream using clock and data recovery

(CDR) techniques.

T = N΄ – N – CS

Data Link Layer

The data link layer is responsible for the low level functions

of passing data across the link. These functions include

optionally scrambling the data, inserting control characters for

multichip synchronization, lane alignment, monitoring and

encoding 8-bit octets into 10-bit symbols. The data link layer is

also responsible for sending the initial lane alignment sequence

(ILAS), which contains the link configuration data used by the

receiver to verify the settings in the transport layer.

The receiver issues a synchronization request by asserting the

SYNCINB pin of the AD6688 low. The JESD204B Tx then begins

sending /K/ characters. After the receiver synchronizes, it waits for

the correct reception of at least four consecutive /K/ symbols. It

then deasserts SYNCINB . The AD6688 then transmits an ILAS

on the following local multiframe clock (LMFC) boundary.

For more information on the code group synchronization

phase, refer to the JEDEC Standard JESD204B, July 2011,

Section 5.3.3.1.

Rev. 0 | Page 70 of 138

Data Sheet

AD6688

The SYNCINB pin operation can also be controlled by the

SPI. The SYNCINB siꢀnal is a differential, dc-coupled LVDS

mode siꢀnal by default, but it can also be driven sinꢀle-ended.

For more information on confiꢀurinꢀ the SYNCINB pin

operation, refer to Reꢀister 0x0572.

User Data and Error Detection

After the initial lane aliꢀnment sequence is complete, the user

data is sent. Normally, within a frame, all characters are considered

user data. However, to monitor the frame clock and multiframe

clock synchronization, there is a mechanism for replacinꢀ

characters with /F/ or /A/ aliꢀnment characters when the data

meets certain conditions. These conditions are different for

unscrambled and scrambled data. The scramblinꢀ operation is

enabled by default; however, it can be disabled usinꢀ the SPI.

The SYNCINB pins can also be confiꢀured to run in CMOS

(sinꢀle-ended) mode by settinꢀ Bit[4] in Reꢀister 0x0572. When

runninꢀ SYNCINB in CMOS mode, connect the CMOS

SYNCINB siꢀnal to Pin 21 (SYNCINB+) and leave Pin 20

(SYNCINB−) ﬂoatinꢀ.

For scrambled data, any 0xFC character at the end of a frame

is replaced by an /F/, and any 0x7C character at the end of a

multiframe is replaced by an /A/. The JESD204B receiver (Rx)

checks for /F/ and /A/ characters in the received data stream

and verifies that they only occur in the expected locations. If an

unexpected /F/ or /A/ character is found, the receiver handles

the situation by usinꢀ dynamic realiꢀnment or assertinꢀ the

SYNCINB siꢀnal for more than four frames to initiate a

resynchronization. For unscrambled data, if the final character

of two subsequent frames is equal, the second character is

replaced with an /F/ if it is at the end of a frame, and an /A/ if

it is at the end of a multiframe.

Initial Lane Alignment Sequence (ILAS)

The ILAS phase follows the CGS phase and beꢀins on the next

LMFC boundary. The ILAS consists of four multiframes, with

an /R/ character markinꢀ the beꢀinninꢀ and an /A/ character

markinꢀ the end. The ILAS beꢀins by sendinꢀ an /R/ character

followed by 0 to 255 ramp data for one multiframe. On the

second multiframe, the link confiꢀuration data is sent, startinꢀ

with the third character. The second character is a /Q/ character

to confirm that the link confiꢀuration data is to follow. All

undefined data slots are filled with ramp data. The ILAS

sequence is never scrambled.

Insertion of aliꢀnment characters can be modified usinꢀ the SPI.

The frame aliꢀnment character insertion (FACI) is enabled by

default. More information on the link controls is available in the

Memory Map section, Reꢀister 0x0571.

The ILAS sequence construction is shown in Fiꢀure 96. The

four multiframes include the followinꢀ:



Multiframe 1: beꢀins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

8-Bit/10-Bit Encoder



Multiframe 2: beꢀins with an /R/ character followed by a

/Q/ character (/K28.4/), followed by link confiꢀuration

parameters over 14 confiꢀuration octets (see Table 30) and

ends with an /A/ character. Many of the parameter values

are of the value – 1 notation.

The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols

and inserts control characters into the stream when needed.

The control characters used in JESD204B are shown in Table 30.

The 8-bit/10-bit encodinꢀ ensures that the siꢀnal is dc balanced by

usinꢀ the same number of ones and zeros across multiple symbols.



Multiframe 3: beꢀins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

Multiframe 4: beꢀins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

The 8-bit/10-bit interface has options that can be controlled

via the SPI. These operations include bypass and invert. These

options are troubleshootinꢀ tools for the verification of the diꢀital

front end (DFE). See the Memory Map section, Reꢀister 0x0572,

Bits[2:1] for information on confiꢀurinꢀ the 8-bit/10-bit encoder.

K

R

D

A

R

Q

C

D

A

R

D

A

R

D

D A D

END OF

MULTIFRAME

START OF

ILAS

START OF LINK

CONFIGURATION DATA

START OF

USER DATA

Figure 96. Initial Lane Alignment Sequence

Table 30. AD6688 Control Characters Used in JESD204B

Abbreviation

Control Symbol

/K28.0/

/K28.3/

/K28.4/

/K28.5/

/K28.7/

8-Bit Value

000 11100

011 11100

100 11100

101 11100

111 11100

10-Bit Value, RD¹= −1

001111 0100

10-Bit Value, RD¹= +1

110000 1011

110000 1100

110000 1101

110000 0101

Description

Start of multiframe

Lane alignment

Start of link configuration data

Group synchronization

Frame alignment

/R/

/A/

/Q/

/K/

/F/

001111 0011

001111 0100

001111 1010

001111 1000

110000 0111

¹RD means running disparity.

Rev. 0 | Page 71 of 138

AD6688

Data Sheet

PHYSICAL LAYER (DRIVER) OUTPUTS

Digital Outputs, Timing, and Controls

The AD6688 physical layer consists of drivers that are defined

in the JEDEC Standard JESD204B, July 2011. The differential

digital outputs are powered up by default. The drivers use a

dynamic 100 Ω internal termination to reduce unwanted

reflections.

Figure 99. Digital Outputs Jitter Histogram, External 100 Ω Terminations at

16 Gbps

Place a 100 ꢀ differential termination resistor at each receiver

input to result in a nominal 0.85 × DRVDD1 V p-p swing at the

receiver (see Figure 97). The swing is adjustable through the SPI

registers. AC coupling is recommended to connect to the

receiver. See the Memory Map section (Register 0x05C0 to

Register 0x05C3 in Table 46) for more details.

DRVDD

100Ω

DIFFERENTIAL

TRACE PAIR

Figure 100. Digital Outputs Bathtub Curve, External 100 Ω Terminations at

16 Gbps

0.1µF

SERDOUTx+

De-Emphasis

RECEIVER

100Ω

De-emphasis enables the receiver eye diagram mask to be met

in conditions where the interconnect insertion loss does not

meet the JESD204B specification. Use the de-emphasis feature

only when the receiver is unable to recover the clock due to

excessive insertion loss. Under normal conditions, it is disabled

to conserve power. Additionally, enabling and setting too high a

de-emphasis value on a short link can cause the receiver eye

diagram to fail. Use the de-emphasis setting with caution

because it can increase electromagnetic interference (EMI). See

the Memory Map section (Register 0x05C4 to Register 0x05CB

in Table 46) for more details.

SERDOUTx–

OUTPUT SWING = 300mV p-p

V

= DRVDD/2

CM

Figure 97. AC-Coupled Digital Output Termination Example

The AD6688 digital outputs can interface with custom application

specific ICs (ASICs) and field-programmable gate array (FPGA)

receivers, providing superior switching performance in noisy

environments. Single point-to-point network topologies are

recommended with a single differential 100 Ω termination

resistor placed as close to the receiver inputs as possible.

Phase-Locked Loop

The phase-locked loop (PLL) generates the serializer clock,

which operates at the JESD204B lane rate. The status of the PLL

lock can be checked in the PLL locked status bit (Register 0x056F,

Bit 7). This read only bit notifies the user if the PLL achieved a

lock for the specific setup. Register 0x056F also has a loss of

lock (LOL) sticky bit (Bit 3) that notifies the user that there was

a loss of lock detected. The sticky bit can be reset by issuing a

JESD204B link restart (Register 0x0571 = 0x15, followed by

Register 0x0571 = 0x14). See Table 32 for the re-initialization of

the link following a link power cycle.

If there is no far end receiver termination, or if there is poor

differential trace routing, timing errors can result. To avoid such

timing errors, it is recommended that the trace length be less

than six inches, and that the differential output traces be close

together and at equal lengths.

Figure 98 to Figure 100 show an example of the digital output

data eye, jitter histogram, and bathtub curve for one AD6688

lane running at 16 Gbps. The format of the output data is twos

complement by default. To change the output data format, see

the Memory Map section (Register 0x0561 in Table 46).

The JESD204B lane rate control, Bits[7:4] of Register 0x056E,

must be set to correspond with the lane rate. Table 31 shows the

lane rates supported by the AD6688 using Register 0x056E.

Table 31. AD6688 Register 0x056E Supported Lane Rates

Value Lane Rate

0x00

0x10

0x30

0x50

Lane rate = 6.75 Gbps to 13.5 Gbps.

Lane rate = 3.375 Gbps to 6.75 Gbps.

Lane rate = 13.5 Gbps to 15.5 Gbps (default for AD6688).

Lane rate = 1.6875 Gbps to 3.375 Gbps.

Figure 98. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps

Rev. 0 | Page 72 of 138

Data Sheet

AD6688

The following SPI writes are necessary to place the device in

f_S× 4 mode:

f_S× 4 MODE

The f_S× 4 mode adds a special packing mode on top of a JESD204B

transmitter/receiver to fix the serial lane rate at four times the

sample rate (f_S).

•

Register 0x0570 = 0xFE. This setting places the device in

M = 2, L = 8, f_S× 4 mode.

Register 0x058B = 0x0F. This setting places the device in

CS = 0, N' = 16.

Register 0x058F = 0x2F. This setting places the device in

Subclass 1 mode, N = 16.

The JESD204B link settings are L = 8; M = 2; F = 2; S = 5; N' = 12;

N = 12; CS = 0; CF = 2; and HD = 1.

However, CF = 2 is not supported by the design; therefore, the

following link parameters are used along with special packing:

L = 8; M = 2; F = 2; S = 4; N' = 16; N = 16; CS = 0; CF = 0; and

HD = 0.

The transmit architecture of the f_S× 4 mode is shown in Figure 101,

and the receive portion is shown in Figure 102. The f_S× 4 mode

only works in full bandwidth mode (Register 0x0200 = 0x00).

In f_S× 4 mode, five 12-bit ADC samples (along with an extra 4 bits)

are packed into four 16-bit JESD204B samples to create a 64-bit

frame.

f_S× 4 MODE (TRANSMIT)

ADC1

ADC0

12-BITS

AT f_S

ADC1 SAMPLE N (12 BITS)

ADC0 SAMPLE N (12 BITS)

64-BITS

1/5 RATE EXCHANGE

0000

AT f /5

S

APPLICATION

LAYER

ADC0

ADC1

64-BITS

(4 BITS)

SAMPLE N (12 BITS)

SAMPLE N + 1 (12 BITS) SAMPLE N + 2 (12 BITS) SAMPLE N + 3 (12 BITS) SAMPLE N + 4 (12 BITS)

SAMPLE N (12 BITS)

SAMPLE N + 1 (12 BITS) SAMPLE N + 2 (12 BITS) SAMPLE N + 3 (12 BITS) SAMPLE N + 4 (12 BITS)

AT f /5

S

S[N][11:0], S[N + 1][11:8]

(16 BITS)

S[N + 1][7:0], S[N + 2][11:4]

(16 BITS)

S[N + 2][3:0], S[N + 3][11:0]

(16 BITS)

S[N + 4][11:0], 0000

(16 BITS)

S[N][11:0], S[N + 1][11:8]

(16 BITS)

S[N + 1][7:0], S[N + 2][11:4]

(16 BITS)

S[N + 2][3:0], S[N + 3][11:0]

(16 BITS)

S[N + 4][11:0], 0000

(16 BITS)

CONVERTER 0

SAMPLE N (16 BITS)

CONVERTER 0

SAMPLE N + 1 (16 BITS)

CONVERTER 0

SAMPLE N + 2 (16 BITS)

CONVERTER 0

SAMPLE N + 3 (16 BITS)

CONVERTER 1

SAMPLE N (16 BITS)

CONVERTER 1

SAMPLE N+1 (16 BITS)

CONVERTER 1

SAMPLE N+2 (16 BITS)

CONVERTER 1

SAMPLE N+3 (16 BITS)

S[N][15:0]

S[N + 1][15:0]

S[N + 2][15:0]

S[N + 3][15:0]

S[N][15:0]

S[N + 1][15:0]

S[N + 2][15:0]

S[N + 3][15:0]

TRANSPORT,

DATA LINK,

AND PHY

JESD204B FRAMER + PHY

(M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0)

LAYERS

LANE 0 LANE 1 LANE 2 LANE 3 LANE 4 LANE 5 LANE 6 LANE 7

Figure 101. f_S× 4 Mode (Transmit)

f_S× 4 MODE (RECEIVE)

LANE 0 LANE 1 LANE 2 LANE 3 LANE 4 LANE 5 LANE 6 LANE 7

DATA LINK,

TRANSPORT,

AND PHY

JESD204B FRAMER + PHY

(M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0)

LAYERS

S[N][15:0]

S[N + 1][15:0]

S[N + 2][15:0]

S[N + 3][15:0]

S[N][15:0]

S[N + 1][15:0]

S[N + 2][15:0]

S[N + 3][15:0]

64-BITS

CONVERTER 0

SAMPLE N (16 BITS)

CONVERTER 0

SAMPLE N + 1 (16 BITS)

CONVERTER 0

SAMPLE N + 2 (16 BITS)

CONVERTER 0

SAMPLE N + 3 (16 BITS)

CONVERTER 1

SAMPLE N (16 BITS)

CONVERTER 1

SAMPLE N + 1 (16 BITS)

CONVERTER 1

SAMPLE N + 2 (16 BITS)

CONVERTER 1

SAMPLE N + 3 (16 BITS)

AT f /5

S

S[N][11:0], S[N + 1][11:8]

(16 BITS)

S[N + 1][7:0], S[N + 2][11:4]

(16 BITS)

S[N + 2][3:0], S[N + 3][11:0]

(16 BITS)

S[N + 4][11:0], 0000

(16 BITS)

S[N][11:0], S[N + 1][11:8]

(16 BITS)

S[N + 1][7:0], S[N + 2][11:4]

(16 BITS)

S[N + 2][3:0], S[N + 3][11:0]

(16 BITS)

S[N+4][11:0], 0000

(16 BITS)

APPLICATION

LAYER

ADC0

SAMPLE N (12 BITS)

ADC0

ADC1

SAMPLE N (12 BITS)

ADC1

64-BITS

(4 BITS)

0000

(4 BITS)

0000

SAMPLE N + 1 (12 BITS) SAMPLE N + 2 (12 BITS) SAMPLE N + 3 (12 BITS) SAMPLE N + 4 (12 BITS)

AT f /5

S

CUSTOMER APPLICATION

Figure 102. f_S× 4 Mode (Receive)

Rev. 0 | Page 73 of 138

AD6688

Data Sheet

If the internal DDCs are used for on-chip digital processing, M

represents the number of virtual converters. The virtual

converter mapping setup is shown in Figure 64.

SETTING UP THE AD6688 DIGITAL INTERFACE

To ensure proper operation of the AD6688 at start-up, some SPI

writes are needed to initialize the link. Additionally, these

registers must be written every time the ADC is reset. Any one

of the following resets warrants the initialization routine for the

digital interface:

The maximum lane rate allowed by the AD6688 is 16 Gbps. The

lane rate is related to the JESD204B parameters using the

following equation:

•

Hard reset, as in power-up.

Power-up using the PDWN pin.

10

8

L











M × N'×

× f

OUT



Lane Rate =

Power-up using the SPI (Register 0x0002, Bits[1:0]).

SPI soft reset (Register 0x0000 = 0x81).

Datapath soft reset (Register 0x0001 = 0x02).

JESD204B link power cycle (Register 0x0571 = 0x15, then

0x14).

f_{ADC _CLOCK}

Decimation Ratio

where f_OUT

=

The decimation ratio (DCM) is the parameter programmed in

Register 0x0201.

The initialization SPI writes are as shown in Table 32.

Use the following steps to configure the output:

Table 32. AD6688 JESD204B Initialization

Register Value Comment

1. Power down the link.

2. Select the JESD204B link configuration options.

3. Configure the detailed options.

4. Set output lane mapping (optional).

5. Set additional driver configuration options (optional).

6. Power up the link.

0x1228

0x1222

0x1262

0x4F

0x0F

0x00

0x04

0x00

0x08

0x00

Reset JESD204B start-up circuit

JESD204B start-up circuit in normal operation

JESD204B PLL force normal operation

Reset JESD204B PLL calibration

JESD204B PLL normal operation

Clear loss of lock bit

7. Initialize the JESD204B link by issuing the commands in

Table 32.

Loss of lock bit normal operation

Table 33 and Table 34 show the JESD204B output configurations

supported for both N΄ = 16 and N΄ = 8 for a given number of

virtual converters. Take care to ensure that the serial lane rate

for a given configuration is within the supported range of

1.6875 Gbps to 16 Gbps.

The AD6688 has one JESD204B link. The serial outputs

(SERDOUT0 to SERDOUT7 ) are considered to be part of

one JESD204B link. The basic parameters that determine the

link setup are

See the Example: ADC with DDC Option (Two ADCs Plus Two

DDCs section for an example describing which JESD204B

transport layer settings are valid for a given chip mode.

•

Number of lanes per link (L)

Number of converters per link (M)

Number of octets per frame (F)

Table 33. JESD204B Output Configurations for N΄ = 16¹

No. of

Virtual

Converters

Supported

Decimation

JESD204B Rates for

Supported

Decimation

Rates for

Lane Rate =

3.4 Gbps to

6.8 Gbps

Supported

Decimation

Rates for

Lane Rate =

6.8 Gbps to

13.5 Gbps

Supported

Decimation

Rates for

Lane Rate =

13.5 Gbps to

Serial

Lane Rate =

1.7 Gbps to

3.4 Gbps

JESD204B Transport Layer Settings³

(Same Value Line

as M)

Rate²

15.5 Gbps

L

M

F

S

HD

N

N'

CS

K

1

20 × f_OUT

2, 4, 5, 6, 8, 10,

12, 20, 24

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12

1, 2, 3, 4

1

2

1

0

8 to

16

16 0 to

3

See

Note 4

1

20 × f_OUT

10 × f_OUT

5 × f_OUT

2, 4, 5, 6, 8, 10,

12, 20, 24

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12

1, 2, 3, 4

1

2

4

8

1

4

1

2

1

2

1

2

1

2

4

8

0

1

0

1

0

1

0

8 to

16

8 to

16

8 to

16

8 to

16

8 to

16

8 to

16

8 to

16

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

See

Note 4

See

Note 4

See

Note 4

See

Note 4

See

Note 4

See

Note 4

See

Note 4

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

1, 2, 3, 4

1, 2

1

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

5 × f_OUT

1, 2

1

2.5 × f_OUT

1

1, 2, 3, 4

1, 2

1

Rev. 0 | Page 74 of 138

Data Sheet

AD6688

No. of

Virtual

Converters

Supported

(Same Value Line

Supported

Decimation

JESD204B Rates for

Supported

Decimation

Rates for

Lane Rate =

3.4 Gbps to

6.8 Gbps

Supported

Decimation

Rates for

Lane Rate =

6.8 Gbps to

13.5 Gbps

Supported

Decimation

Rates for

Lane Rate =

13.5 Gbps to

15.5 Gbps

Serial

Lane Rate =

1.7 Gbps to

3.4 Gbps

JESD204B Transport Layer Settings³

as M)

Rate²

L

M

F

S

HD

N

N'

CS

K

2

40 × f_OUT

4, 8, 10, 12, 15,

16, 20, 24, 30,

40, 48

2, 4, 5, 6, 8, 10,

12, 15, 16, 20,

24, 30

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

1

2

4

1

0

8 to

16

16 0 to

3

See

Note 4

2

40 × f_OUT

20 × f_OUT

4, 8, 10, 12, 15,

16, 20, 24, 30,

40, 48

2, 4, 5, 6, 8, 10,

12, 15, 16, 20,

24, 30

2, 4, 5, 6, 8, 10,

12, 15, 16, 20,

24, 30

2, 4, 5, 6, 8, 10,

12, 15, 16, 20,

24, 30

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

1

2

8

2

4

2

1

2

0

8 to

16

16 0 to

3

See

Note 4

1, 2, 3, 4

8 to

16

16 0 to

3

See

Note 4

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

8 to

16

16 0 to

3

See

Note 4

2

4

10 × f_OUT

5 × f_OUT

1, 2, 3, 4, 5, 6, 8,

10, 12, 15, 16

1, 2, 3, 4, 5, 6, 8,

10, 12, 15, 16

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

1

4

8

1

2

4

1

2

1

2

8

1

2

4

1

0

1

0

8 to

16

8 to

16

8 to

16

8 to

16

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

See

Note 4

See

Note 4

See

Note 4

See

Note 4

1, 2, 3, 4, 5, 6, 8

5 × f_OUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

1

80 × f_OUT

8, 16, 20, 24, 30, 4, 8, 10, 12, 16,

40, 48

2, 4, 6, 8, 10,

12, 16, 20, 24,

30

2, 4, 6, 8, 10, 12,

16

8 to

16

16 0 to

3

See

Note 4

20, 24, 30, 40,

48

4

40 × f_OUT

20 × f_OUT

4, 8, 10, 12, 15,

16, 20, 24, 30,

40, 48

4, 8, 10, 12, 15,

16, 20, 24, 30,

40, 48

2, 4, 5, 6, 8, 10,

12, 15, 16, 20,

24, 30

2, 4, 5, 6, 8, 10,

12, 15, 16, 20,

24, 30

2, 4, 5, 6, 8, 10,

12, 15, 16, 20,

24, 30

2, 4, 5, 6, 8, 10,

12, 15, 16, 20,

24, 30

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

2

4

8

2

4

1

2

1

2

0

8 to

16

16 0 to

3

See

Note 4

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

8 to

16

16 0 to

3

See

Note 4

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

1, 2, 3, 4

8 to

16

16 0 to

3

See

Note 4

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

8 to

16

16 0 to

3

See

Note 4

4

8

10 × f_OUT

160 × f_OUT

80 × f_OUT

40 × f_OUT

20 × f_OUT

1, 2, 3, 4, 5, 6, 8,

10, 12, 15, 16

1, 2, 3, 4, 5, 6, 8,

10, 12, 15, 16

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

8

1

2

4

8

4

8

1

2

1

2

1

2

1

0

8 to

16

8 to

16

8 to

16

8 to

16

8 to

16

8 to

16

8 to

16

8 to

16

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

16 0 to

3

See

Note 4

See

Note 4

See

Note 4

See

Note 4

See

Note 4

See

Note 4

See

Note 4

See

Note 4

2

16, 40, 48

8, 16, 20, 24,

40, 48

4, 8, 12, 16, 20,

24, 40, 48

2, 4, 6, 8, 10,

12, 16, 20, 24

2, 4, 6, 8, 10,

12, 16

2, 4, 6, 8, 10,

12, 16

4, 8, 12, 16, 20,

24

2, 4, 6, 8, 10, 12,

16

2, 4, 6, 8

2, 4

16

8

8, 16, 20, 24, 40, 4, 8, 10, 12, 16,

48

4, 8, 10, 12, 16,

20, 24, 40, 48

4, 8, 10, 12, 16,

20, 24, 40, 48

2, 4, 6, 8, 10, 12,

16, 20, 24

2, 4, 6, 8, 10, 12,

16, 20, 24

20, 24, 40, 48

2, 4, 6, 8, 10,

12, 16, 20, 24

2, 4, 6, 8, 10,

12, 16, 20, 24

2, 4, 6, 8, 10,

12, 16

4

8

2, 4, 6, 8

2

2, 4, 6, 8, 10,

12, 16

2, 4, 6, 8

2, 4

4

¹Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.

²JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter

device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the

virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the

number of frames per multiframe.

³f_{ADC_CLK}is the ADC sample rate; DCM = chip decimation ratio; f_OUTis the output sample rate = f_{ADC_CLK}/DCM; SLR is the JESD204B serial lane rate. The following equations must be

met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ f_{ADC_CLK}; least common multiple (20 × DCM × f_OUT/SLR, DCM) ≤ 64. When the SLR

is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is

< 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50.

⁴Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4,

8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.

Rev. 0 | Page 75 of 138

AD6688

Data Sheet

Table 34. JESD204B Output Configurations (N' = 12) ¹

No. of

Virtual

Converters

Supported

Decimation

Rates for

Lane Rate =

1.7 Gbps to

3.4 Gbps

Supported

Decimation

Rates for

Lane Rate =

3.4 Gbps to

6.8 Gbps

Supported

Decimation

Rates for

Lane Rate =

6.8 Gbps to

13.5 Gbps

Supported

Decimation

Rates for

Lane Rate =

13.5 Gbps

to 15.5 Gbps

JESD204B Transport Layer Settings³

Serial

(Same Value Line

as M)

Rate²

L

M

F

S

HD

N

N'

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

8 to 12 12 0 to 3 See

Note 4

L

K

1

15 × f_OUT

3, 6, 12

3, 6

1

3

2

0

7.5 × f_OUT3, 6

3, 6

3

2

3

1

2

3

4

1

2

3

4

2

4

1

2

4

8

3

6

1

3

1

3

6

3

2

3

6

3

4

8

2

1

2

1

4

1

2

1

0

1

0

1

0

1

0

3, 6

3

5 × f_OUT

1, 2, 3, 4, 5, 6,

8

1, 2, 3, 4

3, 6, 12, 24

3, 6, 12

1, 2

1

2

4

8

30 × f_OUT

15 × f_OUT

10 × f_OUT

3, 6, 12, 24

3, 6, 12

3, 6

3, 6, 12

1, 2, 3, 4, 5, 6,

8, 10, 12, 16

1, 2, 3, 4, 5, 6,

8

3, 6

1, 2, 3, 4

3

1, 2

7.5 × f_OUT3, 6

60 × f_OUT

30 × f_OUT

20 × f_OUT

15 × f_OUT

60 × f_OUT

30 × f_OUT

6, 12, 24, 48

3, 6, 12, 24, 48

3, 6, 12, 24

3, 6, 12

3, 6, 12, 24

2, 4, 5, 6, 8, 10,

12, 16, 20, 24

3, 6, 12

1, 2, 3, 4, 5, 6,

8, 10, 12, 16

3, 6, 12

1, 2, 3, 4, 5,

6, 8

3, 6

1, 2, 3, 4

6, 12, 24, 48

6, 12, 24

6, 12, 24, 48

6, 12, 24

6, 12

¹Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.

²f_{ADC_CLK}is the ADC sample rate; DCM is the chip decimation ratio; f_OUTis the output sample rate = f_{ADC_CLK}/DCM; SLR is the JESD204B serial lane rate. The following equations

must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ f_{ADC_CLK}; least common multiple (20 × DCM × f_OUT/SLR, DCM) ≤ 64.

When the SLR is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set

to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must

be set to 0x50.

³JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter

device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the

virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the

number of frames per multiframe.

⁴Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4,

8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.

Rev. 0 | Page 76 of 138

Data Sheet

AD6688

Table 35. JESD204B Output Configurations for N΄ = 8¹

No. of

Virtual

Converters

Supported

(Same Value

as M)

Supported

Decimation

Rates for

Lane Rate =

1.7 Gbps to

3.4 Gbps

Supported

Decimation Decimation Decimation

Rates for Rates for Rates for

Supported

Serial

Lane

Rate²

Lane Rate = Lane Rate = Lane Rate =

3.4 Gbps to 6.8 Gbps to 13.5 Gbps to

JESD204B Transport Layer Settings³

6.8 Gbps

13.5 Gbps

15.5 Gbps

L

M

F

S

HD

N

N'

CS

K

1

2

10 × f_OUT

5 × f_OUT

1, 2, 3, 4, 5, 6,

8, 10, 12

1, 2, 3, 4, 5, 6,

8, 10, 12

1, 2, 3, 4, 5, 6,

8

1, 2, 3, 4, 5, 6,

8

1, 2, 3, 4, 5,

6, 8

1, 2, 3, 4, 5,

6, 8

1, 2, 3, 4

1, 2

1, 2, 3, 4

1, 2

1

0

7 to 8

8

0 to 1 See

Note 4

0 to 1 See

Note 4

0 to 1 See

Note 4

0 to 1 See

Note 4

0 to 1 See

Note 4

0 to 1 See

Note 4

0 to 1 See

Note 4

0 to 1 See

Note 4

1, 2, 3, 4

1, 2

1

1, 2

1

2

4

1

2

1

2

4

1

2

4

8

4

8

1

0

7 to 8

8

5 × f_OUT

1

5 × f_OUT

1, 2, 3, 4, 5, 6,

8

1

2.5 × f_OUT

20 × f_OUT

1, 2, 3, 4

1, 2

1

2, 4, 5, 6, 8, 10, 1, 2, 3, 4, 5,

12, 15, 16, 20,

24, 30

1, 2, 3, 4, 5, 6,

8, 10, 12, 15,

16

1, 2, 3, 4, 5, 6,

8, 10, 12, 15,

16

1, 2, 3, 4, 5,

6, 8

1, 2, 3, 4

1, 2

6, 8, 10, 12,

15, 16

1, 2, 3, 4, 5,

6, 8

2

10 × f_OUT

1, 2, 3, 4

2

1

2

1

2

0

7 to 8

8

0 to 1 See

Note 4

1, 2, 3, 4, 5,

6, 8

1, 2

0 to 1 See

Note 4

2

5 × f_OUT

1, 2, 3, 4, 5, 6,

8

1, 2, 3, 4, 5, 6,

8

1, 2, 3, 4, 5, 6,

8

1, 2, 3, 4

1, 2

1

4

2

1

2

4

2

4

8

0

7 to 8

8

0 to 1 See

Note 4

0 to 1 See

Note 4

0 to 1 See

Note 4

¹Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.

²f_{ADC_CLK}is the ADC sample rate; DCM is the chip decimation ratio; f_OUTis the output sample rate = f_{ADC_CLK}/DCM; SLR is the JESD204B serial lane rate. The following equations

must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ f_{ADC_CLK}; least common multiple (20 × DCM × f_OUT/SLR, DCM) ≤ 64.

When the SLR is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set

to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must

be set to 0x50.

³JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter

device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the

virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the

number of frames per multiframe.

⁴Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4,

8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.

Rev. 0 | Page 77 of 138

AD6688

Data Sheet

Example: ADC with DDC Option (Two ADCs Plus Two DDCs)

2949.12MSPS

368.64MSPS

7.3728Gbps

SYNC~

F = 2

M (I)

0

VIN_A

REAL

DDC 0

L

0

(REAL INPUT,

DCM = 8

14-BIT

ADC CORE

C2R = BYPASS)

M (Q)

1

M (I)

2

VIN_B

REAL

DDC 1

L

(REAL INPUT,

DCM = 8

1

14-BIT

ADC CORE

M (Q)

3

C2R = BYPASS)

JESD204B LINK

(L = 4, M = 4, F = 2,

S = 1, N’ = 16, N = 16,

CS = 0, HD = 0)

I = REAL COMPONENT

Q = QUADRATURE COMPONENT

DCM = DECIMATION

L

2

C2R = COMPLEX TO REAL

M

= VIRTUAL CONVERTER X

= LANE Y

X

L

Y

S

= SAMPLE Z INSIDE A JESD204B FRAME

Z

C = CONTROL BIT (OVERRANGE, AMONG OTHERS)

T = TAIL BIT

L

3

Figure 103. Two ADC Plus Two DDC Mode (L = 4, M = 4, F = 2, S = 1)

The AD6688 is set up as shown in Figure 103, with the

following configuration:

For L = 2, the PLL control register (Register 0x056E) must be

set to 0x30. For L = 4, the PLL control register (Register 0x056E)

must be set to 0x00.

•

Two 14-bit converters at 2.94912 GSPS.

Two DDC application layer mode with complex outputs

(I/Q).

This example shows the flexibility in the digital and lane config-

urations for the AD6688. The sample rate is 2.94912 GSPS;

however, the outputs are all combined in either two or four

lanes, depending on the input/output speed capability of the

receiving device.

•

Chip decimation ratio = 8.

DDC decimation ratio = 8 (see Table 46).

The JESD204B output configuration is as follows:

•

Virtual converters required = 4 (see Table 33).

Output sample rate (f_OUT) = 2949.12/8 = 368.64 MSPS.

The JESD204B supported output configurations are as follows

(see Table 33):

•

N΄ = 16 bits.

N = 14 bits.

L = 2, M = 4, and F = 4, or L = 4, M = 4, and F = 2.

CS = 0.

K = 32.

Output serial lane rate = 14.7456 Gbps per lane (L = 2) or

7.3728 Gbps per lane (L = 4).

Rev. 0 | Page 78 of 138

Data Sheet

AD6688

DETERMINISTIC LATENCY

Both ends of the JESD204B link contain various clock domains

distributed throughout each system. Data traversing from one

clock domain to a different clock domain can lead to ambiguous

delays in the JESD204B link. These ambiguities lead to non-

repeatable latencies across the link from one power cycle or link

reset to the next. Section 6 of the JESD204B specification

addresses the issue of deterministic latency with mechanisms

defined as Subclass 1 and Subclass 2.

SUBCLASS 1 OPERATION

The JESD204B protocol organizes data samples into octets, frames,

and multiframes as described in the Transport Layer section.

The LMFC is synchronous with the beginnings of these

multiframes. In Subclass 1 operation, the SYSREF is used to

synchronize the LMFCs for each device in a link or across

multiple links (within the AD6688, SYSREF also synchronizes

the internal sample dividers), as shown in Figure 104. The

JESD204B receiver uses the multiframe boundaries and

buffering to achieve consistent latency across lanes (or even

multiple devices), and also to achieve a fixed latency between

power cycles and link reset conditions.

The AD6688 supports JESD204B Subclass 0 and Subclass 1

operation. Register 0x0590, Bit 5 sets the subclass mode for the

AD6688 and its default is set for Subclass 1 operating mode

(Register 0x0590, Bit 5 = 1). If deterministic latency is not a

system requirement, Subclass 0 operation is recommended and

the SYSREF signal may not be required. Even in Subclass 0

mode, the SYSREF signal may be required in an application

where multiple AD6688 devices must be synchronized with

each other. This topic is addressed in the Timestamp Mode

section.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic

latency in a JESD204B Subclass 1 system.

•

SYSREF signal distribution skew within the system must

be less than the desired uncertainty for the system.

SYSREF setup and hold time requirements must be met

for each device in the system.

The total latency variation across all lanes, links, and

devices must be ≤1 LMFC periods (see Figure 104). This

includes both variable delays and the variation in fixed

delays from lane to lane, link to link, and device to device

in the system.

SUBCLASS 0 OPERATION

If there is no requirement for multichip synchronization while

operating in Subclass 0 mode (Register 0x0590, Bit 5 = 0), the

SYSREF input can be left disconnected. In this mode, the

relationship of the JESD204B clocks between the JESD204B

transmitter and receiver are arbitrary, but does not affect the ability

of the receiver to capture and align the lanes within the link.

SYSREF

DEVICE CLOCK

SYSREF-ALIGNED

GLOBAL LMFC

SYSREF TO LMFC DELAY

POWER CYCLE VARIATION

(MUST BE < t_LMFC

)

All LMFCs

DATA

ILAS

DATA

Figure 104. SYSREF and LMFC

Rev. 0 | Page 79 of 138

AD6688

Data Sheet

Setting Deterministic Latency Registers

this adjustment. If the total latency in the system is not near an

integer multiple of the LMFC period or if the appropriate

adjustments have been made to the LMFC phase at the clock

source, it is still possible to have variable latency from one

power cycle to the next. By design, the AD6688 has circuitry in

place to minimize this variation from power-up to power-up. In

this case, the user must check for the possibility that the setup

and hold time requirements for the SYSREF signal are not being

met, by reading the SYSREF setup/hold monitor register

(Register 0x0128). This function is fully described in the

SYSREF Setup/Hold Window Monitor section.

The JESD204B receiver in the logic device buffers data starting

on the LMFC boundary. If the total link latency in the system is

near an integer multiple of the LMFC period, it is possible that

from one power cycle to the next, the data arrival time at the

receive buffer may straddle an LMFC boundary. To ensure

deterministic latency in this case, a phase adjustment of the

LMFC at either the transmitter or receiver must be performed.

Typically, adjustments to accommodate the receive buffer are

made to the LMFC of the receiver. Alternatively, this adjustment

can be made in the AD6688 using the LMFC offset register

(Register 0x0578, Bits[4:0]). This delays the LMFC in frame

clock increments, depending on the F parameter (number of

octets per lane per frame). For F = 1, every fourth setting (0, 4,

8, and so on) is valid and results in a four frame clock shift. For

F = 2, every other setting (0, 2, 4, and so on) is valid and results

in a two frame clock shift. For all other values of F, each setting

results in a one frame clock shift. Figure 105 shows that, when

the link latency is near an LMFC boundary, the local LMFC of

the AD6688 can be adjusted to delay the data arrival time at the

receiver. Figure 106 shows how the LMFC of the receiver is

delayed to accommodate the receive buffer timing. Consult the

applicable JESD204B receiver user guide for details on making

If reading Register 0x128 indicates that there may be a timing

problem, there are a few adjustments that can made in the

AD6688. Changing the SYSREF level that is used for alignment is

possible using the SYSREF transition select bit (Register 0x0120,

Bit 4). Also, changing which edge of CLK is used to capture the

SYSREF signal can be done using the CLK edge select bit

(Register 0x0120, Bit 3). Both of these options are described in

the SYSREF Control Features section. If neither of these

measures helps to achieve an acceptable setup and hold time,

adjusting the phase of SYSREF and/or the device clock (CLK )

may be required.

LMFC DELAY TIME

TX

POWER CYCLE VARIATION

SYREF-ALIGNED

GLOBAL LMFC

Tx LOCAL LMFC

DATA

ILAS

DATA

(AT Tx INPUT)

DATA

(AT Rx INPUT)

ILAS

DATA

Tx LMFC MOVED (DELAYING THE ARRIVAL OF DATA RELATIVE

TO THE GLOBAL LMFC) SO THE RECEIVE BUFFER RELEASE

TIME IS ALWAYS REFERENCED TO THE SAME LMFC EDGE.

Figure 105. Adjusting the JESD204B Tx LMFC in the AD6688

LMFC DELAY TIME

POWER CYCLE VARIATION

RX

SYREF-ALIGNED

GLOBAL LMFC

DATA

(AT Tx INPUT)

ILAS

DATA

(AT Rx OUTPUT)

ILAS

DATA

Rx LOCAL LMFC

Rx LMFC MOVED SO THE RECEIVE BUFFER RELEASE TIME

IS ALWAYS REFERENCED TO THE SAME LMFC EDGE

Figure 106. Adjusting the JESD204B Rx LMFC in the Logic Device

Rev. 0 | Page 80 of 138

Data Sheet

AD6688

MULTICHIP SYNCHRONIZATION

The flowchart in Figure 108 shows the internal mechanism for

multichip synchronization in the AD6688. There are two methods

by which multichip synchronization can take place, as determined

by the chip synchronization mode bit (Register 0x01FF, Bit 0).

Each method involves different applications of the SYSREF signal.

used for synchronization of multiple channels and/or devices.

In this mode, SYSREF resets the sample dividers and the

JESD204B clocking. When the chip sync mode is set to 1, the

clocks are not reset; instead, the coinciding sample is timestamped

using the JESD204B control bits of that sample. To operate in

timestamp mode, these additional settings are necessary:

NORMAL MODE

•

Continuous or N-shot SYSREF must be enabled

(Register 0x0120, Bits[2:1] = 1 or 2).

At least one control bit must be enabled (Register 0x058F,

Bits[7:6] = 1, 2, or 3).

The default sate of the chip synchronization mode bit is 0, which

configures the AD6688 for normal chip synchronization. The

JESD204B standard specifies the use of SYSREF to provide for

deterministic latency within a single link. This same concept,

when applied to a system with multiple converters and logic

devices can also provide multichip synchronization. In Figure 108,

this is referred to as normal mode. Following the process in the

flowchart ensures that the AD6688 is configured appropriately.

The user must also consult the logic devices user IP guide to

ensure that the JESD204B receivers are configured appropriately.

Set the function for one of the control bits to SYSREF:

•

Register 0x0559, Bits[2:0] = 5 if using Control Bit 0.

Register 0x0559, Bits[6:4] = 5 if using Control Bit 1.

Register 0x055A, Bits[2:0] = 5 if using Control Bit 2.

Figure 107 shows how the input sample coincident with SYSREF

is timestamped and ultimately output from the ADC. In this

example, there are two control bits, and Control Bit 0 is the bit

indicating which sample was coincident with the SYSREF rising

edge. Note that the pipeline latencies for each channel are

identical. If so desired, the SYSREF timestamp delay register

(Register 0x0123) can be used to adjust the timing of which

sample is time stamped.

TIMESTAMP MODE

For all AD6688 full bandwidth operating modes, the SYSREF

input can also be used to timestamp samples. This is another

method by which multiple channels and multiple devices can

achieve synchronization. This method is especially effective when

synchronizing multiple devices to one or more logic devices. The

logic devices buffer the data streams, identify the timestamped

samples, and align them. When the chip synchronization mode

bit (Register 0x01FF, Bit 0) is set to 1, the timestamp method is

Note that time stamping is not supported by any AD6688

operating modes that use decimation.

14-BIT SAMPLES OUT

N

N – 1

A

N + 1

N + 2

IN

N – 1 00

N

01 N + 1 00 N + 2 00 N + 3 00

CHANNEL A

N + 3

ENCODE CLK

SYSREF

CONTROL BIT 0 USED TO

TIMESTAMP SAMPLE N

N

N – 1

A

B

N – 1 00

01 N + 1 00 N + 2 00 N + 3 00

IN

CHANNEL B

N + 1

N + 2

N + 3

2 CONTROL BITS

Figure 107. AD6688 Timestamping Example—CS = 2 (Register 0x058F, Bits[7:6] = 2), Control Bit 0 is SYSREF (Register 0x0559, Bits[2:0] = 5)

Rev. 0 | Page 81 of 138

AD6688

Data Sheet

INCREMENT

SYSREF IGNORE

COUNTER

START

NO

SYSREF±

IGNORE

COUNTER

EXPIRED?

(0x0121)

RESET

SYSREF± IGNORE

COUNTER

SYSREF±

ENABLED?

(0x0120)

UPDATE SETUP/HOLD

DETECTOR STATUS

(0x0128)

YES

NO

YES

SYSREF±

ASSERTED?

YES

CLOCK

DIVIDER

AUTO ADJUST

ENABLED?

(0x010D)

INPUT

CLOCK

INCREMENT

SYSREF± COUNTER

(0x012A)

ALIGN CLOCK

DIVIDER PHASE

TO SYSREF

YES

CLOCK DIVIDER

ALIGNMENT

REQUIRED?

DIVIDER

>1?

(0x010B)

NO

SYSREF±

ENABLED

IN CONTROL BITS?

(0x0559, 0x055A,

0x058F)

SYSREF±

TIMESTAMP

DELAY

TIMESTAMP

MODE

SYNCHRO-

NIZATION

MODE?

SYSREF± INSERTED

IN JESD204B

CONTROL BITS

YES

(0x0123)

(0x01FF)

NO

RAMP

SYSREF± RESETS

RAMP TEST MODE

GENERATOR

YES

NORMAL

MODE

TEST MODE

ENABLED?

(0x0550)

BACK TO START

NO

JESD204B

LMFC

ALIGN PHASE OF ALL

SEND INVALID

NORMAL

JESD204B

INITIALIZATION

YES

SEND K28.5

CHARACTERS

INTERNAL CLOCKS

8-BIT/10-BIT

CHARACTERS

(ALL 0s)

ALIGNMENT

REQUIRED?

ASSERTED

NO

(INCLUDING LMFC)

TO SYSREF±

NO

SIGNAL

MONITOR

ALIGNMENT

ENABLED?

(0x026F)

DDC NCO

ALIGN SIGNAL

ALIGN DDC NCO

PHASE

ACCUMULATOR

YES

ALIGNMENT

ENABLED?

(0x0300)

MONITOR

BACK TO START

COUNTERS

NO

Figure 108. SYSREF Capture Scenarios and Multichip Synchronization

machine when set. If in single (or N) shot mode (Register 0x0120,

Bits[2:1] = 2), the SYSREF mode select bit self clears after the

appropriate SYSREF transition is detected. The pulse width

must have a minimum width of two CLK periods. If the clock

divider (Register 0x010B, Bits[3:0]) is set to a value other than

divide by 1, multiply this minimum pulse width requirement by

the divide ratio (that is, if set to divide by 8, the minimum pulse

SYSREF INPUT

The SYSREF input signal is used as a high accuracy system

reference for deterministic latency and multichip synchro-

nization. The AD6688 accepts a single-shot or periodic input

signal. The SYSREF mode select bits (Register 0x0120, Bits[2:1])

select the input signal type and also arm the SYSREF state

Rev. 0 | Page 82 of 138

Data Sheet

AD6688

width is 16 CLK cycles). When using a continuous SYSREF

signal (Register 0x0120, Bits[2:1] = 1), the period of the SYSREF

signal must be an integer multiple of the LMFC. Derive LMFC

using the following formula:

SYSREF trigger. Figure 113 shows an example of the SYSREF

ignore feature when ignoring three SYSREF events.

SETUP

REQUIREMENT

–65ps

SYSREF

SAMPLE POINT

HOLD

REQUIREMENT

95ps

LMFC = ADC clock/(S × K)

where:

CLK

S is the JESD204B parameter for number of samples per converter.

K is the number of frames per multiframe.

SYSREF

The input clock divider, DDCs, signal monitor block, and

JESD204B link are all synchronized using the SYSREF input

when in normal synchronization mode (Register 0x01FF,

Bits 0 = 0). The SYSREF input can also be used to timestamp

an ADC sample to provide a mechanism for synchronizing

multiple AD6688 devices in a system. For the highest level of

timing accuracy, SYSREF must meet setup and hold

requirements relative to the CLK input. There are several

features in the AD6688 that can be used to ensure these

requirements are met; these features are described in the

SYSREF Control Features section.

KEEP OUT WINDOW

Figure 109. SYSREF Setup and Hold Time Requirements—SYSREF Low to

High Transition Using Rising Edge Clock (Default)

SETUP

REQUIREMENT

–65ps

SYSREF

SAMPLE POINT

HOLD

REQUIREMENT

95ps

CLK

SYSREF

Figure 110. SYSREF Low to High Transition Using Falling Edge Clock Capture

(Register 0x0120, Bit 4 = 1’b0; Register 0x0120, Bit 3 = 1’b1)

SYSREF Control Features

SETUP

REQUIREMENT

–65ps

SYSREF is used, along with the input clock (CLK), as part of a

source-synchronous timing interface and requires setup and

hold timing requirements of −65 ps and 95 ps relative to the

input clock (see Figure 109). The AD6688 has several features

that aid users in meeting these requirements. First, the SYSREF

sample event can be defined as either a synchronous low to high

transition or synchronous high to low transition. Second, the

AD6688 allows the SYSREF signal to be sampled using either

the rising edge or falling edge of the input clock. Figure 109,

Figure 110, Figure 111, and Figure 112 show all four possible

combinations.

SYSREF

HOLD

REQUIREMENT

95ps

SAMPLE POINT

CLK

SYSREF

Figure 111. SYSREF High to Low Transition Using Rising Edge Clock Capture

(Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b0)

SETUP

REQUIREMENT

–65ps

SYSREF

SAMPLE POINT

HOLD

REQUIREMENT

95ps

The third SYSREF related feature available is the ability to

ignore a programmable number (up to 16) of SYSREF events.

The AD6688 is able to ignore N SYSREF events (note that the

SYSREF ignore feature is enabled by setting the SYSREF mode

register (Register 0x0120, Bits[2:1]) to 2'b10, which is labeled as

N-shot mode. This feature is useful for handling periodic SYSREF

signals, which need time to settle after startup. Ignoring SYSREF

until the clocks in the system have settled can avoid an inaccurate

CLK

SYSREF

Figure 112. SYSREF High to Low Transition Using Falling Edge Clock Capture

(Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b1)

SYSREF SAMPLE PART 1 SYSREF SAMPLE PART 2 SYSREF SAMPLE PART 3

SYSREF SAMPLE PART 4 SYSREF SAMPLE PART 5

CLK

SYSREF

SAMPLE THE FOURTH SYSREF

IGNORE FIRST THREE SYSREFs

Figure 113. SYSREF Ignore Example (SYSREF Ignore Count, Register 0x0121, Bits[3:0] = 3)

Rev. 0 | Page 83 of 138

AD6688

Data Sheet

SYSREF SKEW WINDOW = ±3

SYSREF SKEW WINDOW = ±2

SYSREF SKEW WINDOW = ±1

SYSREF SKEW WINDOW = 0

CLK

SYSREF

Figure 114. SYSREF Skew Window

When in continuous SYSREF mode (Register 0x0120, Bits[2:1] =

1), the AD6688 monitors the placement of the SYSREF leading

edge compared to the internal LMFC. If the SYSREF is captured

with a clock edge other than the one that is aligned with LMFC,

the AD6688 initiates a resynchronization of the link. Because

input clock rates for AD6688 can be up to 4 GHz, the AD6688

provides another SYSREF related feature that makes it possible

to accommodate periodic SYSREF signals where cycle accurate

capture is not feasible or not required. For these scenarios, the

AD6688 has a programmable SYSREF skew window that allows

the internal dividers to remain undisturbed unless SYSREF

occurs outside the skew window. The resolution of the SYSREF

skew window is set in sample clock cycles. If the SYSREF negative

skew window is 1 and the positive skew window is 1, the total

skew window is 1 sample clock cycles, meaning that, as long as

SYSREF is captured within 1 sample clock cycle of the clock that

is aligned with LMFC, the link continues to operate normally. If

the SYSREF has jitter, which can cause a misalignment between

SYSREF and LMFC, this feature allows the system to continue

running without a resynchronization, while still allowing the

device to monitor for larger errors not caused by jitter. For the

AD6688, the positive and negative skew window is controlled by

the SYSREF window negative register (Register 0x0122, Bits[3:2])

and SYSREF window positive register (Register 0x0122, Bits[1:0]).

Figure 114 shows information on the location of the skew window

settings relative to Phase 0 of the internal dividers. Negative skew

is defined as occurring before the internal dividers reach Phase 0,

and positive skew is defined after the internal dividers reach

Phase 0.

Rev. 0 | Page 84 of 138

Data Sheet

AD6688

for different phases of SYSREF . The setup detector returns the

status of the SYSREF signal before the CLK edge, and the

hold detector returns the status of the SYSREF signal after the

CLK edge. Register 0x0128 stores the status of SYSREF and

notifies the user if the SYSREF signal is captured by the ADC.

SYSREF SETUP/HOLD WINDOW MONITOR

To ensure a valid SYSREF signal capture, the AD6688 has a

SYSREF setup/hold window monitor. This feature allows the

system designer to determine the location of the SYSREF signals

relative to the CLK signals by reading back the amount of

setup/hold margin on the interface through the memory map.

Figure 115 and Figure 116 show the setup and hold status values

Table 36 shows the description of the contents of Register 0x0128

and how to interpret them.

0xF

0xE

0xD

0xC

0xB

0xA

0x9

REG 0x0128[3:0]

0x8

0x7

0x6

0x5

0x4

0x3

0x2

0x1

0x0

CLK±

INPUT

SYSREF±

INPUT

VALID

FLIP-FLOP

HOLD (MIN)

FLIP-FLOP

SETUP (MIN)

FLIP-FLOP

HOLD (MIN)

Figure 115. SYSREF Setup Detector

Rev. 0 | Page 85 of 138

AD6688

Data Sheet

0xF

0xE

0xD

0xC

0xB

0xA

0x9

0x8

0x7

0x6

0x5

0x4

0x3

0x2

0x1

0x0

REG 0x0128[7:4]

CLK±

INPUT

SYSREF±

INPUT

VALID

FLIP-FLOP

SETUP (MIN)

FLIP-FLOP

HOLD (MIN)

FLIP-FLOP

HOLD (MIN)

Figure 116. SYSREF Hold Detector

Table 36. SYSREF Setup/Hold Monitor, Register 0x0128

Register 0x0128, Bits[7:4]

Hold Status

Register 0x0128, Bits[3:0]

Setup Status

Description

0x0

0x0 to 0x8

0x8

0x0 to 0x7

0x8

0x9 to 0xF

0x0

Possible setup error. The smaller this number, the smaller the setup margin.

No setup or hold error (best hold margin).

No setup or hold error (best setup and hold margin).

No setup or hold error (best setup margin).

0x8

0x9 to 0xF

0x0

Possible hold error. The larger this number, the smaller the hold margin.

Possible setup or hold error.

Rev. 0 | Page 86 of 138

Data Sheet

AD6688

LATENCY

END TO END TOTAL LATENCY

EXAMPLE LATENCY CALCULATIONS

Total latency in the AD6688 is dependent on the chip application

mode and the JESD204B configuration. For any given combination

of these parameters, the latency is deterministic; however, the

value of this deterministic latency must be calculated as described

in the Example Latency Calculations section.

Example Configuration 1 is as follows:

•

ADC application mode = full bandwidth

Real outputs

L = 8, M = 2, F = 1, S = 2 (JESD204B mode)

20 × (M/L) = 5

Table 37 shows the combined latency through the ADC and

DSP for the different chip application modes supported by the

AD6688. Table 38 shows the latency through the JESD204B

block for each application mode based on the M/L ratio. For

both tables, latency is typical and is in units of the encode clock.

The latency through the JESD204B block does not depend on

the output data type (real or complex). Therefore, data type is

not included in Table 38.

Latency = 31 + 44 = 75 encode clocks

Example Configuration 2 is as follows:

•

ADC application mode = DCM4

Complex outputs

L = 4, M = 2, F = 1, S = 1 (JESD204B mode)

20 × (M/L) = 10

Latency = 162 + 88 = 250 encode clocks

To determine the total latency, select the appropriate ADC + DSP

latency from Table 37 and add it to the appropriate JESD204B

latency from Table 38. Example calculations are provided in the

following section.

LMFC-REFERENCED LATENCY

Some FPGA vendors may require the end user to know LMFC-

referenced latency to make appropriate deterministic latency

adjustments. If they are required, the latency values in Table 37

and Table 38 can be used for the analog in to LMFC and LMFC

to data out latency values.

Rev. 0 | Page 87 of 138

AD6688

Data Sheet

Table 37. Latency Through the ADC + DSP Blocks (Number of Sample Clocks)¹

Chip Application Mode

Full Bandwidth

DCM1 (Real)

Enabled Filters

Not applicable

HB1

ADC + DSP Latency

31

90

DCM2 (Complex)

DCM3 (Complex)

DCM2 (Real)

DCM4 (Complex)

DCM3 (Real)

DCM6 (Complex)

DCM4 (Real)

DCM8 (Complex)

DCM5 (Real)

DCM10 (Complex)

DCM6 (Real)

DCM12 (Complex)

DCM15 (Real)

DCM8 (Real)

DCM16 (Complex)

DCM10 (Real)

DCM20 (Complex)

DCM12 (Real)

DCM24 (Complex)

DCM30 (Complex)

DCM20 (Real)

DCM40 (Complex)

DCM24 (Real)

DCM48 (Complex)

HB1

TB1

HB2 + HB1

TB2 + HB1

HB3 +HB2 + HB1

FB2 + HB1

90

102

162

212

292

380

424

500

552

694

814

836

1420

1594

FB2 + HB1

TB2 + HB2 + HB1

FB2 + TB1

HB4 + HB3 + HB2 + HB1

FB2 + HB2 + HB1

TB2 + HB3 + HB2 + HB1

HB2 + FB2 + TB1

FB2 + HB3 + HB2 + HB1

TB2 + HB4 + HB3 + HB2 + HB1

¹DCMx indicates the decimation ratio.

Table 38. Latency Through JESD204B Block (Number of Sample Clocks)¹

M/L Ratio²

1

Chip Application

Mode

0.125

82

0.25

44

0.5

25

2

4

8

Full Bandwidth

DCM1

14

7

9

3

82

44

25

7

14

21

27

N/A

7

11

N/A

9

DCM2

DCM3

DCM4

DCM5

DCM6

DCM8

DCM10

DCM12

DCM15

DCM16

DCM20

DCM24

DCM30

DCM40

DCM48

160

237

315

N/A

84

46

67

88

27

39

50

62³

73

96

119

142

176⁴

188⁴

233

279

348⁴

N/A

124

164

203³

243

323

N/A

14

109³

130

172

213

255

318⁴

339⁴

N/A

43³

39

N/A

21

N/A

14

50

27

18

62

33

22

73

39

27

90⁴

96⁴

119

142

176⁴

233⁴

279⁴

47⁴

50⁴

62

33⁴

35⁴

43

73

51

90⁴

119⁴

142⁴

62⁴

82⁴

97⁴

¹N/A indicates that the application mode is not supported at the M/L ratio listed.

²M/L ratio is the number of converters divided by the number of lanes for the configuration.

³The application mode at the M/L ratio listed is only supported in real output mode.

⁴The application mode at the M/L ratio listed is only supported in in complex output mode.

Rev. 0 | Page 88 of 138

Data Sheet

AD6688

TEST MODES

If the application mode is set to select a DDC mode of

ADC TEST MODES

operation, the test modes must be enabled for each DDC

enabled. The test patterns can be enabled via Bit 2 and Bit 0 of

Register 0x0327, Register 0x0347, and Register 0x0367,

depending on which DDC(s) are selected. The (I) data uses the

test patterns selected for Channel A, and the (Q) data uses the

test patterns selected for Channel B. For DDC3 only, the (I) data

uses the test patterns from Channel A, and the (Q) data does

not output test patterns. Bit 0 of Register 0x0387 selects the

Channel A test patterns to be used for the (I) data. For more

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

The AD6688 has various test options that aid in the system level

implementation. The AD6688 has ADC test modes that are

available in Register 0x0550. These test modes are described in

Table 39. When an output test mode is enabled, the analog section

of the ADC is disconnected from the digital back end blocks,

and the test pattern is run through the output formatting block.

Some of the test patterns are subject to output formatting, and

some are not. The pseudorandom number (PN) generators

from the PN sequence tests can be reset by setting Bit 4 or Bit 5

of Register 0x0550. These tests can be performed with or

without an analog signal (if present, the analog signal is

ignored); however, they do require an encode clock.

Table 39. ADC Test Modes

Output Test Mode

Bit Sequence

Default/

Pattern Name

Expression

Seed Value

Not applicable

0x3AFF

0x0092

Not applicable

Sample (N, N + 1, N + 2, …)

Not applicable

0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555

0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6

0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697

0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000

0000

0001

0010

0011

0100

0101

0110

0111

Off (default)

Midscale short

Not applicable

0000 0000 0000

01 1111 1111 1111

10 0000 0000 0000

10 1010 1010 1010

x²³+ x¹⁸+ 1

x⁹+ x⁵+ 1

11 1111 1111 1111

Register 0x551 to

Register 0x558

Positive full-scale short

Negative full-scale short

Checkerboard

PN sequence long

PN sequence short

One-/zero-word toggle

User input

1000

User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2],

User Pattern 1[15:2] … for repeat mode.

User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2],

0x0000 … for single mode.

1111

Ramp Output

(x) % 2¹⁴

Not applicable

(x) % 2¹⁴, (x +1) % 2¹⁴, (x +2) % 2¹⁴, (x +3) % 2¹⁴

Rev. 0 | Page 89 of 138

AD6688

Data Sheet

These tests are shown in Register 0x0571, Bit 5. The test pattern

is equivalent to the raw samples from the ADC.

JESD204B BLOCK TEST MODES

In addition to the ADC pipeline test modes, the AD6688 also has

flexible test modes in the JESD204B block. These test modes are

listed in Register 0x0573 and Register 0x0574. These test patterns

can be injected at various points along the output datapath. These

test injection points are shown in Figure 94. Table 40 describes

the various test modes available in the JESD204B block. For the

AD6688, a transition from test modes (Register 0x0573 ≠ 0x00)

to normal mode (Register 0x0573 = 0x00) requires an SPI soft

reset. This is done by writing 0x81 to Register 0x0000 (self cleared).

Interface Test Modes

The interface test modes are described in Register 0x0573, Bits[3:0].

These test modes are also explained in Table 40. The interface tests

can be injected at various points along the data. See Figure 94

for more information on the test injection points. Register 0x0573,

Bits[5:4] show where these tests are injected.

Table 41, Table 42, and Table 43 show examples of some of the

test modes when injected at the JESD204B sample input, PHY

10-bit input, and scrambler 8-bit input. UPx in the tables

represent the user pattern control bits from the user register

map.

Transport Layer Sample Test Mode

The transport layer samples are implemented in the AD6688 as

defined by Section 5.1.6.3 in the JEDEC JESD204B specification.

Table 40. JESD204B Interface Test Modes

Output Test Mode

Bit Sequence

Pattern Name

Expression

Default

0000

Off (default)

Not applicable

0001

0010

0011

0100

0101

0110

0111

1000

Alternating checker board

1/0 word toggle

0x5555, 0xAAAA, 0x5555, …

0x0000, 0xFFFF, 0x0000, …

x³¹+ x²⁸+ 1

Not applicable

0x0003AFFF

0x003AFF

0x03AF

0x092

0x07

Ramp size depends on test injection point

User Pattern 1 to User Pattern 4, then repeat

User Pattern 1 to User Pattern 4, then zeros

31-bit PN sequence

23-bit PN sequence

15-bit PN sequence

9-bit PN sequence

7-bit PN sequence

Ramp output

x²³+ x¹⁸+ 1

x¹⁵+ x¹⁴+ 1

x⁹+ x⁵+ 1

x⁷+ x⁶+ 1

(x) % 2¹⁶

1110

1111

Continuous/repeat user test

Single user test

Register 0x551 to Register 0x558

Table 41. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573[5:4] = 'b00)

Frame

Number

Converter

Number

Sample

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

PN9

PN23

User Repeat

UP1[15:0]

UP2[15:0]

UP3[15:0]

User Single

UP1[15:0]

UP2[15:0]

UP3[15:0]

UP4[15:0]

0x0000

0

1

2

3

4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0x5555

0xAAAA

0x5555

0xAAAA

0x5555

0x0000

0xFFFF

0x0000

0xFFFF

0x0000

(x) % 2¹⁶

0x496F

0xC9A9

0x980C

0x651A

0x5FD1

0xFF5C

0x0029

0xB80A

0x3D72 UP4[15:0]

0x9B26

(x) % 2¹⁶

(x +1) % 2¹⁶

(x +2) % 2¹⁶

(x +3) % 2¹⁶

(x +4) % 2¹⁶

UP1[15:0]

0x0000

Rev. 0 | Page 90 of 138

Data Sheet

AD6688

Table 42. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 'b01)

10-Bit Symbol

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

(x) % 2¹⁰

PN9

PN23

0x3FD

0x1C0

0x00A

0x1B8

0x028

0x3D7

0x0A6

0x326

0x10F

0x3FD

0x31E

0x008

User Repeat

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

User Single

0

1

2

3

4

5

6

7

8

9

10

11

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x125

0x2FC

0x26A

0x198

0x031

0x251

0x297

0x3D1

0x18E

0x2CB

0x0F1

0x3DD

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

0x000

(x + 1) % 2¹⁰

(x + 2) % 2¹⁰

(x + 3) % 2¹⁰

(x + 4) % 2¹⁰

(x + 5) % 2¹⁰

(x + 6) % 2¹⁰

(x + 7) % 2¹⁰

(x + 8) % 2¹⁰

(x + 9) % 2¹⁰

(x + 10) % 2¹⁰

(x + 11) % 2¹⁰

0x000

Table 43. Scrambler 8-Bit Input (Register 0x0573, Bits[5:4] = 'b10)

8-Bit Octet

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

(x) % 2⁸

PN9

PN23

User Repeat

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

User Single

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

0x00

0

1

2

3

4

5

6

7

8

9

10

11

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x49

0x6F

0xC9

0xA9

0x98

0x0C

0x65

0x1A

0x5F

0xD1

0x63

0xAC

0xFF

0x5C

0x00

0x29

0xB8

0x0A

0x3D

0x72

0x9B

0x26

0x43

0xFF

(x + 1) % 2⁸

(x + 2) % 2⁸

(x + 3) % 2⁸

(x + 4) % 2⁸

(x + 5) % 2⁸

(x + 6) % 2⁸

(x + 7) % 2⁸

(x + 8) % 2⁸

(x + 9) % 2⁸

(x + 10) % 2⁸

(x + 11) % 2⁸

0x00

Data Link Layer Test Modes

inserted at this point are useful for verifying the functionality of

the data link layer. When the data link layer test modes are enabled,

disable SYNCINB by writing 0xC0 to Register 0x0572.

The data link layer test modes are implemented in the AD6688 as

defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification.

These tests are shown in Register 0x0574, Bits[2:0]. Test patterns

Rev. 0 | Page 91 of 138

AD6688

Data Sheet

SERIAL PORT INTERFACE

The AD6688 SPI allows the user to configure the converter for

specific functions or operations through a structured register

space provided inside the ADC. The SPI gives the user added

flexibility and customization, depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the port. Memory is organized into bytes that

can be further divided into fields. These fields are documented

in the Memory Map section. For detailed operational information,

see the Serial Control Interface Standard (Rev. 1.0).

All data is composed of 8-bit words. The first bit of each

individual byte of serial data indicates whether a read or write

command is issued, which allows the SDIO pin to change

direction from an input to an output.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a

readback operation, performing a readback causes the SDIO pin

to change direction from an input to an output at the appropriate

point in the serial frame.

CONFIGURATION USING THE SPI

Three pins define the SPI of the AD6688 ADC: the SCLK pin,

the SDIO pin, and the CSB pin (see Table 44). The SCLK (serial

clock) pin is used to synchronize the read and write data

presented from/to the ADC. The SDIO (serial data input/output)

pin is a dual-purpose pin that allows data to be sent and read

from the internal ADC memory map registers. The CSB (chip

select bar) pin is an active low control that enables or disables

the read and write cycles.

Data can be sent in MSB first mode or in LSB first mode. MSB first

is the default on power-up and can be changed via the SPI port

configuration register. For more information about this and other

features, see the Serial Control Interface Standard (Rev. 1.0).

HARDWARE INTERFACE

The pins described in Table 44 comprise the physical interface

between the user programming device and the serial port of the.

The SCLK pin and the CSB pin function as inputs when using

the SPI interface. The SDIO pin is bidirectional, functioning as

an input during write phases and as an output during readback.

Table 44. Serial Port Interface Pins

Function

SCLK Serial clock. The serial shift clock input that is used to

synchronize serial interface, reads, and writes.

SDIO Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note,

Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.

CSB

Chip select bar. An active low control that gates the read

and write cycles.

Do not activate the SPI port during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is

used for other devices, it may be necessary to provide buffers

between this bus and the AD6688 to prevent these signals from

transitioning at the converter inputs during critical sampling

periods.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the

serial timing and its definitions can be found in Figure 3 and

Table 5.

Other modes involving the CSB pin are available. The CSB pin

can be held low indefinitely, which permanently enables the

device; this is called streaming. The CSB can stall high between

bytes to allow additional external timing. When CSB is tied

high, SPI functions are placed in a high impedance mode. This

mode turns on any SPI pin secondary functions.

SPI ACCESSIBLE FEATURES

Table 45 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the Serial Control Interface Standard (Rev. 1.0). The AD6688

device-specific features are described in the Memory Map section.

Table 45. Features Accessible Using the SPI

Feature Name

Description

Mode

Clock

Allows the user to set either power-down mode or standby mode.

Allows the user to access the clock divider via the SPI.

DDC

Allows the user to set up decimation filters for different applications.

Allows the user to set test modes to have known data on output bits.

Allows the user to set up outputs.

Test Input/Output

Output Mode

SERDES Output Setup

Allows the user to vary SERDES settings such as swing and emphasis.

Rev. 0 | Page 92 of 138

Data Sheet

AD6688

MEMORY MAP

Default Values

READING THE MEMORY MAP REGISTER TABLE

After the AD6688 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 46.

Each address in the memory map register table has eight bit

locations. The memory map is divided into the following

sections:

Logic Levels

•

Analog Devices, Inc., SPI registers (Register 0x0000 to

Register 0x000F)

Clock/SYSREF/chip power-down pin control registers

(Register 0x003F to Register 0x01FF)

Chip operating mode control registers (Register 0x0200 to

Register 0x0201)

Fast detect and signal monitor control registers

(Register 0x0245 to Register 0x027A)

DDC function registers (Register 0x0300 to

Register 0x03CD)

Digital outputs and test modes registers (Register 0x0550 to

Register 0x05CB and Register 0x1222 to Register 0x1262)

Programmable filter control and coefficients registers

(Register 0x0DF8 to Register 0x0F7F)

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

X denotes a don’t care bit.

Channel-Specific Registers

Some channel setup functions, such as the Buffer Control 1

register (Register 0x1A4C), can be programmed to a different

value for each channel. In these cases, channel address locations

are internally duplicated for each channel. These registers and

bits are designated in Table 46 as local. These local registers and

bits can be accessed by setting the appropriate Channel A or

Channel B bits in Register 0x0008. If both bits are set, the

subsequent write affects the registers of both channels. In a read

cycle, set only Channel A or Channel B to read one of the two

registers. If both bits are set during an SPI read cycle, the device

returns the value for Channel A. All other registers and bits are

considered global, and changes to these registers and bits affect the

entire device and the channel features for which independent

settings are not allowed between channels. The settings in

Register 0x0200 do not affect the global registers and bits.

VREF/analog input control registers (Register 0x0701 and

Register 0x18A6 to Register 0x1A4D)

Table 46 (see the Memory Map Register Details section)

documents the default hexadecimal value for each hexadecimal

address shown. For example, Address 0x0561, the output sample

mode register, has a hexadecimal default value of 0x01, which

means that Bit 0 = 1, and the remaining bits are 0s. This setting

is the default output format value, which is twos complement.

For more information on this function and others, see Table 46.

Open and Reserved Locations

SPI Soft Reset

All address and bit locations that are not included in Table 46

are not currently supported for this device. Write unused bits

of a valid address location with zeros unless the default value is

set otherwise. Writing to these locations is required only when

part of an address location is unassigned (for example, Bits[7:3]

of Address 0x0561). If the entire address location is open (for

example, Address 0x0013), do not write to this address location.

After issuing a soft reset by programming 0x81 to Register 0x0000,

the AD6688 requires 5 ms to recover. When programming the

AD6688 for application setup, ensure that an adequate delay is

programmed into the firmware after asserting the soft reset and

before starting the device setup.

Rev. 0 | Page 93 of 138

AD6688

Data Sheet

MEMORY MAP REGISTER DETAILS

All address locations that are not included in Table 46 to Table 53 are not currently supported for this device and must not be written.

Analog Devices SPI Registers

Table 46.

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x0000 SPI Configuration A

7

Soft reset mirror

(self clearing)

Whenever a soft reset is issued, the user must wait 5 ms before 0x0

writing to any other register. This provides sufficient time for

the boot loader to complete.

R/WC

0

1

Do nothing.

Reset the SPI and registers (self clearing).

0x0

6

5

LSB first mirror

R/W

1

0

Least significant bit shifted first for all SPI operations.

Most significant bit shifted first for all SPI operations.

0x0

Address ascension mirror

0

1

Multibyte SPI operations cause addresses to auto-decrement.

Multibyte SPI operations cause addresses to auto-increment.

[4:3] Reserved

Reserved.

0x0

R

2

1

0

Address ascension

R/W

0

1

Multibyte SPI operations cause addresses to auto-decrement.

Multibyte SPI operations cause addresses to auto-increment.

LSB first

0x0

R/W

1

0

Least significant bit shifted first for all SPI operations.

Most significant bit shifted first for all SPI operations.

Soft reset

(self clearing)

Whenever a soft reset is issued, the user must wait 5 ms before 0x0

writing to any other register. This provides sufficient time for

the boot loader to complete.

R/WC

0

1

Do nothing.

Reset the SPI and registers (self clearing).

0x0001 SPI Configuration B [7:2] Reserved

Reserved.

0x0

R

1

Datapath soft reset

R/WC

(self clearing)

0

1

Normal operation.

Datapath soft reset (self clearing).

Reserved.

0

Reserved

0x0

R

0x0002 Chip configuration [7:2] Reserved

(local)

Reserved.

[1:0] Channel power mode

Channel power modes.

0x0

R/W

00

10

Normal mode (power-up).

Standby mode; digital datapath clocks disabled; JESD204B

interface enabled.

11

Power-down mode; digital datapath clocks disabled; digital

datapath held in reset; JESD204B interface disabled.

0x0003 Chip type

0x0004 Chip ID LSB

[7:0] Chip type

Chip type.

High speed ADC.

Chip ID.

0x03

0xE2

R

0x3

[7:0] Chip ID LSB[7:0]

0xE1

0x0

AD6688

0x0005 Chip ID MSB

0x0006 Chip grade

[7:0] Chip ID MSB[15:8]

[7:4] Chip speed grade

[3:0] Reserved

Chip ID.

0x0

0x1

R

Chip speed grade.

Reserved.

R

0x0008 Device index

[7:2] Reserved

Reserved.

R

1

Channel B

R/W

0

1

ADC Core B does not receive the next SPI command.

ADC Core B receives the next SPI command.

0

Channel A

0x1

0x0

R/W

0

1

ADC Core A does not receive the next SPI command.

ADC Core A receives the next SPI command.

0x000A Scratch pad

[7:0] Scratch pad

Chip scratch pad register. This register is used to provide a

consistent memory location for software debug.

Rev. 0 | Page 94 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x000B SPI revision

[7:0] SPI revision

SPI revision register. 0x01: Revision 1.0.

0x1

R

00000001 Revision 1.0.

Vendor ID[7:0].

Vendor ID[15:8].

Reserved.

0x000C Vendor ID LSB

0x000D Vendor ID MSB

0x000F Transfer

[7:0] Vendor ID LSB

[7:0] Vendor ID MSB

[7:1] Reserved

0x56

0x04

0x0

R

0

Chip transfer

Self clearing chip transfer bit. This bit is used to update the

0x0

R/W

DDC phase increment and phase offset registers when DDC

phase update mode (Register 0x0300, Bit 7 ) = 1. This makes it

possible to synchronously update the DDC mixer frequencies.

This bit is also used to update the coefficients for the

programmable filter (PFILT).

0

1

Do nothing. Bit is only cleared after transfer is complete.

Self clearing bit used to synchronize the transfer of data from

master to slave registers.

Clock/SYSREF/Chip Power-Down Pin Control Registers

Table 47.

Addr. Name

Bit(s) Bit Name

Local chip PDWN pin

disable

Setting Description

Reset Access

0x003F Chip PDWN pin

(local)

7

Function is determined by Register 0x0040, Bits[7:6]

0x0

R/W

0

1

Power-down pin (PDWN/STBY) enabled (default).

Power-down pin (PDWN/STBY) disabled/ignored.

Reserved.

[6:0] Reserved

0x0

R

0x0040 Chip Pin Control 1 [7:6] Chip PDWN pin

functionality

External power-down pin functionality. Assertion of the external

power-down pin (PDWN/STBY) has higher priority than the channel

power mode control bits (Register 0x0002, Bits[1:0]). The PDWN/

STBY pin is only used when Register 0x0040, Bits[7:6] = 00 or 01.

R/W

00

01

10

Power-down pin (default). Assertion of external power-down pin

(PDWN/STBY) causes the chip to enter full power-down mode.

Standby pin. Assertion of external power-down pin (PDWN/STBY)

causes the chip to enter standby mode.

Pin disabled. Power-down pin (PDWN/STBY) is ignored.

Fast Detect B/GPIO B0 pin functionality.

[5:3] Chip FD_B/GPIO_B0 pin

0x7

0x0

R/W

functionality

000

001

110

111

Fast Detect B output.

JESD204B LMFC output.

Pin functionality determined by Register 0x0041, Bits[7:4].

Disabled. Configured as input with weak pull-down (default).

Fast Detect A/GPIO A0 pin functionality.

[2:0] Chip FD_A/GPIO_A0 pin

functionality

000

001

110

111

Fast Detect A output.

JESD204B LMFC output.

Pin functionality determined by Register 0x0041, Bits[3:0].

Disabled. Configured as an input with weak pull-down (default).

0x0041 Chip Pin Control 2 [7:4] Chip FD_B/GPIO_B0 pin

secondary functionality

Fast Detect B/GPIO B0 pin secondary functionality (only used

when Register 0x0040, Bits[5:3] = 110).

0000

0001

1000

1001

Chip GPIO B0 input (NCO channel selection).

Chip transfer input.

Master next trigger output (MNTO).

Slave next trigger input (SNTI).

[3:0] Chip FD_A/GPIO_A0 pin

secondary functionality

Fast Detect A/GPIO B0 pin secondary functionality (only used

when Register 0x0040, Bits[2:0] = 110).

0000

0001

1000

1001

Chip GPIO A[0] input (NCO channel selection).

Chip transfer input.

Master next trigger output (MNTO).

Slave next trigger input (SNTI).

Rev. 0 | Page 95 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting Description

GPIO B1 pin functionality.

Reset Access

0x0042 Chip Pin Control 3 [7:4] Chip GPIO_B1 pin

functionality

0xF

R/W

0000

1000

1001

1111

Chip GPIO B1 input (NCO channel selection).

Master next trigger output (MNTO).

Slave next trigger input (SNTI).

Disabled (configured as input with weak pull-down).

GPIO A1 pin functionality.

[3:0] Chip GPIO_B1 pin

functionality

0xF

R/W

0000

1000

1001

1111

Chip GPIO A1 input (NCO channel selection).

Master next trigger output (MNTO).

Slave next trigger input (SNTI).

Disabled (configured as input with weak pull-down).

Reserved.

0x0108 Clock divider control [7:3] Reserved

0x0

R

[2:0] Input clock divider

(CLK pins)

R/W

00

01

11

Divide by 1.

Divide by 2.

Divide by 4.

Reserved.

0x0109 Clock divider phase [7:4] Reserved

(local)

0x0

R

[3:0] Clock divider phase offset

R/W

0000

0001

0010

...

0 input clock cycles delayed.

½ input clock cycles delayed (invert clock).

1 input clock cycles delayed.

...

1110

1111

7 input clock cycles delayed.

7½ input clock cycles delayed.

0x010A Clock divider and

SYSREF control

7

Clock divider auto phase

adjust enable

Clock divider auto-phase adjust enable. When enabled,

Register 0x0129, Bits[3:0] contain the phase of the divider when

SYSREF was captured. The actual divider phase offset =

Register 0x0129, Bits[3:0] + Register 0x0109, Bits[3:0].

0x0

R/W

0

1

Clock divider phase is not changed by SYSREF (disabled).

Clock divider phase is automatically adjusted by SYSREF

(enabled).

[6:4] Reserved

Reserved.

0x0

R

[3:2] Clock divider negative

skew window

Clock divider negative skew window (measured in ½ input

device clocks). Number of ½ clock cycles before the input

device clock by which captured SYSREF transitions are ignored.

Only used when Register 0x010A, Bit 7 = 1. Register 0x010A,

Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0].

This allows some uncertainty in the sampling of SYSREF

without disturbing the input clock divider. Also, SYSREF must

be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing

this control field.

R/W

0

1

No negative skew; SYSREF must be captured accurately.

½ device clock of negative skew.

10

11

1 device clocks of negative skew.

1½ device clocks of negative skew.

[1:0] Clock divider positive

skew window

Clock divider positive skew window (measured in ½ input

device clocks). Number of clock cycles after the input device

clock by which captured SYSREF transitions are ignored. Only

used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2]

+ Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]. This

allows some uncertainty in the sampling of SYSREF without

disturbing the input clock divider. Also, SYSREF must be

disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this

control field.

0x0

R/W

0

1

No positive skew; SYSREF must be captured accurately.

½ device clock of positive skew.

10

11

1 device clocks of positive skew.

1½ device clocks of positive skew.

Rev. 0 | Page 96 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting Description

Reset Access

0x010B Clock divider

SYSREF status

[7:4] Reserved

Reserved.

0x0

R

[3:0] Clock divider SYSREF

offset

Clock divider phase status (measured in ½ clock cycles). Internal 0x0

clock divider phase of the captured SYSREF signal applied to the

phase offset. Only used when Register 0x010A, Bit 7 = 1. When

Register 0x010A, Bit 7 = 1 and Register 0x010A, Bits[3:2] = 0 and

Register 0x010A, Bits[1:0] = 0, clock divider SYSREF offset =

0x0129[3:0].

R

0x0110 Clock delay control [7:3] Reserved

[2:0] Clock delay mode select

Reserved.

0x0

R

Clock delay mode select. Used in conjunction with

Register 0x0111 and Register 0x0112.

R/W

000

010

011

100

110

No clock delay.

Fine delay: only 0 to 16 delay steps are valid.

Fine delay (lowest jitter): only 0 to 16 delay steps are valid.

Fine delay: all 192 delay steps are valid.

Fine delay enabled (all 192 delay steps are valid); super fine

delay enabled (all 128 delay steps are valid).

0x0111 Clock super fine

delay (local)

[7:0] Clock super fine delay

adjust

Clock super fine delay adjust. This is an unsigned control to

adjust the super fine sample clock delay in 0.25 ps steps. These

bits are only used when Register 0x0110, Bits[2:0] = 010 or 110.

0x0

R/W

0x00

...

0 delay steps.

...

0x08

...

8 delay steps.

...

0x80

128 delay steps.

0x0112 Clock fine delay

(local)

[7:0] Set clock fine delay

Clock fine delay adjust. This is an unsigned control to adjust the 0xC0 R/W

fine sample clock skew in 1.725 ps steps. These bits are only

used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6.

Minimum = 0. Maximum = 192. Increment = 1. Unit is delay steps.

0x00

...

0 delay steps.

...

0x08

...

8 delay steps.

...

0xC0

192 delay steps.

0x011B Clock status

[7:1] Reserved

Input clock detect

Reserved.

0x0

R

0

Clock detection status.

Input clock not detected.

Input clock detected/locked.

Reserved.

0

1

0x011C Clock Duty Cycle

Stabilizer 1 control

(local)

[7:2] Reserved

0x0

0x1

R/W

1

0

DCS1 enable

Clock DCS1 enable.

DCS1 bypassed.

DCS1 enabled.

0

1

DCS1 power up

Clock DCS1 power-up.

DCS1 powered down.

DCS1 powered up.

Reserved.

0x1

R/W

0

1

0x011E Clock Duty Cycle

Stabilizer 2 control

[7:2] Reserved

0x0

0x1

R/W

1

DCS2 enable

Clock DCS2 enable.

DCS2 bypassed.

DCS2 enabled.

0

1

0

DCS2 power up

Clock DCS2 power-up.

DCS2 powered down.

DCS2 powered up.

0x1

R/W

0

1

Rev. 0 | Page 97 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting Description

Reset Access

0x0120 SYSREF Control 1

7

6

Reserved

Reserved.

0x0

R

SYSREF flag reset

R/W

0

1

Normal flag operation.

SYSREF flags held in reset (setup/hold error flags cleared).

Reserved.

5

4

Reserved

0x0

R

SYSREF transition select

R/W

0

1

SYSREF is valid on low to high transitions using the selected

CLK edge. When changing this setting, SYSREF mode select

must be set to disabled.

SYSREF is valid on high to low transitions using the selected

CLK edge. When changing this setting, SYSREF mode select

must be set to disabled.

3

CLK edge select

0x0

R/W

0

1

Captured on the rising edge of CLK input.

Captured on the falling edge of CLK input.

[2:1] SYSREF mode select

0

1

10

Disabled.

Continuous.

N-shot.

0

Reserved

Reserved.

0x0

R

0x0121 SYSREF Control 2

[7:4] Reserved

R

[3:0] SYSREF N-shot ignore

counter select

R/W

0000

0001

0010

0011

Next SYSREF transition only (do not ignore).

Ignore the first SYSREF transition.

Ignore the first two SYSREF transitions.

Ignore the first three SYSREF transitions.

…

1110

1111

Ignore the first 14 SYSREF transitions.

Ignore the first 15 SYSREF transitions.

Reserved.

0x0122 SYSREF Control 3

[7:4] Reserved

0x0

R

[3:2] SYSREF window negative

Negative skew window (measured in sample clocks). Number

of clock cycles before the sample clock by which captured

SYSREF transitions are ignored.

R/W

00

01

10

11

No negative skew; SYSREF must be captured accurately.

One sample clock of negative skew.

Two sample clocks of negative skew.

Three sample clocks of negative skew.

[1:0] SYSREF window positive

Positive skew window (measured in sample clocks). Number of 0x0

clock cycles before the sample clock by which captured SYSREF

transitions are ignored.

R/W

00

01

10

11

No positive skew; SYSREF must be captured accurately.

One sample clock of positive skew.

Two sample clocks of positive skew.

Three sample clocks of positive skew.

0x0123 SYSREF Control 4

7

Reserved

Reserved.

0x0

R

[6:0] SYSREF timestamp

delay, Bits[6:0]

SYSREF timestamp delay (in converter sample clock cycles).

0x00 R/W

0

1

…

0 sample clock cycle delay.

1 sample clock cycle delay.

…

111 1111 127 sample clock cycle delay.

SYSREF hold status.

0x0128 SYSREF Status 1

[7:4] SYSREF hold status

[3:0] SYSREF setup status

0x0

R

SYSREF setup status.

Rev. 0 | Page 98 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting Description

Reset Access

0x0129 SYSREF Status 2

[7:4] Reserved

Reserved.

0x0

R

[3:0] Clock divider phase when

SYSREF was captured

SYSREF divider phase. Represents the phase of the divider

when SYSREF was captured.

0000

0001

0010

0011

0100

…

In phase.

SYSREF is ½ cycle delayed from clock.

SYSREF is 1 cycle delayed from clock.

SYSREF is 1½ input clock cycles delayed.

SYSREF is 2 input clock cycles delayed.

…

1111

SYSREF is 7½ input clock cycles delayed.

0x012A SYSREF Status 3

0x01FF Chip sync mode

[7:0] SYSREF counter, Bits[7:0]

increments when a

SYSREF count. Running counter that increments whenever a

SYSREF event is captured. Reset by Register 0x120, Bit 6. Wraps

around at 255. Read these bits only when Register 0x120, Bits[2:1]

are set to disabled.

0x0

R

SYSREF is captured

[7:1] Reserved

Reserved.

0x0

R

0

Synchronization mode

R/W

0

1

JESD204B synchronization mode. The SYSREF signal resets all

internal clock dividers. Use this mode when synchronizing

multiple chips as specified in the JESD204B standard. If the

phase of any of the dividers must change, the JESD204B link

goes down.

Timestamp mode. The SYSREF signal does not reset internal

clock dividers. In this mode, the JESD204B link and the signal

monitor are not affected by the SYSREF signal. The SYSREF

signal timestamps a sample as it passes through the ADC and is

used as a control bit in the JESD204B output word.

Chip Operating Mode Control Registers

Table 48.

Addr. Name

Bit(s) Bit Name

Setting Description

Reset Access

0x0200 Chip mode

[7:6] Reserved

Reserved.

0x0

R/W

5

Chip Q ignore

Chip real (I) only selection.

0

1

Both real (I) and complex (Q) selected.

Only real (I) selected; complex (Q) is ignored.

Reserved.

4

Reserved

0x0

R

[3:0] Chip application mode

R/W

0000

0001

0010

0011

Full bandwidth mode (default).

One DDC mode (DDC0 only).

Two DDC mode (DDC0 and DDC1 only).

Four DDC mode (DDC0, DDC1, DDC2, and DDC3).

Reserved.

0x0201 Chip decimation

ratio

[7:4] Reserved

0x0

R

[3:0] Chip decimation ratio

Chip decimation ratio.

Full sample rate (decimate by 1, DDCs are bypassed).

Decimate by 2.

Decimate by 3.

Decimate by 4.

Decimate by 5.

Decimate by 6.

Decimate by 8.

Decimate by 10.

R/W

0000

0001

1000

0010

0101

1001

0011

0110

1010

0111

0100

1101

1011

1110

1111

1100

Decimate by 12.

Decimate by 15.

Decimate by 16.

Decimate by 20.

Decimate by 24.

Decimate by 30.

Decimate by 40.

Decimate by 48.

Rev. 0 | Page 99 of 138

AD6688

Data Sheet

Fast Detect and Signal Monitor Control Registers

Table 49.

Addr. Name

Bit(s) Bit Name

Setting Description

Reset Access

0x0245 Fast detect control [7:4] Reserved

(local)

Reserved.

0x0

R

3

Force FD_A/FD_B pins

0x0

R/W

0

1

Normal operation of the fast detect pin.

Force a value on the fast detect pin (see Bit 2).

2

Force value of

FD_A/FD_B pins

The fast detect output pin for this channel is set to this value

when the output is forced.

0x0

R/W

1

0

Reserved

Reserved.

0x0

R

Enable fast detect output

R/W

0

1

Fast detect disabled.

Fast detect enabled.

0x0247 Fast detect up LSB [7:0] Fast detect upper

(local) threshold

LSBs of fast detect upper threshold. This register contains the

8 LSBs of the programmable 13-bit upper threshold that is

compared to the fine ADC magnitude.

0x0

R/W

0x0248 Fast detect up MSB [7:5] Reserved

(local)

Reserved.

0x0

R

[4:0] Fast detect upper

LSBs of fast detect upper threshold. This register contains the

8 LSBS of the programmable 13-bit upper threshold that is

compared to the fine ADC magnitude.

R/W

threshold

0x0249 Fast detect low LSB [7:0] Fast detect lower

LSBs of fast detect lower threshold. This register contains the

8 LSBS of the programmable 13-bit lower threshold that is

compared to the fine ADC magnitude.

0x0

R/W

(local)

threshold

0x024A Fast detect low

MSB (local)

[7:5] Reserved

Reserved.

0x0

R

[4:0] Fast detect lower

threshold

LSBs of fast detect lower threshold. This register contains the

8 LSBs of the programmable 13-bit lower threshold that is

compared to the fine ADC magnitude.

R/W

0x024B Fast detect dwell

LSB (local)

[7:0] Fast detect dwell time

[7:2] Reserved

LSBs of fast detect dwell time counter target. This is a load

value for a 16-bit counter that determines how long the ADC

data must remain below the lower threshold before the FD_x

pins are reset to 0.

0x0

R/W

0x024C Fast detect dwell

MSB (local)

LSBs of fast detect dwell time counter target. This is a load

value for a 16-bit counter that determines how long the ADC

data must remain below the lower threshold before the

FD_x pins are reset to 0.

0x026F Signal monitor

sync control

Reserved.

0x0

R

1

Signal monitor next

Signal monitor next synchronization mode.

Continuous mode.

Next synchronization mode. Only the next valid edge of the

SYSREF pin is used to synchronize the signal monitor block.

Subsequent edges of the SYSREF pin are ignored. When the

next SYSREF has been captured, Register 0x026F, Bit 0 is cleared.

The SYSREF pin must an integer multiple of the signal monitor

period for this function to operate correctly in continuous mode.

R/W

synchronization mode

0

1

0

Signal monitor

Signal monitor synchronization enable.

0x0

R/W

synchronization mode

0

1

Synchronization disabled.

If Register 0x026F, Bit 1 = 1, only the next valid edge of the

SYSREF pin is used to synchronize the signal monitor block.

Subsequent edges of the SYSREF pin are ignored. When the

next SYSREF signal is received, this bit is cleared. The SYSREF

input pin must be enabled to synchronize the signal monitor

blocks.

0x0270 Signal monitor

control (local)

[7:2] Reserved

Reserved.

0x0

R

1

Peak detector

R/W

0

1

Peak detector disabled.

Peak detector enabled.

Reserved.

0

Reserved

0x0

R

Rev. 0 | Page 100 of 138

Data Sheet

AD6688

Addr. Name

0x0271 Signal Monitor

Period 0 (local)

Bit(s) Bit Name

[7:0] Signal monitor

period[7:0]

Setting Description

Bits[7:0] of the 24-bit value that sets the number of output

Reset Access

0x80 R/W

clock cycles over which the signal monitor performs its

operation. Only even values are supported.

0x0272 Signal Monitor

Period 1 (local)

[7:0] Signal monitor

period[15:8]

Bits[15:8] of the 24-bit value that sets the number of output

clock cycles over which the signal monitor performs its

operation. Only even values are supported.

0x0

R/W

R

0x0273 Signal Monitor

Period 2 (local)

[7:0] Signal monitor

period[23:16]

Bits[23:16] of the 24-bit value that sets the number of output

clock cycles over which the signal monitor performs its

operation. Only even values are supported.

0x0274 Signal monitor

status control

(local)

[7:5] Reserved

Reserved.

4

Result update

R/WC

1

Update signal monitor status registers, Register 0x0275 to

Register 0x0278. Self clearing.

3

Reserved

Reserved.

0x0

0x1

R

[2:0] Result selection

R/W

001

Peak detector placed on status readback signals.

0x0275 Signal Monitor

Status 0 (local)

[7:0] Signal monitor

result[7:0]

Signal monitor status result. This 20-bit value contains the

status result calculated by the signal monitor block.

0x0

R

0x0276 Signal Monitor

Status 1 (local)

[7:0] Signal monitor

result[15:8]

Signal monitor status result.

0x0277 Signal Monitor

Status 2 (local)

[7:4] Reserved

Reserved.

[3:0] Signal monitor

result[19:16]

Signal monitor status result.

0x0278 Signal monitor

status frame

[7:0] Period count result,

Bits[7:0]

Signal monitor frame counter status bits. Frame counter

increments whenever the period counter expires.

counter (local)

0x0279 Signal monitor

serial framer

[7:2] Reserved

Reserved.

0x0

R

control (local)

[1:0] Signal monitor SPORT

over JESD204B enable

R/W

00

11

Disabled.

Enabled.

Reserved.

0x027A SPORT over

JESD204B input

[7:6] Reserved

0x0

0x1

R

selection (local)

1

SPORT over JESD204B

input selection

Signal monitor serial framer input selection. When each

individual bit is a 1, the corresponding signal statistics

information is sent within the frame.

R/W

0

1

Disabled.

Peak detector data inserted in the serial frame.

Reserved.

0

Reserved

0x0

R

DDC Function Registers (See the Digital Downconverter (DDC) Section)

Table 50.

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0300 DDC SYNC

control

7

DDC FTW/POW/MAW/

MBW update mode

Select DDC FTW/POW/MAW/MBW update mode.

0x0

R/W

0

1

Instantaneous/continuous update. FTW/POW/MAW/MBW values

are updated immediately.

FTW/POW/MAW/MBW values are updated synchronously when

the chip transfer bit (Register 0x000F, Bit 0) is set.

6:5

4

Reserved

Reserved.

0x0

R

DDC NCO soft reset

This bit can be used to synchronize all the NCOs inside the DDC

blocks.

R/W

0

1

Normal operation.

DDC held in reset.

Reserved.

[3:2] Reserved

0x0

R

Rev. 0 | Page 101 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

1 DDC next sync

Setting

Description

Reset

Access

0x0

R/W

0

Continuous mode. The SYSREF frequency must be an integer

multiple of the NCO frequency for this function to operate

correctly in continuous mode.

1

Only the next valid edge of the SYSREF pin is used to

synchronize the NCO in the DDC block. Subsequent edges of the

SYSREF pin are ignored. When the next SYSREF signal is found,

the DDC synchronization enable bit (Register 0x0300, Bit 0) is

cleared.

0

DDC synchronization

mode

The SYSREF input pin must be enabled to synchronize the DDCs. 0x0

R/W

0

1

Synchronization disabled.

If Register 0x0300, Bit 1 = 1, only the next valid edge of the

SYSREF pin is used to synchronize the NCO in the DDC block.

Subsequent edges of the SYSREF pin are ignored. When the next

SYSREF signal is received, this bit is cleared.

0x0310 DDC0 control

7

6

DDC0 mixer select

DDC0 gain select

0x0

R/W

0

1

Real mixer (I and Q inputs must be from the same real channel).

Complex mixer (I and Q must be from separate, real and

imaginary quadrature ADC receive channels; analog

demodulator).

Gain can be used to compensate for the 6 dB loss associated with 0x0

mixing an input signal down to baseband and filtering out its

negative component.

0

1

0 dB gain.

6 dB gain (multiply by 2).

[5:4] DDC0 intermediate

frequency (IF) mode

0x0

00

01

10

11

Variable IF mode.

0 Hz IF mode.

f_SHz IF mode.

Test mode.

0x0

3

DDC0 complex to real

enable

R/W

0

1

Complex (I and Q) outputs contain valid data.

Real (I) output only. complex to real enabled. Uses extra f_Smixing

to convert to real.

[2:0] DDC0 decimation rate

select

Decimation filter selection.

0x0

000

001

010

011

100

101

110

111

HB1 + HB2 filter selection: decimate by 2 (complex to real

enabled), or decimate by 4 (complex to real disabled).

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex

to real enabled), or decimate by 16 (complex to real disabled).

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

HB1 + TB2 filter selection: decimate by 3 (complex to real

enabled), or decimate by 6 (complex to real disabled).

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex

to real enabled), or decimate by 24 (complex to real disabled).

Decimation determined by Register 0x0311, Bits[7:4].

Rev. 0 | Page 102 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0311 DDC0 input

select

[7:4] DDC0 decimation rate

select

Only valid when Register 0x0310, Bits[2:0] = 3'b111.

0x0

R/W

0

TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real

enabled).

10

FB2 + HB1 filter selection: decimate by 10 (complex to real

disabled), or decimate by 5 (complex to real enabled).

11

FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled).

100

111

1000

1001

FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex

to real disabled), or decimate by 20 (complex to real enabled).

TB1 filter selection: decimate by 3 (decimate by 1.5 not

supported).

FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not

supported).

HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by 15

not supported).

3

2

Reserved

Reserved.

0x0

R

DDC0 Q input select

R/W

0

1

Channel A.

Channel B.

Reserved.

1

0

Reserved

0x0

R

DDC0 I input select

R/W

0

1

Channel A.

Channel B.

0x0314 DDC0 NCO

control

[7:4] DDC0 NCO channel

select mode

For edge control, the internal counter wraps after the

Register 0x0314, Bits[3:0] value is reached.

0x0

R/W

0

Use Register 0x0314, Bits[3:0].

1

2'b0, GPIO B0, GPIO A0.

10

2'b0, GPIO B1, GPIO A1.

11

2'b00, GPIO A1, GPIO A0.

100

101

110

1000

1001

1010

1011

2'b00, GPIO B1, GPIO B0.

GPIO B1, GPIO A1, GPIO B0, GPIO A0.

GPIO B1, GPIO B0, GPIO A1, GPIO A0.

Increment internal counter on rising edge of the GPIO_A0 pin.

Increment internal counter on rising edge of the GPIO_A1 pin.

Increment internal counter on rising edge of the GPIO_B0 pin.

Increment internal counter on rising edge of the GPIO_B1 pin.

NCO channel select register map control.

[3:0] DDC0 NCO register

map channel select

0x0

R/W

0

1

10

11

Select NCO Channel 0.

Select NCO Channel 1.

Select NCO Channel 2.

Select NCO Channel 3.

Select NCO Channel 4.

Select NCO Channel 5.

Select NCO Channel 6.

Select NCO Channel 7.

Select NCO Channel 8.

Select NCO Channel 9.

Select NCO Channel 10.

Select NCO Channel 11.

Select NCO Channel 12.

Select NCO Channel 13.

Select NCO Channel 14.

Select NCO Channel 15.

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

Rev. 0 | Page 103 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0315 DDC0 phase

control

[7:4] Reserved

Reserved.

0x0

R

[3:0] DDC0 phase update

index

Indexes the NCO channel whose phase and offset is updated. The 0x0

update method is based on the DDC phase update mode, which

can be continuous or require chip transfer.

R/W

0000

0001

0010

0011

Update NCO Channel 0.

Update NCO Channel 1.

Update NCO Channel 2.

Update NCO Channel 3.

0x0316 DDC0 Phase

Increment 0

[7:0] DDC0 phase

increment[7:0]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0

R/W

R

.

0x0317 DDC0 Phase

Increment 1

[7:0] DDC0 phase

increment[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0318 DDC0 Phase

Increment 2

[7:0] DDC0 phase

increment[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0319 DDC0 Phase

Increment 3

[7:0] DDC0 phase

increment[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x031A DDC0 Phase

Increment 4

[7:0] DDC0 phase

increment[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x031B DDC0 Phase

Increment 5

[7:0] DDC0 phase

increment[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x031D DDC0 Phase

Offset 0

[7:0] DDC0 phase

offset[7:0]

Twos complement phase offset value for the NCO.

Reserved.

0x031E DDC0 Phase

Offset 1

[7:0] DDC0 phase

offset[15:8]

0x031F DDC0 Phase

Offset 2

[7:0] DDC0 phase

offset[23:16]

0x0320 DDC0 Phase

Offset 3

[7:0] DDC0 phase

offset[31:24]

0x0321 DDC0 Phase

Offset 4

[7:0] DDC0 phase

offset[39:32]

0x0322 DDC0 Phase

Offset 5

[7:0] DDC0 phase

offset[47:40]

0x0327 DDC0 test

enable

[7:3] Reserved

2

DDC0 Q output test

mode enable

Q samples always use Test Mode B block. The test mode is

selected using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

Reserved.

1

0

Reserved

0x0

R

DDC0 I output test

mode enable

I samples always use Test Mode A block.. The test mode is

selected using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

0x0330 DDC1 control

7

6

DDC1 mixer select

DDC1 gain select

0x0

R/W

0

1

Real mixer (I and Q inputs must be from the same real channel).

Complex mixer (I and Q must be from separate, real and

imaginary quadrature ADC receive channels; analog

demodulator).

Gain can be used to compensate for the 6 dB loss associated with 0x0

mixing an input signal down to baseband and filtering out its

negative component.

0

1

0 dB gain.

6 dB gain (multiply by 2).

[5:4] DDC1 IF mode

0x0

00

01

10

11

Variable IF mode.

0 Hz IF mode.

f_SHz IF mode.

Test mode.

Rev. 0 | Page 104 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

DDC1 complex to real

enable

Setting

Description

Reset

Access

3

0x0

R/W

0

1

Complex (I and Q) outputs contain valid data.

Real (I) output only. Complex to real enabled. Uses extra f_Smixing

to convert to real.

[2:0] DDC1 decimation rate

select

Decimation filter selection.

0x0

R/W

000

001

010

011

100

101

110

111

HB1 + HB2 filter selection: decimate by 2 (complex to real

enabled), or decimate by 4 (complex to real disabled).

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex

to real enabled), or decimate by 16 (complex to real disabled).

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

HB1 + TB2 filter selection: decimate by 3 (complex to real

enabled), or decimate by 6 (complex to real disabled).

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex

to real enabled), or decimate by 24 (complex to real disabled).

Decimation determined by Register 0x0331, Bits[7:4].

Only valid when Register 0x0310, Bits[2:0] = 3'b111.

0x0331 DDC1 input

select

[7:4] DDC1 decimation rate

select

0x0

R/W

0

TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real

enabled).

10

FB2 + HB1 filter selection: decimate by 10 (complex to real

disabled), or decimate by 5 (complex to real enabled).

11

FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled).

100

111

1000

1001

FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex

to real disabled), or decimate by 20 (complex to real enabled).

TB1 filter selection: decimate by 3 (decimate by 1.5 not

supported).

FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not

supported).

HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by 15

not supported).

3

2

Reserved

Reserved.

0x0

0x1

R

DDC1 Q input select

R/W

0

1

Channel A.

Channel B.

Reserved.

1

0

Reserved

0x0

0x1

R

DDC1 I input select

R/W

0

1

Channel A.

Channel B.

0x0334 DDC1 NCO

control

[7:4] DDC1 NCO channel

select mode

For edge control, the internal counter wraps when the

Register 0x0334, Bits[3:0] value is reached.

0x0

R/W

0

Use Register 0x0314, Bits[3:0].

1

2'b0, GPIO B0, GPIO A0.

10

2'b0, GPIO B1, GPIO A1.

11

2'b00, GPIO A1, GPIO A0.

100

101

110

1000

1001

1010

1011

2'b00, GPIO B1, GPIO B0.

GPIO B1, GPIO A1, GPIO B0, GPIO A0.

GPIO B1, GPIO B0, GPIO A1, GPIO A0.

Increment internal counter when rising edge of the GPIO_A0 pin.

Increment internal counter when rising edge of the GPIO_A1 pin.

Increment internal counter when rising edge of the GPIO_B0 pin.

Increment internal counter when rising edge of the GPIO_B1 pin.

Rev. 0 | Page 105 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

[3:0] DDC1 NCO register

map channel select

NCO channel select register map control.

0x0

R/W

0

1

10

11

Select NCO Channel 0.

Select NCO Channel 1.

Select NCO Channel 2.

Select NCO Channel 3.

Select NCO Channel 4.

Select NCO Channel 5.

Select NCO Channel 6.

Select NCO Channel 7.

Select NCO Channel 8.

Select NCO Channel 9.

Select NCO Channel 10.

Select NCO Channel 11.

Select NCO Channel 12.

Select NCO Channel 13.

Select NCO Channel 14.

Select NCO Channel 15.

Reserved.

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

0x0335 DDC1 phase

control

[7:4] Reserved

0x0

R

[3:0] DDC1 phase update

index

Indexes the NCO channel whose phase and offset gets updated.

The update method is based on the DDC phase update mode,

which can be continuous or require chip transfer.

R/W

0000

0001

0010

0011

Update NCO Channel 0.

Update NCO Channel 1.

Update NCO Channel 2.

Update NCO Channel 3.

0x0336 DDC1 Phase

Increment 0

[7:0] DDC1 phase

increment[7:0]

FTW. Twos complement phase increment value for the NCO.

0x0

R/W

R

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

.

0x0337 DDC1 Phase

Increment 1

[7:0] DDC1 phase

increment[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0338 DDC1 Phase

Increment 2

[7:0] DDC1 phase

increment[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0339 DDC1 Phase

Increment 3

[7:0] DDC1 phase

increment[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x033A DDC1 Phase

Increment 4

[7:0] DDC1 phase

increment[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x033B DDC1 Phase

Increment 5

[7:0] DDC1 phase

increment[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x033D DDC1 Phase

Offset 0

[7:0] DDC1 phase

offset[7:0]

Twos complement phase offset value for the NCO.

Reserved.

0x033E DDC1 Phase

Offset 1

[7:0] DDC1 phase

offset[15:8]

0x033F DDC1 Phase

Offset 2

[7:0] DDC1 phase

offset[23:16]

0x0340 DDC1 Phase

Offset 3

[7:0] DDC1 phase

offset[31:24]

0x0341 DDC1 Phase

Offset 4

[7:0] DDC1 phase

offset[39:32]

0x0342 DDC1 Phase

Offset 5

[7:0] DDC1 phase

offset[47:40]

0x0347 DDC1 test

enable

[7:3] Reserved

2

DDC1 Q output test

mode enable

Q samples always use Test Mode B block. The test mode is

selected using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

Reserved.

1

0

Reserved

0x0

R

DDC1 I output test

mode enable

I samples always use Test Mode A block. The test mode is selected 0x0

using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

Rev. 0 | Page 106 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0350 DDC2 control

7

DDC2 mixer select

0x0

R/W

0

1

Real mixer (I and Q inputs must be from the same real channel).

Complex mixer (I and Q must be from separate, real and

imaginary quadrature ADC receive channels; analog

demodulator).

6

DDC2 gain select

Gain can be used to compensates for the 6 dB loss associated

with mixing an input signal down to baseband and filtering out

its negative component.

R/W

0

1

0 dB gain.

6 dB gain (multiply by 2).

[5:4] DDC2 IF mode

00

01

10

11

Variable IF mode.

0 Hz IF mode.

f_SHz IF mode.

Test mode.

3

DDC2 complex to real

enable

0x0

R/W

0

1

Complex (I and Q) outputs contain valid data.

Real (I) output only. Complex to real enabled. Uses extra f_Smixing

to convert to real.

[2:0] DDC2 decimation rate

select

Decimation filter selection.

000

001

010

011

100

101

110

111

HB1 + HB2 filter selection: decimate by 2 (complex to real

enabled), or decimate by 4 (complex to real disabled).

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex

to real enabled), or decimate by 16 (complex to real disabled).

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

HB1 + TB2 filter selection: decimate by 3 (complex to real

enabled), or decimate by 6 (complex to real disabled).

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex

to real enabled), or decimate by 24 (complex to real disabled).

Decimation determined by Register 0x0351, Bits[7:4].

Only valid when Register 0x0310, Bits[2:0] = 3'b111

0x0351 DDC2 input

select

[7:4] DDC2 decimation rate

select

0x0

R/W

0

TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real

enabled)

10

FB2 + HB1 filter selection: decimate by 10 (complex to real

disabled), or decimate by 5 (complex to real enabled)

11

FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled)

100

FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex

to real disabled), or decimate by 20 (complex to real enabled)

3

2

Reserved

Reserved.

0x0

R

DDC2 Q input select

R/W

0

1

Channel A.

Channel B.

Reserved.

1

0

Reserved

0x0

R

DDC2 I input select

R/W

0

1

Channel A.

Channel B.

Rev. 0 | Page 107 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0354 DDC2 NCO

control

[7:4] DDC2 NCO channel

select mode

For edge control, the internal counter wraps when the

Register 0x0354, Bits[3:0] value is reached.

0x0

R/W

0

Use Register 0x0314, Bits[3:0].

1

2'b0, GPIO B0, GPIO A0.

10

2'b0, GPIO B1, GPIO A1.

11

2'b00, GPIO A1, GPIO A0.

100

101

110

1000

1001

1010

1011

2'b00, GPIO B1, GPIO B0.

GPIO B1, GPIO A1, GPIO B0, GPIO A0.

GPIO B1, GPIO B0, GPIO A1, GPIO A0.

Increment internal counter when rising edge of the GPIO_A0 pin.

Increment internal counter when rising edge of the GPIO_A1 pin.

Increment internal counter when rising edge of the GPIO_B0 pin.

Increment internal counter when rising edge of the GPIO_B1 pin.

NCO channel select register map control.

[3:0] DDC2 NCO register

map channel select

0x0

R/W

0

1

10

11

Select NCO Channel 0.

Select NCO Channel 1.

Select NCO Channel 2.

Select NCO Channel 3.

Select NCO Channel 4.

Select NCO Channel 5.

Select NCO Channel 6.

Select NCO Channel 7.

Select NCO Channel 8.

Select NCO Channel 9.

Select NCO Channel 10.

Select NCO Channel 11.

Select NCO Channel 12.

Select NCO Channel 13.

Select NCO Channel 14.

Select NCO Channel 15.

Reserved.

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

0x0355 DDC2 phase

control

[7:4] Reserved

0x0

R

[3:0] DDC2 phase update

index

Indexes the NCO channel whose phase and offset gets updated.

The update method is based on the DDC phase update mode,

which can be continuous or require chip transfer.

R/W

0000

0001

0010

0011

Update NCO Channel 0.

Update NCO Channel 1.

Update NCO Channel 2.

Update NCO Channel 3.

0x0356 DDC2 Phase

Increment 0

[7:0] DDC2 phase

increment[7:0]

FTW. Twos complement phase increment value for the NCO.

0x0

R/W

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

.

0x0357 DDC2 Phase

Increment 1

[7:0] DDC2 phase

increment[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0358 DDC2 Phase

Increment 2

[7:0] DDC2 phase

increment[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0359 DDC2 Phase

Increment 3

[7:0] DDC2 phase

increment[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x035A DDC2 Phase

Increment 4

[7:0] DDC2 phase

increment[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x035B DDC2 Phase

Increment 5

[7:0] DDC2 phase

increment[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x035D DDC2 Phase

Offset 0

[7:0] DDC2 phase

offset[7:0]

Twos complement phase offset value for the NCO.

0x035E DDC2 Phase

Offset 1

[7:0] DDC2 phase

offset[15:8]

0x035F DDC2 Phase

Offset 2

[7:0] DDC2 phase

offset[23:16]

0x0360 DDC2 Phase

Offset 3

[7:0] DDC2 phase

offset[31:24]

0x0361 DDC2 Phase

Offset 4

[7:0] DDC2 phase

offset[39:32]

Twos complement phase offset value for the NCO.

Rev. 0 | Page 108 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0362 DDC2 Phase

Offset 5

[7:0] DDC2 phase

offset[47:40]

Twos complement phase offset value for the NCO.

0x0

R/W

0x0367 DDC2 test

enable

[7:3] Reserved

Reserved.

R

2

DDC2 Q output test

Q samples always use Test Mode B block. The test mode is

R/W

mode enable

selected using the channel dependent Register 0x0550, Bits[3:0].

0

1

Test mode disabled.

Test mode enabled.

Reserved.

1

0

Reserved

0x0

R

DDC2 I output test

mode enable

I samples always use Test Mode A block. The test mode is selected 0x0

using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

0x0370 DDC3 control

7

6

DDC3 mixer select

DDC3 gain select

0x0

R/W

0

1

Real mixer (I and Q inputs must be from the same real channel).

Complex mixer (I and Q must be from separate, real and

imaginary quadrature ADC receive channels; analog

demodulator).

Gain can be used to compensate for the 6 dB loss associated with 0x0

mixing an input signal down to baseband and filtering out its

negative component.

0

1

0 dB gain.

6 dB gain (multiply by 2).

[5:4] DDC3 IF mode

0x0

00

01

10

11

Variable If mode.

0 Hz IF mode.

f_SHz IF mode.

Test mode.

0x0

3

DDC3 complex to real

enable

R/W

0

1

Complex (I and Q) outputs contain valid data.

Real (I) output only. complex to real enabled. Uses extra f_Smixing

to convert to real.

[2:0] DDC3 decimation rate

select

Decimation filter selection.

0x0

000

001

010

011

100

101

110

111

HB1 + HB2 filter selection: decimate by 2 (complex to real

enabled), or decimate by 4 (complex to real disabled).

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex

to real enabled), or decimate by 16 (complex to real disabled).

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

HB1 + TB2 filter selection: decimate by 3 (complex to real

enabled), or decimate by 6 (complex to real disabled).

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex

to real enabled), or decimate by 24 (complex to real disabled).

Decimation determined by Register 0x0371, Bits[7:4].

Only valid when Register 0x0310, Bits[2:0] = 3'b111.

0x0371 DDC3 input

select

[7:4] DDC3 decimation rate

select

0x0

R/W

0

TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real

enabled).

10

FB2 + HB1 filter selection: decimate by 10 (complex to real

disabled), or decimate by 5 (complex to real enabled).

11

FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled).

100

FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex

to real disabled), or decimate by 20 (complex to real enabled).

3

Reserved

Reserved.

0x0

R

Rev. 0 | Page 109 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

2

DDC3 Q input select

0x1

R/W

0

1

Channel A.

Channel B.

Reserved.

1

0

Reserved

0x0

0x1

R

DDC3 I input select

R/W

0

1

Channel A.

Channel B.

0x0374 DDC3 NCO

control

[7:4] DDC3 NCO channel

select mode

For edge control, the internal counter wraps when the

Register 0x0374, Bits[3:0] value is reached.

0x0

R/W

0

Use Register 0x0314, Bits[3:0].

1

2'b0, GPIO B0, GPIO A0.

10

2'b0, GPIO B1, GPIO A1.

11

2'b00, GPIO A1, GPIO A0.

100

101

110

1000

1001

1010

1011

2'b00, GPIO B1, GPIO B0.

GPIO B1, GPIO A1, GPIO B0, GPIO A0.

GPIO B1, GPIO B0, GPIO A1, GPIO A0.

Increment internal counter when rising edge of GPIO_A0 pin.

Increment internal counter when rising edge of GPIO_A1 pin.

Increment internal counter when rising edge of GPIO_B0 pin.

Increment internal counter when rising edge of GPIO_B1 pin.

NCO channel select register map control.

[3:0] DDC3 NCO register

map channel select

0x0

R/W

0

1

10

11

Select NCO Channel 0.

Select NCO Channel 1.

Select NCO Channel 2.

Select NCO Channel 3.

Select NCO Channel 4.

Select NCO Channel 5.

Select NCO Channel 6.

Select NCO Channel 7.

Select NCO Channel 8.

Select NCO Channel 9.

Select NCO Channel 10.

Select NCO Channel 11.

Select NCO Channel 12.

Select NCO Channel 13.

Select NCO Channel 14.

Select NCO Channel 15.

Reserved.

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

0x0375 DDC3 phase

control

[7:4] Reserved

0x0

R

[3:0] DDC3 phase update

index

Indexes the NCO channel whose phase and offset gets updated.

The update method is based on the DDC phase update mode,

which can be continuous or require chip transfer.

R/W

0000

0001

0010

0011

Update NCO Channel 0.

Update NCO Channel 1.

Update NCO Channel 2.

Update NCO Channel 3.

0x0376 DDC3 Phase

Increment 0

[7:0] DDC3 phase

increment[7:0]

FTW. Twos complement phase increment value for the NCO.

0x0

R/W

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

.

0x0377 DDC3 Phase

Increment 1

[7:0] DDC3 phase

increment[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0378 DDC3 Phase

Increment 2

[7:0] DDC3 phase

increment[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

.

0x0379 DDC3 Phase

Increment 3

[7:0] DDC3 phase

increment[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x037A DDC3 Phase

Increment 4

[7:0] DDC3 phase

increment[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x037B DDC3 Phase

Increment 5

[7:0] DDC3 phase

increment[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x037D DDC3 Phase

Offset 0

[7:0] DDC3 phase

offset[7:0]

Twos complement phase offset value for the NCO.

Rev. 0 | Page 110 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x037E DDC3 Phase

Offset 1

[7:0] DDC3 phase

offset[15:8]

Twos complement phase offset value for the NCO.

0x0

R/W

0x037F DDC3 Phase

Offset 2

[7:0] DDC3 phase

offset[23:16]

Twos complement phase offset value for the NCO.

Reserved.

R/W

R

0x0380 DDC3 Phase

Offset 3

[7:0] DDC3 phase

offset[31:24]

0x0381 DDC3 Phase

Offset 4

[7:0] DDC3 phase

offset[39:32]

0x0382 DDC3 Phase

Offset 5

[7:0] DDC3 phase

offset[47:40]

0x0387 DDC3 test

enable

[7:3] Reserved

2

DDC3 Q output test

Q samples always use Test Mode B block. The test mode is

R/W

mode enable

selected using the channel dependent Register 0x0550, Bits[3:0].

0

1

Test mode disabled.

Test mode enabled.

Reserved.

1

0

Reserved

0x0

R

DDC3 I output test

mode enable

I samples always use Test Mode A block. The test mode is selected 0x0

using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

0x0390 DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment Frac A[7:0]

Numerator correction term for Modulus Phase Accumulator A.

0x0

R/W

Frac A0

0x0391 DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment

Frac A1

Frac A[15:8]

0x0392 DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment

Frac A2

Frac A[23:16]

0x0393 DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment

Frac A3

Frac A[31:24]

0x0394 DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment

Frac A4

Frac A[39:32]

0x0395 DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment

Frac A5

Frac A[47:40]

0x0398 DDC0 Phase

Increment

[7:0] DDC0 Phase

Denominator correction term for Modulus Phase Accumulator B. 0x0

Increment Frac B[7:0]

Frac B0

0x0399 DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment Frac B[15:8]

Frac B1

0x039A DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment

Frac B2

Frac B[23:16]

0x039B DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment

Frac B3

Frac B[31:24]

0x039C DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment

Frac B4

Frac B[39:32]

0x039D DDC0 Phase

Increment

[7:0] DDC0 Phase

Increment

Frac B5

Frac B[47:40]

0x03A0 DDC1 Phase

Increment

[7:0] DDC1 Phase

Numerator correction term for Modulus Phase Accumulator A.

0x0

Increment Frac A[7:0]

Frac A0

0x03A1 DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment

Frac A1

Frac A[15:8]

Rev. 0 | Page 111 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x03A2 DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment

Numerator correction term for Modulus Phase Accumulator A.

0x0

R/W

Frac A2

Frac A[23:16]

0x03A3 DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment

Numerator correction term for Modulus Phase Accumulator A.

0x0

R/W

Frac A3

Frac A[31:24]

0x03A4 DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment

Frac A4

Frac A[39:32]

0x03A5 DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment

Frac A5

Frac A[47:40]

0x03A8 DDC1 Phase

Increment

[7:0] DDC1 Phase

Denominator correction term for Modulus Phase Accumulator B. 0x0

Increment Frac B[7:0]

Frac B0

0x03A9 DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment Frac B[15:8]

Frac B1

0x03AA DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment

Frac B2

Frac B[23:16]

0x03AB DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment

Frac B3

Frac B[31:24]

0x03AC DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment

Frac B4

Frac B[39:32]

0x03AD DDC1 Phase

Increment

[7:0] DDC1 Phase

Increment

Frac B5

Frac B[47:40]

0x03B0 DDC2 Phase

Increment

[7:0] DDC2 Phase

Numerator correction term for Modulus Phase Accumulator A.

0x0

Increment Frac A[7:0]

Frac A0

0x03B1 DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment

Frac A1

Frac A[15:8]

0x03B2 DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment

Frac A2

Frac A[23:16]

0x03B3 DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment

Frac A3

Frac A[31:24]

0x03B4 DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment

Frac A4

Frac A[39:32]

0x03B5 DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment

Frac A5

Frac A[47:40]

0x03B8 DDC2 Phase

Increment

[7:0] DDC2 Phase

Denominator correction term for Modulus Phase Accumulator B. 0x0

Increment Frac B[7:0]

Frac B0

0x03B9 DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment Frac B[15:8]

Frac B1

0x03BA DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment

Frac B2

Frac B[23:16]

0x03BB DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment

Frac B3

Frac B[31:24]

0x03BC DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment

Frac B4

Frac B[39:32]

0x03BD DDC2 Phase

Increment

[7:0] DDC2 Phase

Increment

Frac B5

Frac B[47:40]

Rev. 0 | Page 112 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x03C0 DDC3 Phase

Increment

[7:0] DDC3 Phase

Numerator correction term for Modulus Phase Accumulator A.

0x0

R/W

Increment Frac A[7:0]

Frac A0

0x03C1 DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment

Numerator correction term for Modulus Phase Accumulator A.

R/W

Frac A1

Frac A[15:8]

0x03C2 DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment

Frac A2

Frac A[23:16]

0x03C3 DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment

Frac A3

Frac A[31:24]

0x03C4 DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment

Frac A4

Frac A[39:32]

0x03C5 DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment

Frac A5

Frac A[47:40]

0x03C8 DDC3 Phase

Increment

[7:0] DDC3 Phase

Denominator correction term for Modulus Phase Accumulator B. 0x0

Increment Frac B[7:0]

Frac B0

0x03C9 DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment Frac B[15:8]

Frac B1

0x03CA DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment

Frac B2

Frac B[23:16]

0x03CB DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment

Frac B3

Frac B[31:24]

0x03CC DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment

Frac B4

Frac B[39:32]

0x03CD DDC3 Phase

Increment

[7:0] DDC3 Phase

Increment

Frac B5

Frac B[47:40]

Digital Outputs and Test Modes

Table 51.

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0550 ADC test

7

User pattern selection

Test mode user pattern selection. This bit is only used when

Register 0x0550, Bits[3:0] = 4’b1000 (user input mode). Otherwise,

it is ignored. User Pattern 1 is found in the USR_PAT_1_MSB

(0x0552) and USR_PAT_1_LSB (0x0551) registers. User Pattern 2 is

found in the USR_PAT_2_MSB (0x0554) and USR_PAT_2_LSB

(0x0553) registers, and so on.

0x0

R/W

mode control

(local)

0

1

Continuous/repeat pattern. Place each user pattern (1, 2, 3, and 4)

on the output for 1 clock cycle and then repeat. (Output User

Pattern 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, and so on.)

Single pattern. Place each user pattern (1, 2, 3, and 4) on the

output for 1 clock cycle and then output all zeros. (Output User

Pattern 1, 2, 3, 4, and then output all zeros.)

6

5

Reserved

Reset PN long

generator

Reserved.

0x0

R

R/W

Test mode long pseudorandom number test generator reset.

0

1

Long PN enabled.

Long PN held in reset.

4

Reset PN short

generator

Test mode short pseudorandom number test generator reset.

0x0

R/W

0

1

Short PN enabled.

Short PN held in reset.

Rev. 0 | Page 113 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

[3:0] Test mode selection

Test mode generation selection.

Off (normal operation).

Midscale short.

0x0

R/W

0000

0001

0010

0011

0100

0101

0110

0111

1000

Positive full scale.

Negative full scale.

Alternating checker board.

PN sequence (long).

PN sequence (short).

1/0 word toggle.

User pattern test mode (used with Register 0x0550, Bit 7 and the

User Pattern 1, User Pattern 2, User Pattern 3, and User Pattern 4

registers).

1111

Ramp output.

0x0551 User Pattern 1 [7:0] User Pattern 1[7:0]

LSB

0x0552 User Pattern 1 [7:0] User Pattern 1[15:8]

MSB

0x0553 User Pattern 2 [7:0] User Pattern 2[7:0]

LSB

0x0554 User Pattern 2 [7:0] User Pattern 2[15:8]

MSB

0x0555 User Pattern 3 [7:0] User Pattern 3[7:0]

LSB

0x0556 User Pattern 3 [7:0] User Pattern 3[15:8]

MSB

0x0557 User Pattern 4 [7:0] User Pattern 4[7:0]

LSB

0x0558 User Pattern 4 [7:0] User Pattern 4[15:8]

MSB

User Test Pattern 1 least significant byte.

0x0

R/W

User Test Pattern 1 least significant byte.

User Test Pattern 2 least significant byte.

User Test Pattern 3 least significant bits.

User Test Pattern 4 least significant bits.

0x0559 Output Mode [7:4] Converter control

Control 1

Bit 1 selection

0000

0001

0010

0011

0101

Tie low (1'b0).

Overrange bit.

Signal monitor bit.

Fast detect (FD) bit.

SYSREF.

[3:0] Converter control

Bit 0 selection

0x0

R/W

0000

0001

0010

0011

0101

Tie low (1'b0).

Overrange bit.

Signal monitor bit.

Fast detect (FD) bit.

SYSREF.

0x055A Output Mode [7:4] Reserved

Control 2

Reserved.

0x0

0x1

R

[3:0] Converter control

Bit 2 selection

R/W

0000

0001

0010

0011

0101

Tie low (1'b0).

Overrange bit.

Signal monitor bit.

Fast detect (FD) bit.

SYSREF.

0x0561 Out sample

mode

[7:3] Reserved

Sample invert

Reserved.

0x0

R/W

2

0

1

ADC sample data is not inverted.

ADC sample data is inverted.

[1:0] Data format select

0x1

R/W

00

01

Offset binary.

Twos complement (default)

0x0562 Out overrange [7:0] Data format

clear overrange clear

Overrange clear bits (one bit for each virtual converter). Writing a 1 to 0x0

the overrange clear bit clears the corresponding overrange sticky bit.

0

1

Overrange bit enabled.

Overrange bit cleared.

Rev. 0 | Page 114 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0563 Out overrange [7:0] Data format

Overrange sticky bit status (one bit for each virtual converter).

Writing a 1 to the overrange clear bit clears the corresponding

overrange sticky bit.

0x0

R

status

overrange

0

1

No overrange has occurred.

Overrange has occurred.

Reserved.

0x0564 Out channel

select

[7:1] Reserved

0x0

R

0

Converter channel

swap control

R/W

0

1

Normal channel ordering.

Channel swap enabled.

0x056E PLL control

[7:4] JESD204B lane rate

control

0x3

R/W

0000

0001

0011

0101

Lane rate = 6.75 Gbps to 13.5 Gbps.

Lane rate = 3.375 Gbps to 6.75 Gbps.

Lane rate = 13.5 Gbps to 15.5 Gbps.

Lane rate = 1.6875 Gbps to 3.375 Gbps.

Reserved.

[3:0] Reserved

0x0

R

0x056F PLL status

7

PLL lock status

0

1

Not locked.

Locked.

[6:4] Reserved

Reserved.

0x0

R

3

PLL loss of lock

Loss of lock sticky bit.

1

Indicate a loss of lock has occurred at some time. Cleared by

setting Register 0x0571, Bit 0.

[2:0] Reserved

[7:0]

Reserved.

0x0570 f_S× 4

configuration

See the fS × 4 Mode section.

0xFF

R/W

0xFE

0xFF

f_S× 4 mode enabled. L = 8; M = 2; F = 2; S = 4; N' = 16; N = 16;

CS = 0; CF = 0; HD = 0.

f_S× 4 mode disabled. L, M, and F set by Register 0x058B, Bits[4:0];

Register 0x58E, Bits[7:0]; and Register 0x058C, Bits[7:0], respectively.

0x0571 JESD204B Link

Control 1

7

Standby mode

0x0

R/W

0

1

Standby mode forces zeros for all converter samples.

Standby mode forces code group synchronization (K28.5 characters).

6

5

Tail bit(t) PN

0x0

R/W

0

1

Disable.

Enable.

Long transport layer

test

0

1

JESD204B test samples disabled.

JESD204B test samples enabled; long transport layer test sample

sequence (as specified in JESD204B Section 5.1.6.3) sent on all link

lanes.

4

Lane synchronization

0x1

R/W

0

1

Disable FACI uses /K28.7/.

Enable FACI uses /K28.3/ and /K28.7/.

[3:2] ILAS sequence mode

00

01

11

Initial lane alignment sequence disabled (JESD204B Section

5.3.3.5).

Initial lane alignment sequence enabled (JESD204B Section

5.3.3.5).

Initial lane alignment sequence always on test mode. JESD204B

data link layer test mode where repeated lane alignment

sequence (as specified in JESD204B Section 5.3.3.8.2) sent on all

lanes.

1

FACI

0x0

R/W

0

1

Frame alignment character insertion enabled (JESD204B

Section 5.3.3.4).

Frame alignment character insertion disabled. For debug only

(JESD204B Section 5.3.3.4).

Rev. 0 | Page 115 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Link control

Setting

Description

Reset

Access

0

0x0

R/W

0

JESD204B serial transmit link enabled. Transmission of the /K28.5/

characters for code group synchronization is controlled by the

SYNC~ pin.

1

JESD204B serial transmit link powered down (held in reset and

clock gated).

0x0572 JESD204B Link [7:6] SYNCINB pin control

Control 2

0x0

R/W

00

10

11

Normal mode.

Ignore SYNCINB (force CGS).

Ignore SYNCINB (force ILAS/user data).

5

4

SYNCINB pin invert

SYNCINB pin type

0x0

R/W

0

1

SYNCINB pin not inverted.

SYNCINB pin inverted.

0

1

LVDS differential pair SYNC~ input.

CMOS single-ended SYNC~ input. SYNCINB+ used.

Reserved.

3

2

Reserved

0x0

R

8-bit/10-bit bypass

R/W

0

1

8-bit/10-bit enabled.

8-bit/10-bit bypassed (most significant 2 bits are 0).

1

0

8-bit/10-bit bit invert

Reserved

0x0

R/W

0

1

Normal.

Invert a b c d e f g h i j symbols.

Reserved.

0x0

R/W

0x0573 JESD204B Link [7:6] Checksum mode

Control 3

00

01

Checksum is the sum of all 8-bit registers in the link configuration

table.

Checksum is the sum of all individual link configuration fields (LSB

aligned).

10

11

Checksum is disabled (set to zero). For test purposes only.

Unused.

[5:4] Test injection point

0x0

R/W

0

1

10

N' sample input.

10-bit data at 8-bit/10-bit output (for PHY testing).

8-bit data at scrambler input.

[3:0] JESD204B test mode

patterns

0

1

Normal operation (test mode disabled).

Alternating checkerboard.

1/0 word toggle.

10

11

31-bit PN sequence: x³¹+ x²⁸+ 1.

23-bit PN sequence: x²³+ x¹⁸+ 1.

15-bit PN sequence: x¹⁵+ x¹⁴+ 1.

9-bit PN sequence: x⁹+ x⁵+ 1.

7-bit PN sequence: x⁷+ x⁶+ 1.

Ramp output.

100

101

110

111

1000

1110

1111

Continuous/repeat user test.

Single user test.

Rev. 0 | Page 116 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0574 JESD204B Link [7:4] ILAS delay

Control 4

0x0

R/W

0

1

10

11

Transmit ILAS on first LMFC after SYNCINB deasserted.

Transmit ILAS on second LMFC after SYNCINB deasserted.

Transmit ILAS on third LMFC after SYNCINB deasserted.

Transmit ILAS on fourth LMFC after SYNCINB deasserted.

Transmit ILAS on fifth LMFC after SYNCINB deasserted.

Transmit ILAS on sixth LMFC after SYNCINB deasserted.

Transmit ILAS on seventh LMFC after SYNCINB deasserted.

Transmit ILAS on eighth LMFC after SYNCINB deasserted.

Transmit ILAS on ninth LMFC after SYNCINB deasserted.

Transmit ILAS on tenth LMFC after SYNCINB deasserted.

Transmit ILAS on eleventh LMFC after SYNCINB deasserted.

Transmit ILAS on twelfth LMFC after SYNCINB deasserted.

Transmit ILAS on thirteenth LMFC after SYNCINB deasserted.

Transmit ILAS on fourteenth LMFC after SYNCINB deasserted.

Transmit ILAS on fifteenth LMFC after SYNCINB deasserted.

Transmit ILAS on sixteenth LMFC after SYNCINB deasserted.

Reserved.

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

3

Reserved

0x0

R

R/W

[2:0] Link layer test mode

000

001

010

011

100

101

110

111

Normal operation (link layer test mode disabled).

Continuous sequence of /D21.5/ characters.

Reserved.

Modified RPAT test sequence.

JSPAT test sequence.

JTSPAT test sequence.

Reserved.

0x0578 JESD204B

LMFC offset

[7:5] Reserved

Reserved.

0x0

R

[4:0] LMFC phase offset

value

Local multiframe clock (LMFC) phase offset value (in frame

clocks). Refer to the Deterministic Latency section.

JESD204B serial device identification (DID) number.

R/W

R

0x0580 JESD204B DID [7:0] JESD204B Tx DID

configuration value

0x0581 JESD204B BID [7:4] Reserved

configuration

Reserved.

[3:0] JESD204B Tx BID

JESD204B serial bank identification (BID) number (extension to DID). 0x0

R/W

R

value

0x0583 JESD204B LID0 [7:5] Reserved

configuration

Reserved.

0x0

[4:0] Lane 0 LID value

0x0584 JESD204B LID1 [7:5] Reserved

configuration

JESD204B serial lane identification (LID) number for Lane 0.

Reserved.

0x0

R/W

R

[4:0] Lane 1 LID value

0x0585 JESD204B LID2 [7:5] Reserved

configuration

JESD204B serial LID number for Lane 1.

Reserved.

0x1

0x0

R/W

R

[4:0] Lane 2 LID value

0x0586 JESD204B LID3 [7:5] Reserved

configuration

JESD204B serial LID number for Lane 2.

Reserved.

0x2

0x0

R/W

R

[4:0] Lane 3 LID value

0x0587 JESD204B LID4 [7:5] Reserved

configuration

JESD204B serial LID number for Lane 3.

Reserved.

0x3

0x0

R/W

R

[4:0] Lane 4 LID value

0x0588 JESD204B LID5 [7:5] Reserved

configuration

JESD204B serial LID number for Lane 4.

Reserved.

0x4

0x0

R/W

R

[4:0] Lane 5 LID value

0x0589 JESD204B LID6 [7:5] Reserved

configuration

JESD204B serial LID number for Lane 5.

Reserved.

0x5

0x0

R/W

R

[4:0] Lane 6 LID value

0x058A JESD204B LID7 [7:5] Reserved

configuration

JESD204B serial LID number for Lane 6.

Reserved.

0x6

0x0

R/W

R

[4:0] Lane 7 LID value

JESD204B serial LID number for Lane 7.

Rev. 0 | Page 117 of 138

0x7

R/W

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

JESD204B scrambling

(SCR)

Setting

Description

Reset

Access

0x058B JESD204B

scrambling

7

0x1

R/W

and number

lanes (L)

configuration

0

1

JESD204B scrambler disabled (SCR = 0).

JESD204B scrambler enabled (SCR = 1).

Reserved.

[6:5] Reserved

0x0

0x7

R

[4:0] JESD204B lanes (L)

R/W

0x0

0x1

0x3

0x7

One lane per link (L = 1).

Two lanes per link (L = 2).

Four lanes per link (L = 4).

Eight lanes per Link (L = 8).

0x058C JESD204B link [7:0] JESD204B F

JESD204B number of octets per frame

(F = JESD204B F configuration + 1).

0x0

R/W

number of

octets per

frames (F)

configuration

0

F = 1.

1

F = 2.

10

F = 3.

11

F = 4.

101

111

1111

F = 6.

F = 8.

F = 16.

Reserved.

0x058D JESD204B link [7:5] Reserved

0x0

R

number of

frames per

multiframe (K)

[4:0] JESD204B K

configuration

JESD204B number of frames per multiframe (K = JESD204B K

configuration + 1). Only values where F × K is divisible by 4 can be

used.

0x1F

R/W

0x058E JESD204B link [7:0] JESD204B M

JESD204B number of converters per link/device (M = JESD204B M 0x1

configuration).

number of

configuration

converters (M)

0

1

11

111

Link connected to one virtual converter (M = 1).

Link connected to two virtual converters (M = 2).

Link connected to four virtual converters (M = 4).

Link connected to eight virtual converters (M = 8).

0x0

0x058F JESD204B

[7:6] Number of control

bits (CS) per sample

R/W

number of

control bits

(CS) and ADC

resolution (N)

0

No control bits (CS = 0).

1

10

11

1 control bit (CS = 1), Control Bit 2 only.

2 control bits (CS = 2), Control Bit 2 and Control Bit 1only.

3 control bits (CS = 3), all control bits (Control Bit 2, Control Bit 1,

and Control Bit 0).

5

Reserved

Reserved.

0x0

0xF

R

[4:0] ADC converter

resolution (N)

R/W

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

N = 7-bit resolution.

N = 8-bit resolution.

N = 9-bit resolution.

N = 10-bit resolution.

N = 11-bit resolution.

N = 12-bit resolution.

N = 13-bit resolution.

N = 14-bit resolution.

N = 15-bit resolution.

N = 16-bit resolution.

Rev. 0 | Page 118 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0590 JESD204B

SCV NP

[7:5] Subclass support

0x1

R/W

configuration

000

001

Subclass 0.

Subclass 1.

[4:0] ADC number of bits

per sample(N')

0xF

R/W

0 0111

0 1011

0 1111

N' = 8.

N' = 12

N' = 16.

Reserved.

0x0591 JESD204B JV S [7:5] Reserved

configuration

0x1

0x0

R

[4:0] Samples per converter

Samples per converter frame cycle

(S = Register 0x0591, Bits[4:0] + 1).

frame cycle (S)

0x0592 JESD204B

HD CF

7

HD value

configuration

0

1

High density format disabled.

High density format enabled.

Reserved.

[6:5] Reserved

0x0

R

[4:0] Control words per

frame clock cycle per

link (CF)

Number of control words per frame clock cycle per link

(CF = Register 0x0592, Bits[4:0]).

0x05A0 JESD204B

Checksum 0

[7:0] Checksum 0

checksum value for

SERDOUT0

Serial checksum value for Lane 0. Automatically calculated for

each lane. Sum(all link configuration parameters for Lane 0) mod

256.

0xC3

0xC4

0xC5

0xC6

0x0

R

configuration

0x05A1 JESD204B

Checksum 1

[7:0] Checksum 1

checksum value for

SERDOUT1

Serial checksum value for Lane 1. Automatically calculated for

each lane. Sum(all link configuration parameters for Lane 1) mod

256.

R

configuration

0x05A2 JESD204B

Checksum 2

[7:0] Checksum 2

checksum value for

SERDOUT2

Serial checksum value for Lane 2. Automatically calculated for

each lane. Sum(all link configuration parameters for each lane)

mod 256.

R

configuration

0x05A3 JESD204B

Checksum 3

[7:0] Checksum 3

checksum value for

SERDOUT3

Serial checksum value for Lane 3. Automatically calculated for

each lane. Sum(all link configuration parameters for Lane 3) mod

256.

R

configuration

0x05B0 JESD204B

lane power-

down

7

JESD204B Lane 7

power-down

Physical Lane 7 force power-down.

R/W

0

1

SERDOUT7 normal operation.

SERDOUT7 power-down.

6

5

4

3

2

JESD204B Lane 6

power-down

Physical Lane 6 force power-down.

0x0

R/W

0

1

SERDOUT6 normal operation.

SERDOUT6 power-down.

Physical Lane 5 force power-down.

JESD204B Lane 5

power-down

0

1

SERDOUT5 normal operation.

SERDOUT5 power-down.

Physical Lane 4 force power-down.

JESD204B Lane 4

power-down

0

1

SERDOUT4 normal operation.

SERDOUT4 power-down.

Physical Lane 3 force power-down.

JESD204B Lane 3

power-down

0

1

SERDOUT3 normal operation.

SERDOUT3 power-down.

Physical Lane 2 force power-down.

JESD204B Lane 2

power-down

0

1

SERDOUT2 normal operation.

SERDOUT2 power-down.

Rev. 0 | Page 119 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

1

0

7

JESD204B Lane 1

power-down

Physical Lane 1 force power-down.

0x0

R/W

0

1

SERDOUT1 normal operation.

SERDOUT1 power-down.

Physical Lane 0 force power-down.

JESD204B Lane 0

power-down

0x0

R/W

0

1

SERDOUT0 normal operation.

SERDOUT0 power-down.

Reserved.

0x05B2 JESD204B

Reserved

0x0

0x1

R

Lane Assign 1

[6:4] SERDOUT1 lane

assignment

Physical Lane 1 assignment.

R/W

0

Logical Lane 0.

1

10

Logical Lane 1 (default).

Logical Lane 2.

11

Logical Lane 3.

100

101

110

111

Logical Lane 4.

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

3

Reserved

Reserved.

0x0

R

[2:0] SERDOUT0 lane

assignment

Physical Lane 0 assignment.

R/W

0

1

10

11

100

101

110

111

Logical Lane 0 (default).

Logical Lane 1.

Logical Lane 2.

Logical Lane 3.

Logical Lane 4.

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

Reserved.

0x05B3 JESD204B

Lane Assign 2

7

Reserved

0x0

0x3

R

[6:4] SERDOUT3 lane

assignment

Physical Lane 3 assignment.

R/W

0

Logical Lane 0.

1

Logical Lane 1.

10

Logical Lane 2.

11

Logical Lane 3 (default).

Logical Lane 4.

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

100

101

110

111

3

Reserved

Reserved.

0x0

0x2

R

[2:0] SERDOUT2 lane

assignment

Physical Lane 2 assignment.

R/W

0

1

10

11

100

101

110

111

Logical Lane 0.

Logical Lane 1.

Logical Lane 2 (default).

Logical Lane 3.

Logical Lane 4.

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

Rev. 0 | Page 120 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Reserved

Setting

Description

Reset

Access

0x05B5 JESD204B

Lane Assign 3

7

Reserved.

0x0

R

[6:4] SERDOUT5 lane

assignment

Physical Lane 5 assignment.

0x5

R/W

0

Logical Lane 0.

1

Logical Lane 1.

10

Logical Lane 2.

11

Logical Lane 3.

100

101

110

111

Logical Lane 4.

Logical Lane 5 (default).

Logical Lane 6.

Logical Lane 7.

3

Reserved

Reserved.

0x0

0x4

R

[2:0] SERDOUT4 lane

assignment

Physical Lane 4 assignment.

R/W

0

1

10

11

100

101

110

111

Logical Lane 0.

Logical Lane 1.

Logical Lane 2.

Logical Lane 3.

Logical Lane 4 (default).

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

Reserved.

0x05B6 JESD204B

Lane Assign 4

7

Reserved

0x0

0x7

R

[6:4] SERDOUT7 lane

assignment

Physical Lane 7 assignment.

R/W

0

Logical Lane 0.

1

Logical Lane 1.

10

Logical Lane 2.

11

Logical Lane 3.

100

101

110

111

Logical Lane 4.

Logical Lane 5.

Logical Lane 6.

Logical Lane 7 (default).

Reserved.

3

Reserved

0x0

0x6

R

[2:0] SERDOUT6 lane

assignment

Physical Lane 6 assignment.

R/W

0

Logical Lane 0.

1

Logical Lane 1.

10

Logical Lane 2.

11

Logical Lane 3.

100

101

110

111

Logical Lane 4.

Logical Lane 5.

Logical Lane 6 (default).

Logical Lane 7.

0x05BF SERDOUTx

data invert

7

Invert SERDOUT7 data

Invert SERDOUT7 data.

0x0

R/W

0

1

Normal.

Invert.

6

5

4

Invert SERDOUT6 data

Invert SERDOUT5 data

Invert SERDOUT4 data

Invert SERDOUT6 data.

Normal.

Invert.

0x0

R/W

0

1

Invert SERDOUT5 data.

Normal.

Invert.

0

1

Invert SERDOUT4 data.

Normal.

Invert.

0

1

Rev. 0 | Page 121 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting

Description

Invert SERDOUT3 data.

Normal.

Reset

Access

3

2

1

0

7

Invert SERDOUT3 data

0x0

R/W

0

1

Invert.

Invert SERDOUT2 data

Invert SERDOUT1 data

Invert SERDOUT0 data

Reserved

Invert SERDOUT2 data.

Normal.

Invert.

0x0

R/W

0

1

Invert SERDOUT1 data.

Normal.

Invert.

0

1

Invert SERDOUT0 data.

Normal.

Invert.

0

1

0x05C0 JESD204B

Reserved.

0x0

0x1

R

Swing Adjust 1

[6:4] SERDOUT1 voltage

swing adjust

Output swing level for SERDOUT1 .

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

3

Reserved

Reserved.

0x0

0x1

R

[2:0] SERDOUT0 voltage

swing adjust

Output swing level for SERDOUT0 .

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

0x05C1 JESD204B

Swing Adjust 2

7

Reserved

0x0

0x1

R

[6:4] SERDOUT3 voltage

swing adjust

Output swing level for SERDOUT3 .

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

3

Reserved

Reserved.

0x0

0x1

R

[2:0] SERDOUT2 voltage

swing adjust

Output swing level for SERDOUT2 .

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

0x05C2 JESD204B

Swing Adjust 3

7

Reserved

0x0

0x1

R

[6:4] SERDOUT5 voltage

swing adjust

Output swing level for SERDOUT5 .

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

3

Reserved

Reserved.

0x0

0x1

R

[2:0] SERDOUT4 voltage

swing adjust

Output swing level for SERDOUT4 .

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

0x05C3 JESD204B

Swing Adjust 4

7

Reserved

0x0

0x1

R

[6:4] SERDOUT7 voltage

swing adjust

Output swing level for SERDOUT7 .

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

3

Reserved

0x0

R

Rev. 0 | Page 122 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

[2:0] SERDOUT6 voltage

swing adjust

Output swing level for SERDOUT6 .

0x1

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Post tap enable.

0x05C4 SERDOUT0

pre-emphasis

select

7

Post tap enable

0x0

R/W

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT0

Set post tap level.

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

0x05C5 SERDOUT1

pre-emphasis

select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT1

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

0x05C6 SERDOUT2

pre-emphasis

select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT2

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

0x05C7 SERDOUT3

pre-emphasis

select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT3

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

Reserved.

[3:0] Reserved

Rev. 0 | Page 123 of 138

AD6688

Data Sheet

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x05C8 SERDOUT4

pre-emphasis

select

7

Post tap enable

Post tap enable.

0x0

R/W

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT4

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

0x05C9 SERDOUT5

pre-emphasis

select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT5

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

0x05CA SERDOUT6

pre-emphasis

select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT6

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

0x05CB SERDOUT7

pre-emphasis

select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT7

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

See Table 32.

0x0

R/W

0x1222 JESD204B PLL [7:0]

calibration

0x00

0x04

JESD204B PLL normal operation.

Reset JESD204B PLL calibration.

See Table 32.

0x1228 JESD204B PLL [7:0]

0x0F

R/W

startup

control

0x0F

0x4F

JESD204B startup circuit in normal operation.

Reset JESD204B startup circuit.

Rev. 0 | Page 124 of 138

Data Sheet

AD6688

Addr. Name

Bit(s) Bit Name

Setting

Description

Reset

0x00

Access

0x1262 JESD204B PLL [7:0]

See Table 32.

R/W

LOL bit

control

0x00

0x80

Loss of lock bit normal operation.

Clear loss of lock bit.

Programmable Filter Control and Coefficients Registers

Table 52.

Addr. Name

0x0DF8 PFILT control

Bit(s) Bit Name

[7:3] Reserved

[2:0] PFILT mode

Setting Description

Reset Access

Reserved.

0x0

R

Programmable filter (PFILT) mode.

Disabled (filters bypassed).

Single filter (X only).

R/W

000

001

dout_i[n] = din_i[n] * x_i[n]

dout_q[n] = din_q[n] * x_q[n]

Single filter (X and Y together)

dout_i[n] = din_i[n] * xy_i[n]

dout_q[n] = din_q[n] * xy_q[n]

Cascaded filters (X to Y).

dout_i[n] = din_i[n] * x_i[n] * y_i[n]

dout_q[n] = din_q[n] * x_q[n] * y_q[n]

Complex filters.

dout_i[n] = din_i[n] * x_i[n] + din_q[n] * y_q[n]

dout_q[n] = din_q[n] * x_q[n] + din_i[n] * y_i[n]

Half complex filter.

dout_i[n] = din_i[n]

dout_q[n] = din_q[n] * xy_q[n] + din_i[n] * xy_i[n]

Real 96-tap filter.

010

100

101

110

111

dout_i[n] = din_i[n] * xy_i[n].

dout_q[n] = din_q[n] * xy_q[n]

Reserved.

0x0DF9 PFILT gain

7

Reserved

0x0

R

[6:4] PFILT Y gain

PFILT Y gain.

R/W

110

111

000

001

010

−12 dB loss.

−6 dB loss.

0 dB gain.

+6 dB gain.

+12 dB gain.

3

Reserved

Reserved.

0x0

R

[2:0] PFILT X gain

PFILT X gain.

R/W

110

111

000

001

010

−12 dB loss.

−6 dB loss.

0 dB gain.

+6 dB gain.

+12 dB gain.

0x0E00 PFILT X

Coefficient 0

[7:0] PFILT X Coefficient 0

[7:0] PFILT X Coefficient 1

[7:0] PFILT X Coefficient 2

[7:0] PFILT X Coefficient 3

[7:0] PFILT X Coefficient 4

[7:0] PFILT X Coefficient 5

[7:0] PFILT X Coefficient 6

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0

R/W

0x0E01 PFILT X

Coefficient 1

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E02 PFILT X

Coefficient 2

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E03 PFILT X

Coefficient 3

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E04 PFILT X

Coefficient 4

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E05 PFILT X

Coefficient 5

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E06 PFILT X

Coefficient 6

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Rev. 0 | Page 125 of 138

AD6688

Data Sheet

Addr. Name

0x0E07 PFILT X

Bit(s) Bit Name

Setting Description

Programmable Filter X coefficients. Coefficients are only

Reset Access

[7:0] PFILT X Coefficient 7

0x0

R/W

Coefficient 7

0x0E08 PFILT X

Coefficient 8

0x0E09 PFILT X

Coefficient 9

0x0E0A PFILT X

Coefficient 10

0x0E0B PFILT X

Coefficient 11

0x0E0C PFILT X

Coefficient 12

0x0E0D PFILT X

Coefficient 13

0x0E0E PFILT X

Coefficient 14

0x0E0F PFILT X

Coefficient 15

0x0E10 PFILT X

Coefficient 16

0x0E11 PFILT X

Coefficient 17

0x0E12 PFILT X

Coefficient 18

0x0E13 PFILT X

Coefficient 19

0x0E14 PFILT X

Coefficient 20

0x0E15 PFILT X

Coefficient 21

0x0E16 PFILT X

Coefficient 22

0x0E17 PFILT X

Coefficient 23

0x0E18 PFILT X

Coefficient 24

0x0E19 PFILT X

Coefficient 25

0x0E1A PFILT X

Coefficient 26

0x0E1B PFILT X

Coefficient 27

0x0E1C PFILT X

Coefficient 28

0x0E1D PFILT X

Coefficient 29

0x0E1E PFILT X

Coefficient 30

0x0E1F PFILT X

Coefficient 31

0x0E20 PFILT X

Coefficient 32

0x0E21 PFILT X

Coefficient 33

0x0E22 PFILT X

Coefficient 34

0x0E23 PFILT X

Coefficient 35

0x0E24 PFILT X

Coefficient 36

0x0E25 PFILT X

Coefficient 37

0x0E26 PFILT X

Coefficient 38

applied after the chip transfer bit has been written.

[7:0] PFILT X Coefficient 8

[7:0] PFILT X Coefficient 9

[7:0] PFILT X Coefficient 10

[7:0] PFILT X Coefficient 11

[7:0] PFILT X Coefficient 12

[7:0] PFILT X Coefficient 13

[7:0] PFILT X Coefficient 14

[7:0] PFILT X Coefficient 15

[7:0] PFILT X Coefficient 16

[7:0] PFILT X Coefficient 17

[7:0] PFILT X Coefficient 18

[7:0] PFILT X Coefficient 19

[7:0] PFILT X Coefficient 20

[7:0] PFILT X Coefficient 21

[7:0] PFILT X Coefficient 22

[7:0] PFILT X Coefficient 23

[7:0] PFILT X Coefficient 24

[7:0] PFILT X Coefficient 25

[7:0] PFILT X Coefficient 26

[7:0] PFILT X Coefficient 27

[7:0] PFILT X Coefficient 28

[7:0] PFILT X Coefficient 29

[7:0] PFILT X Coefficient 30

[7:0] PFILT X Coefficient 31

[7:0] PFILT X Coefficient 32

[7:0] PFILT X Coefficient 33

[7:0] PFILT X Coefficient 34

[7:0] PFILT X Coefficient 35

[7:0] PFILT X Coefficient 36

[7:0] PFILT X Coefficient 37

[7:0] PFILT X Coefficient 38

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Rev. 0 | Page 126 of 138

Data Sheet

AD6688

Addr. Name

0x0E27 PFILT X

Coefficient 39

Bit(s) Bit Name

Setting Description

Programmable Filter X coefficients. Coefficients are only

Reset Access

[7:0] PFILT X Coefficient 39

0x0

R/W

applied after the chip transfer bit has been written.

0x0E28 PFILT X

Coefficient 40

[7:0] PFILT X Coefficient 40

[7:0] PFILT X Coefficient 41

[7:0] PFILT X Coefficient 42

[7:0] PFILT X Coefficient 43

[7:0] PFILT X Coefficient 44

[7:0] PFILT X Coefficient 45

[7:0] PFILT X Coefficient 46

[7:0] PFILT X Coefficient 47

[7:0] PFILT X Coefficient 48

[7:0] PFILT X Coefficient 49

[7:0] PFILT X Coefficient 50

[7:0] PFILT X Coefficient 51

[7:0] PFILT X Coefficient 52

[7:0] PFILT X Coefficient 53

[7:0] PFILT X Coefficient 54

[7:0] PFILT X Coefficient 55

[7:0] PFILT X Coefficient 56

[7:0] PFILT X Coefficient 57

[7:0] PFILT X Coefficient 58

[7:0] PFILT X Coefficient 59

[7:0] PFILT X Coefficient 60

[7:0] PFILT X Coefficient 61

[7:0] PFILT X Coefficient 62

[7:0] PFILT X Coefficient 63

[7:0] PFILT X Coefficient 64

[7:0] PFILT X Coefficient 65

[7:0] PFILT X Coefficient 66

[7:0] PFILT X Coefficient 67

[7:0] PFILT X Coefficient 68

[7:0] PFILT X Coefficient 69

[7:0] PFILT X Coefficient 70

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E29 PFILT X

Coefficient 41

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E2A PFILT X

Coefficient 42

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E2B PFILT X

Coefficient 43

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E2C PFILT X

Coefficient 44

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E2D PFILT X

Coefficient 45

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E2E PFILT X

Coefficient 46

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E2F PFILT X

Coefficient 47

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E30 PFILT X

Coefficient 48

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E31 PFILT X

Coefficient 49

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E32 PFILT X

Coefficient 50

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E33 PFILT X

Coefficient 51

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E34 PFILT X

Coefficient 52

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E35 PFILT X

Coefficient 53

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E36 PFILT X

Coefficient 54

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E37 PFILT X

Coefficient 55

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E38 PFILT X

Coefficient 56

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E39 PFILT X

Coefficient 57

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E3A PFILT X

Coefficient 58

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E3B PFILT X

Coefficient 59

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E3C PFILT X

Coefficient 60

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E3D PFILT X

Coefficient 61

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E3E PFILT X

Coefficient 62

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E3F PFILT X

Coefficient 63

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E40 PFILT X

Coefficient 64

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E41 PFILT X

Coefficient 65

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E42 PFILT X

Coefficient 66

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E43 PFILT X

Coefficient 67

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E44 PFILT X

Coefficient 68

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E45 PFILT X

Coefficient 69

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0E46 PFILT X

Coefficient 70

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Rev. 0 | Page 127 of 138

AD6688

Data Sheet

Addr. Name

0x0E47 PFILT X

Bit(s) Bit Name

Setting Description

Programmable Filter X coefficients. Coefficients are only

Reset Access

[7:0] PFILT X Coefficient 71

0x0

R/W

Coefficient 71

0x0E48 PFILT X

Coefficient 72

0x0E49 PFILT X

Coefficient 73

0x0E4A PFILT X

Coefficient 74

0x0E4B PFILT X

Coefficient 75

0x0E4C PFILT X

Coefficient 76

0x0E4D PFILT X

Coefficient 77

0x0E4E PFILT X

Coefficient 78

0x0E4F PFILT X

Coefficient 79

0x0E50 PFILT X

Coefficient 80

0x0E51 PFILT X

Coefficient 81

0x0E52 PFILT X

Coefficient 82

0x0E53 PFILT X

Coefficient 83

0x0E54 PFILT X

Coefficient 84

0x0E55 PFILT X

Coefficient 85

0x0E56 PFILT X

Coefficient 86

0x0E57 PFILT X

Coefficient 87

0x0E58 PFILT X

Coefficient 88

0x0E59 PFILT X

Coefficient 89

0x0E5A PFILT X

Coefficient 90

0x0E5B PFILT X

Coefficient 91

0x0E5C PFILT X

Coefficient 92

0x0E5D PFILT X

Coefficient 93

0x0E5E PFILT X

Coefficient 94

0x0E5F PFILT X

Coefficient 95

0x0E60 PFILT X

Coefficient 96

0x0E61 PFILT X

Coefficient 97

0x0E62 PFILT X

Coefficient 98

0x0E63 PFILT X

Coefficient 99

0x0E64 PFILT X

Coefficient 100

0x0E65 PFILT X

Coefficient 101

0x0E66 PFILT X

Coefficient 102

applied after the chip transfer bit has been written.

[7:0] PFILT X Coefficient 72

[7:0] PFILT X Coefficient 73

[7:0] PFILT X Coefficient 74

[7:0] PFILT X Coefficient 75

[7:0] PFILT X Coefficient 76

[7:0] PFILT X Coefficient 77

[7:0] PFILT X Coefficient 78

[7:0] PFILT X Coefficient 79

[7:0] PFILT X Coefficient 80

[7:0] PFILT X Coefficient 81

[7:0] PFILT X Coefficient 82

[7:0] PFILT X Coefficient 83

[7:0] PFILT X Coefficient 84

[7:0] PFILT X Coefficient 85

[7:0] PFILT X Coefficient 86

[7:0] PFILT X Coefficient 87

[7:0] PFILT X Coefficient 88

[7:0] PFILT X Coefficient 89

[7:0] PFILT X Coefficient 90

[7:0] PFILT X Coefficient 91

[7:0] PFILT X Coefficient 92

[7:0] PFILT X Coefficient 93

[7:0] PFILT X Coefficient 94

[7:0] PFILT X Coefficient 95

[7:0] PFILT X Coefficient 96

[7:0] PFILT X Coefficient 97

[7:0] PFILT X Coefficient 98

[7:0] PFILT X Coefficient 99

[7:0] PFILT X Coefficient 100

[7:0] PFILT X Coefficient 101

[7:0] PFILT X Coefficient 102

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Rev. 0 | Page 128 of 138

Data Sheet

AD6688

Addr. Name

0x0E67 PFILT X

Bit(s) Bit Name

Setting Description

Programmable Filter X coefficients. Coefficients are only

Reset Access

[7:0] PFILT X Coefficient 103

0x0

R/W

Coefficient 103

0x0E68 PFILT X

Coefficient 104

0x0E69 PFILT X

Coefficient 105

0x0E6A PFILT X

Coefficient 106

0x0E6B PFILT X

Coefficient 107

0x0E6C PFILT X

Coefficient 108

0x0E6D PFILT X

Coefficient 109

0x0E6E PFILT X

Coefficient 110

0x0E6F PFILT X

Coefficient 111

0x0E70 PFILT X

Coefficient 112

0x0E71 PFILT X

Coefficient 113

0x0E72 PFILT X

Coefficient 114

0x0E73 PFILT X

Coefficient 115

0x0E74 PFILT X

Coefficient 116

0x0E75 PFILT X

Coefficient 117

0x0E76 PFILT X

Coefficient 118

0x0E77 PFILT X

Coefficient 119

0x0E78 PFILT X

Coefficient 120

0x0E79 PFILT X

Coefficient 121

0x0E7A PFILT X

Coefficient 122

0x0E7B PFILT X

Coefficient 123

0x0E7C PFILT X

Coefficient 124

0x0E7D PFILT X

Coefficient 125

0x0E7E PFILT X

Coefficient 126

0x0E7F PFILT X

Coefficient 127

0x0F00 PFILT Y

Coefficient 0

0x0F01 PFILT Y

Coefficient 1

0x0F02 PFILT Y

Coefficient 2

0x0F03 PFILT Y

Coefficient 3

0x0F04 PFILT Y

Coefficient 4

0x0F05 PFILT Y

Coefficient 5

0x0F06 PFILT Y

Coefficient 6

applied after the chip transfer bit has been written.

[7:0] PFILT X Coefficient 104

[7:0] PFILT X Coefficient 105

[7:0] PFILT X Coefficient 106

[7:0] PFILT X Coefficient 107

[7:0] PFILT X Coefficient 108

[7:0] PFILT X Coefficient 109

[7:0] PFILT X Coefficient 110

[7:0] PFILT X Coefficient 111

[7:0] PFILT X Coefficient 112

[7:0] PFILT X Coefficient 113

[7:0] PFILT X Coefficient 114

[7:0] PFILT X Coefficient 115

[7:0] PFILT X Coefficient 116

[7:0] PFILT X Coefficient 117

[7:0] PFILT X Coefficient 118

[7:0] PFILT X Coefficient 119

[7:0] PFILT X Coefficient 120

[7:0] PFILT X Coefficient 121

[7:0] PFILT X Coefficient 122

[7:0] PFILT X Coefficient 123

[7:0] PFILT X Coefficient 124

[7:0] PFILT X Coefficient 125

[7:0] PFILT X Coefficient 126

[7:0] PFILT X Coefficient 127

[7:0] PFILT Y Coefficient 0

[7:0] PFILT Y Coefficient 1

[7:0] PFILT Y Coefficient 2

[7:0] PFILT Y Coefficient 3

[7:0] PFILT Y Coefficient 4

[7:0] PFILT Y Coefficient 5

[7:0] PFILT Y Coefficient 6

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter X coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Rev. 0 | Page 129 of 138

AD6688

Data Sheet

Addr. Name

0x0F07 PFILT Y

Bit(s) Bit Name

Setting Description

Programmable Filter Y coefficients. Coefficients are only

Reset Access

[7:0] PFILT Y Coefficient 7

0x0

R/W

Coefficient 7

0x0F08 PFILT Y

Coefficient 8

0x0F09 PFILT Y

Coefficient 9

0x0F0A PFILT Y

Coefficient 10

0x0F0B PFILT Y

Coefficient 11

0x0F0C PFILT Y

Coefficient 12

0x0F0D PFILT Y

Coefficient 13

0x0F0E PFILT Y

Coefficient 14

0x0F0F PFILT Y

Coefficient 15

0x0F10 PFILT Y

Coefficient 16

0x0F11 PFILT Y

Coefficient 17

0x0F12 PFILT Y

Coefficient 18

0x0F13 PFILT Y

Coefficient 19

0x0F14 PFILT Y

Coefficient 20

0x0F15 PFILT Y

Coefficient 21

0x0F16 PFILT Y

Coefficient 22

0x0F17 PFILT Y

Coefficient 23

0x0F18 PFILT Y

Coefficient 24

0x0F19 PFILT Y

Coefficient 25

0x0F1A PFILT Y

Coefficient 26

0x0F1B PFILT Y

Coefficient 27

0x0F1C PFILT Y

Coefficient 28

0x0F1D PFILT Y

Coefficient 29

0x0F1E PFILT Y

Coefficient 30

0x0F1F PFILT Y

Coefficient 31

0x0F20 PFILT Y

Coefficient 32

0x0F21 PFILT Y

Coefficient 33

0x0F22 PFILT Y

Coefficient 34

0x0F23 PFILT Y

Coefficient 35

0x0F24 PFILT Y

Coefficient 36

0x0F25 PFILT Y

Coefficient 37

0x0F26 PFILT Y

Coefficient 38

applied after the chip transfer bit has been written.

[7:0] PFILT Y Coefficient 8

[7:0] PFILT Y Coefficient 9

[7:0] PFILT Y Coefficient 10

[7:0] PFILT Y Coefficient 11

[7:0] PFILT Y Coefficient 12

[7:0] PFILT Y Coefficient 13

[7:0] PFILT Y Coefficient 14

[7:0] PFILT Y Coefficient 15

[7:0] PFILT Y Coefficient 16

[7:0] PFILT Y Coefficient 17

[7:0] PFILT Y Coefficient 18

[7:0] PFILT Y Coefficient 19

[7:0] PFILT Y Coefficient 20

[7:0] PFILT Y Coefficient 21

[7:0] PFILT Y Coefficient 22

[7:0] PFILT Y Coefficient 23

[7:0] PFILT Y Coefficient 24

[7:0] PFILT Y Coefficient 25

[7:0] PFILT Y Coefficient 26

[7:0] PFILT Y Coefficient 27

[7:0] PFILT Y Coefficient 28

[7:0] PFILT Y Coefficient 29

[7:0] PFILT Y Coefficient 30

[7:0] PFILT Y Coefficient 31

[7:0] PFILT Y Coefficient 32

[7:0] PFILT Y Coefficient 33

[7:0] PFILT Y Coefficient 34

[7:0] PFILT Y Coefficient 35

[7:0] PFILT Y Coefficient 36

[7:0] PFILT Y Coefficient 37

[7:0] PFILT Y Coefficient 38

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Rev. 0 | Page 130 of 138

Data Sheet

AD6688

Addr. Name

0x0F27 PFILT Y

Coefficient 39

Bit(s) Bit Name

Setting Description

Programmable Filter Y coefficients. Coefficients are only

Reset Access

[7:0] PFILT Y Coefficient 39

0x0

R/W

applied after the chip transfer bit has been written.

0x0F28 PFILT Y

Coefficient 40

[7:0] PFILT Y Coefficient 40

[7:0] PFILT Y Coefficient 41

[7:0] PFILT Y Coefficient 42

[7:0] PFILT Y Coefficient 43

[7:0] PFILT Y Coefficient 44

[7:0] PFILT Y Coefficient 45

[7:0] PFILT Y Coefficient 46

[7:0] PFILT Y Coefficient 47

[7:0] PFILT Y Coefficient 48

[7:0] PFILT Y Coefficient 49

[7:0] PFILT Y Coefficient 50

[7:0] PFILT Y Coefficient 51

[7:0] PFILT Y Coefficient 52

[7:0] PFILT Y Coefficient 53

[7:0] PFILT Y Coefficient 54

[7:0] PFILT Y Coefficient 55

[7:0] PFILT Y Coefficient 56

[7:0] PFILT Y Coefficient 57

[7:0] PFILT Y Coefficient 58

[7:0] PFILT Y Coefficient 59

[7:0] PFILT Y Coefficient 60

[7:0] PFILT Y Coefficient 61

[7:0] PFILT Y Coefficient 62

[7:0] PFILT Y Coefficient 63

[7:0] PFILT Y Coefficient 64

[7:0] PFILT Y Coefficient 65

[7:0] PFILT Y Coefficient 66

[7:0] PFILT Y Coefficient 67

[7:0] PFILT Y Coefficient 68

[7:0] PFILT Y Coefficient 69

[7:0] PFILT Y Coefficient 70

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F29 PFILT Y

Coefficient 41

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F2A PFILT Y

Coefficient 42

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F2B PFILT Y

Coefficient 43

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F2C PFILT Y

Coefficient 44

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F2D PFILT Y

Coefficient 45

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F2E PFILT Y

Coefficient 46

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F2F PFILT Y

Coefficient 47

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F30 PFILT Y

Coefficient 48

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F31 PFILT Y

Coefficient 49

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F32 PFILT Y

Coefficient 50

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F33 PFILT Y

Coefficient 51

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F34 PFILT Y

Coefficient 52

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F35 PFILT Y

Coefficient 53

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F36 PFILT Y

Coefficient 54

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F37 PFILT Y

Coefficient 55

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F38 PFILT Y

Coefficient 56

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F39 PFILT Y

Coefficient 57

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F3A PFILT Y

Coefficient 58

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F3B PFILT Y

Coefficient 59

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F3C PFILT Y

Coefficient 60

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F3D PFILT Y

Coefficient 61

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F3E PFILT Y

Coefficient 62

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F3F PFILT Y

Coefficient 63

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F40 PFILT Y

Coefficient 64

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F41 PFILT Y

Coefficient 65

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F42 PFILT Y

Coefficient 66

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F43 PFILT Y

Coefficient 67

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F44 PFILT Y

Coefficient 68

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F45 PFILT Y

Coefficient 69

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

0x0F46 PFILT Y

Coefficient 70

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Rev. 0 | Page 131 of 138

AD6688

Data Sheet

Addr. Name

0x0F47 PFILT Y

Bit(s) Bit Name

Setting Description

Programmable Filter Y coefficients. Coefficients are only

Reset Access

[7:0] PFILT Y Coefficient 71

0x0

R/W

Coefficient 71

0x0F48 PFILT Y

Coefficient 72

0x0F49 PFILT Y

Coefficient 73

0x0F4A PFILT Y

Coefficient 74

0x0F4B PFILT Y

Coefficient 75

0x0F4C PFILT Y

Coefficient 76

0x0F4D PFILT Y

Coefficient 77

0x0F4E PFILT Y

Coefficient 78

0x0F4F PFILT Y

Coefficient 79

0x0F50 PFILT Y

Coefficient 80

0x0F51 PFILT Y

Coefficient 81

0x0F52 PFILT Y

Coefficient 82

0x0F53 PFILT Y

Coefficient 83

0x0F54 PFILT Y

Coefficient 84

0x0F55 PFILT Y

Coefficient 85

0x0F56 PFILT Y

Coefficient 86

0x0F57 PFILT Y

Coefficient 87

0x0F58 PFILT Y

Coefficient 88

0x0F59 PFILT Y

Coefficient 89

0x0F5A PFILT Y

Coefficient 90

0x0F5B PFILT Y

Coefficient 91

0x0F5C PFILT Y

Coefficient 92

0x0F5D PFILT Y

Coefficient 93

0x0F5E PFILT Y

Coefficient 94

0x0F5F PFILT Y

Coefficient 95

0x0F60 PFILT Y

Coefficient 96

0x0F61 PFILT Y

Coefficient 97

0x0F62 PFILT Y

Coefficient 98

0x0F63 PFILT Y

Coefficient 99

0x0F64 PFILT Y

Coefficient 100

0x0F65 PFILT Y

Coefficient 101

0x0F66 PFILT Y

Coefficient 102

applied after the chip transfer bit has been written.

[7:0] PFILT Y Coefficient 72

[7:0] PFILT Y Coefficient 73

[7:0] PFILT Y Coefficient 74

[7:0] PFILT Y Coefficient 75

[7:0] PFILT Y Coefficient 76

[7:0] PFILT Y Coefficient 77

[7:0] PFILT Y Coefficient 78

[7:0] PFILT Y Coefficient 79

[7:0] PFILT Y Coefficient 80

[7:0] PFILT Y Coefficient 81

[7:0] PFILT Y Coefficient 82

[7:0] PFILT Y Coefficient 83

[7:0] PFILT Y Coefficient 84

[7:0] PFILT Y Coefficient 85

[7:0] PFILT Y Coefficient 86

[7:0] PFILT Y Coefficient 87

[7:0] PFILT Y Coefficient 88

[7:0] PFILT Y Coefficient 89

[7:0] PFILT Y Coefficient 90

[7:0] PFILT Y Coefficient 91

[7:0] PFILT Y Coefficient 92

[7:0] PFILT Y Coefficient 93

[7:0] PFILT Y Coefficient 94

[7:0] PFILT Y Coefficient 95

[7:0] PFILT Y Coefficient 96

[7:0] PFILT Y Coefficient 97

[7:0] PFILT Y Coefficient 98

[7:0] PFILT Y Coefficient 99

[7:0] PFILT Y Coefficient 100

[7:0] PFILT Y Coefficient 101

[7:0] PFILT Y Coefficient 102

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Rev. 0 | Page 132 of 138

Data Sheet

AD6688

Addr. Name

0x0F67 PFILT Y

Bit(s) Bit Name

Setting Description

Programmable Filter Y coefficients. Coefficients are only

Reset Access

[7:0] PFILT Y Coefficient 103

0x0

R/W

Coefficient 103

0x0F68 PFILT Y

Coefficient 104

0x0F69 PFILT Y

Coefficient 105

0x0F6A PFILT Y

Coefficient 106

0x0F6B PFILT Y

Coefficient 107

0x0F6C PFILT Y

Coefficient 108

0x0F6D PFILT Y

Coefficient 109

0x0F6E PFILT Y

Coefficient 110

0x0F6F PFILT Y

Coefficient 111

0x0F70 PFILT Y

Coefficient 112

0x0F71 PFILT Y

Coefficient 113

0x0F72 PFILT Y

Coefficient 114

0x0F73 PFILT Y

Coefficient 115

0x0F74 PFILT Y

Coefficient 116

0x0F75 PFILT Y

Coefficient 117

0x0F76 PFILT Y

Coefficient 118

0x0F77 PFILT Y

Coefficient 119

0x0F78 PFILT Y

Coefficient 120

0x0F79 PFILT Y

Coefficient 121

0x0F7A PFILT Y

Coefficient 122

0x0F7B PFILT Y

Coefficient 123

0x0F7C PFILT Y

Coefficient 124

0x0F7D PFILT Y

Coefficient 125

0x0F7E PFILT Y

Coefficient 126

0x0F7F PFILT Y

Coefficient 127

applied after the chip transfer bit has been written.

[7:0] PFILT Y Coefficient 104

[7:0] PFILT Y Coefficient 105

[7:0] PFILT Y Coefficient 106

[7:0] PFILT Y Coefficient 107

[7:0] PFILT Y Coefficient 108

[7:0] PFILT Y Coefficient 109

[7:0] PFILT Y Coefficient 110

[7:0] PFILT Y Coefficient 111

[7:0] PFILT Y Coefficient 112

[7:0] PFILT Y Coefficient 113

[7:0] PFILT Y Coefficient 114

[7:0] PFILT Y Coefficient 115

[7:0] PFILT Y Coefficient 116

[7:0] PFILT Y Coefficient 117

[7:0] PFILT Y Coefficient 118

[7:0] PFILT Y Coefficient 119

[7:0] PFILT Y Coefficient 120

[7:0] PFILT Y Coefficient 121

[7:0] PFILT Y Coefficient 122

[7:0] PFILT Y Coefficient 123

[7:0] PFILT Y Coefficient 124

[7:0] PFILT Y Coefficient 125

[7:0] PFILT Y Coefficient 126

[7:0] PFILT Y Coefficient 127

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Programmable Filter Y coefficients. Coefficients are only

applied after the chip transfer bit has been written.

Rev. 0 | Page 133 of 138

AD6688

Data Sheet

VREF/Analog Input Control Registers

Table 53.

Addr.

0x0701 DC offset

calibration control

Name

Bit(s) Bit Name

[7:0] DC offset calibration

control

Setting

Description

Reset Access

0x06 R/W

(local)

0x06

0x86

Disable.

Enable.

0x18A6 VREF control

[7:1] Reserved

Reserved.

0x0

R

0

VREF control

R/W

0

1

Internal reference.

External reference.

Reserved.

0x18E3 External VCM

buffer control

7

6

Reserved

0x0

R

External VCM buffer

R/W

0

1

Disable.

Enable.

[5:0] External VCM

buffer[5:0]

See the Input Common Mode section.

0x0

R/W

0x18E6 Temperature diode [7:0] Temperature diode

export

location select

0x00

0x01

0x02

0x03

0x40

0x41

0x42

0x43

0x50

0x51

0x52

0x53

Central diode. VREF pin = high-Z.

Central diode. VREF pin = 1× diode voltage output.

Central diode. VREF pin = 20× diode voltage output.

Central diode. VREF pin = GND.

Channel A diode. VREF pin = high-Z.

Channel A diode. VREF pin = 1× diode voltage output.

Channel A diode. VREF pin = 20× diode voltage output.

Channel A diode. VREF pin = GND.

Channel B diode. VREF pin = high-Z.

Channel B diode. VREF pin = 1× diode voltage output.

Channel B diode. VREF pin = 20× diode voltage output.

Channel B diode. VREF pin = GND.

0x1908 Analog input

control (local)

[7:3] Reserved

Enable dc coupling

Reserved.

0x0

R

2

R/W

0

1

Analog input is optimized for ac coupling.

Analog input is optimized for dc coupling.

Reserved.

[1:0] Reserved

[7:4] Reserved

0x0

R

0x1910 Input full-scale

control (local)

Reserved.

[3:0] TRM VREF 1P8

Full-scale voltage setting.

1.13 V p-p differential.

1.25 V p-p differential.

1.7 V p-p differential.

1.81 V p-p differential.

1.93 V p-p differential.

2.04 V p-p differential.

0xD

R/W

1000

1001

1101

1110

1111

0000

Rev. 0 | Page 134 of 138

Data Sheet

AD6688

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x1A4C Buffer Control 1

(local)

[7:6] Reserved

Reserved.

0x0

R

[5:0] Buffer Control 1

Input Buffer Main Current 1. See the Analog Input Buffer

Controls and SFDR Optimization section.

0x19 R/W

00 0100

00 1001

01 1110

10 0011

10 1000

11 0010

Buffer current set to 400 µA.

Buffer current set to 500 µA.

Buffer current set to 600 µA.

Buffer current set to 700 µA.

Buffer current set to 800 µA.

Buffer current set to 1000 µA.

Reserved.

0x1A4D Buffer Control 2

(local)

[7:6] Reserved

0x0

R

[5:0] Buffer Control 2

Input Buffer Main Current 2. See the Analog Input Buffer

Controls and SFDR Optimization section.

0x19 R/W

00 0100

00 1001

01 1110

10 0011

10 1000

11 0010

Buffer current set to 400 µA.

Buffer current set to 500 µA.

Buffer current set to 600 µA.

Buffer current set to 700 µA.

Buffer current set to 800 µA.

Buffer current set to 1000 µA.

Rev. 0 | Page 135 of 138

AD6688

Data Sheet

APPLICATIONS INFORMATION

It is not necessary to split all of these power domains in all cases.

The recommended solution shown in Figure 117 provides the

lowest noise, highest efficiency power delivery system for the

AD6688. If only one 0.975 V supply is available, route to AVDD1

first and then tap it off and isolate it with a ferrite bead or a

filter choke, preceded by decoupling capacitors for AVDD1_SR,

DVDD, and DRVDD1, in that order. Figure 118 shows the

simplified schematic. The dc resistance (DCR) of the ferrite

bead must be taken into consideration when choosing the

appropriate ferrite bead. Otherwise, excessive loss across the

ferrite bead can lead to a malfunctioning ADC. Adjustable

LDOs can be employed to output a higher voltage to account for

the drop across the ferrite bead.

POWER SUPPLY RECOMMENDATIONS

The power supplies needed to power the AD6688 are shown in

Table 54. A power on sequence is not required to operate the

AD6688. The power supply domains can come up in any order.

Table 54. Typical Power Supplies for AD6688

Domain

Voltage (V)

0.975

1.9

Tolerance (%)

AVDD1

AVDD1_SR

DVDD

DRVDD1

AVDD2

2.5

DRVDD2

SPIVDD

AVDD3

1.9

2.5

Alternatively, the LDOs can be bypassed altogether and the

AD6688 can be driven directly from the dc-to-dc converter.

Note that this approach has risks in that there may be more

power supply noise injected into the power supply domains of

the ADC. To minimize noise, follow the layout guidelines of the

dc-to-dc converter.

For applications requiring an optimal high power efficiency and

low noise performance, it is recommended that the ADP5054

quad switching regulator be used to convert a 6.0 V or 15 V

input voltage to intermediate rails (1.3 V, 2.4 V, and 3.0 V).

These intermediate rails are then postregulated by very low

noise, low dropout (LDO) regulators (ADP1763, ADP7159, and

ADP151). Figure 117 shows the recommended power supply

scheme for the AD6688.

1.3V

ANALOG

AVDD1

0.975V

15V FROM FMC OR

6.0V FROM WALL

SUPPLY

ADP1763

SW1

SW2

AVDD1_SR

0.975V

1.3V

DIGITAL

DVDD

0.975V

ADP5054

1.3V

ANALOG

AVDD1

6.0V

TO

15.0V

0.975V

ADP1763

SW3

SW4

AVDD1_SR

0.975V

DRVDD1

0.975V

OPTIONAL

1.3V

DIGITAL

DVDD

0.975V

ADP5054

AVDD2

1.9V

2.4V

ADP1763

ADP7159

DRVDD2

1.9V

DRVDD1

0.975V

AVDD2

1.9V

2.4V

ADP7159

ADP151

SPIVDD

1.9V

OPTIONAL

AVDD3

2.5V

DRVDD2

1.9V

3.0V

ADP7159

SPIVDD

1.9V

FERRITE BEAD

LDO

SWITCHER

AVDD3

2.5V

3.0V

OPTIONAL PATH

ADP7159

NOTES

1. ALL VOLTAGES REFERENCED TO AGND.

LDO

SWITCHER

OPTIONAL PATH

REFERENCED TO AGND

Figure 118. Simplified Power Solution for the AD6688

The user can employ several different decoupling capacitors to

cover both high and low frequencies. These capacitors must be

located close to the point of entry at the PCB level and close to

the devices, with minimal trace lengths.

Figure 117. High Efficiency, Low Noise Power Solution for the AD6688

Rev. 0 | Page 136 of 138

Data Sheet

AD6688

LAYOUT GUIDELINES

AVDD1_SR (PIN E7) AND AGND (PIN E6 AND PIN E8)

The ADC evaluation board can be used as a guide to follow

good layout practices. The evaluation board layout is done in

such a way as to

AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8) can be

used to provide a separate power supply node to the SYSREF

circuits of the AD6688. If running in Subclass 1, the AD6688

can support periodic one-shot or gapped signals. To minimize

the coupling of this supply into the AVDD1 supply node,

adequate supply bypassing is needed.



Minimize coupling between the analog inputs (Channel A

to Channel B and Channel B to Channel A).



Minimize clock coupling to the analog inputs.

Provide enough power and ground planes for the various

supply domains while reducing cross coupling.

Provide adequate thermal relief to the ADC.



Figure 119 shows the overall layout scheme used for the

AD6688 evaluation board.

CH.A

CLK

ADC

JESD204B LANES

POWER

CH.B

Figure 119. Recommended PCB Layout for the AD6688

Rev. 0 | Page 137 of 138

AD6688

Data Sheet

OUTLINE DIMENSIONS

12.10

12.00 SQ

11.90

A1 BALL

PAD CORNER

A1 BALL

PAD CORNER

14 13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

7.50 SQ

10.40 REF

SQ

K

L

0.80

11.20 SQ

M

N

P

TOP VIEW

BOTTOM VIEW

0.80 REF

DETAIL A

SIDE VIEW

1.53

1.42

1.31

1.19

1.09

0.99

DETAIL

A

0.71

REF

0.38

0.33

0.28

0.34 REF

0.50

0.45

0.40

SEATING

PLANE

COPLANARITY

0.12

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

Figure 120. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]

12 mm × 12 mm

(BP-196-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

AD6688BBPZ-3000

AD6688BBPZRL-3000

AD6688-3000EBZ

−40°C to +85°C

196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]

Evaluation Board for AD6688

BP-196-4

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D15549-0-4/17(0)

Rev. 0 | Page 138 of 138


型号：	AD6688-3000EBZ
厂家：	ADI
描述：	RF Diversity and 1.2 GHz Bandwidth Observation Receiver
文件：	总138页 (文件大小：2535K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD6688-3000EBZ [ADI]

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