AD674BTD/883 [ADI]
IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28, HERMETIC SEALED, CERAMIC, DIP-28, Analog to Digital Converter;型号: | AD674BTD/883 |
厂家: | ADI |
描述: | IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28, HERMETIC SEALED, CERAMIC, DIP-28, Analog to Digital Converter CD 转换器 |
文件: | 总12页 (文件大小:326K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Complete
12-Bit A/D Converters
a
AD674B*/AD774B*
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete Monolithic 12-Bit A/D Converters with
Reference, Clock, and Three-State Output Buffers
Industry Standard Pinout
High Speed Upgrades for AD574A
8- and 16-Bit Microprocessor Interface
8 s (max) Conversion Time (AD774B)
15 s (max) Conversion Time (AD674B)
؎5 V, ؎10 V, 0-10 V, 0-20 V Input Ranges
Commercial, Industrial and Military Temperature
Range Grades
+5V SUPPLY
STATUS
STS
1
28
27
26
25
24
23
22
V
LOGIC
MSB
DATA MODE SELECT
12/8
DB11 (MSB)
2
3
N
3
Y
B
B
L
CHIP SELECT
CS
CONTROL
DB10
S
T
A
T
E
BYTE ADDRESS/
SHORT CYCLE
DB9
DB8
E
4
5
A
0
READ/ CONVERT
R/C
A
12
12
SAR
COMP
CLOCK
O
U
T
P
U
T
CHIP ENABLE
CE
DB7
DB6
6
7
N
Y
B
B
L
+12/+15V SUPPLY
DIGITAL
DATA
OUTPUTS
V
CC
I DAC
+10V REFERENCE
REF OUT
B
U
F
10V
REF
DB5
DB4
8
9
21
20
E
MIL-STD-883 Compliant Versions Available
B
ANALOG COMMON
AC
F
E
R
S
REF
I
REFERENCE INPUT
REF IN
N
Y
B
B
L
DB3
DB2
10
11
12
19
18
17
16
15
19.95k
_
_
12/ 15V SUPPLY
V
EE
BIPOLAR OFFSET
BIPOFF
E
DAC
V
EE
DB1
N
C
10V SPAN INPUT
DB0 (LSB)
13
14
12
VOLTAGE
DIVIDER
10V
LSB
IN
20V SPAN INPUT
DIGITAL COMMON DC
20V
AD674B/AD774B
IN
PRODUCT HIGHLIGHTS
PRODUCT DESCRIPTION
1. Industry Standard Pinout: The AD674B and AD774B utilize
the pinout established by the industry standard AD574A.
The AD674B and AD774B are complete 12-bit successive-
approximation analog-to-digital converters with three-state
output buffer circuitry for direct interface to 8- and 16-bit
microprocessor busses. A high precision voltage reference and
clock are included on chip, and the circuit requires only power
supplies and control signals for operation.
2. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges: 0 to
+10 V and 0 to +20 V unipolar; –5 V to +5 V and –10 V to
+10 V bipolar. The AD674B and AD774B operate on +5 V
and ±12 V or ±15 V power supplies.
The AD674B and AD774B are pin compatible with the industry
standard AD574A, but offer faster conversion time and bus-
access speed than the AD574A and lower power consumption.
The AD674B converts in 15 µs (maximum) and the AD774B
converts in 8 µs (maximum).
3. Flexible Digital Interface: On-chip multiple-mode three-state
output buffers and interface logic allow direct connection to
most microprocessors. The 12 bits of output data can be
read either as one 12-bit word or as two 8-bit bytes (one with
8 data bits, the other with 4 data bits and 4 trailing zeros).
The monolithic design is implemented using Analog Devices’
BiMOS II process allowing high performance bipolar analog cir-
cuitry to be combined on the same die with digital CMOS logic.
Offset, linearity and scaling errors are minimized by active laser-
trimming of thin-film resistors.
4. The internal reference is trimmed to 10.00 volts with 1%
maximum error and 10 ppm/°C typical temperature coeffi-
cient. The reference is available externally and can drive up
to 2.0 mA beyond the requirements of the converter and bi-
polar offset resistors.
Five different grades are available. The J and K grades are speci-
fied for operation over the 0°C to +70°C temperature range.
The A and B grades are specified from –40°C to +85°C, the T
grade is specified from –55°C to +125°C. The J and K grades
are available in a 28-pin plastic DIP or 28-lead SOIC. All other
grades are available in a 28-pin hermetically sealed ceramic
DIP.
5. The AD674B and AD774B are available in versions compli-
ant with MIL-STD-883. Refer to the Analog Devices Mili-
tary Products Databook or current AD674B/AD774B/883B
data sheet for detailed specifications.
*Protected by U.S. Patent Nos. 4,250,445; 4,808,908; RE30586.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD674B/AD774B—SPECIFICATIONS
(TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%,
VLOGIC = +5 V ؎ 10%, VEE = –15 V ؎ 10% or –12 V ؎ 5% unless otherwise noted)
J Grade
K Grade
Typ
Model (AD674B or AD774B)
Min
Typ
Max
Min
Max
RESOLUTION
12
12
LINEARITY ERROR @ +25°C
TMIN to TMAX
؎1
؎1
؎1/2
؎1/2
DIFFERENTIAL LINEARITY ERROR
(Minimum Resolution for Which No
Missing Codes are Guaranteed)
12
12
UNIPOLAR OFFSET1 @ +25°C
BIPOLAR OFFSET1 @ +25°C
؎2
؎6
؎2
؎3
FULL-SCALE CALIBRATION ERROR1, 2 @ +25°C
(with Fixed 50 Ω Resistor from REF OUT to REF IN)
0.1
0.25
+70
0.1
0.125
+70
TEMPERATURE RANGE
0
0
TEMPERATURE DRIFT3
(Using Internal Reference)
Unipolar
؎2
؎2
؎6
؎1
؎1
؎2
Bipolar Offset
Full-Scale Calibration
POWER SUPPLY REJECTION
Max Change in Full-Scale Calibration
VCC = 15 V ± 1.5 V or 12 V ± 0.6 V
VLOGIC = 5 V ± 0.5 V
؎2
؎1/2
؎2
؎1
؎1/2
؎1
VEE = –15 V ± 1.5 V or –12 V ± 0.6 V
ANALOG INPUT
Input Ranges
Bipolar
–5
–10
0
+5
–5
–10
0
+5
+10
+10
+20
+10
+10
+20
Unipolar
0
0
Input Impedance
10 Volt Span
20 Volt Span
3
6
5
10
7
14
3
6
5
10
7
14
POWER SUPPLIES
Operating Range
VLOGIC
+4.5
+5.5
+4.5
+5.5
VCC
VEE
+11.4
–16.5
+16.5
–11.4
+11.4
–16.5
+16.5
–11.4
Operating Current
ILOGIC
ICC
IEE
3.5
3.5
10
7
3.5
3.5
10
7
7
7
14
14
POWER CONSUMPTION
220
175
375
220
175
375
INTERNAL REFERENCE VOLTAGE
Output Current (Available for External Loads)
(External Load Should Not Change During the Conversion)
9.9
10.0
10.1
2.0
9.9
10.0
10.1
2.0
NOTES
1Adjustable to zero.
2Includes internal voltage reference error.
3Maximum change from +25°C value to the value at TMIN or TMAX
.
4Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +16.5 V, VEE = –16.5 V, VLOGIC = +5.5 V, and outputs in high-Z mode.
5Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +12 V, VEE = –12 V, VLOGIC = +5 V, and outputs in high-Z mode.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at TMIN, +25°C, and TMAX, and results from those tests are used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
–2–
REV. B
AD674B/AD774B
A Grade
Typ
B Grade
Typ
T Grade
Typ
Min
Max
Min
Max
Min
Max
Units
12
12
12
Bits
؎1
؎1
؎1/2
؎1/2
؎1/2
؎1
LSB
LSB
12
12
12
Bits
؎2
؎6
؎2
؎3
؎2
؎3
LSB
LSB
0.1
0.25
+85
0.1
0.125
+85
0.1
0.125
+125
% of FS
–40
–40
–55
°C
؎2
؎2
؎8
؎1
؎1
؎5
؎1
؎2
؎7
LSB
LSB
LSB
؎2
؎1/2
؎2
؎1
؎1/2
؎1
؎1
؎1/2
؎1
LSB
LSB
LSB
–5
–10
0
+5
–5
–10
0
+5
–5
–10
0
+5
Volts
Volts
Volts
Volts
+10
+10
+20
+10
+10
+20
+10
+10
+20
0
0
0
3
6
5
10
7
14
3
6
5
10
7
14
3
6
5
10
7
14
kΩ
kΩ
+4.5
+11.4
–16.5
+5.5
+16.5
–11.4
+4.5
+11.4
–16.5
+5.5
+16.5
–11.4
+4.5
+11.4
–16.5
+5.5
+16.5
–11.4
Volts
Volts
Volts
3.5
3.5
10
7
7
14
3.5
3.5
10
7
7
14
3.5
3.5
10
7
7
14
mA
mA
mA
220
175
375
220
175
375
220
175
375
mW4
mW5
9.9
10.0
10.1
2.0
9.9
10.0
10.1
2.0
9.9
10.0
10.1
2.0
Volts
mA
REV. B
–3–
AD674B/AD774B
DIGITAL SPECIFICATIONS
Parameter
(for all grades TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%, VLOGIC = +5 V ؎ 10%,
VEE = –15 V ؎ 10% or –12 V ؎ 5%)
Test Conditions
Min
Max
Units
LOGIC INPUTS
VIH
VIL
IIH
IIL
CIN
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
+2.0
–0.5
–10
VLOGIC +0.5 V
V
V
µA
µA
pF
+0.8
+10
+10
10
VIN = VLOGIC
VIN = 0 V
–10
LOGIC OUTPUTS
VOH
VOL
IOZ
High Level Output Voltage
IOH = 0.5 mA
IOL = 1.6 mA
VIN = 0 to VLOGIC
+2.4
–10
V
V
µA
pF
Low Level Output Voltage
High-Z Leakage Current
High-Z Output Capacitance
+0.4
+10
10
COZ
(for all grades TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%,
VLOGIC = +5 V ؎ 10%, VEE = –15 V ؎ 10% or –12 V ؎ 5%; unless otherwise noted)
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
tHEC
CE
__
tHSC
J, K, A, B Grades
Symbol Min Typ Max Min Typ Max Units
T Grade
CS
tSSC
tSRC
Parameter
_
R/C
tHRC
Conversion Time
8-Bit Cycle (AD674B) tC
12-Bit Cycle (AD674B) tC
8-Bit Cycle (AD774B) tC
12-Bit Cycle (AD774B) tC
6
9
4
6
8
10
6
9
4
6
8
10
µs
µs
µs
µs
12 15
5
7.3
12 15
5
7.3
A
tSAC
tHAC
0
6
8
6
8
STS Delay from CE
CE Pulse Width
CS to CE Setup
CS Low During CE High tHSC
R/C to CE Setup tSRC
R/C LOW During CE High tHRC
A0 to CE Setup tSAC
A0 Valid During CE High tHAC
tDSC
tHEC
tSSC
200
225 ns
STS
C
t
50
50
50
50
50
0
50
50
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
tDSC
HIGH IMPEDANCE
DB11 – DB0
Figure 1. Convert Start Timing
50
50
CE
CS
t
SSR
t HSR
tHRR
_
R/C
READ TIMING—FULL CONTROL MODE (Figure 2)
J, K, A, B Grades T Grade
tSRR
tHAR
A
0
tSAR
Parameter
Symbol Min Typ Max Min Typ Max Units
STS
Access Time
CL = 100 pF
Data Valid After CE Low tHD
tHD
1
tDD
75 150
150
75 150 ns
HIGH
IMPEDANCE
DATA
VALID
HIGH
IMP.
DB11 – DB0
252
203
252
154
ns
ns
150 ns
tDD
tHL
5
Output Float Delay
CS to CE Setup
R/C to CE Setup
tHL
Figure 2. Read Cycle Timing
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
50
0
50
0
0
50
50
0
50
0
0
50
ns
ns
ns
ns
ns
ns
+5V
A0 to CE Setup
3k
CS Valid After CE Low
R/C High After CE Low
A0 Valid After CE Low
DB
N
DB
N
3k
100pF
100pF
NOTES
1tDD is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
High-Z to Logic 1
High-Z to Logic 0
Figure 3a. Load Circuit for Access Time Test
20°C to TMAX
3At –40°C.
4At –55°C.
.
+5V
3k
5tHL is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
DB
N
DB
N
3k
Specifications shown in boldface are tested on all devices at final electrical test with
worst case supply voltages at TMIN, +25°C, and TMAX. Results from those tests are used
to calculate outgoing quality levels. All min and max specifications are guaranteed, al-
though only those shown in boldface are tested.
10pF
10pF
Logic 1 to High-Z
Figure 3b. Load Circuit for Output Float Delay Test
REV. B
Logic 0 to High-Z
Specifications subject to change without notice.
–4–
AD674B/AD774B
tHRL
TIMING—STAND-ALONE MODE (Figures 4a and 4b)
R/C
J, K, A, B Grades
T Grade
Parameter
Symbol Min Typ Max Min Typ Max Units
tDS
Data Access Time
Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low tHDR
STS Delay After Data Valid tHS
tDDR
tHRL
tDS
150
200
150 ns
ns
225 ns
ns
50
50
25
STS
25
30
150
tC
200 600
30 200 600 ns
150 ns
tHS
tHDR
High R/C Pulse Width
tHRH
HIGH-Z
DATA
VALID
_
DB11 DB0
DATA VALID
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
t
DS
VCC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +16.5 V
Flgure 4a. Stand-Alone Mode Timing Low Pulse R/C
V
V
EE to Digital Common . . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V
LOGIC to Digital Common . . . . . . . . . . . . . . . . . . . . 0 to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . . ±1 V
Digital Inputs to Digital Common . . . –0.5 V to VLOGIC +0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . . VEE to VCC
20 VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . ±24 V
REF OUT . . . . . . . . . . . . . . . . . . Indefinite Short to Common
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VCC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Lead Temperature, Soldering . . . . . . . . . . . . . . 300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
R/C
tDS
tHRH
STS
tC
tDDR
HIGH-Z
tHDR
HIGH-Z
DATA
VALID
_
DB11 DB0
tHL
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 4b. Stand-Alone Mode Timing High Pulse for R/C
ORDERING GUIDE
Conversion
Time (max) (TMIN to TMAX
INL
Package
Description
Package
Option2
Modell
Temperature
)
AD674BJN
AD674BKN
AD674BJR
AD674BKR
AD674BAD
AD674BBD
AD674BTD
AD774BJN
AD774BKN
AD774BJR
AD774BKR
AD774BAD
AD774BBD
AD774BTD
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
15 µs
15 µs
15 µs
15 µs
15 µs
15 µs
15 µs
8 µs
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1 LSB
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1 LSB
Plastic DIP
Plastic DIP
N-28
N-28
R-28
R-28
D-28
D-28
D-28
N-28
N-28
R-28
R-28
D-28
D-28
D-28
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
Plastic DIP
8 µs
Plastic DIP
15 µs
15 µs
8 µs
8 µs
8 µs
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
NOTES
1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military
Products Databook or current AD674B/ AD774B/883B data sheet.
2N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD674B/AD774B features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
AD674B/AD774B
DEFINITION OF SPECIFICATIONS
QUANTIZATION UNCERTAINTY
Analog-to-digital converters exhibit an inherent quantization
uncertainty of ±1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
LINEARITY ERROR
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale.” The point
used as “zero” occurs 1/2 LSB (1.22 mV for 10 volt span) be-
fore the first code transition (all zeroes to only the LSB “on”).
“Full scale” is defined as a level 1 1/2 LSB beyond the last code
transition (to all ones). The deviation of a code from the true
straight line is measured from the middle of each particular
code.
LEFT-JUSTIFIED DATA
The output data format is left-justified. This means that the
data represents the analog input as a fraction of full scale, rang-
ing from 0 to 4095/4096. This implies a binary point 4095 to
the left of the MSB.
The K, B. and T grades are guaranteed for maximum nonlinear-
ity of ±1/2 LSB. For these grades, this means that an analog
value which falls exactly in the center of a given code width will
result in the correct digital output code. Values nearer the upper
or lower transition of the code width may produce the next up-
per or lower digital output code. The J and A grades are guaran-
teed to ±1 LSB max error. For these grades, an analog value
which falls within a given code width will result in either the
correct code for that region or either adjacent one.
FULL-SCALE CALIBRATION ERROR
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 volts for 10.000 volts full scale). The full-scale
calibration error is the deviation of the actual level at the last
transition from the ideal level. This error, which is typically 0.05
to 0.1% of full scale, can be trimmed out as shown in Figures 7
and 8. The full-scale calibration error over temperature is given
with and without the initial error trimmed out. The temperature
coefficients for each grade indicate the maximum change in
the full-scale gain from the initial value using the internal 10 V
reference.
Note that the linearity error is not user adjustable.
DIFFERENTIAL LINEARITY ERROR (NO MISSING
CODES)
A specification which guarantees no missing codes requires that
every code combination appear in a monotonic increasing se-
quence as the analog input level is increased. Thus every code
must have a finite width. The AD674B and AD774B guarantee
no missing codes to 12-bit resolution, requiring that all 4096
codes must be present over the entire operating temperature
ranges.
TEMPERATURE DRIFT
The temperature drift for full-scale calibration, unipolar offset,
and bipolar offset specifies the maximum change from the initial
(+25°C) value to the value at TMIN or TMAX
.
POWER SUPPLY REJECTION
The standard specifications assume use of +5.00 V and
±15.00 V or ±12.00 V supplies. The only effect of power supply
error on the performance of the device will be a small change in
the full-scale calibration. This will result in a linear change in all
low-order codes. The specifications show the maximum full-
scale change from the initial value with the supplies at the vari-
ous limits.
UNIPOLAR OFFSET
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the ac-
tual transition from that point. This offset can be adjusted as
discussed later. The unipolar offset temperature coefficient
specifies the maximum change of the transition point over tem-
perature, with or without external adjustment.
CODE WIDTH
A fundamental quantity for A/D converter specifications is the
code width. This is defined as the range of analog input values
for which a given digital output code will occur. The nominal
value of a code width is equivalent to 1 least significant bit
(LSB) of the full-scale range or 2.44 mV out of 10 volts for a
12-bit ADC.
BIPOLAR OFFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
–6–
REV. B
AD674B/AD774B
AD674B AND AD774B PIN DESCRIPTION
Type Name and Function
Symbol
Pin No.
AGND
A0
9
4
P
Analog Ground (Common).
DI
Byte Address/Short Cycle. If a conversion is started with A0 Active LOW, a full 12-bit conversion
cycle is initiated. If A0 is Active HIGH during a convert start, a shorter 8-bit conversion cycle
results. During Read (R/C = 1) with 12/8 LOW, A0 = LOW enables the 8 most significant bits,
and A0 = HIGH enables DB3-DB0 and sets DB7-DB4 = 0.
BIP OFF
12
AI
Bipolar Offset. Connect through a 50 Ω resistor to REF OUT for bipolar operation or to Analog
Common for unipolar operation.
CE
6
3
DI
Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
CS
DI
Chip Select. Chip Select is Active LOW.
DB11-DB8 27-24
DO
Data Bits 11 through 8. In the 12-bit format (see 12/8 and A0 pins), these pins provide the upper
4 bits of data. In the 8-bit format, they provide the upper 4 bits when A0 is LOW and are
disabled when A0 is HIGH.
DB7-DB4
DB3-DB0
23-20
19-16
DO
DO
Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
8-bit format they provide the middle 4 bits when A0 is LOW and all zeroes when A0 is HIGH.
Data Bits 3 through 0. In both the 12-bit and 8-bit format these pins provide the lower 4 bits of
data when A0 is HIGH; they are disabled when A0 is LOW.
DGND
REF OUT
R/C
15
8
P
Digital Ground (Common).
AO
DI
+10 V Reference Output.
5
Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW
for a convert operation. In the stand-alone mode, the falling edge of R/C initiates a conversion.
Reference Input is connected through a 50 Ω resistor to +10 V Reference for normal operation.
REF IN
STS
10
28
AI
DO
Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
completed.
VCC
7
P
+12 V/+15 V Analog Supply.
VEE
11
1
P
–12 V/–15 V Analog Supply.
+5 V Logic Supply.
VLOGIC
10 VIN
P
13
AI
10 V Span Input, 0 to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the
20 V Span, 10 VIN should not be connected.
20 VIN
14
2
AI
20 V Span Input, 0 to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using the
10 V Span, 20 VIN should not be connected.
12/8
DI
The 12/8 pin determines whether the digital output data is to be organized as two 8-bit words
(12/8 LOW) or a single 12-bit word (12/8 HIGH).
PIN CONFIGURATION
TYPE: AI =
AO =
Analog Input
Analog Output
Digital Input
V
1
2
3
4
5
28 STS
LOGIC
DI =
_
DB11 (MSB)
12/8
27
26
25
DO = Digital Output
P = Power
__
CS
DB10
DB9
A
0
_
R/C
24 DB8
AD674B
or
6
7
23
CE
DB7
AD774B
V
22
CC
DB6
REF OUT
AGND
8
9
21
20
19
18
17
16
15
DB5
DB4
DB3
DB2
TOP VIEW
(Not to Scale)
REF IN
10
11
12
V
EE
BIP OFF
DB1
10V
IN
13
14
DB0 (LSB)
DGND
20V
IN
REV. B
–7–
AD674B/AD774B
CIRCUIT OPERATION
mately a 1 MHz rate. Thus it is important to recognize that the
signal source driving the ADC must be capable of holding a
constant output voltage under dynamically-changing load
conditions.
The AD674B and AD774B are complete 12-bit monolithic A/D
converters which require no external components to provide the
complete successive-approximation analog-to-digital conversion
function. A block diagram is shown in Figure 5.
+5V SUPPLY
STATUS
STS
1
28
27
26
25
24
23
V
LOGIC
MSB
DATA MODE SELECT
12/8
DB11 (MSB)
DB10
2
3
N
3
CHIP SELECT
CS
Y
B
B
L
CONTROL
S
T
A
T
E
BYTE ADDRESS/
SHORT CYCLE
DB9
DB8
4
5
E
A
0
READ/ CONVERT
R/C
12
12
A
SAR
COMP
CLOCK
O
U
T
P
U
T
CHIP ENABLE
CE
N
Y
B
B
L
DB7
6
7
+12/+15V SUPPLY
DIGITAL
DATA
OUTPUTS
22 DB6
V
CC
I
DAC
E
+10V REFERENCE
REF OUT
B
U
F
10V
REF
DB5
8
9
21
B
ANALOG COMMON
AC
DB4
20
F
E
R
S
REF
I
REFERENCE INPUT
REF IN
DB3
19
10
11
12
N
Y
B
B
L
19.95k
_
_
12/ 15V SUPPLY
DB2
18
V
EE
BIPOLAR OFFSET
BIPOFF
E
DAC
V
EE
DB1
17
N
Figure 6. Op Amp—ADC Interface
C
10V SPAN INPUT
DB0 (LSB)
DIGITAL COMMON DC
13
14
16
15
12
VOLTAGE
DIVIDER
10V
LSB
IN
The closed-loop output impedance of an op amp is equal to the
openloop output impedance (usually a few hundred ohms) di-
vided by the loop gain at the frequency of interest. It is often
assumed that the loop gain of a follower-connected op amp is
sufficiently high to reduce the closed-loop output impedance to
a negligibly small value, particularly if the signal is low fre-
quency. However, the amplifier driving the ADC must either
have sufficient loop gain at 1 MHz to reduce the closed-loop
output impedance to a low value or have low open-loop output
impedance. This can be accomplished by using a wideband op
amp, such as the AD711.
20V SPAN INPUT
20V
AD674B/AD774B
IN
Figure 5. Block Diagram of AD674B and AD774B
When the control section is commanded to initiate a conversion
(as described later), it enables the clock and resets the
successive-approximation register (SAR) to all zeroes. Once a
conversion cycle has begun, it cannot be stopped or restarted
and data is not available from the output buffers. The SAR,
timed by the clock, will sequence through the conversion cycle
and return an end-of-convert flag to the control section. The
control section will then disable the clock, bring the output
status flag low, and enable control functions to allow data read
by external command.
If a sample-hold amplifier is required, the monolithic AD585 or
AD781 is recommended, with the output buffer driving the
AD674B or AD774B input directly. A better alternative is the
AD1674 which is a 10 µs sampling ADC in the same pinout
as the AD574A, AD674A or AD774B and is functionally
equivalent.
During the conversion cycle, the internal 12-bit current output
DAC is sequenced by the SAR from the most-significant-bit
(MSB) to least-significant-bit (LSB) to provide an output cur-
rent which accurately balances the input signal current through
the divider network. The comparator determines whether the
addition of each successively-weighted bit current causes the
DAC current sum to be greater or less than the input current; if
the sum is less, the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12-bit binary code
which accurately represents the input signal to within ±1/2 LSB.
SUPPLY DECOUPLING AND LAYOUT
CONSIDERATION
It is critically important that the power supplies be filtered, well
regulated, and free from high frequency noise. Use of noisy sup-
plies will cause unstable output codes. Switching power supplies
are not recommended for circuits attempting to achieve 12-bit
accuracy unless great care is used in filtering any switching
spikes present in the output. Few millivolts of noise represent
several counts of error in a 12-bit ADC.
The temperature-compensated reference provides the primary
voltage reference to the DAC and guarantees excellent stability
with both time and temperature. The reference is trimmed to
10.00 volts ±1%; it can supply up to 2.0 mA to an external load
in addition to the requirements of the reference input resistor
(0.5 mA) and bipolar offset resistor (0.5 mA). Any external load
on the reference must remain constant during conversion. The
thin film application resistors are trimmed to match the fullscale
output current of the DAC. The input divider network provides
a 10 V or 20 V input range. The bipolar offset resistor is
grounded for unipolar operation and connected to the 10 volt
reference for bipolar operation.
Decoupling capacitors should be used on all power supply pins;
the +5 V supply decoupling capacitor should be connected di-
rectly from Pin 1 to Pin 15 (digital common) and the +VCC and
–VEE pins should be decoupled directly to analog common (Pin
9). A suitable decoupling capacitor is a 4.7 µF tantalum type in
parallel with a 0.1 µF ceramic disc type.
Circuit layout should attempt to locate the ADC, associated
analog input circuitry, and interconnections as far as possible
from logic circuitry. For this reason, the use of wire-wrap circuit
construction is not recommended. Careful printed-circuit layout
and manufacturing is preferred.
DRIVING THE ANALOG INPUT
The AD674B and AD774B are successive-approximation analog-
to-digital converters. During the conversion cycle, the ADC
input current is modulated by the DAC test current at approxi-
–8–
REV. B
AD674B/AD774B
UNIPOLAR RANGE CONNECTIONS FOR THE AD674B
AND AD774B
If Pin 12 is connected to Pin 9, the unit will behave in this man-
ner, within specifications. If the offset trim (R1) is used, it
should be trimmed as above, although a different offset can be
set for a particular system requirement. This circuit will give ap-
proximately ±15 mV of offset trim range.
The AD674B and AD774B contain all the active components
required to perform a complete 12-bit A/D conversion. Thus,
for most situations, all that is necessary is connection of the
power supplies (+5 V, +12/+15 V and –12/–15 V), the analog
input, and the conversion initiation command, as discussed on
the next page.
The full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 for a 10 V range). Trim R2 to
give the last transition (1111 1111 1110 to 1111 1111 1111).
BIPOLAR OPERATION
The connections for bipolar ranges are shown in Figure 8.
Again, as for the unipolar ranges, if the offset and gain specifica-
tions are sufficient, one or both of the trimmers shown can be
replaced by a 50 Ω ±1% fixed resistor. The analog input is
applied as for the unipolar ranges. Bipolar calibration is similar
to unipolar calibration. First, a signal 1/2 LSB above negative
full scale (–4.9988 V for the ±5 V range) is applied and R1 is
trimmed to give the first transition (0000 0000 0000 to 0000
0000 0001). Then a signal 1 1/2 LSB below positive full scale
(+4.9963 V for the ±5 V range) is applied and R2 trimmed to
give the last transition (1111 1111 1110 to 1111 1111 1111).
Figure 7. Unipolar Input Connections
All of the thin-film application resistors of the AD674B and
AD774B are factory trimmed for absolute calibration. There-
fore, in many applications, no calibration trimming will be re-
quired. The absolute accuracy for each grade is given in the
specification tables. For example, if no trims are used, ±2 LSB
max zero offset error and ±0.25% (10 LSB) max full-scale error
are guaranteed. If the offset trim is not required, Pin 12 can be
connected directly to Pin 9; the two resistors and trimmer for
Pin 12 are then not needed. If the full-scale trim is not required,
a 50 Ω 1% metal film resistor should be connected between Pin
8 and Pin 10.
The analog input is connected between Pins 13 and 9 for a 0 to
+10 V input range, between Pins 14 and 9 for a 0 to +20 V in-
put range. Input signals beyond the supplies are easily accom-
modated. For the 10 volt span input, the LSB has a nominal
value of 2.44 mV; for the 20 volt span, 4.88 mV. If a 10.24 V
range is desired (nominal 2.5 mV/bit), the gain trimmer (R2)
should be replaced by a 50 Ω resistor, and a 200 Ω trimmer in-
serted in series with the analog input to Pin 13 (for a full-scale
range of 20.48 V (5 mV/bit), use a 500 Ω trimmer into Pin 14).
The gain trim described below is now done with these trimmers.
The nominal input impedance into Pin 13 is 5 kΩ, and 10 kΩ
into Pin 14.
Figure 8. Bipolar Input Connections
GROUNDING CONSIDERATIONS
The analog common at Pin 9 is the ground reference point for
the internal reference and is thus the “high quality” ground for
the ADC; it should be connected directly to the analog refer-
ence point of the system. In order to achieve the high accuracy
performance available from the ADC in an environment of high
digital noise content, it is required that the analog and digital
commons be connected together at the package. In some situa-
tions, the digital common at Pin 15 can be connected to the
most convenient ground reference point; digital power return is
preferred.
UNIPOLAR CALIBRATION
The connections for unipolar ranges are shown in Figure 7. The
AD674B or AD774B is trimmed to a nominal 1/2 LSB offset so
that the exact analog input for a given code will be in the middle
of that code (halfway between the transitions to the codes above
and below it). Thus, when properly calibrated, the first transi-
tion (from 0000 0000 0000 to 0000 0000 0001) will occur for
an input level of +1/2 LSB (1.22 mV for 10 V range).
REV. B
–9–
AD674B/AD774B
VALUE OF A AT LAST CONVERT COMMAND
0
Q
EOC 12
D
D
EOC 8
EN
EN
START CONVERT
R
S
Q
Q
S
SAR
RESET
QB
R
CE
CS
HIGH IF CONVERSION
IN PROGRESS
CLK EN
STATUS
R/C
NYBBLE A
ENABLE
NYBBLE B
ENABLE
A
0
READ
TO
OUTPUT
BUFFERS
NYBBLE C
ENABLE
12/8
NYBBLE B = 0
ENABLE
Figure 9. Equivalent Internal Logic Circuitry
CONTROL LOGIC
Table I. Truth Table
The AD674B and AD774B contain on-chip logic to provide
conversion initiation and data read operations from signals
commonly available in microprocessor systems; this internal
logic circuitry is shown in Figure 9.
CE CS R/C 12/8 A0 Operation
0
X
1
1
1
1
1
X
1
0
0
0
0
0
X
X
0
0
1
X
X
X
X
1
X
X
0
1
X
0
None
None
The control signals CE, CS, and R/C control the operation of
the converter. The state of R/C when CE and CS are both as-
serted determines whether a data read (R/C = 1) or a convert
(R/C = 0) is in progress. The register control inputs A0 and
12/8 control conversion length and data format. If a conversion
is started with A0 low, a full 12-bit conversion cycle is initiated.
If A0 is high during a convert start, a shorter 8-bit conversion
cycle results. During data read operations, A0 determines
whether the three-state buffers containing the 8 MSBs of the
conversion result (A0 = 0) or the 4 LSBs (A0 = 1) are enabled.
The 12/8 pin determines whether the output data is to be orga-
nized as two 8-bit words (12/8 tied to DIGITAL COMMON)
or a single 12-bit word (12/8 tied to VLOGIC). In the 8-bit mode,
the byte addressed when A0 is high contains the 4 LSBs from
the conversion followed by four trailing zeroes. This organiza-
tion allows the data lines to be overlapped for direct interface to
8-bit buses without the need for external three-state buffers.
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
Enable 12-Bit Parallel Output
Enable 8 Most Significant Bits
Enable 4 LSBs +4 Trailing Zeroes
1
1
0
0
1
The ADC may be operated in one of two modes, thefull-control
mode and the stand-alone mode. The full-control mode utilizes
all the control signals and is useful in systems that address de-
code multiple devices on a single data bus. The stand-alone
mode is useful in systems with dedicated input ports available.
In general, the stand-alone mode is capable of issuing start-con-
vert commands on a more precise basis and, therefore, produces
higher accuracy results. The following sections describe these
two modes in more detail.
FULL-CONTROL MODE
Chip Enable (CE), Chip Select (CS) and Read/Convert (R/C)
are used to control Convert or Read modes of operation. Either
CE or CS may be used to initiate a conversion. The state of R/C
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
–10–
REV. B
AD674B/AD774B
when CE and CS are both asserted determines whether a data
Read (R/C = 1) or a Convert (R/C = 0) is in progress. R/C
should be LOW before both CE and CS are asserted; if R/C is
HIGH, a Read operation will momentarily occur, possibly re-
sulting in system bus contention.
GENERAL A/D CONVERTER INTERFACE
CONSIDERATIONS
A typical A/ D converter interface routine involves several op-
erations. First, a write to the ADC address initiates a conver-
sion. The processor must then wait for the conversion cycle to
complete, since most integrated circuit ADCs take longer than
one instruction cycle to complete a conversion. Valid data can,
of course, only be read after the conversion is complete. The
AD674B and AD774B provide an output signal (STS) which
indicates when a conversion is in progress. This signal can be
polled by the processor by reading it through an external three-
state buffer (or other input port). The STS signal can also be
used to generate an interrupt upon completion of conversion if
the system timing requirements are critical and the processor
has other tasks to perform during the ADC conversion cycle.
Another possible time-out method is to assume that the ADC
will take its maximum conversion time to convert, and insert a
sufficient number of “no-op” instructions to ensure that this
amount of processor time is consumed.
STAND-ALONE MODE
“Stand-alone” mode is useful in systems with dedicated input
ports available and thus not requiring full bus interface capabil-
ity. Stand-alone mode applications are generally able to issue
conversion start commands more precisely than full-control
mode, resulting in improved accuracy.
CE and 12/8 are wired HIGH, CS and A0 are wired LOW, and
conversion is controlled by R/C. The three-state buffers are en-
abled when R/C is HIGH and a conversion starts when R/C
goes LOW. This gives rise to two possible control signals—a
high pulse or a low pulse. Operation with a low pulse is shown
in Figure 4a. In this case, the outputs are forced into the high
impedance state in response to the falling edge of R/C and re-
turn to valid logic levels after the conversion cycle is completed.
The STS line goes HIGH 200 ns after R/C goes LOW and re-
turns low 600 ns after data is valid.
Once conversion is complete, the data can be read. For convert-
ers with more data bits than are available on the bus, a choice of
data formats is required, and multiple read operations are
needed. The AD674B and AD774B include internal logic to
permit direct interface to 8-bit and 16-bit data buses, selected
by the 12/8 input. In 16-bit bus applications (12/8 high) the
data lines (DB11 through DB0) may be connected to either the
12 most significant or 12 least significant bits of the data bus.
The remaining four bits should be masked in software. The in-
terface to an 8-bit data bus (12/8 low) is done in a left-justified
format. The even address (A0 low) contains the 8 MSBs (DB11
through DB4). The odd address (A0 high) contains the 4 LSBs
(DB3 through DB0) in the upper half of the byte, followed by
four trailing zeroes, thus eliminating bit masking instructions.
If conversion is initiated by a high pulse as shown in Figure 4b,
the data lines are enabled during the time when R/C is HIGH.
The falling edge of R/C starts the next conversion, and the data
lines return to three-state (and remain three-state) until the next
high pulse of R/C.
CONVERSION TIMING
Once a conversion is started, the STS line goes HIGH. Convert
start commands will be ignored until the conversion cycle is
complete. The output data buffers can be enabled up to 1.2 µs
prior to STS going LOW. The STS line will return LOW at the
end of the conversion cycle.
It is not possible to rearrange the output data lines for right-jus-
tified 8-bit bus interface.
The register control inputs, A0 and 12/8, control conversion
length and data format. If a conversion is started with A0 LOW,
a full 12-bit conversion cycle is initiated. If A0 is HIGH during a
convert start, a shorter 8-bit conversion cycle results.
D7
D0
DB4
XXX0
(EVEN ADDR)
DB11
(MSB)
DB10 DB9 DB8 DB7
DB6 DB5
During data read operations, A0 determines whether the three-
state buffers containing the 8 MSBs of the conversion result
(A0 = 0) or the 4 LSBs (A0 = 1) are enabled. The 12/8 pin de-
termines whether the output data is to be organized as two 8-bit
words (12/8 tied LOW) or a single 12-bit word (12/8 tied
HIGH). In the 8-bit mode, the byte addressed when A0 is high
contains the 4 LSBs from the conversion followed by four trail-
ing zeroes. This organization allows the data lines to be over-
lapped for direct interface to 8-bit buses without the need for
external three-state buffers.
XXX1
(ODD ADDR)
DB0
(LSB)
DB1
0
DB3 DB2
0
0
0
Figure 10. Data Format for 8-Bit Bus
REV. B
–11–
AD674B/AD774B
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Ceramic DIP Package (D-28)
0.05 (1.27)
0.045 (1.14)
0.050 (12.83)
28
1
15
30o
0.08 (2.0)
0.59
+
0.01
–
(14.98)
0.125 MIN (3.17)
SEATING
PLANE
14
0.085
(2.16)
+
1.42 (36.07)
1.40 (35.56)
0.145 0.02
–
0.095 (2.41)
(3.68)
+
0.010 0.002
–
–
+
(0.254 0.05)
0.050
+
0.010
–
(1.27)
+
0.1 (2.54)
0.6 (15.24)
0.017 0.003
–
+
0.047 0.007
(0.43)
–
(1.19)
28-Lead Plastic DIP Package (N-28A)
28
15
0.550 (13.97)
0.530 (13.462)
14
1
0.200
(5.080)
MAX
0.606 (15.39)
1.450 (36.83)
1.440 (36.576)
0.594 (15.09)
0.160 (4.06)
0.140 (3.56)
15o
0o
0.012 (0.305)
0.008 (0.203)
0.065 (1.65)
0.045 (1.14)
0.175 (4.45)
0.120 (3.05)
0.020 (0.508)
0.015 (0.381)
0.105 (2.67)
0.095 (2.41)
LEADS ARE SOLDER DIPPED OR TIN - PLATED ALLOY 42 OR COPPER.
–12–
REV. B
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