AD679 [ADI]
14-Bit 128 kSPS Complete Sampling ADC; 14位128 kSPS的完整采样ADC
| 型号： | AD679 |
| 厂家： | 
ADI |
| 描述： | 14-Bit 128 kSPS Complete Sampling ADC |
| 文件： | 总12页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit 128 kSPS
Complete Sampling ADC
a
AD679*
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AC and DC Characterized and Specified
(K, B, T Grades)
128k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
80 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 M⍀ Input Impedance
8-Bit Bus Interface (See AD779 for 16-Bit Interface)
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Pin Compatible with AD678 12-Bit, 200 kSPS ADC
MIL-STD-883 Compliant Versions Available
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD679 is a complete, multipurpose 14-bit monolithic
analog-to-digital converter, consisting of a sample-hold ampli-
fier (SHA), a microprocessor compatible bus interface, a voltage
reference and clock generation circuitry.
1. COMPLETE INTEGRATION: The AD679 minimizes
external component requirements by combining a high
speed sample-hold amplifier (SHA), ADC, 5 V reference,
clock and digital interface on a single chip. This provides a
fully specified sampling A/D function unattainable with
discrete designs.
The AD679 is specified for ac (or “dynamic”) parameters such
as S/N+D ratio, THD and IMD which are important in signal
processing applications. In addition, the AD679K, B and T
grades are fully specified for dc parameters which are important
in measurement applications.
2. SPECIFICATIONS: The AD679K, B and T grades provide
fully specified and tested ac and dc parameters. The AD679J,
A and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica-
tions (such as INL, gain and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD and IMD) are of value in signal process-
ing applications.
The 14 data bits are accessed in two read operations (8+6), with
left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input im-
pedance (10 MΩ) allows direct connection to unbuffered
sources without signal degradation. Conversions can be initiated
either under microprocessor control or by an external clock
asynchronous to the system clock.
3. EASE OF USE: The pinout is designed for easy board lay-
out, and the two read output provides compatibility with 8-
bit buses. Factory trimming eliminates the need for calibration
modes or external trimming to achieve rated performance.
This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging al-
gorithm which includes error correction and flash converter cir-
cuitry to achieve high speed and resolution.
4. RELIABILITY: The AD679 utilizes Analog Devices’ mono-
lithic BiMOS technology. This ensures long term reliability
compared to multichip and hybrid designs.
5. UPGRADE PATH: The AD679 provides the same pinout as
the 12-bit, 200 kSPS AD678 ADC.
6. The AD679 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD679/883B data sheet for detailed
specifications.
The AD679 operates from +5 V and ±12 V supplies and dissi-
pates 560 mW (typ). 28-pin plastic DIP, ceramic DIP and 44
J-leaded ceramic surface mount packages are available.
*Protected by U.S. Patent Nos. 4,804,960; 4,814,767; 4,833,345; 4,250,445;
4,808,908; RE 30,586
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD679–SPECIFICATIONS
(TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%, VDD = +5 V ؎ 10%, fSAMPLE = 128 kSPS, fIN = 10.009 kHz
unless otherwise noted)
1
AC SPECIFICATIONS
AD679J/A/S
Typ
AD679K/B/T
Parameter
Min
Max
Min
Typ
Max
Units
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO2
–0.5 dB Input (Referred to –0 dB Input)
–20 dB Input (Referred to –20 dB Input)
78
58
18
79
59
19
80
60
20
81
61
21
dB
dB
dB
–60 dB Input (Referred to –60 dB Input)
TOTAL HARMONIC DISTORTION (THD)3
@ +25°C
–90
0.003
–84
0.006
–90
0.003
–84
0.006
dB
%
TMIN to TMAX
–88
0.004
–82
0.008
–88
0.004
–82
0.008
dB
%
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
FULL POWER BANDWIDTH
–90
1
–84
–90
1
–84
dB
MHz
kHz
FULL LINEAR BANDWIDTH
500
500
INTERMODULATION DISTORTION (IMD)4
2nd Order Products
3rd Order Products
–90
–90
–84
–84
–90
–90
–84
–84
dB
dB
DIGITAL SPECIFICATIONS
(All device types TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%, VDD = +5 V ؎ 10%)
Parameter
Test Conditions
Min
Max
Units
LOGIC INPUTS
VIH
VIL
IIH
IIL
CIN
High Level Input Voltage
2.0
0
–10
–10
VDD
0.8
+10
+10
10
V
V
µA
µA
pF
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIN = 5 V
VIN = 0 V
LOGIC OUTPUTS
VOH
High Level Output Voltage
IOH = 0.1 mA
4.0
2.4
V
V
I
OH = 0.5 mA
VOL
IOZ
COZ
Low Level Output Voltage
High Z Leakage Current
High Z Output Capacitance
IOL = 1.6 mA
VIN = 0 or 5 V
0.4
+10
10
V
µA
pF
–10
NOTES
1flN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal
unless otherwise noted.
2See Figure 15 for higher frequencies and other input amplitudes.
3See Figures 13 and 14 for higher frequencies and other input amplitudes.
4fA = 9.08 kHz, fB = 9.58 kHz, with fSAMPLE 100 kSPS. See Definition of Specifications section.
Specifications subject to change without notice.
–2–
REV. C
AD679
(TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%, VDD = +5 V ؎ 10% unless otherwise noted)
DC SPECIFICATIONS
AD679J/A/S
Typ
AD679K/B/T
Typ
Parameter
Min
Max
Min
Max
Units
TEMPERATURE RANGE
J, K Grades
A, B Grades
0
–40
–55
+70
+85
+125
0
–40
–55
+70
+85
+125
°C
°C
°C
S, T Grades
ACCURACY
Resolution
14
14
14
14
Bits
LSB
Bits
% FSR*
% FSR
% FSR
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Unipolar Zero Error1 (@ +25°C)
Bipolar Zero Error1 (@ +25°C)
Gain Error1, 2 (@ +25°C)
Temperature Drift
Unipolar Zero3
J, K Grades
±2
±1
؎2
0.08
0.08
0.12
0.05
0.05
0.09
0.07
0.07
0.11
0.04
0.05
0.09
0.04
0.05
0.09
0.05
0.07
0.10
% FSR
% FSR
% FSR
A, B Grades
S, T Grades
Bipolar Zero3
J, K Grades
A, B Grades
0.02
0.04
0.08
0.02
0.04
0.08
0.04
0.05
0.09
% FSR
% FSR
% FSR
S, T Grades
Gain3
J, K Grades
A, B Grades
0.09
0.10
0.20
0.09
0.10
0.20
0.11
0.16
0.25
% FSR
% FSR
% FSR
S, T Grades
Gain4
J, K Grades
A, B Grades
S, T Grades
0.04
0.05
0.09
0.04
0.05
0.09
0.05
0.07
0.10
% FSR
% FSR
% FSR
ANALOG INPUT
Input Ranges
Unipolar Mode
Bipolar Mode
0
–5
+10
+5
0
–5
+10
+5
V
V
Input Resistance
Input Capacitance
Input Settling Time
Aperture Delay
Aperture Jitter
10
10
10
10
MΩ
pF
µs
ns
ps
1.5
1.5
10
150
10
150
INTERNAL VOLTAGE REFERENCE
Output Voltage5
4.98
5.02
4.98
5.02
V
External Load
Unipolar Mode
Bipolar Mode
+1.5
+0.5
+1.5
+0.5
mA
mA
POWER SUPPLIES
Power Supply Rejection
VCC = +12 V ± 5%
VEE = –12 V ± 5%
VDD = +5 V ± 10%
Operating Current
ICC
±6
±6
±6
؎6
؎6
؎6
LSB
LSB
LSB
18
25
8
20
34
12
18
25
8
20
34
12
mA
mA
mA
IEE
IDD
Power Consumption
560
745
560
745
mW
NOTES
1Adjustable to zero. See Figures 5 and 6.
2Includes internal voltage reference error.
3Includes internal voltage reference drift.
4Excludes internal voltage reference drift.
5With maximum external load applied.
*% FSR = percent of full-scale range.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at TMIN, 25°C and TMAX. Results from those tests are used to
calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
REV. C
–3–
AD679
TIMING SPECIFICATIONS
(All device types TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%,
VDD = +5 V ؎ 10%)
Parameter
Symbol
Min
Max Units
SC Delay
tSC
tC
50
ns
Conversion Time
Conversion Rate1
Convert Pulse Width
Aperture Delay
Status Delay
6.3
7.8
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCR
tCP
tAD
tSD
tBA
0.097 3.0
5
0
10
10
10
20
400
100
574
80
Access Time2, 3
Float Delay5
Output Delay
Format Setup
OE Delay
Read Pulse Width
Conversion Delay
EOCEN Delay
tFD
tOD
tFS
tOE
tRP
tCD
tEO
0
100
20
195
400
50
Figure 1. Conversion Timing
NOTES
1Includes Acquisition Time.
2Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.
3COUT = 100 pF.
4COUT = 50 pF.
5Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the
output voltage changes by 0.5. See Figure 4; COUT = 10 pF.
Specifications subject to change without notice.
ORDERING GUIDE1
Tested
Figure 2. Output Timing
Temperature
Range
and
Package
Model2
Package
Specified Option3
AD679JN 28-Pin Plastic DIP
AD679KN 28-Pin Plastic DIP
AD679JD 28-Pin Ceramic DIP
AD679KD 28-Pin Ceramic DIP
AD679AD 28-Pin Ceramic DIP
AD679BD 28-Pin Ceramic DIP
AD679SD 28-Pin Ceramic DIP
AD679TD 28-Pin Ceramic DIP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
AC
AC + DC N-28
AC D-28
AC + DC D-28
AC D-28
AC + DC D-28
D-28
–55°C to +125°C AC + DC D-28
N-28
–55°C to +125°C AC
AD679AJ 44-Lead Ceramic JLCC –40°C to +85°C
AD679BJ 44-Lead Ceramic JLCC –40°C to +85°C
AD679SJ 44-Lead Ceramic JLCC –55°C to +125°C AC
AC
AC + DC J-44
J-44
J-44
AD679TJ 44-Lead Ceramic JLCC –55°C to +125°C AC + DC J-44
Figure 3. EOC Timing
NOTES
1For parallel read (14-bits) interface to 16-bit buses, see AD779.
2For details grade and package offerings screened in accordance with MIL-STD-
883, refer to the Analog Devices Miliary Products Databook or current AD679/
883B data sheet.
3N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.
Figure 4. Load Circuit for Bus Timing Specifications
–4–
REV. C
AD679
ABSOLUTE MAXIMUM RATINGS*
With
Respect
To
With
Respect
To
Specification
Min
Max
Units
Specification
Min
Max
Units
VCC
VEE
AGND
AGND
VEE
DGND
DGND
AGND
DGND
DGND
–0.3
–18
–0.3
0
+18
+0.3
+26.4
+7
+1
VCC
+7
V
V
V
V
V
V
V
Operating
Temperature
VCC (Note 1)
J and K Grades
A and B Grades
S and T Grades
Storage Temperature
Lead Temperature
(10 sec max)
0
+70
+85
+125
+150
°C
°C
°C
°C
VDD
AGND
–40
–55
–65
–1
AIN, REFIN
Digital Inputs
Digital Outputs
Max Junction
Temperature
VEE
–0.5
–0.5
VDD + 0.3 V
+300
°C
NOTES
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1The AD679 is not designed to operate from ±15 V supplies.
175
°C
CAUTION
The AD679 features input protection circuitry consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast,
low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD679 has
been classified as a Category 1 device.
WARNING!
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equip-
ment and discharge without detection. Unused devices must be stored in conductive foam or shunts,
and the foam should be discharged to the destination socket before devices are removed. For further
information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
ESD SENSITIVE DEVICE
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Ceramic DIP Package (D-28)
44-Lead J-Leaded Chip Carrier (J-44)
28-Lead Plastic DIP Package (N-28)
REV. C
–5–
AD679
PIN DESCRIPTION
28-Pin
DIP
Pin No.
44-Lead
JLCC
Pin No.
Symbol
Type Name and Function
AGND
AIN
BIPOFF
7
6
10
11
10
15
P
AI
AI
Analog Ground. This is the ground return for AIN only.
Analog Signal Input.
Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight
binary output coding. Connect to REFOUT for ±5 V input bipolar mode and
twos complement binary output coding.
CS
DGND
4
6
23
DI
P
Chip Select. Active LOW.
Digital Ground.
12, 14
DB7–DB0 26–19
40, 39, 37, 36,
35, 34, 33, 31
42
DO
Data Bits. These pins provide all 14 bits in two bytes (8+6 bits). Active HIGH.
EOC
27
DO
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH
when the conversion finishes. In asynchronous mode, EOC is an open drain
output and requires an external 3 kΩ pull-up resistor. See EOCEN and SYNC
pins for information on EOC gating.
EOCEN
HBE
1
15
1
25
DI
DI
End-of-Convert Enable. Enables EOC pin. Active LOW.
High Byte Enable. If LOW, output contains high byte. If HIGH, output
contains low byte (corresponding to the most recently read high byte).
Output Enable. A down-going transition on OE enables DB7–DB0. Gated with
CS. Active LOW.
OE
2
3
DI
REFIN
REFOUT
SC
9
8
3
13
14
12
5
AI
Reference Input. +5 V input gives 10 V full-scale range.
+5 V Reference Output. Tied to REFIN for normal operation.
Start Convert. Active LOW. See SYNC pin for gating.
SYNC Control. If tied to VDD (synchronous mode), SC and EOCEN are gated
by CS. If tied to DGND (asynchronous mode), SC and EOCEN are indepen-
dent of CS, and EOC is an open drain output. EOC requires an external 3 kΩ
pull-up resistor in asynchronous mode.
AO
DI
DI
SYNC
21
VCC
VEE
VDD
—
11
5
28
16
17
8
43
P
P
P
U
U
+12 V Analog Power.
–12 V Analog Power.
+5 V Digital Power.
Tie to DGND.
—
17–18
2, 4, 7, 9, 13,
16, 18, 19, 20,
22, 24, 26, 27,
28, 29, 30, 32,
38, 41, 44
These pins are unused and should be connected to DGND or VDD.
Type: AI = Analog Input. AO = Analog Output. DI = Digital Input (TTL and 5 V CMOS compatible). DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers. P = Power. U = Unused.
PIN CONFIGURATION
DIP Package
JLCC Package
–6–
REV. C
AD679
NYQUIST FREQUENCY
APERTURE JITTER
An implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
INPUT SETTLING TIME
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
Settling time is a function of the SHA’s ability to track fast slew-
ing signals. This is specified as the maximum time required in
track mode after a full-scale step input to guarantee rated con-
version accuracy.
TOTAL HARMONIC DISTORTION (THD)
DIFFERENTIAL NONLINEARITY (DNL)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is ex-
pressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
In an ideal ADC, code transitions are 1 LSB apart. Differential
linearity is the deviation from this ideal value. It is often speci-
fied in terms of resolution for which no missing codes (NMC)
are guaranteed.
INTEGRAL NONLINEARITY (INL)
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
The ideal transfer function for a linear ADC is a straight line
drawn between “zero” and “full scale.” The point used as
“zero” occurs 1/2 LSB before the first code transition. “Full
scale” is defined as a level 1 1/2 LSB beyond the last code tran-
sition. Integral linearity error is the worst case deviation of a
code from the straight line. The deviation of each code is mea-
sured from the middle of that code.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms are (fa + fb) and (fa – fb) and the third or-
der terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
The IMD products are expressed as the decibel ratio of the rms
sum of the measured input signals to the rms sum of the distor-
tion terms. The two signals applied to the converter are of equal
amplitude and the peak value of their sum is –0.5 dB from full-
scale (9.44 V p-p). The IMD products are normalized to a 0-dB
input signal.
Note that the linearity error is not user adjustable.
POWER SUPPLY REJECTION
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
TEMPERATURE DRIFT
This is the maximum change in the parameter from the initial
value (@ +25°C) to the value at TMIN or TMAX
.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. Unipolar zero error is the devia-
tion of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than –0.1 dB. Beyond this frequency, dis-
tortion of the sampled input signal increases significantly.
BIPOLAR ZERO ERROR
In the bipolar mode, the major carry transition (11 1111 1111
1111 to 00 0000 0000 0000 ) should occur at an analog value
1/2 LSB below analog ground. Bipolar zero error is the devia-
tion of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
The AD679 has been designed to optimize input bandwidth, al-
lowing it to undersample input signals with frequencies signifi-
cantly above the converter’s Nyquist frequency.
GAIN ERROR
APERTURE DELAY
The last transition should occur at an analog value 1 1/2 LSB
below the nominal full scale (9.9991 volts for a 0 V–10 V range,
4.9991 volts for a ±5 V range). The gain error is the deviation of
the actual level at the last transition from the ideal level with the
zero error trimmed out. This error can be adjusted as shown in
the Input Connections and Calibration section.
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of Start Convert (SC) to when
the input signal is held for conversion. In synchronous mode,
Chip Select (CS) should be LOW before SC to minimize aper-
ture delay.
REV. C
–7–
AD679
CONVERSION CONTROL
END-OF-CONVERT
In synchronous mode (SYNC = HIGH), both Chip Select (CS)
and Start Convert (SC) must be brought LOW to start a con-
version. CS should be LOW tSC before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started by
bringing SC low, regardless of the state of CS.
In asynchronous mode, End-of-Convert (EOC) is an open drain
output (requiring a minimum 3 kΩ pull-up resistor) enabled by
End-of-Convert Enable (EOCEN). In synchronous mode, EOC
is a three-state output which is enabled by EOCEN and CS. See
Conversion Status Truth Table. Access (tBA) and float (tFD
)
timing specifications do not apply in asynchronous mode where
they are a function of the time constant formed by the external
load capacitance and the pull-up resistor.
Before a conversion is started, End-of-Convert (EOC) is HIGH
and the sample-hold is in track mode. After a conversion is
started, the sample-hold goes into hold mode and EOC goes
LOW, signifying that a conversion is in progress. During the
conversion, the sample-hold will go back into track mode and
start acquiring the next sample.
OUTPUT ENABLE OPERATION
The data bits (DB7–DB0) are three-state outputs that are en-
abled by Chip Select (CS) and Output Enable (OE). CS should
be LOW tOE before OE is brought LOW.
In track mode, the sample-hold will settle to ±0.003% (14 bits)
in 1.5 µs maximum. The acquisition time does not affect the
throughput rate as the AD679 goes back into track mode more
than 2 µs before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW.
When EOC goes HIGH, the conversion is completed and the
output data may be read. The output is read in two steps as a
16-bit word, with the high byte read first, followed by the low
byte. High Byte Enable (HBE) controls the output sequence.
The 14-bit result is left justified within the 16-bit field.
Bringing OE LOW tOE after CS goes LOW makes the output
register contents available on the output data bits (DB7–DB0).
A period of time tCD is required after OE is brought HIGH be-
fore the next SC instruction is issued.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFOUT),
output coding is twos-complement binary.
If SC is held LOW, conversion accuracy may deteriorate. For
this reason, SC should not be held low in an attempt to operate
in a continuously converting mode.
POWER-UP
The AD679 typically requires 10 µs after power-up to reset in-
ternal logic.
START CONVERSION TRUTH TABLE
INPUTS
CONVERSION STATUS TRUTH TABLE
SYNC CS
SC
STATUS
INPUTS
OUTPUT
SYNC CS EOCEN EOC
STATUS
1
1
1
0
X
f
No Conversion
Start Conversion
Synchronous
Mode
1
1
1
1
0
0
1
0
0
X
1
0
1
Converting
Not Converting
Either
1
1
f
0
0
Start Conversion
Synchronous
Mode
High Z
High Z
(Not Recommended)
Continuous Conversion
(Not Recommended)
X
Either
0
0
0
0
X
X
X
0
0
1
0
Converting
Not Converting
Either
Asynchronous
Mode*
High Z
High Z
0
0
0
X
X
X
1
f
0
No Conversion
Start Conversion
Continuous Conversion
(Not Recommended)
Asynchronous
Mode
NOTES
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
NOTES
*EOC requires a pull-up resistor in asynchronous mode.
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
OUTPUT ENABLE TRUTH TABLE
= HIGH to LOW transition. Must stay low for t = tCP
.
INPUTS
(CS U OE)
OUTPUTS
DB7 . . . DB0
14-BIT MODE CODING FORMAT (1 LSB = 0.61 mV)
HBE
X
1
← High Z →
Unipolar Coding
(Straight Binary)
Bipolar Coding
(Twos Complement)
Unipolar or
Bipolar
0
1
0
0
a b c d e f g h
i
j
k l m n 0 0
VIN*
Output Code
VIN*
Output Code
NOTES
0.00000 V
5.00000 V
9.99939 V
000 . . . 0
100 . . . 0
111 . . . 1
–5.00000 V
–0.00061 V
0.00000 V
+2.50000 V
+4.99939 V
100 . . . 0
111 . . . 1
000 . . . 0
010 . . . 0
011 . . . 1
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
a = MSB.
n = LSB.
U = Logical OR.
Data coding is binary for Unipolar Mode and 2s Complement Binary for Bipolar
Mode.
*Code center.
–8–
REV. C
AD679
INPUT CONNECTIONS AND CALIBRATION
UNIPOLAR RANGE INPUTS
The high (10 MΩ) input impedance of the AD679 eases the
task of interfacing to high source impedances or multiplexer
channel-to-channel mismatches of up to 300 Ω. The 10 V p-p
full-scale input range accepts the majority of signal voltages
without the need for voltage divider networks which could dete-
riorate the accuracy of the ADC.
Offset and gain errors can be trimmed out by using the configu-
ration shown in Figure 6. This circuit allows approximately
±25 mV of offset trim range (±40 LSB) and ±0.5% of gain trim
range (±80 LSB).
The nominal offset is 1/2 LSB so that the analog range that cor-
responds to each code will be centered in the middle of that
code (halfway between the transitions to the codes above and
below it). Thus the first transition (from 00 0000 0000 0000 to
00 0000 0000 0001) should nominally occur for an input level
of +1/2 LSB (0.305 mV above ground for a 10 V range). To
trim unipolar zero to this nominal value, apply a 0.305 mV sig-
nal to AIN and adjust R1 until the first transition is located.
The AD679 is factory trimmed to minimize offset, gain and lin-
earity errors. In unipolar mode, the only external component
that is required is a 50 Ω ±1% resistor. Two resistors are re-
quired in bipolar mode. If offset and gain are not critical (as in
some ac applications), even these components can be eliminated.
In some applications, offset and gain errors need to be trimmed
out completely. The following sections describe the correct pro-
cedure for these various situations.
The gain trim is done by adjusting R2. If the nominal value is
required, apply a signal 1 1/2 LSB below full scale (9.9997 V for
a 10 V range) and adjust R2 until the last transition is located
(11 1111 1111 1110 to 11 1111 1111 1111).
BIPOLAR RANGE INPUTS
The connections for the bipolar mode are shown in Figure 5. In
this mode, data output coding will be twos complement binary.
This circuit will allow approximately ±25 mV of offset trim
range (±40 LSB) and ±0.5% of gain trim range (±80 LSB).
If offset adjustment is not required, BIPOFF should be con-
nected directly to AGND. If gain adjustment is not required, R2
should be replaced with a fixed 50 Ω ±1% metal film resistor. If
REFOUT is connected directly to REFIN, the additional gain
error will be approximately 1%.
Either or both of the trim pots can be replaced with 50 Ω ±1%
fixed resistors if the AD679 accuracy limits are sufficient for ap-
plication. If the pins are shorted together, the additional offset
and gain errors will be approximately 80 LSB.
To trim bipolar zero to its nominal value, apply a signal 1/2 LSB
below midrange (–0.305 mV for a ±5 V range) and adjust R1
until the major carry transition is located (11 1111 1111 1111 to
00 0000 0000 0000). To trim the gain, apply a signal 1 1/2 LSB
below full scale (+4.9991 V for a ±5 V range) and adjust R2 to
give the last positive transition (01 1111 1111 1110 to 01 1111
1111 1111). These trims are interactive so several iterations may
be necessary for convergence.
A single pass calibration can be done by substituting a bipolar
offset trim (error at minus full scale) for the bipolar zero trim
(error at midscale), using the same circuit. First, apply a signal
1/2 LSB above minus full scale (–4.9997 V for a ±5 V range)
and adjust R1 until the minus full-scale transition is located
(10 0000 0000 0000 to 10 000 000 0001). Then perform the
gain error trim as outlined above.
Figure 6. Unipolar Input Connections with Gain and
Offset Trims
REFERENCE DECOUPLING
It is recommended that a 10 µF tantalum capacitor be con-
nected between REFIN (Pin 9) and ground. This has the effect
of improving the S/N+D ratio through filtering possible broad-
band noise contributions from the voltage reference.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is a significant issue.
A 1.22 mA current through a 0.5 Ω trace will develop a voltage
drop of 0.6 mV, which is 1 LSB at the 14 bit level for a 10 V
full-scale span. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
Figure 5. Bipolar Input Connections with Gain and
Offset Trims
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
REV. C
–9–
AD679
and digital ground planes are also desirable, with a single inter-
connection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
tial value at 25°C. REFIN (Pin 9) scales its input by a factor of
two; thus, this change becomes effectively 4.5 mV. When ap-
plied to the AD679, this results in a total gain drift of 0.09%
FSR, which is an improvement over the on-chip reference per-
formance of 0.11% FSR. A noise-reduction capacitor, CN, has
been shown.
The AD679 incorporates several features to help the user’s lay-
out. Analog pins (VEE, AIN, AGND, REFOUT, REFIN, BIPOFF,
V
CC) are adjacent to help isolate analog from digital signals. In
This capacitor reduces the broadband noise of the AD586 out-
put, thereby optimizing the overall ac and dc performance of the
AD679.
addition, the 10 MΩ input impedance of AIN minimizes input
trace impedance errors. Finally, ground currents have been
minimized by careful circuit architecture. Current through
AGND is 200 µA, with no code dependent variation. The cur-
rent through DGND is dominated by the return current for
DB7–DB0 and EOC.
SUPPLY DECOUPLING
The AD679 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and analog ground. A 10 µF
tantalum capacitor in parallel with a 0.1 µF ceramic capacitor
provides adequate decoupling.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD679, associated analog input circuitry and interconnec-
tions as far as possible from logic circuitry. A solid analog
ground plane around the AD679 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit con-
struction is preferred.
Figure 7. Bipolar Input with Gain and Offset Trims
Figure 8 shows the AD679 in unipolar input mode with the
AD588 reference. The AD588 output is accurate to 0.65 mV
from its value at 25°C over the 0°C to 70°C range. This results
in a 0.06% FSR total gain drift for the AD679, which is a sub-
stantial improvement over the on-chip reference performance of
0.11% FSR. A noise-reduction network on Pins 4, 6 and 7 has
been shown. The 1 µF capacitors form low pass filters with the
internal resistance of the AD588 Zener and amplifier cells and
external resistance. This reduces the high frequency (to 1 MHz)
noise of the AD588, providing optimum ac and dc performance
of the AD679.
GROUNDING
If a single AD679 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD679. If multiple AD679s are used or the AD679 shares ana-
log supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This prevents large ground loops which inductively
couple noise and allow digital currents to flow through the ana-
log system.
USE OF EXTERNAL VOLTAGE REFERENCE
The AD679 features an on-chip voltage reference. For improved
gain accuracy over temperature, a high performance external
voltage reference may be used in place of the on-chip reference.
The AD586 and AD588 are popular references appropriate for
use with high resolution converters. The AD586 is a low cost
reference which utilizes a buried Zener architecture to provide
low noise and drift. The AD588 is a higher performance refer-
ence which uses a proprietary implanted buried Zener diode in
conjunction with laser-trimmed thin-film resistors for low offset
and low drift.
Figure 8. Unipolar Input with Gain and Offset Trims
INTERFACING THE AD679 TO MICROPROCESSORS
The I/O capabilities of the AD679 allow direct interfacing to
general purpose and DSP microprocessor buses. The asynchro-
nous conversion control feature allows complete flexibility and
control with minimal external hardware.
Figure 7 shows the use of the AD586 with the AD679 in a bipo-
lar input mode. Over the 0°C to +70°C range, the AD586
L-grade exhibits less than a 2.25 mV output change from its ini-
–10–
REV. C
AD679
The following examples illustrate typical AD679 interface
configurations.
one 80 ns cycle, the digital signal processor supports the AD679
interface with one wait state.
AD679 to TMS320C25
The converter is configured to run asynchronously using a sam-
pling clock. The EOC output of the AD679 gets asserted at the
end of each conversion and causes an interrupt. Upon interrupt,
the ADSP-2101 immediately asserts its FO pin LOW. In the
following cycle, the processor starts a data memory read by pro-
viding an address on the DMA bus. The decoded address gener-
ates OE for the converter, and the high byte of the conversion
result is read over the data bus. The read operation is extended
with one wait state and thus started and completed within two
processor cycles (160 ns). Next, the ADSP-2101 asserts its FO
HIGH. This allows the processor to start reading the lower byte
of data. This read operation executes in a similar manner to the
first and is completed during the next 160 ns.
In Figure 9 the AD679 is mapped into the TMS320C25 I/O
space. AD679 conversions are initiated by issuing an OUT in-
struction to Port 1. EOC status and the conversion result are
read in with an IN instruction to Port 1. A single wait state is in-
serted by generating the processor READY input from IS, Port
1 and MSC. Address line A0 provides HBE decoding to select
between the high and low bytes of data. This configuration sup-
ports processor clock speeds of 20 MHz and is capable of sup-
porting processor clock speeds of 40 MHz if a NOP instruction
follows each AD679 read instruction.
Figure 9. AD679 to TMS320C25 Interface
Figure 11. AD679 to ADSP-2101 Interface
AD679 to 80186
AD679 to Analog Devices ADSP-2100A
Figure 10 shows the AD679 interfaced to the 80186 micropro-
cessor. This interface allows the 80186’s built-in DMA control-
ler to transfer the AD679 output into a RAM based FIFO buffer
of any length, with no microprocessor intervention.
Figure 12 demonstrates the AD679 interfaced to an ADSP-2100A.
With a clock frequency of 12.5 MHz, and instruction execution in
one 80 ns cycle, the digital signal processor will support theAD679
data memory interface with three hardware wait states.
In this application the AD679 is configured in the asynchronous
mode, which allows conversions to be initiated by an external
trigger source independent of the microprocessor clock. After
each conversion, the AD679 EOC signal generates a DMA re-
quest to Channel 1 (DRQ1). The subsequent DMA READ se-
quences the high and low byte AD679 data and resets the
interrupt latch. The system designer must assign a sufficient pri-
ority to the DMA channel to ensure that the DMA request will
be serviced before the completion of the next conversion. This
configuration can be used with 6 MHz and 8 MHz 80186
processors.
The converter is configured to run asynchronously using a sam-
pling clock. The EOC output of the AD679 gets asserted at the
end of each conversion and causes an interrupt. Upon interrupt,
the ADSP-2100A immediately executes a data memory write in-
struction which asserts HBE. In the following cycle, the proces-
sor starts a data memory read (high byte read) by providing an
address on the DMA bus. The decoded address generates OE
for the converter. OE, together with logic and latch, is used to
force the ADSP-2100A into a one cycle wait state by generating
DMACK. The read operation is thus started and completed
within two processor cycles (160 ns). HBE is released during
“high byte read.” This allows the processor to read the lower
byte of data as soon as “high byte read” is complete. The low
byte read operation executes in a similar manner to the first and
is completed during the next 160 ns.
Figure 10. AD679 to 80186 DMA Interface
AD679 to Analog Devices ADSP-2101
Figure 11 demonstrates the AD679 interfaced to an ADSP-2101.
With a clock frequency of 12.5 MHz, and instruction execution in
Figure 12. AD679 to ADSP-2100A Interface
REV. C
–11–
AD679
Figure 16. 5-Plot Averaged 2048 Point FFT at 128
kSPS, fIN = 10.009 kHz
Figure 13. Harmonic Distortion vs. Input Frequency
(–0.5 dB Input)
Figure 14. Total Harmonic Distortion vs. Input
Frequency and Amplitude
Figure 17. Nonaveraged IMD Plot for fIN = 9.08 kHz
(fa), 9.58 kHz (fb) at 128 kSPS
Figure 15. S/(N+D) vs. Input Frequency and Amplitude
Figure 18. Power Supply Rejection (fIN = 10 kHz,
fSAMPLE = 128 kSPS, VRIPPLE = 0.1 V p-p)
–12–
REV. C
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