AD688ARWZ [ADI]
High Precision 10 V Reference; 高精度10 V参考
| 型号： | AD688ARWZ |
| 厂家： | 
ADI |
| 描述： | High Precision 10 V Reference |
| 文件： | 总16页 (文件大小：490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Precision
± ±1 ꢀ ꢁeꢂerence
AD688
FUNCTIONAL BLOCK DIAGRAM
FEATURES
10 ꢀ tracking outputs
Kelvin connections
NOISE
+10V OUT
V
REDUCTION
A3 IN SENSE
HIGH
6
7
4
3
Low tracking error: 1.5 mꢀ
Low initial error: 2.0 mꢀ
Low drift: 1.5 ppm/°C
+10V OUT
FORCE
A3
A4
1
R
B
A1
R1
AD688
Low noise: 6 μꢀ p-p
–10V OUT
SENSE
14
15
R4
Flexible output force and sense terminals
High impedance ground sense
Wide body SOIC and CERDIP packages
–10V OUT
FORCE
R2
R5
+V
S
2
R6
R3
GENERAL DESCRIPTION
A2
16 –V
S
The AD688 is a high precision ±±1 ꢀ ꢁracking reference. Low
ꢁracking error, low iniꢁial error, and low ꢁemperaꢁure drifꢁ give
ꢁhe AD688 reference absoluꢁe ±±1 ꢀ accuracy performance
previously unavailable in monoliꢁhic form. The AD688 uses a
proprieꢁary ion-implanꢁed buried Zener diode, and laser wafer
drifꢁ ꢁrimming of high sꢁabiliꢁy ꢁhin-film resisꢁors ꢁo provide
ouꢁsꢁanding performance.
5
9
10
8
12
11
13
GAIN
ADJ
GND
SENSE
+IN
NC
V
BAL
ADJ
NC A4 IN
LOW
NC = NO CONNECT
Figure 1.
The AD688 includes ꢁhe basic reference cell and ꢁhree
addiꢁional amplifiers. The amplifiers are laser-ꢁrimmed for low
offseꢁ and low drifꢁ and mainꢁain ꢁhe accuracy of ꢁhe reference.
The amplifiers are configured ꢁo allow Kelvin connecꢁions ꢁo
ꢁhe load and/or boosꢁers for driving long lines or high currenꢁ
loads, delivering ꢁhe full accuracy of ꢁhe AD688 where iꢁ is
required in ꢁhe applicaꢁion circuiꢁ.
PRODUCT HIGHLIGHTS
±. Precision Tracking. The AD688 offers precision ꢁracking
±±1 ꢀ Kelvin ouꢁpuꢁ connecꢁions wiꢁh no exꢁernal
componenꢁs. Tracking error is less ꢁhan ±.5 mꢀ and fine-
ꢁrim is available for applicaꢁions requiring exacꢁ symmeꢁry
beꢁween ꢁhe +±1 ꢀ and −±1 ꢀ ouꢁpuꢁs.
The low iniꢁial error allows ꢁhe AD688 ꢁo be used as a sysꢁem
reference in precision measuremenꢁ applicaꢁions requiring
±2-biꢁ absoluꢁe accuracy. In such sysꢁems, ꢁhe AD688 can
provide a known volꢁage for sysꢁem calibraꢁion; ꢁhe cosꢁ of
periodic recalibraꢁion can ꢁherefore be eliminaꢁed.
Furꢁhermore, ꢁhe mechanical insꢁabiliꢁy of a ꢁrimming
poꢁenꢁiomeꢁer and ꢁhe poꢁenꢁial for improper calibraꢁion can be
eliminaꢁed by using ꢁhe AD688 and calibraꢁion sofꢁware.
2. Accuracy. The AD688 offers ±2-biꢁ absoluꢁe accuracy
wiꢁhouꢁ any user adjusꢁmenꢁs. Opꢁional fine-ꢁrim
connecꢁions are provided for applicaꢁions requiring higher
precision. The fine-ꢁrimming does noꢁ alꢁer ꢁhe operaꢁing
condiꢁions of ꢁhe Zener or ꢁhe buffer amplifiers and ꢁhus
does noꢁ increase ꢁhe ꢁemperaꢁure drifꢁ.
3. Low ouꢁpuꢁ noise. Ouꢁpuꢁ noise of ꢁhe AD688 is low—
ꢁypically 6 μꢀ p-p. A pin is provided for broadband noise
filꢁering using an exꢁernal capaciꢁor.
The AD688 is available in commercial version. Specified over
ꢁhe −41oC ꢁo +85oC ꢁemperaꢁure range, ꢁhe AD688 is offered in
wide body ±6-lead SOIC and ±6-lead CERDIP packages,
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD688
TABLE OF CONTENTS
Specifications..................................................................................... 3
Turn On Time ................................................................................8
Temperature Performance............................................................9
Kelvin Connections.......................................................................9
Dynamic Performance............................................................... 11
Bridge Driver Circuit................................................................. 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Theory of Operation ........................................................................ 6
Applications....................................................................................... 7
Calibration..................................................................................... 7
Noise Performance and Reduction ............................................ 8
REVISION HISTORY
3/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Added AD688ARWZ .........................................................Universal
Removed AD688SQ ...........................................................Universal
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 13
Rev. B | Page 2 of 16
AD688
SPECIFICATIONS
Typical @ 25°C, +10 V output, VS = 15 V unless otherwise noted.1 Specifications shown in boldface are tested on all production units at
final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed.
Table 1.
AD688AQ
Typ
AD688BQ
Typ Max
AD688ARWZ
Min
Max
Min
Min
Typ
Max
Unit
OUTPUT VOLTAGE ERROR
+10 V, −10 V Outputs
10 V TRAꢀCKNG ERROR
OUTPUT VOLTAGE DRKFT
+10 V, −10 V Outputs
0°ꢀ to +70°ꢀ (A, B)
−40°ꢀ to +85°ꢀ (A, B)
GAKN ADJ AND BAL ADJ2
Trim Range
mV
mV
−5
−3
+5
+3
−2
+2
−4
+4
−1.5
+1.5
−1.5
+1.5
2
ppm/°ꢀ
ppm/°ꢀ
–1.5
–3
+1.5
+3
−3
+3
–8
+8
5
150
5
150
5
150
mV
kΩ
Knput Resistance
LKNE REGULATKON
3
TMKN to TMAX
µV/V
–200
+200
–200
+200
–200
+200
LOAD REGULATKON
TMKN to TMAX
+10 V Output, 0<KOUT<10 mA
−10 V Output, −10<KOUT<0 mA
SUPPLY ꢀURRENT
50
50
50
50
50
50
µV/mA
µV/mA
TMKN to TMAX
9
9
mA
12
12
12
Power Dissipation
270
360
270
360
360
mW
OUTPUT NOKSE (ANY OUTPUT)
0.1 Hz to 10 Hz
6
6
6
µV p-p
Spectral Density, 100 Hz
LONG-TERM STABKLKTY (@ 25°ꢀ)
BUFFER AMPLKFKERS
Offset Voltage
Offset Voltage Drift
Bias ꢀurrent
140
15
140
15
140
15
nV√Hz
ppm/1000 hours
100
1
20
100
1
20
100
1
20
µV
µV/°ꢀ
nA
Open-Loop Gain
110
110
110
dB
Output ꢀurrent A3, A4
ꢀommon-Mode Rejection (A3, A4)
VꢀM = 1 V p-p
Short-ꢀircuit ꢀurrent
TEMPERATURE RANGE
Specified Performance
A, B Grades
mA
−10
+10
−10
+10
−10
+10
100
50
100
50
100
50
dB
mA
−40
+85
−40
+85
−40
+85
°ꢀ
1 See Figure 4 for output configuration.
2 Gain and balance adjustments guaranteed capable of trimming output voltage error and symmetry error to zero.
3 Test ꢀonditions: +VS = +18 V, −VS = –18 V; +VS = +13.5 V, −VS = −13.5 V.
Rev. B | Page 3 of 16
AD688
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect reliability.
Rating
+VS to −VS
Power Dissipation (25°ꢀ)
Q Package
Storage Temperature
Lead Temperature
(Soldering, 10 s)
36 V
600 mW
−65°ꢀ to +150°ꢀ
+300°ꢀ
Package Thermal Resistance
Q (θJA/θJꢀ)
120/35°ꢀ/W
Output Protection:
All outputs safe if shorted
to ground
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
Rev. B | Page 4 of 16
AD688
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
+10V OUT FORCE
+V
1
2
3
4
5
6
7
8
16 –V
S
15 –10V OUT FORCE
14 –10V OUT SENSE
13 A4 IN
S
+10V OUT SENSE
A3 IN
AD688
TOP VIEW
(Not to Scale)
GAIN ADJ
12 BAL ADJ
11 NC
V
HIGH
NOISE REDUCTION
10 NC
V
9 GND SENSE +IN
LOW
NC = NO CONNECT
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
+10 V OUT FORꢀE
+VS
+10 V OUT SENSE
A3 KN
GAKN ADJ
VHKGH
NOKSE REDUꢀTKON
Description
1
2
3
4
5
6
7
+10 V Output with Celvin Force. ꢀonnect to Pin 3.
Positive Power Supply.
+10 V Output with Celvin Sense. ꢀonnect to Pin 1.
+ Knput to A3. ꢀonnect to VHKGH, Pin 6.
Reference Gain Adjustment for ꢀalibration. See the ꢀalibration section.
Unbuffered Reference High Output.
Noise Filtering Pin. ꢀonnect external 1 µF capacitor to ground to reduce output noise, see the
Noise Performance and Reduction section. May be left open.
8
VLOW
Unbuffered Reference Low Output.
9
GND SENSE +KN
Gound with Celvin Sense.
10
11
12
13
14
15
16
Nꢀ
Nꢀ
BAL ADJ
A4 KN
−10 V OUT SENSE
−10 V OUT FORꢀE
−VS
No ꢀonnection. Leave floating.
No ꢀonnection. Leave floating.
Reference ꢀentering Adjustment for ꢀalibration. See the ꢀalibration section.
+ Knput to A4. ꢀonnect to VLOW, Pin 8.
−10 V Output with Celvin Sense. ꢀonnect to Pin 15.
−10 V Output with Celvin Force. ꢀonnect to Pin 14.
Negative Power Supply.
Rev. B | Page 5 of 16
AD688
THEORY OF OPERATION
The AD688 consists of a buried Zener diode reference,
amplifiers and associated thin-film resistors as shown in
Figure 3. The temperature compensation circuitry provides the
device with a temperature coefficient of 1.5 ppm/°C or less.
Amplifiers A3 and A4 are internally compensated and are used
to buffer the voltages at Pin 6 and Pin 8 as well as to provide a
full Kelvin output. Thus, the AD688 has a full Kelvin capability
by providing the means to sense a system ground, and forced
and sensed outputs referenced to that ground.
Amplifier A1 performs several functions. A1 primarily acts to
amplify the Zener voltage to the required 20 V. In addition, A1
also provides for external adjustment of the 20 V output
through Pin 5 (GAIN ADJ). Using the bias compensation
resistor between the Zener output and the noninverting input to
A1, a capacitor can be added at the noise reduction pin (Pin 7)
to form a low-pass filter and reduce the noise contribution of
the Zener to the circuit. Two matched 12 kΩ nominal thin-film
resistors (R4 and R5) divide the 20 V output in half.
NOISE
+10V OUT
V
REDUCTION
A3 IN SENSE
HIGH
6
7
4
3
+10V OUT
FORCE
A3
A4
1
R
B
A1
R1
AD688
–10V OUT
SENSE
14
15
R4
–10V OUT
FORCE
R2
R5
Ground sensing for the circuit is provided by amplifier A2. The
noninverting input (Pin 9) senses the system ground and forces
the midpoint of resistors R4 and R5 to be a virtual ground.
Pin 12 (BAL ADJ) can be used for fine adjustment of this
midpoint transfer.
+V
S
2
R6
R3
A2
16 –V
S
5
9
10
8
12
11
13
GAIN
ADJ
GND
SENSE
+IN
NC
V
LOW
BAL
ADJ
NC A4 IN
NC = NO CONNECT
Figure 3. Functional Block Diagram
Rev. B | Page 6 of 16
AD688
APPLICATIONS
voltage and the position of the center tap within the span. The
gain adjustment should be performed first. Although the trims
are not interactive within the device, the gain trim will move the
balance trim point as it changes the magnitude of the span.
The AD688 can be configured to provide 10 V reference
outputs as shown in Figure 4. The architecture of the AD688
provides ground sense and uncommitted output buffer
amplifiers which offer the user a great deal of functional
flexibility. The AD688 is specified and tested in the
Figure 5 shows the gain and balance trims of the AD688. A
100 kΩ 20-turn potentiometer is used for each trim. The
potentiometer for the gain trim is connected between Pin 6
(VHIGH) and Pin 8 (VLOW) with the wiper connected to Pin 5
(GAIN ADJ). The potentiometer is adjusted to produce exactly
20 V between Pin 1 and Pin 15, the amplifier outputs. The
balance potentiometer, also connected between Pin 6 and Pin 8
with the wiper to Pin 12 (BAL ADJ), is then adjusted to center
the span from +10 V to −10 V.
configuration shown in Figure 4. The user may choose to take
advantage of other configuration options available with the
AD688; however performance in these configurations is not
guaranteed to meet the stringent data sheet specifications.
Unbuffered outputs are available at Pin 6 and Pin 8. Loading of
these unbuffered outputs will impair circuit performance.
Amplifiers A3 and A4 can be used interchangeably. However,
the AD688 is tested (and the specifications are guaranteed) with
the amplifiers connected as indicated in Figure 4. When either
A3 or A4 is unused, its output force and sense pins should be
connected and the input tied to ground.
Input impedance on both the GAIN ADJ and the BAL ADJ pins
is approximately 150 kΩ. The gain adjustment trim network
effectively attenuates the 20 V across the trim potentiometer by
a factor of about 1150 to provide a trim range of –5.8 mV to
+12.0 mV with a resolution of approximately 900 µV/turn
(20-turn potentiometer). The balance adjustment trim network
attenuates the trim voltage by a factor of about 1250, providing
a trim range of 8 mV with a resolution of 800 µV/turn.
Two outputs of the same voltage polarity may be obtained by
connecting both A3 and A4 to the appropriate unbuffered
output on Pin 6 or Pin 8. Performance in these dual output
configurations will typically meet data sheet specifications.
Trimming the AD688 introduces no additional errors over
temperature, so precision potentiometers are not required.
4
7
6
3
A3
A4
1
+10V
R
B
When balance adjustment is not necessary, Pin 12 should be left
floating. If gain adjustment is not required, Pin 5 should also be
left floating.
AD688
A1
R1
14
R4
R5
15
2
–10V
20kΩ
R2
+15V
NOISE
REDUCTION
+15V SUPPLY
1µF
R6
0.1
µ
F
F
7
6
4
3
R3
SYSTEM
GROUND
A2
16
0.1µ
A3
A4
1
+10V
R
5
9
10
8
12
13
11
–15V SUPPLY
B
AD688
A1
R1
SYSTEM
GROUND
14
R4
R5
Figure 4. +10 V and −10 V Outputs
15
2
–10V
R2
CALIBRATION
+15V SUPPLY
R6
0.1
0.1
µ
F
F
R3
5
Generally, the AD688 will meet the requirements of a precision
system without additional adjustment. Initial output voltage
error of 2 mV and output noise specs of 6 µV p-p allow for
accuracies of 12 to 16 bits. However, in applications where an
even greater level of accuracy is required, additional calibration
may be called for. The provision for trimming has been made
through the use of the GAIN ADJ and BAL ADJ pins (Pin 5 and
Pin 12, respectively).
SYSTEM
GROUND
A2
16
µ
10
8
9
12
11 13
–15V SUPPLY
SYSTEM
GROUND
100kΩ
20T
BALANCE
ADJUST
100kΩ
20T
GAIN ADJUST
The AD688 provides a precision 20 V span with a center tap
which is used with the buffer and ground sense amplifiers to
achieve the 10 V output configuration. GAIN ADJ and
BAL ADJ can be used to trim the magnitude of the 20 V span
Figure 5. Gain and Balance Adjustment with Noise Reduction
Rev. B | Page 7 of 16
AD688
any thermal tails when the horizontal scale is expanded to
2 ms/cm in Figure 9.
NOISE PERFORMANCE AND REDUCTION
The noise generated by the AD688 is typically less than
6 µV p-p over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz
bandwidth is approximately 840 µV p-p. The dominant source
of this noise is the buried Zener which contributes
approximately 140 nV/√Hz. In comparison, the op amp’s
contribution is negligible. Figure 6 shows the 0.1 Hz to 10 Hz
noise of a typical AD688.
1mV
100µs
10V
+V
S
100
90
–V
S
5s
1mV
+V
OUT
10
100
90
0%
10V
1µV
Figure 8. Turn On Characteristics: Electrical Turn On
10V
1mV
2ms
10
0%
+V
S
100
90
Figure 6. 0.1 Hz to 10 Hz Noise
–V
S
If further noise reduction is desired, an optional capacitor can
be added between the noise reduction pin and ground as shown
in Figure 5. This will form a low-pass filter with the 5 kΩ RB on
the output of the Zener cell. A 1 µF capacitor will have a 3 dB
point at 32 Hz and will reduce the high frequency noise (to
1 MHz) to about 250 µV p-p. Figure 7 shows the 1 MHz noise of
a typical AD688 both with and without a 1 µF capacitor.
+V
OUT
10
0%
10V
Figure 9. Turn On Characteristics: Extended Time Scale
Output turn on time is modified when an external noise
reduction capacitor is used. When present, this capacitor
presents an additional load to the internal Zener diode’s current
source, resulting in a somewhat longer turn on time. In the case
of a 1 µF capacitor, the initial turn on time is approximately
100 ms (Figure 10).
200µV
50µs
C
= 1µF
N
When the noise reduction feature is used, a 20 kΩ resistor
between Pin 6 and Pin 2 is required for proper startup.
NO C
N
10V
1mV
20ms
+V
S
100
90
Figure 7. Effect of 1 µF Noise Reduction Capacitor on Broadband Noise
TURN ON TIME
–V
S
Upon application of power (cold start), the time required for
the output voltage to reach its final value within a specified
error is the turn on settling time. Two components normally
associated with this are: time for active circuits to settle and
time for thermal gradients on the chip to stabilize. Figure 8 and
Figure 9 show the turn on characteristics of the AD688. They
show the settling time to be about 600 µs. Note the absence of
+V
OUT
10
0%
10V
Figure 10. Turn On With 1 µF CN
Rev. B | Page 8 of 16
AD688
MAXIMUM OUTPUT CHANGE (mV)
TEMPERATURE PERFORMANCE
DEVICE GRADE
0 TO +70°C
1.40 (TYP)
1.05
–40°C TO +85°C
The AD688 is designed for precision reference applications
where temperature performance is critical. Extensive
temperature testing ensures that the device’s high level of
performance is maintained over the operating temperature
range.
AD688AQ
3.75
3.75
4.0
AD688BQ
AD688ARWZ
Figure 12. Maximum + 10 V or −10 V Output Change
Figure 11 shows the typical output voltage drift and illustrates
the test methodology. The box in Figure 11 is bounded on the
sides by the operating temperature extremes, and on top and
bottom by the maximum and minimum +10 V output error
voltages measured over the operating temperature range. The
slopes of the diagonals drawn for both the +10 V and –10 V
outputs determine the performance grade of the device.
Duplication of these results requires a combination of high
accuracy and stable temperature control in a test system.
Evaluation of the AD688 will produce curves similar to those in
Figure 11, but output readings may vary depending on the test
methods and equipment utilized.
KELVIN CONNECTIONS
E
– E
MIN
MAX
+10V OUTPUT SLOPE = T.C. =
=
Force and sense connections, also referred to as Kelvin
connections, offer a convenient method of eliminating the
effects of voltage drops in circuit wires. As seen in Figure 13a,
the load current and wire resistance produce an error (VERROR
R × IL) at the load. The Kelvin connection of Figure 13b
–6
(T
– T
) × 10 × 10
MIN
MAX
2.2mV – –3.2mV
(85°C – –40°C) × 10 × 10
= 3ppm/°C
–6
=
6
5
–10V OUT
overcomes the problem by including the wire resistance within
the forcing loop of the amplifier and sensing the load voltage.
The amplifier corrects for any errors in the load voltage. In the
circuit shown, the output of the amplifier would actually be at
10 V + VERROR and the voltage at the load would be the desired
10 V.
4
3
+10V E
MAX
2
SLOPE
1
0
–1
–2
–3
–4
–5
–6
+10V OUT
R
i = 0
+10V E
MIN
V = 10V
R
V = 10V – RI
R
R
L
+
–
R
I
LOAD
L
R
i = 0
10V
LOAD
I
L
–60 –50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
T
V = 10V + RI
L
a.
b.
Figure 13. Advantage of Kelvin Connection
T
TEMPERATURE (°C)
MAX
MIN
Figure 11. Typical AD688AQ Temperature Drift
The AD688 has three amplifiers which can be used to
implement Kelvin connections. Amplifier A2 is dedicated to the
ground force-sense function while uncommitted amplifiers A3
and A4 are free for other force-sense chores.
Each AD688A and B grade unit is tested at −40°C, −25°C, 0°C,
+25°C, +50°C, +70°C, and +85°C. This approach ensures that
the variations of output voltage that occur as the temperature
changes within the specified range will be contained within a
box whose diagonal has a slope equal to the maximum specified
drift. The position of the box on the vertical scale will change
from device to device as initial error and the shape of the curve
vary. Maximum height of the box for the appropriate
In some applications, one amplifier may be unused. In such
cases, the unused amplifier should be connected as a unity-gain
follower (force and sense pins tied together) and the input
should be connected to ground.
temperature range is shown in Figure 12.
An unused amplifier may be used for other circuit functions as
well. Figure 14 through Figure 19 show the typical performance
of A3 and A4.
Rev. B | Page 9 of 16
AD688
100
90
80
70
60
50
40
30
20
10
0
100
80
60
40
20
0
0
–30
–60
–90
–120
–150
–180
GAIN
PHASE
–20
10
1
10
100
1k
10k
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. A3, A4 Open-Loop Frequency Response
Figure 17. Input Noise Voltage Spectral Density
110
100
80
60
40
20
0
V
V
= ±15V
CM
S
= 1V p-p 25°C
50µs
5V
100
90
10
0%
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 15. A3, A4 CMR vs. Frequency
Figure 18. Unity-Gain Follower Pulse Response (Large Signal)
110
100
80
V
= ±15V WITH
S
1V p-p SINE WAVE
50mV
2µs
+SUPPLY
–SUPPLY
100
90
60
40
20
10
0%
10
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 16. A3, A4 PSR vs. Frequency
Figure 19. Unity-Gain Follower Pulse Response (Small Signal)
Rev. B | Page 10 of 16
AD688
A3 OR A4
DYNAMIC PERFORMANCE
V
OUT
The output buffer amplifiers (A3 and A4) are designed to
provide the AD688 with static and dynamic load regulation
superior to less complete references.
I
L
2k
Ω
2kΩ
+
10V
10V
0V
V
L
–
Many A/D and D/A converters present transient current loads
to the reference, and poor reference response can degrade the
converter’s performance.
Figure 23. Transient and Constant Load Test Circuit
1mV
200mV
1µs
Figure 20, Figure 21, and Figure 22 display the characteristic of
the AD688 output amplifier driving a 0 mA to 10 mA load.
V
100
90
OUT
1mV/CM
A3 OR A4
V
V
OUT
OUT
200mV/
I
1kΩ
10V
L
CM
10V
V
L
0V
10
0%
Figure 20. Transient Load Test Circuit
V
L
5V
5V
200mV
500ns
Figure 24. Transient Response 5 mA to 10 mA Load
100
90
In some applications, a varying load may be both resistive and
capacitive in nature, or may be connected to the AD688 by a
long capacitive cable. Figure 25 and Figure 26 display the output
amplifier characteristics driving a 1000 pF, 0 mA to 10 mA load.
V
OUT
10
V
OUT
1000pF
1kΩ
V
L
C
L
10V
10V
0V
V
L
Figure 21. Large-Scale Transient Response
Figure 25. Capacitive Load Transient Response Test Circuit
5V
2µs
1mV
200mV
1µs
100
90
100
90
C
= 0
L
V
OUT
C
=
L
1000pF
10
10
0%
0%
V
L
V
L
5V
Figure 22. Fine-Scale Settling for Transient Load
Figure 26. Output Response with Capacitive Load
Figure 23 and Figure 24 display the output amplifier
characteristic driving a 5 mA to 10 mA load, a common
situation found when the reference is shared among multiple
converters or is used to provide bipolar offset current.
Figure 27 and Figure 28 display the crosstalk between output
amplifiers. The top trace shows the output of A4, dc-coupled
and offset by 10 V, while the output of A3 is subjected to a 0 mA
to 10 mA load current step. The transient at A4 settles in about
1 µs, and the load-induced offset is about 100 µV.
Rev. B | Page 11 of 16
AD688
V
OUT
A3
A4
1kΩ
10V
+
+
100
90
V
10V
10V
–
IN
V
L
–
0V
Figure 27. Load Crosstalk Test Circuit
1mV
5V
2µs
V
10
OUT
0%
100
90
10V
1V
200µs
Figure 31. Output Amplifier Step Response Using Figure 30 Compensation
V
OUT
BRIDGE DRIVER CIRCUIT
The Wheatstone bridge is a common transducer. In its simplest
form, a bridge consists of four 2-terminal elements connected to
form a quadrilateral, a source of excitation connected along one
of the diagonals and a detector comprising the other diagonal.
10
0%
V
L
Figure 28. Load Crosstalk
In this unipolar drive configuration, the output voltage of the
bridge is riding on a common-mode voltage signal equal to
approximately VIN/2. Further processing of this signal may
necessarily be limited to high common-mode rejection
techniques such as instrumentation or isolation amplifiers.
However, if the bridge is driven from a pair of bipolar supplies,
then the common-mode voltage is ideally eliminated and the
restrictions on any processing elements that follow are relaxed.
Attempts to drive a large capacitive load (in excess of 1000 pF)
may result in ringing or oscillation, as shown in the step
response photo (Figure 29). This is due to the additional pole
formed by the load capacitance and the output impedance of
the amplifier, which consumes phase margin. The recom-
mended method of driving capacitive loads of this magnitude is
shown in Figure 30. The 150 Ω resistor isolates the capacitive
load from the output stage, while the 10 kΩ resistor provides a
dc feedback path and preserves the output accuracy. The 1 µF
capacitor provides a high frequency feedback loop. The
performance of this circuit is shown in Figure 31.
As shown in Figure 32, the AD688 is an excellent choice for the
control element in a bipolar bridge driver scheme. Transistors
Q1 and Q2 serve as series pass elements to boost the current
drive capability to the 57 mA required by the typical 350 Ω
bridge. A differential gain stage may still be required if the
bridge balance is not perfect.
100
90
+15V
V
IN
220Ω
Q
=
1
2N3904
7
4
6
3
1
V
A3
A4
OUT 10
0%
–
+
R
B
E
O
A1
R1
AD688
14
15
10V
1V
200µs
R4
220Ω
Q
=
2
Figure 29. Output Amplifier Step Response, CL = 1 µF
R2
2N3906
R5
10k
Ω
–15V
+V
1
µF
2
R6
S
R3
5
A2
16
–V
S
150
Ω
V
OUT
C
10
9
8
12
11
13
+
L
1µF
VIN
–
Figure 32. Bipolar Bridge Drive
Figure 30. Compensation for Capacitive Loads
Rev. B | Page 12 of 16
AD688
OUTLINE DIMENSIONS
0.005
(0.13)
MIN
0.098 (2.49)
MAX
0.310 (7.87)
0.220 (5.59)
16
9
8
1
PIN 1
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.290 (7.37)
0.200 (5.08)
0.840 (21.34) MAX
MAX
0.150 (3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15°
0°
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 33. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
BSC
× 45°
0.30 (0.0118)
0.10 (0.0039)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 34. 16-Lead Standard Small Outline Package [SOIC]
Wide Body
(RW-16)
Dimensions shown in millimeter and (inches)
ORDERING GUIDE
Initial
Error
Temperature
Model
Coefficient
3 ppm/°ꢀ
3 ppm/°ꢀ
8 ppm/°ꢀ
Temperature Range
−40°ꢀ to + 85°ꢀ
−40°ꢀ to + 85°ꢀ
−40°ꢀ to + 85°ꢀ
Package Description
16-Lead ꢀERDKP
16-Lead ꢀERDKP
16-Lead SOKꢀ
Package Option
Q-16
Q-16
AD688AQ
AD688BQ
AD688ARWZ1
5 mV
2 mV
4 mV
RW-16
1 Z = Pb-free part.
Rev. B | Page 13 of 16
AD688
NOTES
Rev. B | Page 14 of 16
AD688
NOTES
Rev. B | Page 15 of 16
AD688
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00815-0-3/05(B)
Rev. B | Page 16 of 16
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