AD698AP [ADI]
Universal LVDT Signal Conditioner; 通用LVDT信号调理器
| 型号： | AD698AP |
| 厂家： | 
ADI |
| 描述： | Universal LVDT Signal Conditioner |
| 文件： | 总12页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Universal
LVDT Signal Conditioner
a
AD698
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Single Chip Solution, Contains Internal Oscillator and
Voltage Reference
No Adjustm ents Required
Interfaces to Half-Bridge, 4-Wire LVDT
DC Output Proportional to Position
20 Hz to 20 kHz Frequency Range
Unipolar or Bipolar Output
Will Also Decode AC Bridge Signals
Outstanding Perform ance
VOLTAGE
REFERENCE
AMP
OSCILLATOR
AD698
B
A
B
AMP
FILTER
Linearity: 0.05%
A
Output Voltage: ؎11 V
Gain Drift: 20 ppm / ؇C (typ)
Offset Drift: 5 ppm / ؇C (typ)
P RO D UCT D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD698 is a complete, monolithic Linear Variable Differen-
tial T ransformer (LVDT ) signal conditioning subsystem. It is
used in conjunction with LVDT s to convert transducer mechan-
ical position to a unipolar or bipolar dc voltage with a high de-
gree of accuracy and repeatability. All circuit functions are
included on the chip. With the addition of a few external passive
components to set frequency and gain, the AD698 converts the
raw LVDT output to a scaled dc signal. T he device will operate
with half-bridge LVDT s, LVDT s connected in the series op-
posed configuration (4-wire), and RVDT s.
1. T he AD698 offers a single chip solution to LVDT signal
conditioning problems. All active circuits are on the mono-
lithic chip with only passive components required to com-
plete the conversion from mechanical position to dc voltage.
2. T he AD698 can be used with many different types of posi-
tion sensors. T he circuit is optimized for use with any
LVDT , including half-bridge and series opposed, (4 wire)
configurations. T he AD698 accommodates a wide range of
input and output voltages and frequencies.
3. T he 20 Hz to 20 kHz excitation frequency is determined by a
single external capacitor. T he AD698 provides up to 24 volts
rms to differentially drive the LVDT primary, and the
AD698 meets its specifications with input levels as low as
100 millivolts rms.
T he AD698 contains a low distortion sine wave oscillator to
drive the LVDT primary. T wo synchronous demodulation
channels of the AD698 are used to detect primary and second-
ary amplitude. T he part divides the output of the secondary by
the amplitude of the primary and multiplies by a scale factor.
T his eliminates scale factor errors due to drift in the amplitude
of the primary drive, improving temperature performance and
stability.
4. Changes in oscillator amplitude with temperature will not af-
fect overall circuit performance. T he AD698 computes the
ratio of the secondary voltage to the primary voltage to deter-
mine position and direction. No adjustments are required.
T he AD698 uses a unique ratiometric architecture to eliminate
several of the disadvantages associated with traditional ap-
proaches to LVDT interfacing. T he benefits of this new cir-
cuit are: no adjustments are necessary; temperature stability is
improved; and transducer interchangeability is improved.
5. Multiple LVDT s can be driven by a single AD698 either in
series or parallel as long as power dissipation limits are not
exceeded. T he excitation output is thermally protected.
6. T he AD698 may be used as a loop integrator in the design of
simple electromechanical servo loops.
T he AD698 is available in two performance grades:
7. T he sum of the transducer secondary voltages do not need to
be constant.
Gr ade
AD698AP
AD698SQ
Tem per atur e Range
–40°C to +85°C
–55°C to +125°C
P ackage
28-Pin PLCC
24-Pin Cerdip
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(@ T = +25؇C, V = 0 V, and V+, V– = ؎15 V dc, unless otherwise noted)
AD698–SPECIFICATIONS
A
CM
AD 698SQ
Typ
AD 698AP
Typ
P aram eter
Min
Max
Min
Max
1.65
Unit
A
B
T RANSFER FUNCT ION1
V
VOUT
=
× 500 µA × R2
OVERALL ERROR TMIN to TMAX
0.4
1.65
0.4
% of FS
SIGNAL OUT PUT CHARACT ERIST ICS
Output Voltage Range
Output Current, TMIN to T MAX
Short Circuit Current
Nonlinearity2 TMIN to TMAX
Gain Error3
؎11
؎11
V
mA
mA
11
20
75
0.1
20
0.02
5
100
11
20
75
0.1
20
0.02
5
100
؎500
؎1.0
؎100
؎1
؎500 ppm of FS
؎1.0 % of FS
؎100 ppm/°C of FS
Gain Drift
Output Offset
Offset Drift
؎1
؎25
% of FS
ppm/°C of FS
ppm/dB
؎25
Excitation Voltage Rejection4
Power Supply Rejection (±12 V to ±18 V)
PSRR Gain
50
15
300
100
50
15
300
100
ppm/V
ppm/V
PSRR Offset
Common-Mode Rejection (±3 V)
CMRR Gain
25
2
4
100
100
25
2
4
100
100
ppm/V
ppm/V
mV rms
CMRR Offset
Output Ripple5
EXCITATION OUTPUT CHARACTERISTICS (@ 2.5 kHz)
Excitation Voltage Range
Excitation Voltage (Resistors Are 1% Absolute Values)
(R1 = Open)6
2.1
24
2.1
24
V rms
1.2
2.6
14
2.15
4.35
21.2
1.2
2.6
14
2.15
4.35
21.2
V rms
V rms
V rms
ppm/°C
mA rms
mA rms
mA
(R1 = 12.7 kΩ)
(R1 = 487 Ω)
Excitation Voltage T C7
Output Current
100
50
40
100
50
40
30
30
T MIN to TMAX
Short Circuit Current
60
60
DC Offset Voltage (Differential, R1 = 12.7 kΩ)
T MIN to TMAX
30
؎100
30
؎100
mV
Frequency
20
20 k
20
20 k
Hz
Frequency T C
T otal Harmonic Distortion
200
–50
200
–50
ppm/°C
dB
SIGNAL INPUT CHARACT ERIST ICS
A/B Ratio Usable Full-Scale Range
Signal Voltage B Channel
Signal Voltage A Channel
Input Impedance
Input Bias Current (BIN, AIN)
Signal Reference Bias Current
Excitation Frequency
0.1
0.1
0.0
0.9
3.5
3.5
0.l
0.1
0.0
0.9
3.5
3.5
V rms
V rms
kΩ
µA
µA
200
1
2
200
1
2
5
10
20 k
5
10
20 k
0
0
Hz
POWER SUPPLY REQUIREMENT S
Operating Range
Dual Supply Operation (±10 V Output)
Single Supply Operation
13
±13
36
13
±13
36
V
V
0 V to +10 V Output
0 V to 10 V Output
17.5
17.5
17.5
17.5
V
V
Current (No Load at Signal and Excitation Outputs)
T MIN to TMAX
12
15
18
12
15
18
mA
mA
OPERAT ING T EMPERAT URE RANGE
–55
+125
–40
+85
°C
–2–
REV. B
AD698
NOT ES
1A and B represent the Mean Average Deviation (MAD) of the detected sine waves VA and VB. T he polarity of VOUT is affected by the sign of the A comparator, i.e.,
multiply VOUT × +1 for ACOMP+ > ACOMP–, and VOUT × –1 for ACOMP– > ACOMP+
.
2Nonlinearity of the AD698 only in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD698 output voltage from a
straight line. T he straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage.
3See T ransfer Function.
4For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm.
5Output ripple is a function of the AD698 bandwidth determined by C1 and C2. A 1000 pF capacitor should be connected in parallel with R2 to reduce the output
ripple. See Figures 7, 8 and 13.
6R1 is shown in Figures 7, 8 and 13.
7Excitation voltage drift is not an important specification because of the ratiometric operation of the AD698.
8From T MIN to T MAX the overall error due to the AD698 alone is determined by combining gain error, gain drift and offset drift. For example, the typical overall
error for the AD698AP from T MIN to T MAX is calculated as follows: Overall Error = Gain Error at +25°C (±0.2% Full Scale) + Gain Drift from –40°C to +25°C
(20 ppm/°C × 65°C) + Offset Drift from –40°C to +25°C (5 ppm/°C × 65°C) = ±0.36% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels.
All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
CO NNECTIO N D IAGRAMS
28-P in P LCC
ABSO LUTE MAXIMUM RATINGS
T otal Supply Voltage (+VS to –VS) . . . . . . . . . . . . . . . . . 36 V
Storage T emperature Range
P Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Q Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range
4
3
2
1
28 27 26
AD698SQ . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
AD698AP . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead T emperature Range (Soldering 60 sec) . . . . . . . . +300°C
Power Dissipation Derates above +65°C
P Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C
Q Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C
LEV1
LEV2
5
6
25 NC
24 SIG REF
FREQ1
FREQ2
NC
23
SIG OUT
7
AD698
TOP VIEW
(Not to Scale)
8
22 FEEDBACK
21 OUT FILT
20 AFILT1
9
BFILT1
BFILT2
10
11
TH ERMAL CH ARACTERISTICS
19 AFILT2
θJC
θJA
60°C/W
62°C/W
12
14 15 16 17 18
13
P Package 30°C/W
Q Package 26°C/W
NC = NO CONNECT
O RD ERING GUID E
24-P in Cerdip
Model
P ackage D escription
P ackage O ption
AD698AP
AD698SQ
28-Pin PLCC
24-Pin Double Cerdip
P-28A
Q-24A
–V
1
24
23
+V
S
S
EXC1
EXC2
2
3
OFFSET1
22 OFFSET2
21 SIG REF
LEV1
4
LEV2
5
20
19
18
17
SIG OUT
FEEDBACK
OUT FILT
AFILT1
AD698
TOP VIEW
(Not to Scale)
FREQ1
FREQ2
6
7
8
BFILT1
BFILT2
–BIN
9
16 AFILT2
10
11
12
15
14
–ACOMP
+ACOMP
+BIN
–AIN
13 +AIN
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD698 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD698
(at +25°C and V = ±15 V unless otherwise noted)
Typical Characteristics
S
240
120
80
200
160
40
GAIN PSRR 15–18V
120
80
20
0
40
20
GAIN PSRR 12–15V
–20
–40
–60
OFFSET PSRR 12–15V
0
OFFSET PSRR 15–18V
–20
–80
–60 –40 –20
–60 –40 –20
0
20
40
60
80
100 120 140
0
20
40
60
80
100 120 140
TEMPERATURE – °C
TEMPERATURE – °C
Figure 1. Gain and Offset PSRR vs. Tem perature
Figure 3. Typical Gain Drift vs. Tem perature
0
20
15
OFFSET CMRR ± 3V
–05
–10
–15
–20
–25
–30
10
5
0
–5
GAIN CMRR ± 3V
–10
–15
–20
–35
–40
–45
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE – °C
TEMPERATURE – °C
Figure 2. Gain and Offset CMRR vs. Tem perature
Figure 4. Typical Offset Drift vs. Tem perature
–4–
REV. B
AD698
TH EO RY O F O P ERATIO N
gain error in the output. T he AD698, eliminates these errors by
calculating the ratio of the LVDT output to its input excitation in
order to cancel out any drift effects. T his device differs from the
AD598 LVDT signal conditioner in that it implements a different
circuit transfer function and does not require the sum of the LVDT
secondaries (A + B) to be constant with stroke length.
A block diagram of the AD698 along with an LVDT (linear
variable differential transformer) connected to its input is shown
in Figure 5 below. T he LVDT is an electromechanical trans-
ducer—its input is the mechanical displacement of a core, and
its output is an ac voltage proportional to core position. T wo
popular types of LVDT s are the half-bridge type and the series
opposed or four-wire LVDT . In both types the moveable core
couples flux between the windings. T he series-opposed con-
nected LVDT transducer consists of a primary winding ener-
gized by an external sine wave reference source and two
secondary windings connected in the series opposed configuration.
T he output voltage across the series secondary increases as the core
is moved from the center. T he direction of movement is detected
by measuring the phase of the output. Half-bridge LVDT s have a
single coil with a center tap and work like an autotransformer. T he
excitation voltage is applied across the coil; the voltage at the center
tap is proportional to position. T he device behaves similarly to a
resistive voltage divider.
T he AD698 block diagram is shown below. T he inputs consist
of two independent synchronous demodulation channels. T he B
channel is designed to monitor the drive excitation to the LVDT .
T he full wave rectified output is filtered by C2 and sent to the
computational circuit. Channel A is identical except that the
comparator is pinned out separately. Since the A channel may
reach 0 V output at LVDT null, the A channel demodulator is
usually triggered by the primary voltage (B Channel). In addi-
tion, a phase compensation network may be required to add a
phase lead or lag to the A Channel to compensate for the LVDT
primary to secondary phase shift. For half-bridge circuits the
phase shift is noncritical, and the A channel voltage is large
enough to trigger the demodulator.
C2
+V
VOLTAGE
REFERENCE
BFILT1
BFILT2
S
AMP
OSCILLATOR
B
C5
R2
AD698
CHANNEL
B
–BIN
+BIN
±1
A
B
V/I
OUT
FILTER
FILTER
FB
AMP
V
OUT
C4
FILTER
A
COMP
DUTY CYCLE
DIVIDER
A/B = 1 = 100%
DUTY
A
B
–ACOMP
COMP
V/I
Figure 5. Functional Block Diagram
+ACOMP
–AIN
OFF 1
OFF 2
FILTER
T he AD698 energizes the LVDT coil, senses the LVDT output
voltages and produces a dc output voltage proportional to core
position. T he AD698 has a sine wave oscillator and power am-
plifier to drive the LVDT . T wo synchronous demodulation
stages are available for decoding the primary and secondary
voltages. A decoder determines the ratio of the output signal
voltage to the input drive voltage (A/B). A filter stage and out-
put amplifier are used to scale the resulting output.
IREF
500µA
V
±1
+AIN
DEMODULATOR
AD698
A
CHANNEL
AFILT1
AFILT2
–V
S
C3
Figure 6. AD698 Block Diagram
T he oscillator comprises a multivibrator that produces a triwave
output. T he triwave drives a sine shaper that produces a low dis-
tortion sine wave. Frequency and amplitude are determined by a
single resistor and capacitor. Output frequency can range from
20 Hz to 20 kHz and amplitude from 2 V to 24 V rms. T otal har-
monic distortion is typically –50 dB.
Once both channels are demodulated and filtered a division cir-
cuit, implemented with a duty cycle multiplier, is used to calcu-
late the ratio A/B. T he output of the divider is a duty cycle.
When A/B is equal to 1, the duty cycle will be equal to 100%.
(T his signal can be used as is if a pulse width modulated output
is required.) T he duty cycle drives a circuit that modulates and
filters a reference current proportional to the duty cycle. T he
output amplifier scales the 500 µA reference current converting
it to a voltage. T he output transfer function is thus:
T he AD698 decodes LVDT s by synchronously demodulating
the amplitude modulated input (secondaries), A, and a fixed in-
put reference (primary or sum of secondaries or fixed input), B.
A common problem with earlier solutions was that any drift in
the amplitude of the drive oscillator corresponded directly to a
VOUT = IREF × A/B × R2, where IREF = 500 µA
REV. B
–5–
AD698
CO NNECTING TH E AD 698
3. Select a suitable LVDT that will operate with an excitation
frequency of 2.5 kHz. T he Schaevitz E100, for instance, will
operate over a range of 50 Hz to 10 kHz and is an eligible
candidate for this example.
T he AD698 can easily be connected for dual or single supply
operation as shown in Figures 7, 8 and 13. T he following gen-
eral design procedures demonstrate how external component
values are selected and can be used for any LVDT that meets
AD698 input/output criteria. T he connections for the A and B
channels and the A channel comparators will depend on which
transducer is used. In general follow the guidelines below.
4. Select excitation frequency determining component C1.
C1 = 35 µF Hz/fEXCITATION
Parameters set with external passive components include: exci-
tation frequency and amplitude, AD698 input signal frequency,
and the scale factor (V/inch). Additionally, there are optional
features; offset null adjustment, filtering, and signal integration,
which can be implemented by adding external components.
+15V
–15V
6.8µF
100nF
100nF
6.8µF
–V
1
2
24
S
+V
S
AD698
R4
R3
23
EXC1
EXC2
LEV1
LEV2
OFFSET1
OFFSET2
SIG REF
SIG OUT
22
21
20
3
4
SIGNAL
REFERENCE
+15V
–15V
6.8µF
100nF
R
L
R1
C1
C2
100nF
6.8µF
5
V
R2
OUT
–V
1
2
24
S
+V
S
6
AD698
FREQ1 FEEDBACK 19
R4
R3
C4
1000pF
23
EXC1
EXC2
LEV1
LEV2
OFFSET1
OFFSET2
SIG REF
SIG OUT
18
OUT FILT
7
FREQ2
BFILT1
BFILT2
–BIN
22
21
20
3
4
SIGNAL
REFERENCE
8
AFILT1 17
AFILT2 16
C3
9
R
R1
L
5
V
R2
33kΩ
10
11
15
–ACOMP
+ACOMP 14
13
OUT
6
FREQ1 FEEDBACK 19
+BIN
C1
1000pF
C4
A
B
15nF
18
OUT FILT
7
FREQ2
BFILT1
BFILT2
–BIN
12 –AIN
+AIN
PHASE
LAG/LEAD
NETWORK
8
AFILT1 17
AFILT2 16
C3
C2
9
1M
10
11
15
–ACOMP
+ACOMP 14
13
D
C
+BIN
PHASE LEAD
PHASE LAG
A
12 –AIN
+AIN
A
B
B
PHASE LAG = Arc Tan (Hz RC);
C
R
R
T
S
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = R // (R + R )
R
S
S
T
T
C
R
C
R
S
S
Figure 7. Interconnection Diagram for Half-Bridge LVDT
and Dual Supply Operation
C
D
C
D
Figure 8. AD698 Interconnection Diagram for Series
Opposed LVDT and Dual Supply Operation
D ESIGN P RO CED URE
D UAL SUP P LY O P ERATIO N
Figure 7 shows the connection method for half-bridge LVDT s.
Figure 8 demonstrates the connections for 3- and 4-wire
LVDT s connected in the series opposed configuration. Both ex-
B. D eter m ine the O scillator Am plitude
Amplitude is set such that the primary signal is in the 1.0 V to
3.5 V rms range and the secondary signal is in the 0.25 V to
3.5 V rms range when the LVDT is at its mechanical full-scale
position. T his optimizes linearity and minimizes noise suscepti-
bility. Since the part is ratiometric, the exact value of the excita-
tion is relatively unimportant.
amples use dual ±15 volt power supplies.
A. D eter m ine the O scillator Fr equency
Frequency is often determined by the required BW of the sys-
tem. However, in some systems the frequency is set to match
the LVDT zero phase frequency as recommended by the
manufacturer; in this case skip to Step 4.
5. Determine optimum LVDT excitation voltage, VEXC. For a
4-wire LVDT determine the voltage transformation ratio,
VT R, of the LVDT at its mechanical full scale. VT R =
LVDT sensitivity × Maximum Stroke Length from null.
1. Determine the mechanical bandwidth required for LVDT
position measurement subsystem, fSUBSYST EM. For this ex-
ample, assume fSUBSYST EM = 250 Hz.
LVDT sensitivity is listed in the LVDT manufacturer’s cata-
log and has units of volts output per volts input per inch dis-
placement. T he E100 has a sensitivity of 2.4 mV/V/mil. In
the event that LVDT sensitivity is not given by the manufac-
turer, it can be computed. See section on determining LVDT
sensitivity.
2. Select minimum LVDT excitation frequency approximately
10 × fSUBSYSTEM. Therefore, let excitation frequency = 2.5 kHz.
–6–
REV. B
AD698
Multiply the primary excitation voltage by the VT R to get
the expected secondary voltage at mechanical full scale. For
example, for an LVDT with a sensitivity of 2.4 mV/V/mil and
a full scale of ±0.1 inch, the VT R = 0.0024 V/V/Mil × 100
mil = 0.24. Assuming the maximum excitation of 3.5 V rms,
the maximum secondary voltage will be 3.5 V rms × 0.24 =
0.84 V rms, which is in the acceptable range.
b. Full-scale core displacement from null, d
S × d = VT R and also equals the ratio A/B at mechanical full
scale. T he VT R should be converted to units of V/V.
For a full-scale displacement of d inches, voltage out of the
AD698 is computed as
VOUT = S × d × 500 µA × R2
Conversely the VT R may be measured explicitly. With the
LVDT energized at its typical drive level VPRI, as indicated
by the manufacturer, set the core displacement to its me-
chanical full-scale position and measure the output VSEC of
the secondary. Compute the LVDT voltage transformation
ratio, VT R. VTR = VSEC//VPRI. For the E100, VSEC = 0.72 V
for VPRI = 3 V. VT R = 0.24.
VOUT is measured with respect to the signal reference,
Pin 21, shown in Figure 7.
Solving for R2,
VOUT
S × d × 500 µA
R2 =
(1)
For VOUT = ±10 V full-scale range (20 V span) and d = ±0.1
inch full-scale displacement (0.2 inch span)
For situations where LVDT sensitivity is low, or the me-
chanical FS is a small fraction of the total stroke length, an
input excitation of more than 3.5 V rms may be needed. In
this case a voltage divider network may be placed across the
LVDT primary to provide smaller voltage for the +BIN and
–BIN input. If, for example, a network was added to divide
the B Channel input by 1/2, then the VT R should also be re-
duced by 1/2 for the purpose of component selection.
20V
R2 =
= 83. 3 kΩ
2. 4 × 0.2 × 500 µA
VOUT as a function of displacement for the above example is
shown in Figure 10.
VOUT (VOLTS)
Check the power supply voltages by verifying that the peak
values of VA and VB are at least 2.5 volts less than the volt-
ages at +VS and –VS.
+10
+0.1d (INCHES)
–0.1
6. Referring to Figure 9, for VS = ±15 V, select the value of the
amplitude determining component R1 as shown by the curve
in Figure 9.
–10
Figure 10. VOUT (±10 V Full Scale) vs. Core Displace-
m ent (±0.1 Inch)
30
25
20
E. O ptional O ffset of O utput Voltage Swing
9. Selections of R3 and R4 permit a positive or negative output
voltage offset adjustment.
1
1
VOS = 1. 2 V × R2 ×
–
(2)
4
R3 + 2 kΩ
R
+ 2 kΩ
15
V rms
For no offset adjustment R3 and R4 should be open circuit.
10
5
T o design a circuit producing a 0 V to +10 V output for a
displacement of +0.1 inch, set VOUT to +10 V, d = 0.2 inch
and solve Equation (1) for R2.
V
(VOLTS)
OUT
+5
0
0.01
0.1
1
10
100
1k
R1 – kΩ
+0.1d (INCHES)
–0.1
Figure 9. Excitation Voltage VEXC vs. R1
–5
7. C2, C3 and C4 are a function of the desired bandwidth of
the AD698 position measurement subsystem. T hey should
be nominally equal values.
Figure 11. VOUT (±5 V Full Scale) vs. Core Displacem ent
(±0.1 Inch)
C2 = C3 = C4 = 10–4 Farad Hz/f5UBSYSTEM (Hz)
If the desired system bandwidth is 250 Hz, then
C2 = C3 = C4 = 10-4 Farad Hz/250 Hz = 0.4 µF
T his will produce a response shown in Figure 11.
In Equation (2) set VOS = 5 V and solve for R3 and R4. Since a
positive offset is desired, let R4 be open circuit. Rearranging
Equation (2) and solving for R3
See Figures 14, 15 and 16 for more information about
AD698 bandwidth and phase characterization.
1. 2 × R2
VOS
R3 =
– 2 kΩ = 7.02 kΩ
D . Set the Full-Scale O utput Voltage
8. T o compute R2, which sets the AD698 gain or full-scale
output range, several pieces of information are needed:
a. LVDT sensitivity, S
REV. B
–7–
AD698
11. T he voltage drop across R5 must be greater than
Note that VOS should be chosen so that R3 cannot have negative
value .
1. 2 V
VOUT
2 +10 kΩ
T herefore
+ 250 µA +
Volts
Figure 12 shows the desired response.
R 4 + 2 k Ω
4 × R2
VOUT (VOLTS)
+10
+5
1. 2 V
R 4 + 2 k Ω
100 µA
VOUT
4 × R2
2 +10 kΩ
+ 250 µA +
+0.1d (INCHES)
–0.1
R5 ≥
Ohms
Based upon the constraints of R5 + R6 (Step 10) and R5 (Step
11), select an interim value of R6.
Figure 12. VOUT (0 V–10 V Full Scale) vs. Displacem ent
12. Load current through RL returns to the junction of R5 and
R6, and flows back to VPS. Under maximum load condi-
tions, make sure the voltage drop across R5 is met as de-
fined in Step 11.
(±0.1 Inch)
D ESIGN P RO CED URE
SINGLE SUP P LY O P ERATIO N
Figure 13 shows the single supply connection method.
As a final check on the power supply voltages, verify that
the peak values of VA and VB are at least 2.5 volts less than
the voltage between +VS and –VS.
+30V
R5
R6
0.1µF
C5
6.8µF
V
ps
13. C5 is a bypass capacitor in the range of 0.1 µF to 1 µF.
Gain P hase Char acter istics
–V
T o use an LVDT in a closed-loop mechanical servo application,
it is necessary to know the dynamic characteristics of the trans-
ducer and interface elements. T he transducer itself is very quick
to respond once the core is moved. T he dynamics arise prima-
rily from the interface electronics. Figures 14, 15 and 16 show
the frequency response of the AD698 LVDT Signal Conditioner.
Note that Figures 15 and 16 are basically the same; the differ-
ence is frequency range covered. Figure 15 shows a wider range
of mechanical input frequencies at the expense of accuracy.
1
2
24
23
22
21
20
+V
S
S
AD698
R4
R3
EXC1
EXC2
LEV1
LEV2
OFFSET1
OFFSET2
SIG REF
SIG OUT
3
4
SIGNAL
REFERENCE
R
L
R1
5
V
R2
OUT
6
FREQ1 FEEDBACK 19
C4
C1
C2
1000pF
18
OUT FILT
7
FREQ2
BFILT1
BFILT2
–BIN
8
AFILT1 17
AFILT2 16
10
0
C3
9
10
11
15
–ACOMP
+ACOMP 14
13
–10
+BIN
0.1µF
2.0µF
A
B
–20
–30
12 –AIN
+AIN
PHASE
LAG/LEAD
NETWORK
1M
0.33µF
–40
D
C
–50
–60
PHASE LEAD
PHASE LAG
A
B
A
B
R2 = 81kΩ
–70
f
= 2.5kHz
C
EXC
R
R
PHASE LAG = Arc Tan (Hz RC);
T
S
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = R // (R + R )
R
T
C
R
S
C
R
S
S
S
T
0
–60
C
D
C
D
0.1µF
–120
–180
–240
–300
–360
–420
2.0µF
0.33µF
Figure 13. Interconnection Diagram for Single Supply
Operation
For single supply operation, repeat Steps 1 through 10 of the
design procedure for dual supply operation. R5, R6 and C5 are
additional component values to be determined. VOUT is mea-
sured with respect to SIGNAL REFERENCE.
R2 = 81kΩ
f
= 2.5kHz
EXC
10. Compute a maximum value of R5 and R6 based upon the
relationship
0
100
FREQUENCY – Hz
1k
10k
R5 + R6 ≤ VPS/100 µA
Figure 14. Gain and Phase Characteristics vs. Frequency
(0 kHz–10 kHz)
–8–
REV. B
AD698
10
0
Figure 16 shows a more limited frequency range with enhanced
accuracy. T he figures are transfer functions with the input to be
considered as a sinusoidally varying mechanical position and the
output as the voltage from the AD698; the units of the transfer
function are volts per inch. T he value of C2, C3, and C4, from
Figure 7, are all equal and designated as a parameter in the fig-
ures. T he response is approximately that of two real poles.
However, there is appreciable excess phase at higher frequen-
cies. An additional pole of filtering can be introduced with a
shunt capacitor across R2, Figure 7; this will also increase phase
lag.
0.033µF
–10
–20
–30
–40
–50
–60
–70
0
0.1µF
0.01µF
R2 = 81kΩ
= 10kHz
f
EXC
When selecting values of C2, C3 and C4 to set the bandwidth of
the system, a trade-off is involved. T here is ripple on the “dc”
position output voltage, and the magnitude is determined by the
filter capacitors. Generally, smaller capacitors will give higher
system bandwidth and larger ripple. Figures 17 and 18 show the
magnitude of ripple as a function of C2, C3 and C4, again all
equal in value. Note also a shunt capacitor across R2, Figure 7,
is shown as a parameter. T he value of R2 used was 81 kΩ with a
Schaevitz E100 LVDT .
0.033µF
–60
–120
–180
–240
–300
–360
–420
0.01µF
0.1µF
1k
R2 = 81kΩ
f
= 10kHz
EXC
100
0
100
1k
FREQUENCY – Hz
10k
100k
10
1
Figure 15. Gain and Phase Characteristics vs. Frequency
(0 kHz–50 kHz)
10
2.5kHz, C
2.5kHz, C
1nF
0.01µF
SHUNT
0
10nF
SHUNT
0.1
0.01
–10
–20
–30
–40
–50
–60
–70
0.033µF
0.1
1
10
C2, C3, C4; C2 = C3 = C4 – µF
Figure 17. Output Voltage Ripple vs. Filter Capacitance
0.1µF
1k
R2 = 81kΩ
= 10kHz
f
EXC
100
10
0.01µF
0
–60
1
10kHz, C
10kHz, C
1nF
SHUNT
0.1µF
–120
–180
–240
–300
–360
10nF
0.033µF
SHUNT
0.1
0.001
0.01
0.1
1
10
R2 = 81kΩ
= 10kHz
C2, C3, C4; C2 = C3 = C4 – µF
f
EXC
Figure 18. Output Voltage Ripple vs. Filter Capacitance
0
100
FREQUENCY – Hz
1k
10k
Figure 16. Gain and Phase Characteristics vs. Frequency
(0 kHz–10 kHz)
REV. B
–9–
AD698
D eter m ining LVD T Sensitivity
– Low Cost Setpoint Controller
LVDT sensitivity can be determined by measuring the LVDT
secondary voltages as a function of primary drive and core posi-
tion, and performing a simple computation.
– Mechanical Follower Servo Loop
– Differential Gaging and Precision Differential Gaging
AC BRID GE SIGNAL CO ND ITIO NER
Energize the LVDT at its recommended primary drive level,
VPRI (3 V rms for the E100). Set the core displacement to its
mechanical full-scale position and measure secondary voltages
VA and VB.
Bridge circuits which use dc excitation are often plagued by er-
rors caused by thermocouple effects, 1/f noise, dc drifts in the
electronics, and line noise pickup. One way to get around these
problems is to excite the bridge with an ac waveform, amplify
the bridge output with an ac amplifier, and synchronously de-
modulate the resulting signal. T he ac phase and amplitude in-
formation from the bridge is recovered as a dc signal at the
output of the synchronous demodulator. T he low frequency
system noise, dc drifts, and demodulator noise all get mixed to
the carrier frequency and can be removed by means of a low-
pass filter.
VSECONDARY
Sensitivity =
VPRI × d
From Figure 19,
0.72
Sensitivity =
= 2.4 mV /V mil
3 V × 100 mils
T he AD698 with the addition of a simple ac gain stage can be
used to implement an ac bridge. Figure 20 shows the connec-
tions for such a system. T he AD698 oscillator provides ac
excitation for the bridge. T he low level bridge signal is amplified
by the gain stage created by A1, A2 to provide a differential in-
put to the A Channel of the AD698. T he signal is then synchro-
nously detected by A Channel. T he B Channel is used to detect
the level of the bridge excitation. T he ratio of A/B is then calcu-
lated and converted to an output voltage by R2. An optional
phase lag/lead network can be added in front of the A compara-
tor to adjust for phase delays through the bridge and the ampli-
fier, or if the phase delay is small, it can be ignored or compensated
for by a gain adjustment.
VSEC WHEN VPRI 3V rms
VA
1.71V rms
0.99V rms
VB
d = –100 mils
d = 0
d = +100 mils
Figure 19. LVDT Secondary Voltage vs. Core
Displacem ent
T his circuit can be used for resistive bridges such as strain
gages, or for inductive or capacitive bridges that are commonly
used for pressure or flow sensors. T he low level signal outputs of
these sensors are susceptible to noise and interference and are
good candidates for ac signal processing techniques.
Ther m al Shutdown and Loading Consider ations
T he AD698 is protected by a thermal overload circuit. If the die
temperature reaches 165°C, the sine wave excitation amplitude
gradually reduces, thereby lowering the internal power dissipa-
tion and temperature.
Com ponent Selection
Amplifiers A1, A2 will be chosen depending on the type of
bridge that is conditioned. Capacitive bridges should use an
amplifier with low bias current; a large bleeder resistor will be
required from the amplifier inputs to ground to provide a path
for the dc bias current. Resistive and inductive bridges can use a
more general purpose amplifier. T he dc performance of A1, A2
are not as important as their ac performance. DC errors such as
voltage offset will be chopped out by the AD698 since they are
not synchronous to the carrier frequency.
Due to the ratiometric operation of the decoder circuit, only
small errors result from the reduction of the excitation ampli-
tude. Under these conditions the signal-processing section of
the AD698 continues to meet its output specifications.
T he thermal load depends upon the voltage and current deliv-
ered to the load as well as the power supply potentials. An
LVDT Primary will present an inductive load to the sine wave
excitation. T he phase angle between the excitation voltage and
current must also be considered, further complicating thermal
calculations.
T he oscillator amplitude and span resistor for the AD698 may
be chosen by first computing the transfer function or sensitivity
of the bridge and the ac amplifier. T his ratio will correspond to
the A/B term in the AD698 transfer function. For example, sup-
pose that a resistive strain gage with a sensitivity, S, of 2 mV/V
at full scale is used. Select an arbitrary target value for A/B that
is close to its maximum value such as A/B = 0.8. T hen choose a
gain for the ac amplifier so that the strain gage transfer function
from excitation to output also equals 0.8. T hus the required am-
plifier gain will be [A/B]/ S; or 0.8/ 0.002 V/V = 400. T hen
select values for RS and RG. For the gain stage:
AP P LICATIO NS
Most of the applications for the AD598 can also be imple-
mented with the AD698. Please refer to the applications written
for the AD598 for a detailed explanation.
See AD598 data sheet for:
– Proving Ring-Weigh Scale
– Synchronous Operation of Multiple LVDT s
– High Resolution Position-to-Frequency Circuit
–10–
REV. B
AD698
Since A/B is known, the value of R2, the output FS resistor may
be chosen by the formula:
2 × RS
RG +1
VOUT
=
×VIN
VOUT = A/B × 500 µA × R2
For a 10 V output at FS, with an A/B of 0.8; solve for R2.
R2 = 10 V [0.8 × 500 µA] = 25.0 kΩ
Solving for VOUT /VIN = 400 and setting RG = 100 Ω then:
RS = [400 – 1] × RG/2 = 19.95 kΩ
Choose an oscillator amplitude that is in the range of 1 V to
3.5 V rms. For an input excitation level of 3 V rms, the output
signal from the amplifier gain stage will be 3.5 V rms × 0.8 V or
2.4 V rms, which is in the acceptable range.
T his will result in a VOUT of 10 V for a full-scale signal from the
bridge. T he other components, C1, C2, C3, C4 may be selected
by following the guidelines on general device operation men-
tioned earlier.
If a gain trim is required, then a trim resistor can be used to ad-
just either R2 or RG. Bridge offsets should be adjusted by a trim
network on the OFFSET 1 and OFFSET 2 pins of the AD698.
+15V
–15V
6.8µF
100nF
6.8µF
100nF
–V
1
2
24
23
22
21
20
+V
S
S
AD698
R4
R3
EXC1
OFFSET1
OFFSET2
SIG REF
SIG OUT
3
4
EXC2
LEV1
LEV2
SIGNAL
REFERENCE
R
L
R1
C1
C2
5
V
R2
OUT
6
FREQ1 FEEDBACK 19
C4
1000pF
RESISTORS,
INDUCTORS
OR CAPACITORS
18
OUT FILT
7
FREQ2
BFILT1
BFILT2
–BIN
8
AFILT1 17
AFILT2 16
C3
9
10
11
15
–ACOMP
+ACOMP 14
13
A1
+BIN
PHASE LEAD
PHASE LAG
R
S
A
B
A
B
A
B
12 –AIN
+AIN
C
R
R
PHASE
LAG/LEAD
NETWORK
T
R
G
R
S
S
R
T
C
R
C
R
S
S
D
C
A2
C
D
C
D
DUAL
OP AMP
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = R // (R + R )
S
S
T
Figure 20. AD698 Interconnection Diagram for AC Bridge Applications
REV. B
–11–
AD698
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
24-P in Cerdip (Wide)
0.005 (0.13) MIN
24
0.098 (2.49) MAX
13
0.610 (15.5)
0.520 (13.2)
PIN 1
1
12
0.620 (15.75)
0.590 (15.00)
1.280 (32.51) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
15
°
0°
SEATING
PLANE
0.023 (0.58)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.014 (0.36)
28-P in P LCC
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
4
26
PIN 1
IDENTIFIER
5
25
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
0.430 (10.92)
0.390 (9.91)
TOP VIEW
0.032 (0.81)
0.026 (0.66)
19
11
12
18
0.020
0.040 (1.01)
0.025 (0.64)
(0.50)
R
0.456 (11.58)
0.450 (11.43)
SQ
SQ
0.110 (2.79)
0.085 (2.16)
0.495 (12.57)
0.485 (12.32)
–12–
REV. B
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