AD708JNZ [ADI]
Ultralow Offset Voltage Dual Op Amp; 超低失调电压双通道运算放大器
| 型号： | AD708JNZ |
| 厂家： | 
ADI |
| 描述： | Ultralow Offset Voltage Dual Op Amp |
| 文件： | 总16页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Offset Voltage
Dual Op Amp
AD708
FEATURES
PIN CONFIGURATION
Very high dc precision
30 μV maximum offset voltage
0.3 μV/°C maximum offset voltage drift
0.35 μV p-p maximum voltage noise (0.1 Hz to 10 Hz)
5 million V/V minimum open-loop gain
130 dB minimum CMRR
AD708
OUTPUT A
–IN A
1
2
3
4
8
7
6
5
+V
S
OUTPUT B
–IN B
–A
+IN A
+
B –
–V
+
+IN B
S
TOP VIEW
(Not to Scale)
120 dB minimum PSRR
Matching characteristics
Figure 1. PDIP (N) and CERDIP (Q) Packages
30 μV maximum offset voltage match
0.3 μV/°C maximum offset voltage drift match
130 dB minimum CMRR match
Available in 8-lead narrow body, PDIP, and
hermetic CERDIP and CERDIP/883B packages
GENERAL DESCRIPTION
The AD708 is a high precision, dual monolithic operational
amplifier. Each amplifier individually offers excellent dc
precision with maximum offset voltage and offset voltage drift
of any dual bipolar op amp.
The AD708S is rated over the military temperature range of
−55°C to +125°C and is available in a CERDIP military version
processed to MIL-STD-883B.
PRODUCT HIGHLIGHTS
The matching specifications are among the best available in any
dual op amp. In addition, the AD708 provides 5 V/μV mini-
mum open-loop gain and guaranteed maximum input voltage
noise of 350 nV p-p (0.1 Hz to 10 Hz). All dc specifications
show excellent stability over temperature, with offset voltage
drift typically 0.1 μV/°C and input bias current drift of
25 pA/°C maximum.
1. The combination of outstanding matching and individual
specifications make the AD708 ideal for constructing high
gain, precision instrumentation amplifiers.
2. The low offset voltage drift and low noise of the AD708
allow the designer to amplify very small signals without
sacrificing overall system performance.
The AD708 is available in four performance grades. The
AD708J is rated over the commercial temperature range of
0°C to 70°C and is available in a narrow body, PDIP. The
AD708A and AD708B are rated over the industrial temperature
range of −40°C to +85°C and are available in a CERDIP.
3. The AD708 10 V/ꢀV typical open-loop gain and 140 dB
common-mode rejection make it ideal for precision
applications.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD708
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 10
Crosstalk Performance .............................................................. 10
Operation with a Gain of −100................................................. 11
High Precision Programmable Gain Amplifier ..................... 11
Bridge Signal Conditioner......................................................... 12
Precision Absolute Value Circuit ............................................. 12
Selection of Passive Components............................................. 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Matching Characteristics............................................................. 9
REVISION HISTORY
1/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Removed TO-99 Package ..................................................Universal
Deleted AD707 References................................................Universal
Deleted LT1002 Reference............................................................... 1
Deleted Figure 1................................................................................ 1
Deleted Metalization Photograph .................................................. 5
Moved Figure 25, Figure 26, and Figure 27
to Theory of Operation section .................................................... 10
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 13
2/91—Rev. A to Rev. B
Rev. C | Page 2 of 16
AD708
SPECIFICATIONS
@ 25°C and 15 V dc, unless otherwise noted.
Table 1.
AD708J/AD708A
AD708B
AD708S
Parameter
INPUT OFFSET VOLTAGE2
Conditions
TMIN to TMAX
Min1 Typ Max1 Min1 Typ Max1 Min1 Typ Max1 Unit
30
50
0.3
0.3
1.0
2.0
15
0.5
2.0
2
5
5
μV
μV
μV/°C
μV/month
nA
nA
pA/°C
nA
nA
pA/°C
100
150
1.0
50
65
0.4
30
50
0.3
15
0.1
0.3
0.5
1.0
10
0.1
0.2
1
15
0.1
0.3
0.5
1.0
10
0.1
0.2
1
Drift
Long Term Stability
INPUT BIAS CURRENT
2.5
4.0
40
1.0
2.0
25
1
4
30
1
1.5
25
TMIN to TMAX
Average Drift
OFFSET CURRENT
VCM = 0 V
TMIN to TMAX
2.0
4.0
60
1.0
1.5
25
Average Drift
MATCHING CHARACTERISTICS3
Offset Voltage
50
μV
80
30
TMIN to TMAX
150
1.0
4.0
5.0
75
μV
μV/°C
nA
nA
dB
dB
dB
dB
dB
50
Offset Voltage Drift
Input Bias Current
0.4
1.0
2.0
0.3
1.0
2.0
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
Common-Mode Rejection
Power Supply Rejection
140
140
140
120
110
110
110
135
130
130
120
120
140
130
130
120
120
140
Channel Separation
INPUT VOLTAGE NOISE
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
0.23 0.6
10.3 18
10.0 13.0
0.23 0.6
10.3 12
10.0 11.0
0.23
10.3 12
10.0 11
9.6
14
0.32 0.8
0.14 0.23
0.12 0.17
140
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
pA p-p
pA/√Hz
pA/√Hz
pA/√Hz
dB
0.35
9.6
14
11.0
35
9.6
14
11.0
35
11
35
INPUT CURRENT NOISE
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
0.32 0.9
0.14 0.27
0.12 0.18
140
0.32 0.8
0.14 0.23
0.12 0.17
140
COMMON-MODE REJECTION RATIO VCM = 13 V
TMIN to TMAX
120
120
130
130
130
130
140
140
140
dB
OPEN-LOOP GAIN
VO = 10 V
RLOAD ≥ 2 kΩ
TMIN to TMAX
10
10
10
10
10
7
V/μV
V/μV
dB
3
3
5
5
4
4
POWER SUPPLY REJECTION RATIO
VS = 3 V to 18 V
TMIN to TMAX
130
130
130
130
130
130
110
110
120
120
120
120
dB
FREQUENCY RESPONSE
Closed-Loop Bandwidth
Slew Rate
0.5
0.15
0.9
0.3
0.5
0.15
0.9
0.3
0.5
0.15
0.9
0.3
MHz
V/μs
INPUT RESISTANCE
Differential
60
200
200
400
200
400
MΩ
GΩ
Common Mode
Rev. C | Page 3 of 16
AD708
AD708J/AD708A
AD708B
AD708S
Parameter
Conditions
RLOAD ≥ 10 kΩ
RLOAD ≥ 2 kΩ
RLOAD ≥ 1 kΩ
TMIN to TMAX
Min1 Typ Max1 Min1 Typ Max1 Min1 Typ Max1 Unit
OUTPUT VOLTAGE
14
14.0
13.0
12.5
13.0
60
14
13
12.5
13
V
V
V
V
13.5
12.5
12.0
12.0
13.5
12.5
12.0
12.0
13.5
12.5
12.0
12.0
13.0
12.5
13.0
60
OPEN-LOOP OUTPUT RESISTANCE
POWER SUPPLY
60
Ω
Quiescent Current
Power Consumption
4.5
135
12
5.5
165
18
4.5
135
12
5.5
165
18
4.5
135
12
5.5
165
18
mA
mW
mW
V
VS = 15 V
VS = 3 V
Operating Range
3
18
3
18
3
18
1 All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to
calculate outgoing quality levels.
2 Input offset voltage specifications are guaranteed after five minutes of operation at TA = 25°C.
3 Matching is defined as the difference between parameters of the two amplifiers.
Rev. C | Page 4 of 16
AD708
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
Parameter
Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Supply Voltage
Internal Power Dissipation1
Input Voltage2
22 V
VS
Output Short-Circuit Duration
Differential Input Voltage
Storage Temperature Range (Q)
Storage Temperature Range (N)
Lead Temperature (Soldering 60 sec)
Indefinite
+VS and −VS
−65°C to +150°C
−65°C to +125°C
300°C
1 Thermal Characteristics
8-lead PDIP: θJC = 33°C/W, θJA = 100°C/W
8-lead CERDIP: θJC = 30°C/W, θJA = 110°C/W
2 For supply voltages less than 22 V, the absolute maximum input voltage is
equal to the supply voltage.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 5 of 16
AD708
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 15 V and TA = 25°C, unless otherwise noted.
+V
S
8
7
6
5
4
3
2
1
0
–0.5
+V
–1.0
–1.5
1.5
1.0
–V
0.5
–V
S
0
5
10
15
20
25
0
3
6
9
12
15
18
21
24
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
Figure 2. Input Common-Mode Range vs. Supply Voltage
Figure 5. Supply Current vs. Supply Voltage
+V
100
90
80
70
60
50
40
30
20
10
0
S
256 UNITS TESTED
–55°C TO +125°C
–0.5
+V
OUT
–1.0
–1.5
R
R
= 10kΩ
= 2kΩ
L
L
1.5
1.0
0.5
–V
OUT
–V
S
0
5
10
15
20
25
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
SUPPLY VOLTAGE (±V)
OFFSET VOLTAGE DRIFT (µV/°C)
Figure 3. Output Voltage Swing vs. Supply Voltage
Figure 6. Typical Distribution of Offset Voltage Drift
35
30
25
20
15
10
5
100
10
I
= 1mA
O
A
= +1000
V
1
A
= +1
V
±15V SUPPLIES
0.1
0.01
0.001
0.0001
0
10
100
1k
10k
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
100k
LOAD RESISTANCE (Ω)
Figure 7. Output Impedance vs. Frequency
Figure 4. Output Voltage Swing vs. Load Resistance
Rev. C | Page 6 of 16
AD708
40
35
30
25
20
15
10
5
16
14
12
10
8
V
= ±10V
OUT
6
4
R
R
= 10kΩ
= 2kΩ
L
L
2
0
0
0
1
10
100
–60 –40 –20
0
20
40
60
80
100 120 140
DIFFERENTIAL VOLTAGE (±V)
TEMPERATURE (°C)
Figure 11. Open-Loop Gain vs. Temperature
Figure 8. Input Bias Current vs. Differential Input Voltage
16
14
12
10
8
45
40
35
30
25
20
15
10
5
R
= 2kΩ
LOAD
1/F CORNER
0.7Hz
6
4
2
0
0
0
5
10
15
20
25
0.1
1
10
100
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
Figure 9. Input Noise Spectral Density
Figure 12. Open-Loop Gain vs. Supply Voltage
140
120
100
80
0
R
C
= 2kꢀ
= 1000pF
L
L
1s
30
60
90
PHASE
MARGIN = 43°
60
120
150
180
40
GAIN
20
0
–20
0.01 0.1
1
10
100
1k
10k 100k 1M 10M
TIME (1s/DIV)
FREQUENCY (Hz)
Figure 10. 0.1 Hz to 10 Hz Voltage Noise
Figure 13. Open-Loop Gain and Phase vs. Frequency
Rev. C | Page 7 of 16
AD708
160
140
120
100
80
2mV/DIV
60
40
CH1
20
0
0.1
TIME (2µs/DIV)
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 14. Common-Mode Rejection vs. Frequency
Figure 17. Small Signal Transient Response; AV = +1, RL = 2 kΩ, CL = 50 pF
35
30
25
20
15
10
5
R
= 2kꢀ
25°C
= ±15V
F
= 2.8kHz
L
MAX
2mV/DIV
V
S
CH1
0
1k
TIME (2µs/DIV)
10k
100k
1M
FREQUENCY (Hz)
Figure 18. Small Signal Transient Response; AV = +1, RL = 2 kΩ, CL = 1000 pF
Figure 15. Large Signal Frequency Response
160
140
120
100
80
60
40
20
0
0.001
0.01
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 16. Power Supply Rejection vs. Frequency
Rev. C | Page 8 of 16
AD708
MATCHING CHARACTERISTICS
32
16
14
12
10
8
25°C
28
24
20
16
12
8
6
4
4
2
0
0
–50 –40 –30 –20 –10
0
10
20
30
40
50
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
OFFSET VOLTAGE MATCH (µV)
OFFSET CURRENT MATCH (nA)
Figure 19. Typical Distribution of Offset Voltage Match
Figure 22. Typical Distribution of Input Offset Current Match
32
28
24
20
16
12
8
160
140
120
100
80
–55°C TO +125°C
60
40
4
20
0
0
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
–60 –40 –20
0
20
40
60
80
100 120 140
OFFSET DRIFT MATCH (µV/°C)
TEMPERATURE (°C)
Figure 20. Typical Distribution of Offset Voltage Drift Match
Figure 23. PSRR Match vs. Temperature
16
14
12
10
8
160
140
120
100
80
6
60
4
40
2
20
0
0
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
–60 –40 –20
0
20
40
60
80
100 120 140
INPUT BIAS CURRENT MATCH (nA)
TEMPERATURE (°C)
Figure 21. Typical Distribution of Input Bias Current Match
Figure 24. CMRR Match vs. Temperature
Rev. C | Page 9 of 16
AD708
THEORY OF OPERATION
CROSSTALK PERFORMANCE
The AD708 exhibits very low crosstalk as shown in Figure 25,
Figure 26, and Figure 27. Figure 25 shows the offset voltage
induced on Side B of the AD708 when Side A output is moving
slowly (0.2 Hz) from −10 V to +10 V under no load. This is the
least stressful situation to the part because the overall power in
the chip does not change. Only the location of the power in the
output device changes. Figure 26 shows the input offset voltage
change to Side B when Side A is driving a 2 kΩ load. Here the
power changes in the chip with the maximum power change
occurring at 7.5 V. Figure 27 shows crosstalk under the most
severe conditions. Side A is connected as a follower with
0 V input, and is forced to sink and source 5 mA of output
current.
A
V
OUTA
V
= ±10V
IN
2kꢀ
10kꢀ
B
V
OUTB
10ꢀ
10ꢀ
2V
Power = (30 V)(5 mA) = 150 mW
Even this large change in power causes only an 8 μV (linear)
change in the input offset voltage of Side B.
A
V
OUTA
V
= ±10V
IN
V
= 2V/DIV
10kꢀ
OUTA
Figure 26. Crosstalk with 2 kΩ Load
B
V
OUTB
10ꢀ
10ꢀ
I
= ±5mA
IN
A
2kꢀ
V
= ±10V
IN
2V
10kꢀ
B
V
OUTB
10ꢀ
10ꢀ
2V
V
= 2V/DIV
OUTA
Figure 25. Crosstalk with No Load
IN = 1mA/DIV
A
Figure 27. Crosstalk Under Forced Source and Sink Conditions
Rev. C | Page 10 of 16
AD708
1/2
AD708
OPERATION WITH A GAIN OF −100
V
INA
To show the outstanding dc precision of the AD708 in a real
application, Table 3 shows an error budget calculation for a gain
of −100. This configuration is shown in Figure 28.
OUT
1–4
10kꢀ
10kꢀ
10kꢀ
A0
A1
S1
S2
S3
S4
9.9kꢀ
R
A
Table 3.
10kꢀ
10kꢀ
Maximum Error Contribution
AV = 100 (S Grade)
(Full Scale: VOUT = 10 V, VIN = 100 mV)
AD7502
AD707
100ꢀ
1kꢀ
10kꢀ
–V
S
S
S8
S7
S6
S5
Error Sources
+V
9.9kꢀ
VOS
30 μV/100 mV
= 300 ppm
= 10 ppm
= 20 ppm
= 4 ppm
R
B
IOS
(100 kΩ)(1 nA)/10 V
10 V/(5 × 106)/100 mV
0.35 mV/100 mV
OUT
5–8
10kꢀ
10kꢀ
10kꢀ
Gain (2 kΩ Load)
Noise
V
INB
1/2
AD708
VOS Drift
(0.3 mV/°C)/100 mV
= 3 ppm/°C
Total Unadjusted
Error
Figure 29. Precision PGA
@ 25°C
= 334 ppm > 11 bits
= 634 ppm > 10 bits
The gains of the circuit are controlled by the select lines, A0 and
A1, of the AD7502 multiplexer, and are 1, 10, 100, and 1000 in
this design.
−55°C to +125°C
With Offset
Calibrated Out @ 25°C
−55°C to +125°C
= 34 ppm > 14 bits
= 334 ppm > 11 bits
The input stage attains very high dc precision due to the 30 μV
maximum offset voltage match of the AD708S and the 1 nA
maximum input bias current match. The accuracy is main-
tained over temperature because of the ultralow drift
performance of the AD708.
100kꢀ
+V
7
S
0.1µF
0.1µF
1kꢀ
To achieve 0.1% gain accuracy, along with high common-mode
rejection, the circuit should be trimmed.
–
2
V
IN
1/2
AD708
6
V
OUT
To maximize common-mode rejection
4
3
+
1kꢀ
1. Set the select lines for gain = 1 and ground VINB
.
–V
S
2. Apply a precision dc voltage to VINA and trim RA until
VO = −VINA to the required precision.
Figure 28. Gain of −100 Configuration
This error budget assumes no error in the resistor ratio and no
error from power supply variation (the 120 dB minimum PSRR
of the AD708S makes this a good assumption). The external
resistors can cause gain error from mismatch and drift over
temperature.
3. Connect VINB to VINA and apply an input voltage equal to
the full-scale common mode expected.
4. Trim RB until VO = 0 V.
To minimize gain errors
HIGH PRECISION PROGRAMMABLE GAIN
AMPLIFIER
1. Select gain = 10 with the control lines and apply a
differential input voltage.
The three op amp programmable gain amplifier shown in
Figure 29 takes advantage of the outstanding matching
characteristics of the AD708 to achieve high dc precision.
2. Adjust the 100 Ω potentiometer to VO = 10 VIN
(adjust VIN magnitude as necessary).
3. Repeat Step 1 and Step 2 for gain = 100 and gain = 1000,
adjusting the 1 kΩ and 10 kΩ potentiometers, respectively.
The design shown in Figure 29 should allow for 0.1% gain
accuracy and 0.1 μV/V common-mode rejection when 1%
resistors and 5% potentiometers are used.
Rev. C | Page 11 of 16
AD708
AD708 enables this circuit to accurately resolve the input signal.
In addition, the tight offset voltage drift match maintains the
resolution of the circuit over the full military temperature
range. The high dc open-loop gain and exceptional gain
linearity allows the circuit to perform well at both large and
small signal levels.
BRIDGE SIGNAL CONDITIONER
The AD708 can be used in the circuit shown in Figure 30 to
produce an accurate and inexpensive dynamic bridge condi-
tioner. The low offset voltage match and low offset voltage drift
match of the AD708 combine to achieve circuit performance
better than all but the best instrumentation amplifiers. The
outstanding specifications of the AD708, such as open-loop
gain, input offset currents, and low input bias currents, do not
limit circuit accuracy.
In this circuit, the only significant dc errors are due to the offset
voltage of the two amplifiers, the input offset current match of
the amplifiers, and the mismatch of the resistors. Errors
associated with the AD708S contribute less than 0.001% error
over −55°C to +125°C.
As configured, the circuit only requires a gain resistor, RG, of
suitable accuracy and a stable, accurate voltage reference. The
transfer function is
Maximum error at 25°C
VO = VREF [ΔR/(R + ΔR)][RG/R]
30 μV +
10 kΩ1 nA
= 40 μV/10 μV = 4 ppm
10 V
The only significant errors due to the AD708S are
V
V
OS_OUT = (VOS_MATCH)(2RG/R) = 30 mV
Maximum error at +125°C or −55°C
50 μV +
2 nA10 kΩ
OS_OUT (T) = (VOS_DRIFT)(2RG/R) = 0.3 mV/°C
= 7 ppm @ +125°C
10 V
To achieve high accuracy, Resistor RG should be 0.1% or better
with a low drift coefficient.
Figure 32 shows VOUT vs. VIN for this circuit with a 3 mV input
signal at 0.05 Hz. Note that the circuit exhibits very low offset at
the zero crossing. This circuit can also produce VOUT = −|VIN| by
reversing the polarity of the two diodes.
+15V
AD580
2.5V
R
G
175kꢀ
R
R
R = 350ꢀ
R + ΔR
V
1/2
AD708
REF
1mV
1mV
V
O
1/2
AD708
887ꢀ
–15V
Figure 30. Bridge Signal Conditioning Circuit
10kꢀ
10kꢀ
IN459
10kꢀ
5kꢀ
1
V
= |V |
IN
O
V
= 1mV/DIV
IN
1
IN459
1/2
AD708
10kꢀ
5kꢀ
Figure 32. Absolute Value Circuit Performance
(Input Signal = 0.05 Hz)
3.75kꢀ
V
IN
1/2
AD708
SELECTION OF PASSIVE COMPONENTS
NOTE
Use high quality passive components to take full advantage of
the high precision and low drift characteristics of the AD708.
Discrete resistors and resistor networks with temperature
coefficients of less than 10 ppm/°C are available from Vishay,
Caddock, Precision Replacement Parts (PRP), and others.
1
LOW LEAKAGE DIODES
Figure 31. Precision Absolute Value Circuit
PRECISION ABSOLUTE VALUE CIRCUIT
The AD708 is ideally suited to the precision absolute value
circuit shown in Figure 31. The low offset voltage match of the
Rev. C | Page 12 of 16
AD708
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.005 (0.13)
MIN
0.055 (1.40)
MAX
8
5
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.310 (7.87)
0.220 (5.59)
1
4
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
0.100 (2.54)
0.100 (2.54) BSC
0.405 (10.29) MAX
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
0.320 (8.13)
0.290 (7.37)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.022 (0.56)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.018 (0.46)
0.014 (0.36)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
15°
0°
0.070 (1.78)
0.030 (0.76)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-001-BA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP]
Figure 34. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
AD708JN
AD708JNZ1
AD708AQ
AD708BQ
AD708SQ/883B
Temperature Range
0°C to +70°C
0°C to +70°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
Package Description
Package Option
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
N-8
N-8
Q-8
Q-8
Q-8
1 Z = Pb-free part.
Rev. C | Page 13 of 16
AD708
NOTES
Rev. C | Page 14 of 16
AD708
NOTES
Rev. C | Page 15 of 16
AD708
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C05789-0-1/06(C)
Rev. C | Page 16 of 16
相关型号：
AD708SCHIPS
IC DUAL OP-AMP, 50 uV OFFSET-MAX, 0.9 MHz BAND WIDTH, UUC8, DIE-8, Operational Amplifier
ADI
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