AD712CN [ADI]
Dual Precision, Low Cost, High Speed, BiFET Op Amp; 双路精密，低成本，高速， BiFET运算放大器
| 型号： | AD712CN |
| 厂家： | 
ADI |
| 描述： | Dual Precision, Low Cost, High Speed, BiFET Op Amp |
| 文件： | 总15页 (文件大小：638K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Precision, Low Cost,
High Speed, BiFET Op Amp
a
AD712
FEATURES
CONNECTION DIAGRAMS
Enhanced Replacements for LF412 and TL082
TO-99
(H) Package
AC PERFORMANCE
Settles to ؎0.01% in 1.0 ms
16 V/s min Slew Rate (AD712J)
3 MHz min Unity Gain Bandwidth (AD712J)
+V
AMPLIFIER NO. 1
OUTPUT
AMPLIFIER NO. 2
OUTPUT
S
INVERTING
OUTPUT
INVERTING
INPUT
DC PERFORMANCE
0.30 mV max Offset Voltage: (AD712C)
5 V/؇C max Drift: (AD712C)
AD712
NONINVERTING
INPUT
NONINVERTING
OUTPUT
200 V/mV min Open-Loop Gain (AD712K)
4 V p-p max Noise, 0.1 Hz to 10 Hz (AD712C)
Surface Mount Available in Tape and Reel in Accor-
dance with EIA-481A Standard
–V
S
Plastic Mini-DIP (N) Package
SOIC (R) Package and Cerdip (Q) Package
AMPLIFIER NO. 1
AMPLIFIER NO. 2
MIL-STD-883B Parts Available
Single Version Available: AD711
Quad Version: AD713
Available in Plastic Mini-DIP, Plastic SOIC, Hermetic
Cerdip, Hermetic Metal Can Packages and Chip Form
1
8
V+
OUTPUT
INVERTING
OUTPUT
2
3
4
OUTPUT
7
6
5
NONINVERTING
OUTPUT
INVERTING
INPUT
NONINVERTING
INPUT
V–
AD712
PRODUCT DESCRIPTION
screening includes 168-hour burn-in, as well as other environ-
mental and physical tests.
The AD712 is a high speed, precision monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that use
older precision BiFETs and, in many cases, bipolar op amps.
The AD712 is available in an 8-lead plastic mini-DIP, SOIC,
cerdip, TO-99 metal can, or in chip form.
PRODUCT HIGHLIGHTS
1. The AD712 offers excellent overall performance at very
competitive prices.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16 V/µs
and a settling time of 1 µs to ±0.01%, the AD712 is ideal as a
buffer for 12-bit D/A and A/D Converters and as a high-speed
integrator. The settling time is unmatched by any similar IC
amplifier.
2. Analog Devices’ advanced processing technology and with
100% testing guarantees a low input offset voltage (0.3 mV
max, C grade, 3 mV max, J grade). Input offset voltage is
specified in the warmed-up condition. Analog Devices’ laser
wafer drift trimming process reduces input offset voltage
drifts to 5 µV/°C max on the AD712C.
The combination of excellent noise performance and low input
current also make the AD712 useful for photo diode preamps.
Common-mode rejection of 88 dB and open loop gain of
400 V/mV ensure 12-bit performance even in high-speed unity
gain buffer circuits.
3. Along with precision dc performance, the AD712 offers
excellent dynamic response. It settles to ±0.01% in 1 µs and
has a minimum slew rate of 16 V/µs. Thus this device is ideal
for applications such as DAC and ADC buffers which re-
quire a combination of superior ac and dc performance.
The AD712 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD712J and
AD712K are rated over the commercial temperature range of
0°C to +70°C. The AD712A, AD712B and AD712C are rated
over the industrial temperature range of –40°C to +85°C. The
AD712S and AD712T are rated over the military temperature
range of –55°C to +125°C and are available processed to MIL-
STD-883-B, Rev. C.
4. The AD712 has a guaranteed and tested maximum voltage
noise of 4 µV p-p, 0.1 Hz to 10 Hz (AD712C).
5. Analog Devices’ well-matched, ion-implanted JFETs ensure
a guaranteed input bias current (at either input) of 50 pA
max (AD712C) and an input offset current of 10 pA max
(AD712C). Both input bias current and input offset current
are guaranteed in the warmed-up condition.
Extended reliability PLUS screening is available, specified over
the commercial and industrial temperature ranges. PLUS
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
(V = ؎15 V @ T = +25؇C unless otherwise noted)
AD712–SPECIFICATIONS
S
A
AD712J/A/S
AD712K/B/T
Typ
AD712C
Typ
Parameter
Min
Typ
Max
Min
Max
Min
Max
Units
INPUT OFFSET VOLTAGE1
Initial Offset
0.3
3/1/1
4/2/2
20/20/20
0.2
1.0/0.7/0.7
2.0/1.5/1.5
10
0.1
0.3
0.6
5
mV
mV
µV/°C
dB
dB
T
MIN to TMAX
vs. Temp
vs. Supply
7
95
7
100
3
110
76
76/76/76
80
80
86
86
T
MIN to TMAX
Long-Term Offset Stability
15
15
15
µV/Month
INPUT BIAS CURRENT2
VCM = 0 V
25
75
20
75
20
1.3
50
3.2
75
pA
nA
pA
V
CM = 0 V @ TMAX
0.6/1.6/26
1.7/4.8/77
100
0.5/1.3/20
1.7/4.8/77
100
VCM = ±10 V
INPUT OFFSET CURRENT
V
CM = 0 V
10
25
5
25
5
0.3
10
0.7
pA
nA
VCM = 0 V @ TMAX
0.3/0.7/11
0.6/1.6/26
0.1/0.3/5
0.6/1.6/26
MATCHING CHARACTERISTICS
Input Offset Voltage
3/1/1
4/2/2
20/20/20
25
1.0/0.7/0.7
2.0/1.5/1.5
10
0.3
0.6
5
mV
mV
µV/°C
pA
dB
dB
T
MIN to TMAX
Input Offset Voltage Drift
Input Bias Current
Crosstalk @ f = 1 kHz
@ f = 100 kHz
25
10
120
90
120
90
120
90
FREQUENCY RESPONSE
Small Signal Bandwidth
Full Power Response
Slew Rate
Settling Time to 0.01%
Total Harmonic Distortion
3.0
4.0
200
20
1.0
0.0003
3.4
4.0
200
20
1.0
0.0003
3.4
4.0
200
20
1.0
0.0003
MHz
kHz
V/µs
µs
16
18
18
1.2
1.2
1.2
%
INPUT IMPEDANCE
Differential
Common Mode
3 × 1012ʈ5.5
3 × 1012ʈ5.5
3 × 1012ʈ5.5
3 × 1012ʈ5.5
3 × 1012ʈ5.5
ΩʈpF
ΩʈpF
3 × 1012ʈ5.5
INPUT VOLTAGE RANGE
Differential3
±20
+14.5, –11.5
±20
+14.5, –11.5
±20
+14.5, –11.5
V
Common-Mode Voltage4
TMIN to TMAX
–VS + 4
+VS – 2
–VS + 4
+VS – 2
–VS + 4
+VS – 2 V
Common-Mode
Rejection Ratio
V
V
CM = ±10 V
MIN to TMAX
CM = ±11 V
76
76/76/76
70
88
84
84
80
80
80
76
74
88
84
84
80
86
86
76
74
94
90
90
84
dB
T
dB
dB
dB
TMIN to TMAX
70/70/70
INPUT VOLTAGE NOISE
2
2
2
µV p-p
45
22
18
16
45
22
18
16
45
22
18
16
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
INPUT CURRENT NOISE
OPEN-LOOP GAIN
0.01
400
0.01
400
0.01
400
pA/√Hz
150
100/100/100
200
100
200
100
V/mV
V/mV
OUTPUT CHARACTERISTICS
Voltage
+13, –12.5
+13.9, –13.3
±12/±12/؎12 +13.8, –13.1
25
+13, –12.5 +13.9, –13.3
+13, –12.5 +13.9, –13.3
V
V
mA
؎12
+13.8, –13.1
25
؎12
+13.8, –13.1
25
Current
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
±15
±15
±15
V
V
mA
؎4.5
؎18
6.8
؎4.5
؎18
6.0
؎4.5
؎18
5.6
5.0
5.0
5.0
NOTES
1Input Offset Voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C.
2Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperatures, the current doubles every 10°C.
3Defined as voltage between inputs, such that neither exceeds ±10 V from ground.
4Typically exceeding –14.1 V negative common-mode voltage on either input results in an output phase reversal.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
–2–
REV. B
AD712
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2
Temperature
Range
Package
Description
Package
Option
Model
Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (Q, H) . . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD712ACHIPS
AD712AH
AD712AQ
AD712BH
AD712BQ
AD712CH
AD712CN
AD712JN
AD712JR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
Bare Die
8-Lead Metal Can
H-08A
8-Lead Ceramic DIP Q-8
8-Lead Metal Can
H-08A
8-Lead Ceramic DIP Q-8
8-Lead Metal Can
8-Lead Plastic DIP
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
H-08A
AD712J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD712A/B/C . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
AD712S/T . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
N-8
N-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
AD712JR-REEL
AD712JR-REEL7
AD712KN
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD712KR
AD712KR-REEL
AD712KR-REEL7
AD712SCHIPS
AD712SQ
AD712SQ/883B
AD712TQ
–55°C to +125°C Bare Die
2Thermal Characteristics:
–55°C to +125°C 8-Lead Ceramic DIP Q-8
–55°C to +125°C 8-Lead Ceramic DIP Q-8
–55°C to +125°C 8-Lead Ceramic DIP Q-8
–55°C to +125°C 8-Lead Ceramic DIP Q-8
8-Lead Plastic Package:
8-Lead Cerdip Package:
θJA = 165°C/Watt
θJC = 22°C/Watt; θJA = 110°C/Watt
8-Lead Metal Can Package: θJC = 65°C/Watt; θJA = 150°C/Watt
AD712TQ/883B
8-Lead SOIC Package:
θJA = 100°C
3For supply voltages less than ±18 V, the absolute maximum input voltage is equal
to the supply voltage.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
–3–
REV. B
AD712
–Typical Performance Characteristics
20
20
30
25
20
15
10
5
15
10
5
15
+V
OUT
–V
؎15V SUPPLIES
10
5
OUT
R
= 2k⍀
L
R
= 2k⍀
L
25؇C
25؇C
0
0
0
0
5
10
15
20
5
10
15
20
0
10
100
1k
10k
SUPPLY VOLTAGE ؎ Volts
SUPPLY VOLTAGE ؎ Volts
LOAD RESISTANCE – ⍀
Figure 1. Input Voltage Swing vs.
Supply Voltage
Figure 2. Output Voltage Swing vs.
Supply Voltage
Figure 3. Output Voltage Swing
vs. Load Resistance
6
6
5
4
3
2
10
100
10
7
10
8
10
9
10
1.0
10
10
0.1
11
10
12
10
0.01
–60 –40 –40
20 40 60 80 100 120 140
0
TEMPERATURE – ؇C
5
10
15
20
0
1k
10k
100k
1M
10M
SUPPLY VOLTAGE ؎ Volts
FREQUENCY – Hz
Figure 5. Input Bias Current vs.
Temperature
Figure 4. Quiescent Current vs.
Supply Voltage
Figure 6. Output Impedance vs.
Frequency
26
5.0
4.5
4.0
100
24
+ OUTPUT CURRENT
MAX J GRADE LIMIT
75
50
22
20
V
= +15V
S
25؇C
18
– OUTPUT CURRENT
16
14
25
0
3.5
3.0
12
10
–60 –40 –20
0
20 40 60 80 100 120 140
–60 –40 –20
0
20 40 60 80 100 120 140
–10
–5
0
5
10
AMBIENT TEMPERATURE – ؇C
COMMON MODE VOLTAGE – Volts
TEMPERATURE – ؇C
Figure 8. Short Circuit Current
Limit vs. Temperature
Figure 7. Input Bias Current vs.
Common Mode Voltage
Figure 9. Unity Gain Bandwidth vs.
Temperature
–4–
REV. B
AD712
125
120
115
110
100
100
80
100
80
+ SUPPLY
80
60
40
20
0
60
40
20
60
40
20
R
= 2k⍀
L
25؇C
110
105
GAIN
PHASE
2k⍀
100pF
LOAD
– SUPPLY
V
= ؎15V SUPPLIES
S
WITH 1V p-p SINE
WAVE 25؇C
100
95
0
0
–20
10
–20
10M
5
10
15
20
0
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
SUPPLY VOLTAGE ؎ Volts
SUPPLY MODULATION FREQUENCY – Hz
FREQUENCY – Hz
Figure 12. Power Supply Rejection
vs. Frequency
Figure 11. Open-Loop Gain vs.
Supply Voltage
Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency
30
25
20
10
8
100
80
6
4
V
V
= ؎15V
S
R
= 2k⍀
= 1Vp-p
L
CM
2
60
40
20
0
25؇C
V = ؎15V
S
1% 0.1%
0.01%
0.01%
25؇C
15
0
–2
–4
–6
ERROR 1% 0.1%
10
5
–8
0
100k
–10
0.5
1M
INPUT FREQUENCY – Hz
10M
0.7
0.6
0.8
0.9
1.0
10
100
1k
10k
100k
1M
SETTLING TIME – s
FREQUENCY – Hz
Figure 15. Output Swing and Error
vs. Settling Time
Figure 14. Large Signal Frequency
Response
Figure 13. Common Mode Rejec-
tion vs. Frequency
1k
25
20
15
10
5
–70
–80
3V RMS
R
= 2k⍀
L
L
100
10
1
–90
C
= 100pF
–100
–110
–120
–130
0
1
10
100
1k
10k
100k
0
100 200 300 400 500 600 700 800 900
100
1k
10k
100k
FREQUENCY – Hz
INPUT ERROR SIGNAL – mV
(AT SUMMING JUNCTION)
FREQUENCY – Hz
Figure 17. Input Noise Voltage
Spectral Density
Figure 18. Slew Rate vs. Input
Error Signal
Figure 16. Total Harmonic Distor-
tion vs. Frequency
–5–
REV. B
AD712
+V
S
25
0.1F
1/2
AD712
OUTPUT
INPUT
100pF
2k⍀
0.1F
20
–V
S
Figure 20. T.H.D. Test Circuit
V
OUT
15
–60 –40 –20
20k⍀
2.2k⍀
+V
0
20
40
60
80
100 120
140
S
TEMPERATURE – ؇C
2
3
6
5
8
1/2
AD712
1/2
AD712
1
Figure 19. Slew Rate vs. Temperature
7
5k⍀
20V p-p
5k⍀
4
V
IN
V
OUT
–V
S
CROSSTALK = 20 LOG
10V
IN
Figure 21. Crosstalk Test Circuit
100
90
100
90
+V
S
0.1F
V
OUT
1/2
AD712
10
10
R
C
0%
0%
L
L
V
IN
100pF
2k⍀
100ns
50mV
1s
0.1F
5V
SQUARE
WAVE
INPUT
–V
S
Figure 22c. Unity Gain Follower
Pulse Response (Small Signal)
Figure 22a. Unity Gain Follower
Figure 22b. Unity Gain Follower
Pulse Response (Large Signal)
100
90
100
90
5k⍀
+V
S
0.1F
5k⍀
V
IN
V
OUT
1/2
AD712
10
10
0%
R
C
L
0%
L
SQUARE
WAVE
INPUT
100pF
2k⍀
200ns
50mV
1s
0.1F
5V
–V
S
Figure 23c. Unity Gain Inverter
Pulse Response (Small Signal)
Figure 23a. Unity Gain Inverter
Figure 23b. Unity Gain Inverter Pulse
Response (Large Signal)
–6–
REV. B
AD712
OPTIMIZING SETTLING TIME
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD711/AD712 family assures 12-bit accuracy over
the full operating temperature range.
Most bipolar high-speed D/A converters have current outputs;
therefore, for most applications, an external op amp is required
for current-to-voltage conversion. The settling time of the con-
verter/op amp combination depends on the settling time of the
DAC and output amplifier. A good approximation is:
The excellent high-speed performance of the AD712 is shown in
the oscilloscope photos of Figure 25. Measurements were taken
using a low input capacitance amplifier connected directly to the
summing junction of the AD712 – both photos show the worst
case situation: a full-scale input transition. The DAC’s 4 kΩ
[10 kΩ||8 kΩ = 4.4 kΩ] output impedance together with a
10 kΩ feedback resistor produce an op amp noise gain of 3.25.
The current output from the DAC produces a 10 V step at the
op amp output (0 to –10 V Figure 25a, –10 V to 0 V Figure
25b.)
tS Total = (tS DAC )2 +(tS AMP )2
The settling time of an op amp DAC buffer will vary with the
noise gain of the circuit, the DAC output capacitance, and with
the amount of external compensation capacitance across the
DAC output scaling resistor.
Settling time for a bipolar DAC is typically 100 ns to 500 ns.
Previously, conventional op amps have required much longer
settling times than have typical state-of-the-art DACs; therefore,
the amplifier settling time has been the major limitation to a
high-speed voltage-output D-to-A function. The introduction of
the AD711/AD712 family of op amps with their 1 µs (to ±0.01%
of final value) settling time now permits the full high-speed
capabilities of most modern DACs to be realized.
Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%)
requires that 375 µV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD712 summing junction) must be
less than 375 µV. As shown in Figure 25, the total settling time
for the AD712/AD565 combination is 1.2 microseconds.
0.1F
BIPOLAR
OFFSET ADJUST
R1
100⍀
REF
OUT
BIPOLAR
OFF
V
CC
R2
100⍀
20V
SPAN
GAIN
ADJUST
+
–
10V
5k⍀
AD565A
10pF
9.95k⍀
+15V
10V
SPAN
REF
IN
0.1F
19.95k⍀
0.5mA
5k⍀
8k⍀
DAC
OUT
I
REF
DAC
REF
GND
1/2
AD712
I
OUTPUT
–10V TO +10V
O
I
I
= 4
؋
20k⍀
OUT
؋
CODE REF
0.1F
POWER
GND
–V
EE
MSB
LSB
–15V
0.1F
Figure 24. ±10 V Voltage Output Bipolar DAC
1mV
5V
1mV
5V
100
90
100
90
SUMMING
JUNCTION
SUMMING
JUNCTION
0V
0V
OUTPUT
10
OUTPUT
10
0%
0%
–10V
–10V
500ns
500ns
b. (Full-Scale Positive Transition)
a. (Full-Scale Negative Transition)
Figure 25. Settling Characteristics for AD712 with AD565A
–7–
REV. B
AD712
OP AMP SETTLING TIME -
A MATHEMATICAL MODEL
When RO and IO are replaced with their Thevenin VIN and RIN
equivalents, the general purpose inverting amplifier of Figure
26b is created. Note that when using this general model, capaci-
tance CX is EITHER the input capacitance of the op amp if a
simple inverting op amp is being simulated OR it is the com-
bined capacitance of the DAC output and the op amp input if
the DAC buffer is being modeled.
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(20 V/µs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the
AD712 settles to ±0.01%, with a 10 V output step, in under
1 µs, while retaining the ability to drive a 250 pF load capaci-
tance when operating as a unity gain follower.
1/2
AD712
V
OUT
R
C
L
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of ωο/2π, Equation 1 will accurately de-
scribe the small signal behavior of the circuit of Figure 26a,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the op amp’s
finite slew rate and other nonlinear effects.
L
C
F
R
R
IN
V
C
IN
X
Figure 26b. Simplified Model of the AD712
Used as an Inverter
Equation 1.
VO
IIN
–R
GN
In either case, the capacitance CX causes the system to go from
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Since the value of CX can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor,
CF, to cancel the input pole and optimize amplifier response.
Figure 27 is a graphical solution of Equation 2 for the AD712
with R = 4 kΩ.
=
R(Cf = CX
)
s2 +
+ RCf s +1
ωο
ωο
ω
2π
where ο =op amp’s unity gain frequency
R
1+
GN = “noise” gain of circuit
RO
This equation may then be solved for Cf:
Equation 2.
60
50
2 RCX ωο +(1 − GN )
Rωο
2 − GN
Rωο
Cf
=
+
G
= 4.0
40
30
20
N
In these equations, capacitor CX is the total capacitor appearing
the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 26a
can be used directly; capacitance CX is the total capacitance of
the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).
G
N
= 3.0
G
= 2.0
= 1.5
N
G
N
G
= 1.0
10
0
N
0
10
20
30
C
40
50
60
1/2
AD712
F
V
OUT
R
C
L
L
Figure 27. Value of Capacitor CF vs. Value of CX
C
F
R
I
R
C
X
O
O
Figure 26a. Simplified Model of the AD712 Used as a
Current-Out DAC Buffer
–8–
REV. B
AD712
The photos of Figures 28a and 28b show the dynamic response
of the AD712 in the settling test circuit of Figure 29.
The input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2 and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.
5V
100
90
10
0%
GUARDING
5mV
The low input bias current (15 pA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 30, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should not
be extended for any unnecessary length on the printed circuit
board.
500ns
Figure 28a. Settling Characteristics 0 V to +10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
5V
100
90
TO-99 (H) PACKAGE
PLASTIC MINI-DIP (N) PACKAGE
CERDIP (Q) PACKAGE
AND SOIC (R) PACKAGE
4
4
5
10
5
6
7
8
0%
3
5mV
2
500ns
3
2
6
Figure 28b. Settling Characteristics 0 V to –10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
1
7
1
8
Figure 30. Board Layout for Guarding Inputs
5pF
TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP
INPUT SECTION
V
؋
5 ERROR
1/2
205⍀
AD712
HP2835
20pF
1M⍀
HP2835
0.47F
0.47F
4.99k⍀
4.99k⍀
–15V +15V
10k⍀
200⍀
DATA
DYNAMICS
5109
5-18pF
10k⍀
1.1k⍀
V
IN
0.2-0.6pF
10k⍀
1/2
AD712
V
OUT
10pF
5k⍀
(OR EQUIVALENT
FLAT TOP
PULSE
GENERATION)
0.1F
0.1F
+15V
–15V
Figure 29. Settling Time Test Circuit
–9–
REV. B
AD712
V
V
D/A CONVERTER APPLICATIONS
R2A*
DD
The AD712 is an excellent output amplifier for CMOS DACs.
It can be used to perform both 2 quadrant and 4 quadrant op-
eration. The output impedance of a DAC using an inverted
R-2R ladder approaches R for codes containing many 1s, 3R for
codes containing a single 1, and for codes containing all zero,
the output impedance is infinite.
+15V
C1A
33pF
0.1F
GAIN
ADJUST
R
FB
DD
OUT1
1/2
AD712
V
IN
AD7545
V
V
OUTA
REF
R1A*
AGND
DGND
*REFER TO
TABLE I
ANALOG
COMMON
For example, the output resistance of the AD7545 will modu-
late between 11 kΩ and 33 kΩ. Therefore, with the DAC’s
internal feedback resistance of 11 kΩ, the noise gain will vary
from 2 to 4/3. This changing noise gain modulates the effect of
the input offset voltage of the amplifier, resulting in nonlinear
DAC amplifier performance.
DB11–DB0
R2B*
V
DD
DD
C1B
33pF
GAIN
ADJUST
The AD712K with guaranteed 700 µV offset voltage minimizes
this effect to achieve 12-bit performance.
R
V
FB
OUT1
1/2
AD712
V
IN
AD7545
V
V
OUTB
REF
Figures 31 and 32 show the AD712 and AD7545 (12-bit
CMOS DAC) configured for unipolar binary (2-quadrant multi-
plication) or bipolar (4-quadrant multiplication) operation.
Capacitor C1 provides phase compensation to reduce overshoot
and ringing.
R1B*
AGND
DGND
0.1F
*REFER TO
TABLE I
ANALOG
COMMON
–15V
DB11–DB0
Figure 31. Unipolar Binary Operation
R1 and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are shown below.
Table I. Recommended Trim Resistor Values vs. Grades
of the AD7545 for VDD = +5 V
Trim
Resistor
JN/AQ/SD KN/BQ/TD
LN/UD
GLN/GUD
R1
R2
500 Ω
150 Ω
200 Ω
68 Ω
100 Ω
33 Ω
20 Ω
6.8 Ω
R2*
V
V
R4
20k⍀ 1%
DD
+15V
C1
33pF
0.1F
R5
20k⍀ 1%
GAIN
ADJUST
R
FB
DD
OUT1
1/2
AD712
AD7545
V
V
REF
IN
1/2
R3
10k⍀ 1%
R1*
AGND
V
OUT
AD712
DGND
DB11–DB0
12
0.1F
DATA INPUT
*FOR VALUES OF
R1 AND R2 SEE TABLE I
–15V
ANALOG
COMMON
Figure 32. Bipolar Operation
–10–
REV. B
AD712
Figures 33a and 33b show the settling time characteristics of the
AD712 when used as a DAC output buffer for the AD7545.
DRIVING THE ANALOG INPUT OF AN A/D CONVERTER
An op amp driving the analog input of an A/D converter, such
as that shown in Figure 34, must be capable of maintaining a
constant output voltage under dynamically changing load condi-
tions. In successive-approximation converters, the input current
is compared to a series of switched trial currents. The compari-
son point is diode clamped but may deviate several hundred
millivolts resulting in high frequency modulation of A/D input
current. The output impedance of a feedback amplifier is made
artificially low by the loop gain. At high frequencies, where the
loop gain is low, the amplifier output impedance can approach
its open loop value. Most IC amplifiers exhibit a minimum open
loop output impedance of 25 Ω due to current limiting resistors.
100
90
10
0%
500ns
a. Full-Scale Positive Transition
12/8
STS
CS
HIGH
BITS
A
O
GAIN
ADJUST
AD574
R/C
100
90
CE
MIDDLE
BITS
REF IN
R2
100⍀
LOW
BITS
REF OUT
BIP OFF
R1
100⍀
+15V
0.1F
+5V
+15V
–15V
10
10V
IN
OFFSET
ADJUST
0%
1/2
20V
IN
500ns
AD712
؎10V
ANALOG
INPUT
ANA
COM
DIG
COM
0.1F
b. Full-Scale Negative Transition
ANALOG COM
Figure 33. Settling Characteristics for AD712 with AD7545
–15V
Figure 34. AD712 as ADC Unity Gain Buffer
NOISE CHARACTERISTICS
A few hundred microamps reflected from the change in converter
loading can introduce errors in instantaneous input voltage. If
the A/D conversion speed is not excessive and the bandwidth of
the amplifier is sufficient, the amplifier’s output will return to
the nominal value before the converter makes its comparison.
However, many amplifiers have relatively narrow bandwidth
yielding slow recovery from output transients. The AD712 is
ideally suited to drive high speed A/D converters since it offers
both wide bandwidth and high open-loop gain.
The random nature of noise, particularly in the 1/f region,
makes it difficult to specify in practical terms. At the same time,
designers of precision instrumentation require certain guaran-
teed maximum noise levels to realize the full accuracy of their
equipment.
The AD712C grade is specified at a maximum level of 4.0 µV
p-p, in a 0.1 Hz to 10 Hz bandwidth. Each AD712C receives a
100% noise test for two 10-second intervals; devices with any
excursion in excess of 4.0 µV are rejected. The screened lot is
then submitted to Quality Control for verification on an AQL
basis.
All other grades of the AD712 are sample-tested on an AQL
basis to a limit of 6 µV p-p, 0.1 Hz to 10 Hz.
–11–
REV. B
AD712
PD711 BUFF
1s
5V
100
90
100
90
10
10
0%
0%
500mV
200ns
–10V ADC IN
a. Source Current = 2 mA
Figure 37. Transient Response RL = 2 kΩ, CL = 500 pF
ACTIVE FILTER APPLICATIONS
PD711 BUFF
In active filter applications using op amps, the dc accuracy of
the amplifier is critical to optimal filter performance. The
amplifier’s offset voltage and bias current contribute to output
error. Offset voltage will be passed by the filter and may be
amplified to produce excessive output offset. For low frequency
applications requiring large value input resistors, bias currents
flowing through these resistors will also generate an offset voltage.
100
90
10
0%
In addition, at higher frequencies, an op amp’s dynamics must
be carefully considered. Here, slew rate, bandwidth, and
open-loop gain play a major role in op amp selection. The slew
rate must be fast as well as symmetrical to minimize distortion.
The amplifier’s bandwidth in conjunction with the filter’s gain
will dictate the frequency response of the filter.
500mV
200ns
–5V ADC IN
b. Sink Current = 1 mA
Figure 35. ADC Input Unity Gain Buffer Recovery Times
DRIVING A LARGE CAPACITIVE LOAD
The use of a high performance amplifier such as the AD712 will
minimize both dc and ac errors in all active filter applications.
The circuit in Figure 36 employs a 100 Ω isolation resistor
which enables the amplifier to drive capacitive loads exceeding
1500 pF; the resistor effectively isolates the high frequency
feedback from the load and stabilizes the circuit. Low frequency
feedback is returned to the amplifier summing junction via the
low pass filter formed by the 100 Ω series resistor and the load
capacitance, CL. Figure 37 shows a typical transient response
for this connection.
4.99k⍀
30pF
+V
IN
0.1F
+
–
4.99k⍀
100⍀
1/2
INPUT
OUTPUT
AD712
C
1
R
1
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
0.1F
+
–
R
C UP TO
1
1
–V
2k⍀
10k⍀
20⍀
1500pF
1500pF
1000pF
IN
Figure 36. Circuit for Driving a Large Capacitive Load
–12–
REV. B
AD712
SECOND ORDER LOW PASS FILTER
REF 20.0 dBm
10 dB/DIV
OFFSET .0 Hz
RANGE 15.0 dBm 0 dB
Figure 38 depicts the AD712 configured as a second order
Butterworth low pass filter. With the values as shown, the corner
frequency will be 20 kHz; however, the wide bandwidth of the
AD712 permits a corner frequency as high as several hundred
kilohertz. Equations for component selection are shown below.
TYPICAL BIFET
R1 = R2 = user selected (typical values: 10 kΩ – 100 kΩ)
1.414
(2π)( f cutoff )( R1)
0.707
(2π)( f cutoff )( R1)
C1 (in farads) =
C2 =
AD712
C1
560pF
+15V
0.1F
R1
20k⍀
R2
20k⍀
SPAN 10 000 000.0 Hz
ST .8 SEC
CENTER 5 000 000.0 Hz
RBW 30 kHz
VBW 30 kHz
1/2
AD712
C2
280pF
V
OUT
Figure 39.
V
IN
0.1F
–15V
Figure 38. Second Order Low Pass Filter
An important property of filters is their out-of-band rejection.
The simple 20 kHz low pass filter shown in Figure 38, might be
used to condition a signal contaminated with clock pulses or
sampling glitches which have considerable energy content at
high frequencies.
The low output impedance and high bandwidth of the AD712
minimize high frequency feedthrough as shown in Figure 39.
The upper trace is that of another low-cost BiFET op amp
showing 17 dB more feedthrough at 5 MHz.
–13–
REV. B
AD712
+15V
0.1F
+15V
0.1F
V
IN
0.001F
2800⍀
6190⍀
6490⍀
6190⍀
2800⍀
A1
AD711
A2
AD711
V
–15
–15
–15
–15
OUT
4.9395E
5.9276E
5.9276E
4.9395E
0.1F
A
B
C
D
0.1F
4.99k⍀
4.99k⍀
–15V
*
*
*
*
–15V
100k⍀
0.001F
124k⍀
SEE TEXT
*
Figure 40. 9-Pole Chebychev Filter
9-POLE CHEBYCHEV FILTER
REF 5.0 dBm
10 dB/DIV
MARKER 96 800.0 Hz
RANGE –5.0 dBm –90 dBm
Figure 40 shows the AD712 and its dual counterpart, the
AD711, as a 9-pole Chebychev filter using active frequency
dependent negative resistors (FDNR). With a cutoff frequency
of 50 kHz and better than 90 dB rejection, it may be used as an
antialiasing filter for a 12-bit Data Acquisition System with
100 kHz throughput.
As shown in Figure 40, the filter is comprised of four FDNRs
(A, B, C, D) having values of 4.9395 ϫ 10–15 and 5.9276 ϫ
10–15 farad-seconds. Each FDNR active network provides a
two-pole response; for a total of 8 poles. The 9th pole consists
of a 0.001 µF capacitor and a 124 kΩ resistor at Pin 3 of ampli-
fier A2. Figure 41 depicts the circuits for each FDNR with the
proper selection of R. To achieve optimal performance, the
0.001 µF capacitors must be selected for 1% or better matching
and all resistors should have 1% or better tolerance.
STOP 200 000.0 Hz
ST 69.6 SEC
START.0 Hz
RBW 300 Hz
VBW 30 Hz
Figure 42. High Frequency Response for 9-Pole
Chebychev Filter
+15V
0.1F
0.001F
1/2
AD712
R
0.1F
1/2
AD712
0.001F
–15V
1.0k⍀
4.99k⍀
–15
R: 24.9k⍀ FOR 4.9395E
–15
29.4k⍀ FOR 5.9276E
Figure 41. FDNR for 9-Pole Chebychev Filter
–14–
REV. B
AD712
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Cerdip
(Q-8)
Mini-DIP
(N-8)
0.390 (9.91)
0.005 (0.13)
0.055 (1.35)
MIN
MAX
8
5
4
0.250 0.310
(6.35) (7.87)
8
5
0.25R
(0.64)
0.310 (7.87)
1
0.300 (7.62)
REF
0.220 (5.59)
1
PIN 1
4
0.035 ؎0.01
(0.890 ؎0.25)
0.195 (4.95)
0.115 (2.93)
0.165 ؎0.01
4.19 ؎0.25
PIN 1
0.220 (5.59)
0.310 (7.87)
0.405 (10.29)
MAX
0.18 ؎0.01
(4.57 ؎0.76)
0.015 (0.38)
0.060 (1.52)
0.125 (3.18)
MIN
0.200 (5.08)
MAX
0.011 ؎0.003
(0.204 ؎0.081)
SEATING
PLANE
0.033 (0.84)
NOM
0.150
(3.81)
MIN
0.018 ؎0.003
(0.460 ؎0.081)
0.100
(2.54)
TYP
0.125 (3.18)
0.200 (5.08)
15؇
0؇
0.008 (0.20)
0.015 (0.38)
SEATING
PLANE
0.014 (0.36) 0.100
0.030 (0.76)
15؇
0؇
(2.54)
BSC
0.023 (0.58)
0.070 (1.78)
TO-99
SOIC
(H-08A)
(R-8)
REFERENCE PLANE
0.1968 (5.00)
0.1890 (4.80)
0.500 (12.70)
MIN
0.185 (4.70)
0.165 (4.19)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
5
1
4
3
6
0.045 (1.1)
0.020 (0.51)
0.0688 (1.75)
0.0532 (1.35)
0.200
(5.1)
TYP
0.0196 (0.50)
0.0099 (0.25)
PIN 1
x 45؇
7
2
8
0.0098 (0.25)
0.0040 (0.10)
BOTTOM VIEW
8؇
0؇
0.100
(2.54)
BSC
0.019 (0.48)
0.016 (0.41)
0.0500 0.020 (0.51)
0.050 (1.27)
0.016 (0.40)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
(1.27)
BSC
0.013 (0.33)
0.034 (0.86)
0.028 (0.71)
0.040 (1.01) MAX
0.021 (0.53)
0.016 (0.41)
INSULATION
0.05 (1.27) MAX
45؇ BSC
BASE & SEATING PLANE
EQUALLY SPACED
–15–
REV. B
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