AD7143 [ADI]
Programmable Controller for Capacitance Touch Sensors; 对于电容式触摸传感器的可编程控制器
| 型号： | AD7143 |
| 厂家： | 
ADI |
| 描述： | Programmable Controller for Capacitance Touch Sensors |
| 文件： | 总56页 (文件大小：697K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Programmable Controller for
Capacitance Touch Sensors
AD7143
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Programmable capacitance-to-digital converter
25 ms update rate (@ maximum sequence length)
Better than 1 fF resolution
8 capacitance sensor input channels
No external RC tuning components required
Automatic conversion sequencer
On-chip automatic calibration logic
Automatic compensation for environmental changes
Automatic adaptive threshold and sensitivity levels
On-chip RAM to store calibration data
I2C®-compatible serial interface
Separate VDRIVE level for serial interface
Interrupt output for host controller
16-lead, 4 mm x 4 mm LFCSP-VQ
POWER-ON
RESET
AD7143
15
16
1
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
LOGIC
CALIBRA-
TION
ENGINE
16-BIT
Σ-Δ
CDC
2
3
4
5
CALIBRA-
TION
9
VCC
GND
6
CONTROL
AND
RAM
10
DATA
REGISTERS
250kHz
7
8
CSHIELD
SRC
EXCITATION
SOURCE
INTERRUPT
LOGIC
2
I C SERIAL INTERFACE
AND CONTROL LOGIC
2.6 V to 3.6 V supply voltage
Low operating current
11
12
13
14
Full power mode: less than 1 mA
VDRIVE SDA SCLK
INT
Low power mode: 50 μA
Figure 1.
APPLICATIONS
Personal music and multimedia players
Cell phones
Digital still cameras
Smart hand-held devices
Television, A/V, and remote controls
Gaming consoles
The AD7143 has on-chip calibration logic to account for
changes in the ambient environment. The calibration sequence is
performed automatically and at continuous intervals, while the
sensors are not touched. This ensures that there are no false or
nonregistering touches on the external sensors due to a
changing environment.
GENERAL DESCRIPTION
The AD7143 is an integrated capacitance-to-digital converter
(CDC) with on-chip environmental calibration for use in
systems requiring a novel user input method. The AD7143
interfaces to external capacitance sensors implementing
functions, such as capacitive buttons, scroll bars, and
scroll wheels.
The AD7143 has an I2C-compatible serial interface and a
separate VDRIVE pin for I2C serial interface operating voltages
between 1.65 V and 3.6 V.
The CDC has eight inputs channeled through a switch matrix to
a 16-bit, 250 kHz sigma-delta (∑-Δ) capacitance-to-digital
converter. The CDC is capable of sensing changes in the
capacitance of the external sensors and uses this information to
register a sensor activation. The external sensors can be
arranged as a series of buttons, as a scroll bar or wheel, or as a
combination of sensor types. By programming the registers, the
user has full control over the CDC setup. High resolution
sensors require software to run on the host processor.
The AD7143 is available in a 16-lead, 4 mm × 4 mm LFCSP-VQ
and operates from a 2.6 V to 3.6 V supply. The operating
current consumption is less than 1 mA, falling to 50 μA in low
power mode (conversion interval of 400 ms).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD7143
TABLE OF CONTENTS
Features .............................................................................................. 1
Proximity Sensitivity.................................................................. 17
Slow FIFO.................................................................................... 19
SLOW_FILTER_UPDATE_LVL.............................................. 19
Environmental Calibration ........................................................... 22
Capacitance Sensor Behavior without Calibration................ 22
Capacitance Sensor Behavior with Calibration...................... 23
Adaptive Threshold and Sensitivity ............................................. 25
Interrupt Output............................................................................. 26
CDC Conversion Complete Interrupt..................................... 26
Sensor Touch Interrupt.............................................................. 26
Serial Interface ................................................................................ 28
I2C Compatible Interface........................................................... 28
PCB Design Guidelines ................................................................. 31
Capacitive Sensor Board Mechanical Specifications............. 31
Chip Scale Packages ................................................................... 31
Power-Up Sequence ....................................................................... 32
Typical Application Circuits ......................................................... 33
Register Map ................................................................................... 34
Detailed Register Descriptions ..................................................... 35
Bank 1 Registers ......................................................................... 35
Bank 2 Registers ......................................................................... 43
Bank 3 Registers ......................................................................... 47
Outline Dimensions....................................................................... 55
Ordering Guide .......................................................................... 55
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
I2C Timing Specifications............................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
Capacitance Sensing Theory..................................................... 11
Operating Modes........................................................................ 12
Capacitance Sensor Input Configuration.................................... 13
CIN Input Multiplexer Setup.................................................... 13
Capacitiance-to-Digital Converter............................................... 14
Oversampling the CDC Output ............................................... 14
Capacitance Sensor Offset Control.......................................... 14
Conversion Sequencer ............................................................... 14
CDC Conversion Sequence Time ............................................ 15
CDC Conversion Results........................................................... 16
Noncontact Proximity Detection ................................................. 17
Recalibration ............................................................................... 17
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 56
AD7143
SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CAPACITANCE-TO-DIGITAL CONVERTER
Update Rate
Resolution
CIN Input Range1
23
25
16
2
26
ms
Bit
pF
Bit
Eight conversion stages in sequencer, decimation = 256
Guaranteed by design, but not production tested
No Missing Codes
16
CIN Input Leakage
Total Unadjusted Error
Output Noise (Peak-to-Peak)
25
nA
%
20
7
3
0.8
0.5
Codes
Codes
Codes
Codes
pF
Decimation rate = 128
Decimation rate = 256
Decimation rate = 128
Decimation rate = 256
Parasitic capacitance to ground, per CIN input guaranteed
by characterization
Output Noise (RMS)
Parasitic Capacitance
40
5
CBULK Offset Range1
CBULK Offset Resolution
Low Power Mode Delay Accuracy
EXCITATION SOURCE
Frequency
20
156.25
pF
fF
%
% of 200 ms, 400 ms, 600 ms, or 800 ms
Capacitance load on source to ground
237.5
240
262.5 kHz
Output Voltage
VCC
V
Short-Circuit Source Current
Short-Circuit Sink Current
Maximum Output Load
CSHIELD Output Drive
CSHIELD Bias Level
20
50
250
10
VCC/2
mA
mA
pF
μA
V
LOGIC INPUTS (SCLK, SDA)
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Voltage
IIL Input Low Voltage
Hysteresis
0.7 × VDRIVE
−1
V
V
μA
μA
mV
0.4
1
VIN = GND
150
OPEN-DRAIN OUTPUTS (SCLK, SDA, INT)
VOL Output Low Voltage
IOH Output High Leakage Current
POWER
VCC
VDRIVE
0.4
1
V
μA
ISINK = −1 mA
+0.1
3.3
2.6
1.65
3.6
3.6
1
20
30
4.5
15
V
V
ICC
0.9
mA
μA
μA
μA
μA
In full power mode
Low power mode, converter idle, TA = 25°C
Low power mode, converter idle
Full shutdown, TA = 25°C
Full shutdown
16
2.25
1 CIN and CBULK are defined as follows:
C
IN
PLASTIC OVERLAY
SENSOR BOARD
C
BULK
CAPACITIVE SENSOR
Rev. 0 | Page 3 of 56
AD7143
Table 2. Typical Average Current in Low Power Mode, VCC = 3.6 V, T = 25°C, Load of 50 pF on SRC Pin
Number of Conversion Stages, Current Values Expressed in ꢀA
Low Power Mode Delay
Decimation Rate
1
2
3
4
5
6
7
8
200 ms
128
256
128
256
128
256
128
256
26.4
35.6
21.3
26
19.6
22.7
18.7
21.1
33.3
49.1
24.8
32.9
21.9
27.4
20.5
24.6
40.1
62.2
28.3
39.7
24.3
32
46.9
74.9
31.7
46.5
26.6
25.6
24
53.5
87.3
35.2
53.1
28.9
41.1
25.7
35
60
66.5
111
42
66.1
33.5
50
72.8
122.3
45.4
72.4
35.8
54.4
31
99.3
38.6
59.6
31.2
45.6
27.5
38.4
400 ms
600 ms
800 ms
22.2
28.1
29.2
41.8
31.5
45.2
Table 3. Maximum Average Current in Low Power Mode, VCC = 3.6 V, Load of 50 pF on SRC Pin
Number of Conversion Stages, Current Values Expressed in ꢀA
Low Power Mode Delay
Decimation Rate
1
2
3
4
5
6
7
8
200 ms
128
256
128
256
128
256
128
256
42.2
53.2
36.1
41.8
34.1
37.9
33.1
35.9
50.5
69.3
40.4
50.1
37.0
43.5
35.2
40.1
58.7
84.9
44.5
58.2
39.7
49.0
37.3
44.3
66.7
100.0
48.7
66.2
42.5
54.5
39.4
48.4
74.6
114.6
52.8
74.1
45.3
60.0
41.5
52.6
82.3
128.7
56.9
82.0
48.1
65.2
43.6
56.6
90.0
142.5
60.9
89.5
50.8
70.5
45.7
60.7
97.5
155.8
64.5
97.1
53.4
75.7
47.7
64.7
400 ms
600 ms
800 ms
Rev. 0 | Page 4 of 56
AD7143
I2C TIMING SPECIFICATIONS
TA = −40°C to +85°C, VCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals timed
from a voltage level of 1.6 V.
Table 4. I2C Timing Specifications1
Parameter
Limit
400
0.6
1.3
0.6
100
300
0.6
0.6
1.3
Unit
Description
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
kHz max
μs min
μs min
μs min
ns min
ns min
μs min
μs min
μs min
ns max
ns max
Start condition hold time, tHD; STA
Clock low period, tLOW
Clock high period, tHIGH
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Stop condition setup time, tSU; STO
Start condition setup time, tSU; STA
Bus free time between stop and start conditions, tBUF
Clock/data rise time
tR
tF
300
300
Clock/data fall time
1 Guaranteed by design, not production tested.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 5 of 56
AD7143
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VCC to GND
−0.3 V to +3.6 V
−0.3 V to VCC + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3V to VDRIVE + 0.3 V
10 mA
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except
Supplies1
ESD Rating (Human Body Model)
Operating Temperature Range
Storage Temperature Range
Junction Temperature
LFCSP_VQ
2.5 kV
−40°C to +150°C
−65°C to +150°C
150°C
ESD CAUTION
Power Dissipation
450 mW
θJA Thermal Impedance
IR Reflow Peak Temperature
135.7°C/W
260°C ( 0.5°C)
Lead Temperature (Soldering 10 sec) 300°C
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. 0 | Page 6 of 56
AD7143
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 SDA
CIN2
CIN3
CIN4
CIN5
1
2
3
4
11 VDRIVE
10 GND
AD7143
TOP VIEW
(Not to Scale)
9
VCC
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
7
8
CSHIELD
SRC
CDC Shield Potential Output. Requires 10 nF capacitor to ground.
CDC Excitation Source Output.
9
VCC
CDC Supply Voltage.
10
11
12
13
14
15
16
GND
VDRIVE
SDA
SCLK
INT
Ground Reference Point for All CDC Circuitry. Tie to ground plane.
I2C Serial Interface Operating Voltage
I2C Serial Data Input/Output. SDA requires pull-up resistor.
Clock Input for Serial Interface. SCLK requires pull-up resistor.
General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor.
Capacitance Sensor Input.
CIN0
CIN1
Capacitance Sensor Input.
Rev. 0 | Page 7 of 56
AD7143
TYPICAL PERFORMANCE CHARACTERISTICS
1000
2.45
2.30
2.15
2.00
1.85
1.70
1.55
1.40
980
DEVICE 1
DEVICE 2
960
DEVICE 3
940
920
DEVICE 2
DEVICE 1
DEVICE 3
900
880
860
840
820
2.7
2.8
2.9
3.0
3.1
V
3.2
(V)
3.3
3.4
3.5
3.6
2.7
2.8
2.9
3.0
3.1
V
3.2
(V)
3.3
3.4
3.5
3.6
CC
CC
Figure 4. Supply Current vs. Supply Voltage
Figure 7. Shutdown Supply Current vs. Supply Voltage
1.10
180
DEVICE 1
LP_CONV_DELAY = 200ms
160
140
120
100
80
1.05
1.00
0.95
0.90
0.85
0.80
LP_CONV_DELAY = 400ms
DEVICE 3
DEVICE 2
LP_CONV_DELAY = 600ms
LP_CONV_DELAY = 800ms
60
40
2.7
2.8
2.9
3.0
3.1
V
3.2
(V)
3.3
3.4
3.5
3.6
0
50
100 150 200 250 300 350 400 450 500
CAPACITANCE LOAD ON SOURCE (pF)
CC
Figure 8. Supply Current vs. Capacitive Load on SRC
Figure 5. Low Power Supply Current vs. Supply Voltage,
Decimation Rate = 256
120
16015
16010
16005
16000
15995
15990
15985
15980
DEVICE 1
100
80
LP_CONV_DELAY = 200ms
DEVICE 2
LP_CONV_DELAY = 400ms
LP_CONV_DELAY = 600ms
60
DEVICE 3
40
LP_CONV_DELAY = 800ms
20
0
50
100 150 200 250 300 350 400 450 500
CAPACITANCE LOAD ON SOURCE (pF)
2.7
2.8
2.9
3.0
3.1
3.2
(V)
3.3
3.4
3.5
3.6
V
CC
Figure 9. Output Code vs. Capacitive Load on SRC
Figure 6. Low Power Supply Current vs. Supply Voltage
Decimation Rate = 128
Rev. 0 | Page 8 of 56
AD7143
0.020
0.015
0.010
0.005
0
960
940
920
900
880
860
840
820
800
780
3.6V
3.3V
CDC OUTPUT CODE
–0.005
–0.010
2.7V
0
10k
20k
30k
40k
50k
60k
70k
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
CDC OUTPUT CODE
Figure 13. 3.3 V Linearity Error
Figure 10. Supply Current vs. Temperature
12
10
8
2.5
2.0
1.5
1.0
0.5
0
100mV
200mV
300mV
400mV
500mV
6
3.6V
3.3V
4
2
2.7V
100
0
–40
–20
0
20
40
60
80
120
10
1k
100k
FREQUENCY (Hz)
10M
TEMPERATURE (°C)
Figure 11. Shutdown Supply Current vs. Temperature
Figure 14. Power Supply Sine Wave Rejection
180
160
140
120
100
80
4.8
4.3
3.8
3.3
2.8
2.3
1.8
1.3
CDC OUTPUT CODE
300mV
200mV
60
40
100mV
50mV
25mV
20
0
100
1k
10k
100k
1M
10M
0
10k
20k
30k
40k
50k
60k
SQUARE WAVE FREQUENCY (Hz)
CDC OUTPUT CODE
Figure 15. Power Supply Square Wave Rejection
Figure 12. 3.3 V Linearity
Rev. 0 | Page 9 of 56
AD7143
32900
32800
32700
32600
32500
32400
32300
32200
32100
32000
PARASITIC
CAPACITANCE
31900
0
10
20
30
40
50
60
PCB PARASITIC CAPACITANCE (pF)
Figure 16. CDC Output Codes vs. Parasitic Capacitance
Rev. 0 | Page 10 of 56
AD7143
THEORY OF OPERATION
The AD7143 is a capacitance-to-digital converter (CDC) with
on-chip environmental compensation, intended for use in
portable systems requiring high resolution user input. The
internal circuitry consists of a 16-bit, ∑-Δ converter that
converts a capacitive input signal into a digital value. There are
eight input pins, CIN0 to CIN7, on the AD7143. A switch
matrix routes the input signals to the CDC. The result of each
capacitance-to-digital conversion is stored in on-chip registers.
The host subsequently reads the results over the serial interface.
The AD7143 has an I2C interface, ensuring that the parts are
compatible with a wide range of host processors.
The AD7143 operates from a 2.6 V to 3.6 V supply, and is
available in a 16-lead, 4 mm × 4 mm LFCSP_VQ.
CAPACITANCE SENSING THEORY
The AD7143 uses a method of sensing capacitance known as
the shunt method. Using this method, an excitation source is
connected to a transmitter generating an electric field to a
receiver. The field lines measured at the receiver are translated
into the digital domain by a ∑-Δ converter. When a finger, or
other grounded object, interferes with the electric field, some of
the field lines are shunted to ground and do not reach the
receiver (see Figure 17). Therefore, the total capacitance
measured at the receiver decreases when an object comes close
to the induced field.
The AD7143 interfaces with up to eight external capacitance
sensors. These sensors can be arranged as buttons, scroll bars,
wheels, or as a combination of sensor types. The external
sensors consist of electrodes on a single or multiple layer PCB
that interface directly to the AD7143.
The AD7143 can be set up to implement any set of input
sensors by programming the on-chip registers. The registers can
also be programmed to control features such as averaging,
offsets, and gains for each of the external sensors. There is a
sequencer on-chip to control how each of the capacitance
inputs is polled.
PLASTIC COVER
Rx
PCB LAYER
Tx
16-BIT
DATA
The AD7143 has on-chip digital logic and 528 words of RAM
used for environmental compensation. The effects of humidity,
temperature, and other environmental factors can effect the
operation of capacitance sensors. Transparent to the user, the
AD7143 performs continuous calibration to compensate for
these effects, allowing the AD7143 to give error-free results at
all times.
EXCITATION
SIGNAL
250kHz
Σ-Δ
ADC
AD7143
Figure 17. Single Layer Sensing Capacitance Method
In practice, the excitation source and ∑-Δ ADC are implemented
on the AD7143, while the transmitter and receiver are constructed
on a PCB that comprises the external sensor.
The AD7143 requires some minor companion software that
runs on the host or other microcontroller to implement high
resolution sensor functions, such as a scroll bar or wheel.
However, no host software is required to implement buttons,
including 8-way button functionality. Button sensors are
implemented completely in digital logic on-chip with the status
of each button reported in interrupt status registers.
Registering a Sensor Activation
When a sensor is approached, the total capacitance associated
with that sensor, measured by the AD7143, changes. When the
capacitance changes to such an extent that a set threshold is
exceeded, the AD7143 registers this as a sensor touch and then
automatically updates the internal interrupt status registers.
The AD7143 can be programmed to operate in either full power
mode, or in low power automatic wake-up mode. The
automatic wake-up mode is particularly suited for portable
devices that require low power operation giving the user
significant power savings coupled with full functionality.
Preprogrammed threshold levels are used to determine if a
change in capacitance is due to a button being activated. If the
capacitance exceeds one of the threshold limits, the AD7143
registers this as a true button activation. The same threshold
principle is used to determine if other types of sensors, such as
sliders or scroll wheels, are activated.
INT
The AD7143 has an interrupt output,
, to indicate when
INT
new data has been placed into the registers.
interrupt the host on sensor activation.
is used to
Rev. 0 | Page 11 of 56
AD7143
Full Power Mode
Complete Solution for Capacitance Sensing
In full power mode, all sections of the AD7143 remain fully
powered at all times. While a sensor is being touched, the
AD7143 processes the sensor data. If no sensor is touched, the
AD7143 measures the ambient capacitance level and uses this
data for the on-chip compensation routines. In full power
mode, the AD7143 converts at a constant rate. See the CDC
Conversion Sequence Time section for more information.
Analog Devices, Inc. provides a complete solution for
capacitance sensing. The two main elements to the solution are
the sensor PCB and the AD7143.
If the application requires high resolution sensors, such as scroll
bars or wheels, software is required that runs on the host
processor. (No software is required for button sensors.) The
memory requirements for the host depend upon the sensor, and
are typically 9 kB of code and 600 bytes of data memory.
Low Power Mode
When in low power mode, the AD7143 POWER_MODE bits
are set to 10 upon device initialization. If the external sensors
are not touched, the AD7143 reduces its conversion frequency,
thereby greatly reducing its power consumption. The part
remains in a reduced power state when the sensors are not
touched. Every LP_CONV_DELAY ms (200 ms, 400 ms, 600
ms or 800 ms), the AD7143 performs a conversion and uses this
data to update the compensation logic. When an external
sensor is touched, the AD7143 begins a conversion sequence
every 25 ms to read back data from the sensors.
SENSOR PCB
S1
S2
S3
S4
S5
S6
S7
S8
HOST PROCESSOR
1 MIPS
2
I C
8
AD7143
9kB ROM
600 BYTES RAM
SRC
In low power mode, the total current consumption of the
AD7143 is an average of the current used during a conversion,
and the current used while the AD7143 is waiting for the next
conversion to begin. For example, when LP_CONV_DELAY is
400 ms, the AD7143 typically uses 0.9 mA current for 25 ms
and 15 ꢀA for 400 ms of the conversion interval. Note that these
conversion timings can be altered through the register settings.
See the CDC Conversion Sequence Time section for more
information.
Figure 18. Three Part Capacitance Sensing Solution
Analog Devices supplies the sensor PCB footprint design
libraries to the customer based on the customer’s specifications,
and supplies any necessary software on an open-source basis.
OPERATING MODES
The AD7143 has three operating modes. Full power mode,
where the device is always fully powered, is suited for applications
where power is not a concern. One example is game consoles
that have an ac power supply. Low power mode, where the part
automatically powers down, is tailored to give significant power
savings over full power mode, and is suited for mobile applications
where power must be conserved. In shutdown mode, the part
shuts down completely.
AD7143 SETUP
AND INITIALIZATION
POWER_MODE = 10
ANY
NO
YES
SENSOR
TOUCHED?
CONVERSION SEQUENCE
EVERY LP_CONV_DELAY ms
UPDATE COMPENSATION
LOGIC DATA PATH
CONVERSION SEQUENCE
EVERY 25ms FOR
SENSOR READBACK
The POWER_MODE bits (Bit 0 and Bit 1) of the control
register set the operating mode on the AD7143. The control
register is at Address 0x000. Table 6 shows the POWER_MODE
settings for each operating mode. To put the AD7143 into
shutdown mode, set the POWER_MODE bits to either 01 or 11.
YES
ANY SENSOR
TOUCHED?
NO
Table 6. POWER_MODE Settings
TIMEOUT
PROXIMITY TIMER
COUNT DOWN
POWER_MODE Bits
Operating Mode
Figure 19. Low Power Mode Operation
00
01
10
11
Full power mode
Full shutdown mode
Low power mode
Full shutdown mode
The time taken for the AD7143 to go from a full power state to
a reduced power state, once the user stops touching the external
sensors, is configurable. Once the sensors are not touched, the
PWR_DWN_TIMEOUT bits, in the Ambient Compensation
Ctrl 0 Register at Address 0x002, control the amount of time
necessary for the device to return to a reduced power state.
The power-on default setting of the POWER_MODE bits is 00,
full power mode.
Rev. 0 | Page 12 of 56
AD7143
CAPACITANCE SENSOR INPUT CONFIGURATION
Each input connection from the external capacitance sensors to
the AD7143 converter can be uniquely configured by using the
registers in Table 38 and Table 39. These registers are used to
configure input pin connection setups, sensor offsets, sensor
sensitivities, and sensor limits for each stage. Each sensor can be
individually optimized. For example, a button sensor connected
to STAGE0 can have a different sensitivity and offset values
than a button with a different function that is connected to a
different stage.
The AD7143 has an on-chip multiplexer to route the input
signals from each pin to the input of the converter. Each input
pin can be tied to either the negative or the positive input of the
CDC or can be left floating. Each input can also be internally
connected to the CSHIELD signal to help prevent cross coupling. If
an input is not used, always connect it to CSHIELD
.
Connecting a CINx input pin to the positive CDC input results
in a decrease in CDC output code when the corresponding
sensor is activated. Connecting a CINx input pin to the negative
CDC input results in an increase in CDC output code when the
corresponding sensor is activated.
CIN INPUT MULTIPLEXER SETUP
The CIN_CONNECTION_SETUP registers in Table 38 list the
available options for connecting the sensor input pin to the CDC.
Two bits in each sequencer stage register control the mux
setting for the input pin.
CIN CONNECTION SETUP BITS
CIN SETTING
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
00
01
10
11
CINx FLOATING
CINx CONNECTED TO
NEGATIVE CDC INPUT
+
–
CDC
CINx CONNECTED TO
POSITIVE CDC INPUT
CINx CONNECTED TO
INTERNAL BIAS
Figure 20. Input Mux Configuration Options
Rev. 0 | Page 13 of 56
AD7143
CAPACITIANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7143 has a Σ-ꢁ
architecture with 16-bit resolution. Eight possible inputs to the
CDC are connected to the input of the converter through a
switch matrix. The sampling frequency of the CDC is 250 kHz.
A simplified block diagram in Figure 22 shows how to apply the
STAGE_OFFSET registers to null the offsets. The 7-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET registers program
the offset DAC to provide 0.16 pF resolution offset adjustment
over a range of 20 pF. Apply the positive and negative offsets
to either the positive or the negative CDC input using the
NEG_AFE_OFFSET register and POS_AFE_OFFSET register.
This process is only required once during the initial capacitance
sensor characterization.
OVERSAMPLING THE CDC OUTPUT
The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the PWR_CONTROL register located at Address 0x000
and listed in Table 7.
7
+DAC
(20pF RANGE)
Table 7. CDC Decimation Rate
POS_AFE_OFFSET
Decimation Bit
Value
Decimation
Rate
CDC Output Rate
Per Stage
00
01
101
111
256
128
–
3.072 ms
1.525 ms
–
–
POS_AFE_OFFSET_SWAP BIT
CIN
+
_
16
16-BIT
CDC
–
1 Do not use this setting.
NEG_AFE_OFFSET_SWAP BIT
The decimation process on the AD7143 is an averaging process
where a number of samples are taken and the averaged result is
output. Due to the architecture of the digital filter employed, the
amount of samples taken (per stage) is equal to 3× the
decimation rate. Therefore, 3 × 256 or 3 × 128 samples are
averaged to obtain each stage result.
SRC
7
–DAC
(20pF RANGE)
NEG_AFE_OFFSET
CIN_CONNECTION_SETUP
REGISTER
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage thus, a trade-off is possible
between a noise free signal and speed of sampling.
Figure 22. Analog Front-End Offset Control
CONVERSION SEQUENCER
The AD7143 has an on-chip sequencer to implement
conversion control for the input channels. Up to eight
conversion stages can be performed in sequence. Each of the
eight conversion stages can measure an input from a different
sensor. By using the Bank 2 registers, each stage can be uniquely
configured to support multiple capacitance sensor interface
requirements. For example, a sensor S1 can be assigned to
STAGE1 and sensor S2 assigned to STAGE2.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7143 to
null any capacitance sensor offsets. These offsets are associated
with printed circuit board capacitance or capacitance due to any
other source, such as connectors. In Figure 21, CIN is the
capacitance of the input sensors, while CBULK is the capacitance
between layers of the sensor PCB. CBULK can be offset using the
on-board DACs.
The AD7143 on-chip sequence controller provides conversion
control beginning with STAGE0. Figure 23 shows a block diagram of
the CDC conversion stages and CIN inputs. A conversion sequence is
a sequence of CDC conversions starting at STAGE0 and ending at
the stage determined by the value programmed in the
C
IN
PLASTIC OVERLAY
SENSOR BOARD
C
BULK
CAPACITIVE SENSOR
SEQUENCE_STAGE_NUM register. Depending on the number and
type of capacitance sensors used, not all conversion stages are
required. Use the SEQUENCE_STAGE_NUM register to set the
number of conversions in one sequence, depending on the sensor
interface requirements. For example, this register is set to 5 if the CIN
inputs are mapped to only six stages. In addition, set the
STAGE_CAL_EN registers according to the number of stages that
are used.
Figure 21. Capacitances Around the Sensor PCB
Rev. 0 | Page 14 of 56
AD7143
STAGE7
STAGE6
In this case, only one button from the pair is activated at a time;
pressing both buttons together activates neither button. This
example is shown in Figure 24 for sensor buttons S2 and S3.
STAGE5
STAGE4
STAGE3
A scroll bar or slider requires eight stages. The result from each
stage is used by the host software to determine the user’s
position on the scroll bar. The algorithm that performs this
process is available from Analog Devices free of charge, upon
signing a software license. Scroll wheels also require eight stages.
STAGE2
STAGE1
STAGE0
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CDC CONVERSION SEQUENCE TIME
The time required for one complete measurement for all eight
stages by the CDC is defined as the CDC conversion sequence
time. The SEQUENCE_STAGE_NUM register and
DECIMATION register determine the conversion time as listed
in Table 8.
Σ-Δ
16-BIT
ADC
CE
N
E
U
Q
E
S
N
O
I
RS
E
NV
Table 8. CDC Conversion Times for Full Power Mode
CO
Conversion Time (ms)
Figure 23. CDC Conversion Stages
SEQUENCE_STAGE_NUM
Decimation = 128
1.525
Decimation = 256
3.072
0
1
2
3
4
5
6
7
The number of required conversion stages depends completely
on the number of sensors attached to the AD7143. Figure 24
shows how many conversion stages are required for each sensor,
and how many inputs each sensor requires to the AD7143.
3.072
4.608
6.144
7.68
9.216
10.752
12.288
6.144
9.216
12.288
15.25
18.432
21.504
24.576
AD7143
SEQUENCER
STAGE0
+
8-ELEMENT
SLIDER
CDC
–
For example, while operating with a decimation rate of 128,
if the SEQUENCE_STAGE_NUM register is set to 5 for the
conversion of six stages in a sequence, the conversion sequence
time is 9.216 ms.
STAGE1
+
CDC
–
AD7143
STAGE2
SEQUENCER
+
BUTTONS
S1
CDC
–
STAGE0
+
Full Power Mode CDC Conversion Sequence Time
CDC
–
STAGE3
+
CDC
–
The full power mode CDC conversion sequence time for all
eight stages is set by configuring the SEQUENCE_STAGE_NUM
register and the DECIMATION register as outlined in Table 8.
STAGE1
S2
S3
+
STAGE4
CDC
–
+
CDC
–
STAGE5
SRC
+
Figure 25 shows a simplified timing diagram of the full power
CDC conversion time. The full power mode CDC conversion
time tCONV_FP is set using Table 8.
CDC
–
STAGE6
+
CDC
–
STAGE7
SRC
tCONV_FP
+
CDC
–
CONVERSION
CONVERSION
CONVERSION
CDC
CONVERSION
SEQUENCE N SEQUENCE N + 1 SEQUENCE N + 2
Figure 24. Sequencer Setup for Sensors
Figure 25. Full Power Mode CDC Conversion Sequence Time
A button sensor generally requires one sequencer stage.
However, it is possible to configure two button sensors to
operate differentially for special applications where the user
should not press both buttons simultaneously, such as a with
rocker zoom switch on a digital camera.
Rev. 0 | Page 15 of 56
AD7143
Low Power Mode CDC Conversion Sequence Time
with Delay
Figure 26 shows a simplified timing example of the low power
CDC conversion time. As shown, the low power CDC
conversion time is set by tCONV_FP and the LP_CONV_DELAY
register.
The frequency of each CDC conversion while operating in the
low power automatic wake-up mode is controlled by using the
LP_CONV_DELAY register located at Address 0x000[3:2], in
addition to the registers listed in Table 8.
tCONV_LP
tCONV_FP
This feature provides some flexibility for optimizing the
conversion time to meet system requirements vs. AD7143
power consumption. For example, maximum power savings is
achieved when the LP_CONV_DELAY register is set to 3. With
a setting of 3, the AD7143 automatically wakes up, performing a
conversion every 800 ms.
CDC
CONVERSION
SEQUENCE N
CONVERSION
SEQUENCE N + 1
LP_CONV_DELAY
CONVERSION
Figure 26. Low Power Mode CDC Conversion Sequence Time
CDC CONVERSION RESULTS
Certain high-resolution sensors require the host to read back
the CDC conversion results for processing. The registers
required for host processing are located in the Bank 3 registers.
The host processes the data readback from these registers using
a software algorithm to determine position information. In
addition to the results registers in the Bank 3 registers, the
AD7143 provides the 16-bit CDC output data directly starting
at Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.
Table 9. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits
Delay Between Conversions
00
01
10
11
200 ms
400 ms
600 ms
800 ms
Rev. 0 | Page 16 of 56
AD7143
NONCONTACT PROXIMITY DETECTION
The AD7143 internal signal processing continuously monitors
all capacitance sensors for noncontact proximity detection. This
feature provides the ability to detect when a user is approaching
a sensor, immediately disabling all internal calibration while the
AD7143 is automatically configured to detect a valid contact.
timeout is controlled by FP_PROXIMITY_RECAL and in low
power mode, it is controlled by LP_PROXMTY_RECAL.
Recalibration timeout in full power mode =
FP_PROXIMITY_RECAL × Time for one conversion
sequence in full power mode
The proximity control register bits are described in Table 10.
FP_PROXIMITY_CNT register bits and LP_PROXIMITY
_CNT register bits control the length of the calibration disable
period after proximity is detected in full power and low power
modes. The calibration is disabled during this time and enabled
again at the end of this period if the user is no longer
approaching, or in contact with, the sensor. Figure 27 and Figure
28 show examples of how these registers are used to set the full
and low power mode calibration disable periods.
Recalibration timeout in low power mode =
LP_PROXIMITY_RECAL × Time taken for one conversion
sequence in low power mode
Figure 29 and Figure 30 show examples of using the
FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL
register bits to force a recalibration while operating in the full
and low power modes. These figures show the result of a user
approaching a sensor then leaving the sensor while the
proximity detection remains active after the user discontinues
contact with the sensor. This situation could occur if the user
interaction created some moisture on the sensor causing the
new sensor value to be different from the expected value. In this
case, the internal recalibration is applied to automatically
recalibrate the sensor. The forced recalibration event takes two
interrupt cycles; therefore, it should not be set again during this
interval.
Calibration disable period in full power mode =
(FP_PROXIMITY_CNT × 16 × Time for one conversion
sequence in full power mode)
Calibration disable period in low power mode =
(LP_PROXIMITY_CNT × 4 × Time for one conversion
sequence in low power mode)
RECALIBRATION
PROXIMITY SENSITIVITY
In certain situations, the proximity flag can be set for a long
period, such as when a user hovers over a sensor for a long
time. The environmental calibration on the AD7143 is
suspended while the proximity is detected, but changes may
occur to the ambient capacitance level during the proximity
event. Even when the user has left the sensor untouched, the
proximity flag may still be set. This could occur if the user
interaction creates some moisture on the sensor causing the
new sensor value to be different from the expected value. In this
case, the AD7143 automatically forces an internal recalibration.
This ensures that the ambient values are recalibrated, regardless
of how long the user hovers over a sensor.
The fast filter in Figure 31 is used to detect when some one is in
close proximity to the sensor. Two conditions set the internal
proximity detection signal using Comparator 1 and Comparator 2.
Comparator 1 detects when a user is approaching a sensor.
The PROXIMITY_DETECTION_RATE register controls the
sensitivity of Comparator 1. Consider, for example, if the
PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1
signal is set when the absolute difference between WORD1 and
WORD3 exceeds four LSB codes.
Comparator 2 detects when a user hovers over a sensor or
approaches a sensor very slowly. The PROXIMITY_RECAL_LVL
register (Address 0x003) controls the sensitivity of Comparator 2.
For example, if PROXIMITY_RECAL_LVL is set to 75, the
Proximity 2 signal is set when the absolute difference between
the fast filter average value and the ambient value exceeds 75
LSB codes.
The AD7143 recalibrates automatically when the measured CDC value
exceeds the stored ambient value by an amount determined by
PROXIMITY_RECAL_LVL, for a set period know as the
recalibration timeout. In full power mode, the recalibration
Table 10. Proximity Control Registers (See Figure 31)
Register
Length
4 bits
4 bits
8 bits
6 bits
8 bits
6 bits
Register Address
Description
FP_PROXIMITY_CNT
LP_PROXIMITY_CNT
FP_PROXIMITY_RECAL
LP_PROXIMITY_RECAL
PROXIMITY_RECAL_LVL
PROXIMITY_DETECTION_RATE
0x002 [7:4]
0x002 [11:8]
0x004 [9:0]
0x004 [15:10]
0x003 [13:8]
0x003 [7:0]
Calibration disable time in full power mode
Calibration disable time in low power mode
Full power mode proximity recalibration control
Low power mode proximity recalibration control
Proximity recalibration level
Proximity detection rate
Rev. 0 | Page 17 of 56
AD7143
USER APPROACHES USER LEAVES SENSOR
SENSOR HERE AREA HERE
tCONV_FP
CDC CONVERSION
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tCALDIS
SEQUENCE
(INTERNAL)
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
Figure 27. Full Power Mode Proximity Detection Example with FP_PROXIMITY_CNT = 1
USER APPROACHES USER LEAVES SENSOR
SENSOR HERE
AREA HERE
tCONV_LP
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CDC CONVERSION
SEQUENCE
(INTERNAL)
tCALDIS
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP = tCONV_FP + LP_CONV_DELAY.
2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED.
3. tCALDIS = (tCONV_LP × LP_PROXIMITY_CNT × 4).
Figure 28. Low Power Mode Proximity Detection with LP_PROXIMITY_CNT = 4 and LP_CONV_DELAY = 0
USER APPROACHES
SENSOR HERE
tRECAL
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
USER LEAVES SENSOR
AREA HERE
tCONV_FP
16
30
70
CDC CONVERSION
SEQUENCE
(INTERNAL)
tCALDIS
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
RECALIBRATION TIMEOUT
tRECAL_TIMEOUT
CALIBRATION ENABLED
RECALIBRATION
COUNTER
(INTERNAL)
NOTES
1. tCALDIS
=
tCONV_FP × FP_PROXIMITY_CNT × 16.
2. tRECAL_TIMEOUT
= tCONV_FP × FP_PROXIMITY_RECAL.
3. tRECAL = 2 × tCONV_FP
.
Figure 29. Full Power Mode Proximity Detection with Forced Recalibration Example with FP_PROXIMIT_CNT = 1 and FP_PROXIMITY_RECAL = 40
Note that in Figure 29, the sequence conversion time, tCONV_FP, is determined from Table 8.
Rev. 0 | Page 18 of 56
AD7143
USER APPROACHES
SENSOR HERE
tRECAL
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
USER LEAVES SENSOR
AREA HERE
tCONV_FP
16
30
70
CDC CONVERSION
SEQUENCE
(INTERNAL)
PROXIMITY
DETECTION
(INTERNAL)
tCALDIS
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
RECALIBRATION TIMEOUT
tRECAL_TIMEOUT
CALIBRATION ENABLED
RECALIBRATION
(INTERNAL)
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP
2. tCALDIS tCONV_LP × LP_PROXIMITY_CNT × 4.
3. tRECAL_TIMEOUT tCONV_FP × LP_PROXIMITY_RECAL.
4. tRECAL = 2 × tCONV_LP
=
tCONV_FP + LP_CONV_DELAY.
=
=
.
Figure 30. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMIT_CNT = 4 and LP_PROXIMITY_RECAL = 10
FF_SKIP_CNT
capacitance value tracks the measured capacitance value read by
the converter.
The proximity detection fast FIFO is used by the on-chip logic
to determine if proximity is detected. The fast FIFO expects to
receive samples from the converter at a set rate. Using
FF_SKIP_CNT normalizes the frequency of the samples going
into the FIFO, regardless of how many conversion stages are in a
sequence. In Register 0x02, Bits[3:0] are the fast filter skip control,
FF_SKIP_CNT. This value determines which CDC samples are not
used (skipped) in the proximity detection fast FIFO.
Slow FIFO update rate in full power mode is equal to
AVG_FP_SKIP × [(3 × Decimation Rate) ×
(SEQUENCE_STAGE_NUM +1) × (FF_SKIP_CNT +1) × 4 × 10-7]
Slow FIFO update rate in low power mode is equal to
(AVG_LP_SKIP +1) × [(3 × Decimation Rate) ×
SEQUENCE_STAGE_NUM +1) × (FF_SKIP_CNT +1) × 4 × 10-7] /
[(FF_SKIP_CNT +1)+ LP_CONV_DELAY]
Determining the FF_SKIP_CNT value is required only once
during the initial setup of the capacitance sensor interface.
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples
from the converter at a rate of 33 ms to 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many
conversion stages are in a sequence.
Table 11 shows how FF_SKIP_CNT controls the update rate to
the fast FIFO. The recommended value for FF_SKIP_CNT
when using all 12 conversion stages on the AD7143 is
FF_SKIP_CNT = 0000 = no samples skipped
Determining the AVG_FP_SKIP and AVG_LP_SKIP value is
only required once during the initial setup of the capacitance
sensor interface. Recommended values for these settings when
using all 12 conversion stages on the AD7143 are
SLOW FIFO
As shown in Figure 31, a number of FIFOs are implemented on
the AD7143. These FIFOs are located in Bank 3 of the on-chip
memory. The slow FIFOs are used by the on-chip logic to
monitor the ambient capacitance level from each sensor.
AVG_FP_SKIP = 00 = skip 3 samples
AVG_LP_SKIP = 00 = no samples skipped
AVG_FP_SKIP and AVG_LP_SKIP
SLOW_FILTER_UPDATE_LVL
In Register 0x001, Bits[13:12] are the slow FIFO skip control for
full power mode, AVG_FP_SKIP. Bits[15:14] in the same
register are the slow FIFO skip control for low power mode,
AVG_LP_SKIP. These values determine which CDC samples
are not used (skipped) in the slow FIFO. Changing theses values
slows down or speeds up the rate at which the ambient
The SLOW_FILTER_UPDATE_LVL controls whether or not
the most recent CDC measurement goes into the slow FIFO
(slow filter). The slow filter is updated when the difference
between the current CDC value and last value pushed into the
slow FIFO is greater than SLOW_FILTER_UPDATE_LVL. This
variable is in Ambient Control Register 1, at Address 0x003.
Rev. 0 | Page 19 of 56
AD7143
Table 11. FF_SKIP_CNT Settings
FAST FIFO Update Rate
Decimation = 256
FF_SKIP_CNT
Decimation = 128
0
1
2
3
4
5
6
7
1.525 × (SEQUENCE_STAGE_NUM + 1) ms
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
4.608 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
7.68 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
10.752 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
13.824 × (SEQUENCE_STAGE_NUM + 1) ms
15.25 × (SEQUENCE_STAGE_NUM + 1) ms
16.896 × (SEQUENCE_STAGE_NUM + 1) ms
18.432 × (SEQUENCE_STAGE_NUM + 1) ms
19.968 × (SEQUENCE_STAGE_NUM + 1) ms
21.504 × (SEQUENCE_STAGE_NUM + 1) ms
23.04 × (SEQUENCE_STAGE_NUM + 1) ms
24.576 × (SEQUENCE_STAGE_NUM + 1) ms
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
15.25 × (SEQUENCE_STAGE_NUM + 1) ms
18.432 × (SEQUENCE_STAGE_NUM + 1) ms
21.504 × (SEQUENCE_STAGE_NUM + 1) ms
24.576 × (SEQUENCE_STAGE_NUM + 1) ms
27.648 × (SEQUENCE_STAGE_NUM + 1) ms
30.72 × (SEQUENCE_STAGE_NUM + 1) ms
33.792 × (SEQUENCE_STAGE_NUM + 1) ms
25.864 × (SEQUENCE_STAGE_NUM + 1) ms
39.925 × (SEQUENCE_STAGE_NUM + 1) ms
43.008 × (SEQUENCE_STAGE_NUM + 1) ms
46.08 × (SEQUENCE_STAGE_NUM + 1) ms
49.152 × (SEQUENCE_STAGE_NUM + 1) ms
8
9
10
11
12
13
14
15
Rev. 0 | Page 20 of 56
AD7143
FP_PROXIMITY_CNT
REGISTER 0x002
LP_PROXIMITY_CNT
REGISTER 0x002
16
CDC
STAGE_FF_WORD0
STAGE_FF_WORD1
STAGE_FF_WORD2
STAGE_FF_WORD3
STAGE_FF_WORD4
STAGE_FF_WORD5
STAGE_FF_WORD6
STAGE_FF_WORD7
PROXIMITY 1
PROXIMITY
COMPARATOR 1
PROXIMITY TIMING
CONTROL LOGIC
|WORD0 TO WORD3|
PROXIMITY_DETECTION_RATE
REGISTER 0x003
FP_PROXIMITY_RECAL
REGISTER 0x004
LP_PROXIMITY_RECAL
REGISTER 0x004
BANK 3 REGISTERS
7
WORD(N)
STAGE_FF_AVG
BANK 3 REGISTERS
Σ
N = 0
8
COMPARATOR 2
|AVERAGE–AMBIENT|
STAGE_FF_WORDx
PROXIMITY
SW1
SLOW_FILTER_EN
PROXIMITY_RECAL_LVL
REGISTER 0x003
STAGE_SF_WORD0
STAGE_SF_WORD1
STAGE_SF_WORD2
STAGE_SF_WORD3
STAGE_SF_WORD4
STAGE_SF_WORD5
STAGE_SF_WORD6
STAGE_SF_WORD7
COMPARATOR 3
WORD0 TO WORD1
AMBIENT
VALUE
STAGE_SF_AMBIENT
BANK 3 REGISTERS
STAGE_SF_WORDx
SLOW_FILTER_UPDATE_LVL
REGISTER 0x003
SENSOR
CONTACT
TIME
NOTES
|STAGE_SF_
|
1. SLOW FILTER EN IS SET AND SW1 IS CLOSED WHEN
WORD 0 TO STAGE_SF_WORD 1 EXCEEDS THE VALUE PROGRAMMED IN THE
SLOW_FILTER_UPDATE_LVL REGISTER PROVIDINGPROXIMITY IS NOT SET.
|STAGE_FF_
|
2. PROXIMITY 1 IS SET WHEN
WORD 0 TO STAGE_FF_WORD 3 EXCEEDS THE VALUE PROGRAMMED IN THE
PROXIMITY_DETECTION_RATE REGISTER.
|
|
3. PROXIMITY 2 IS SET WHEN AVERAGE–AMBIENT EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER.
4. DESCRIPTION OF COMPARATOR FUNCTIONS:
COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR.
COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR, OR APPROACHING A SENSOR VERY SLOWLY.
ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION.
FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR.
COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW FILTER EN IS SET AND
PROXIMITY IS NOT SET.
Figure 31. AD7143 Proximity Detection and Environmental Calibration
STAGE_MAX_WORD0
STAGE_MAX_WORD1
BANK 3 REGISTERS
STAGE_MAX_WORD2
STAGE_MAX_WORD3
STAGE_MAX_AVG
BANK 3 REGISTERS
MAX LEVEL
DETECTION
LOGIC
Σ-Δ
16-BIT
CDC
16
STAGE_MAX_TEMP
BANK 3 REGISTERS
STAGE_HIGH_THRESHOLD
BANK 3 REGISTERS
STAGE_MIN_WORD0
STAGE_MIN_WORD1
STAGE_MIN_WORD2
STAGE_MIN_WORD3
BANK 3 REGISTERS
STAGE_MIN_AVG
BANK 3 REGISTERS
MIN LEVEL
DETECTION
LOGIC
STAGE_MIN_AVG
BANK 3 REGISTERS
STAGE_LOW_THRESHOLD
BANK 3 REGISTERS
Figure 32. AD7143 Maximum and Minimum Level Detection Logic
Rev. 0 | Page 21 of 56
AD7143
ENVIRONMENTAL CALIBRATION
SENSOR 1 INT
ASSERTED
The AD7143 provides on-chip capacitance sensor calibration to
automatically adjust for environmental conditions that have an
effect on the capacitance sensor ambient levels. Capacitance
sensor output levels are sensitive to temperature, humidity, and
in some cases, dirt. The AD7143 achieves optimal and reliable
sensor performance by continuously monitoring the CDC
ambient levels and correcting for any changes by adjusting the
STAGE_HIGH_THRESHOLD and STAGE_LOW_THRESHOLD
register values as described in Equation 1 and Equation 2. The
CDC ambient level is defined as the capacitance sensor output
level during periods when the user is not approaching or in
contact with the sensor.
STAGE_HIGH_THRESHOLD
CDC AMBIENT VALUE
STAGE_LOW_THRESHOLD
SENSOR 2 INT
ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 33. Ideal Sensor Behavior with a Constant Ambient Level
The compensation logic runs automatically on every conversion
after configuration when the AD7143 is not being touched. This
allows the AD7143 to account for rapidly changing
environmental conditions.
CAPACITANCE SENSOR BEHAVIOR WITHOUT
CALIBRATION
Figure 34 shows the typical behavior of a capacitance sensor
with no applied calibration. This figure shows ambient levels
drifting over time as environmental conditions change. The
ambient level drift has resulted in the detection of a missed user
contact on Sensor 2.
The ambient compensation control registers located at
Address 0x002, Address 0x003 and Address 0x004 give the host
access to general setup and controls for the compensation
algorithm. The RAM stores the compensation data for each
conversion stage, as well as setup information specific to each stage.
This is a result of the initial STAGE_LOW_THRESHOLD
remaining constant while the ambient levels drifted upward
beyond the detection range. The Capacitance Sensor Behavior
with Calibration section describes how the AD7143 adaptive
calibration algorithm prevents errors such as this from
occurring.
Figure 33 shows an example of an ideal capacitance sensor
behavior where the CDC ambient level remains constant
regardless of the environmental conditions. The CDC output
shown is for a pair of differential button sensors, where one
sensor caused an increase, and the other a decrease in measured
capacitance when activated.
SENSOR 1 INT
ASSERTED
STAGE_HIGH_THRESHOLD
The positive and negative sensor threshold levels are calculated
as a percentage of the STAGE_OFFSET_HIGH and
STAGE_OFFSET_LOW values based on the threshold
sensitivity settings and the ambient value. These values for this
example are sufficient to detect a sensor contact, resulting with
CCDC AMBIENT
VALUE DRIFTING
INT
the AD7143 asserting the
are exceeded.
output when the threshold levels
STAGE_LOW_THRESHOLD
SENSOR 2 INT
NOT ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 34. Typical Sensor Behavior without Calibration Applied
Rev. 0 | Page 22 of 56
AD7143
SENSOR 1 INT
ASSERTED
CAPACITANCE SENSOR BEHAVIOR WITH
CALIBRATION
3
STAGE_HIGH_THRESHOLD
(POST CALIBRATED
REGISTER VALUE)
2
1
The AD7143 on-chip adaptive calibration algorithm prevents
sensor detection errors, such as the one shown in Figure 34.
This is achieved by monitoring the CDC ambient levels and
readjusting the initial STAGE_OFFSET_HIGH and
STAGE_OFFSET_LOW values according to the amount of
ambient drift measured on each sensor.
CDC AMBIENT
VALUE DRIFTING
6
5
STAGE_LOW_THRESHOLD
(POST CALIBRATED
REGISTER VALUE)
4
The internal STAGE_HIGH_THRESHOLD and
SENSOR 2 INT
ASSERTED
STAGE_LOW_THRESHOLD values, shown in Equation 1 and
Equation 2, are automatically updated based on the new
STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values.
This closed-loop routine ensures the reliability and repeatable
operation of every sensor connected to the AD7143 under
dynamic environmental conditions. Figure 35 shows a
simplified example of how the AD7143 applies the adaptive
calibration process resulting in no interrupt errors under
changing CDC ambient levels due to environmental conditions.
t
CHANGING ENVIRONMENTAL CONDITIONS
1
2
3
4
5
6
INITIAL STAGE_OFFSET_HIGH REGISTER VALUE.
POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD.
POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD.
INITIAL STAGE_LOW_THRESHOLD.
POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD.
POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD.
Figure 35. Typical Sensor Behavior with Calibration Applied on the Data Path
On-Chip Logic Stage High Threshold Calculation
STAGE _ OFFSET _ HIGH
⎛
⎜
⎝
⎞
⎠
STAGE _ HIGH _ THRESHOLD = STAGE _ SF _ AMBIENT +
+
⎟
4
STAGE _ OFFSET _ HIGH
⎛
⎜
⎞
⎛
⎜
⎝
⎞
⎟
⎠
(1)
(2)
STAGE _ OFFSET _ HIGH −
⎟
⎟
4
⎜
× POS _ THRESHOLD _ SENSITIVITY
⎜
⎜
⎝
16
⎟
⎟
⎠
On-Chip Logic Stage Low Threshold Calculation
STAGE _ OFFSET _ LOW
⎛
⎞
STAGE _ LOW _ THRESHOLD = STAGE _ SF _ AMBIENT +
+
⎜
⎟
⎝
4
⎠
STAGE _ OFFSET _ LOW
⎛
⎜
⎞
⎛
⎜
⎝
⎞
⎟
⎠
STAGE _ OFFSET _ LOW −
⎟
⎟
4
⎜
× NEG _ THRESHOLD _ SENSITIVITY
⎜
⎜
⎝
16
⎟
⎟
⎠
Rev. 0 | Page 23 of 56
AD7143
Table 12. Additional Information about Environmental Calibration and Adaptive Threshold Registers
Register
Location Description
NEG_THRESHOLD_SENSITIVITY
NEG_PEAK_DETECT
Bank 2
Bank 2
Used in Equation 2. This value is programmed once at start up.
Used by Internal Adaptive Threshold Logic Only. The NEG_PEAK_DETECT is set to a
percentage of the difference between the ambient CDC value and the minimum
average CDC value. If the output of the CDC gets within the NEG_PEAK_DETECT
percentage of the minimum average, only then is the minimum average value updated.
POS_THRESHOLD_SENSITIVITY
POS_PEAK_DETECT
Bank 2
Bank 2
Used in Equation 1. This value is programmed once at startup.
Used by Internal Adaptive Threshold Logic Only. The POS_PEAK_DETECT is set to a
percentage of the difference between the ambient CDC value, and the maximum
average CDC value. If the output of the CDC gets within the POS_PEAK_DETECT
percentage of the minimum average, only then is the maximum average value updated.
STAGE_OFFSET_LOW
Bank 2
Bank 2
Bank 2
Used in Equation 2. An initial value (based on sensor characterization) is programmed
into this register at startup. The AD7143 on-chip calibration algorithm automatically
updates this register based on the amount of sensor drift due to changing ambient
conditions. Set to 80% of the STAGE_OFFSET_LOW_CLAMP value.
Used in Equation 1. An initial value (based on sensor characterization) is programmed
into this register at startup. The AD7143 on-chip calibration algorithm automatically
updates this register based on the amount of sensor drift due to changing ambient
conditions. Set to 80% of the STAGE_OFFSET_HIGH_CLAMP value.
STAGE_OFFSET_HIGH
STAGE_OFFSET_HIGH_CLAMP
Used by Internal Environmental Calibration and Adaptive Threshold Algorithms Only.
An initial value (based on sensor characterization) is programmed into this register at
startup. The value in this register prevents a user from causing a sensor output value to
exceed the expected nominal value. Set to the maximum expected sensor response,
maximum change in CDC output code.
STAGE_OFFSET_LOW_CLAMP
STAGE_SF_AMBIENT
Bank 2
Bank 3
Used by Internal Environmental Calibration and Adaptive Threshold Algorithms Only.
An initial value (based on sensor characterization) is programmed into this register at
startup. The value in this register prevents a user from causing a sensor output value to
exceed the expected nominal value. Set to the minimum expected sensor response,
minimum change in CDC output code .
Used in Equation 1 and Equation 2. This is the ambient sensor output, when the sensor
is not touched, as calculated using the slow FIFO.
STAGE_HIGH_THRESHOLD
STAGE_LOW_THRESHOLD
Bank 3
Bank 3
Equation 1 Value.
Equation 2 Value.
Rev. 0 | Page 24 of 56
AD7143
ADAPTIVE THRESHOLD AND SENSITIVITY
The AD7143 provides an on-chip self-learning adaptive
threshold and sensitivity algorithm. This algorithm continu-
ously monitors the output levels of each sensor and automatically
rescales the threshold levels proportionally to the sensor area
covered by the user. As a result, the AD7143 maintains optimal
threshold and sensitivity levels for all types of users regardless
of their finger sizes.
On configuration, initial estimates are supplied for both
STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW after
which the calibration engine automatically adjusts the
STAGE_HIGH_THRESHOLD and STAGE_LOW_THRESHOLD
values for sensor response.
Reference A in Figure 36 shows an under sensitive threshold
level for a small finger user, demonstrating the disadvantages of
a fixed threshold level. By enabling the adaptive threshold and
sensitivity algorithm, the positive and negative threshold levels
are determined by the POS_THRESHOLD_SENSITIVITY and
NEG_THRESHOLD_SENSITIVITY register values and the
most recent average maximum sensor output value. These
registers can be used to select 16 different positive and negative
sensitivity levels ranging between 25% and 95.32% of the most
recent average maximum output level referenced from the
ambient value. The smaller the sensitivity percentage setting,
the easier it is to trigger a sensor activation. Reference B shows
that the positive adaptive threshold level is set at almost mid-
sensitivity with a 62.51% threshold level by setting
The threshold level is always referenced from the ambient level
and is defined as the CDC converter output level that must be
exceeded for a valid sensor contact. The sensitivity level is
defined as how sensitive the sensor is before a valid contact is
registered.
Figure 36 provides an example of how the adaptive threshold and
sensitivity algorithm works. The positive and negative sensor
threshold levels are calculated as a percentage of the
STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values
based on the threshold sensitivity settings and the ambient value.
POS_THRESHOLD_SENSITIVITY = 1000. Figure 36 also
provides a similar example for the negative threshold level with
NEG_THRESHOLD_SENSITIVITY = 0001.
AVERAGE MAX VALUE
95.32%
STAGE_OFFSET_HIGH
IS UPDATED
AVERAGE MAX VALUE
62.51% = POS ADAPTIVE
THRESHOLD LEVEL
A
STAGE_OFFSET_HIGH
95.32%
STAGE_OFFSET_HIGH
IS UPDATED HERE
62.51% = POS
ADAPTIVE
THRESHOLD LEVEL
25%
B
25%
AMBIENT LEVEL
25%
NEG ADAPTIVE THRESHOLD LEVEL = 39.08%
STAGE_OFFSET_LOW
IS UPDATED HERE
25%
STAGE_OFFSET_LOW
NEG ADAPTIVE THRESHOLD LEVEL = 39.08%
95.32%
STAGE_OFFSET_LOW
IS UPDATED HERE
95.32%
SENSOR CONTACTED
BY LARGE FINGER
SENSOR CONTACTED
BY SMALL FINGER
Figure 36. Threshold Sensitivity Example with POS_THRESHOLD_SENSITIVITY = 1000 and NEG_THRESHOLD_SENSITIVITY = 0011
Rev. 0 | Page 25 of 56
AD7143
INTERRUPT OUTPUT
The AD7143 has an interrupt output that triggers an interrupt
Configuring the AD7143 into this mode results in the interrupt
being asserted when the user makes contact with the sensor and
again when the user lifts off the sensor. The second interrupt is
required to alert the host processor that the user is no longer
contacting the sensor.
INT
service routine on the host processor. The
signal is on
Pin 14, and is an open-drain output. There are two types of
interrupt events on the AD7143: a CDC conversion complete
interrupt and a sensor touch interrupt. Each interrupt has
enable and status registers described in Table 13. The
conversion complete and sensor threshold interrupts can be
enabled on a per conversion stage basis. The status registers
The registers located at Address 0x005 and Address 0x006 are
used to enable the interrupt output for each stage. The registers
located at Address 0x008 and Address 0x009 are used to read
back the interrupt status for each stage.
INT
indicate what type of interrupt triggered the
pin. Status
INT
registers are cleared, and the
signal is reset high, during a
read operation of the interrupt status registers. The signal
returns high as soon as the read address has been set up.
Figure 37 shows the interrupt output timing during contact with
one of the sensors connected to STAGE0 while operating in the
sensor touch interrupt mode. For a low limit configuration, the
interrupt output is asserted as soon as the sensor is contacted and
again after the user has stopped contacting the sensor.
CDC CONVERSION COMPLETE INTERRUPT
The AD7143 interrupt signal asserts low to indicate the
completion of a conversion stage, and new conversion result
data is available in the registers.
Note that the interrupt output remains low until the host
processor reads back the interrupt status registers located at
Address 0x008 and Address 0x009.
The interrupt can be independently enabled for each conversion
stage. Each conversion stage complete interrupt can be enabled
via the STAGE_COMPLETE_EN register (Address 0x007). This
register has a bit that corresponds to each conversion stage.
Setting this bit to 1 enables the interrupt for that stage. Clearing
this bit to 0 disables the conversion complete interrupt for that
stage. Figure 38 shows an end of conversion interrupt timing
with the STAGE0 interrupt enabled.
The interrupt output is asserted when there is a change in the
threshold status bits. This could indicate that a user is now
touching the sensor(s) for the first time, the number of sensors
being touched has changed, or the user is no longer touching
the sensor(s). Reading the status bits in the interrupt status
register shows the current sensor activations.
FINGER ON SENSOR
In normal operation, the AD7143’s interrupt is enabled only for
the last stage in a conversion sequence as shown in Figure 38.
1
3
FINGER OFF SENSOR
Register 0x00A is the conversion complete interrupt status
register. Each bit in this register corresponds to a conversion
stage. If a bit is set, it means that the conversion complete
interrupt for the corresponding stage was triggered. This
register is cleared on a read, provided the underlying condition
that triggered the interrupt has gone away.
CONVERSION
STAGE
STAGE0
STAGE1
2
4
SERIAL
READ BACK
INT OUTPUT
SENSOR TOUCH INTERRUPT
1
2
3
4
The sensor touch interrupt mode is implemented when the host
processor requires an interrupt only when a sensor is contacted.
USER TOUCHING DOWN ON SENSOR.
ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT.
USER LIFTING OFF OF SENSOR.
ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT.
Figure 37. Example of Sensor Touch Interrupt
Rev. 0 | Page 26 of 56
AD7143
Table 13. Interrupt Mode Registers
Interrupt Enable
Interrupt Status
Register Address
Interrupt Mode
Register Address
Notes
Sensor Touch
Interrupt asserted when the user contacts a sensor.
See Figure 37.
Low
0x005
0x006
0x007
0x008
0x009
0x00A
Enable for the CIN inputs connected to the CDC
positive stage.
Enable for the CIN inputs connected to the CDC
negative stage.
Continuous interrupt at the end of each STAGEx that
is enabled.
High
CDC Conversion Complete
STAGE0 STAGE1 STAGE2 STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 STAGE8 STAGE9 STAGE10 STAGE11 STAGE0 STAGE1
CONVERSIONS
INT
1
2
SERIAL
READS
NOTES
1. THIS IS AN EXAMPLE OF A CDC CONVERSION COMPLETE INTERRUPT.
2. THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED
AT THE END OF A CONVERSION CYCLE FOR STAGE0 ONLY.
3. STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5, AND STAGE9 (x = 0, 5, 9)
STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0
STAGEx_COMPLETE_EN (ADDRESS 0x007) = 1
Figure 38. Example of Configuring the Registers for End of Conversion Interrupt Setup
Rev. 0 | Page 27 of 56
AD7143
SERIAL INTERFACE
The AD7143 is available with a fixed address I2C-compatible
interface.
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
W
7-bit address (MSB first) plus an R/ bit that determines the
I2C COMPATIBLE INTERFACE
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus now remain idle
while the selected device waits for data to be read from, or
The AD7143 supports the industry standard 2-wire I2C serial
interface protocol. The two wires associated with the I2C timing are
the SCLK and the SDA inputs. The SDA is an I/O pin that allows
both register write and register readback operations. The AD7143 is
always a slave device on the I2C serial interface bus.
W
written to it. If the R/ bit is a 0, the master writes to the slave
W
device. If the R/ bit is a 1, the master reads from the slave device.
The AD7143 has a single fixed 7-bit device address,
Address 0101 110. The AD7143 responds when the master
device sends its device address over the bus. The AD7143
cannot initiate data transfers on the bus.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period, since a low-to-high transition when the clock is
high can be interpreted as a stop signal. The number of data
bytes transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave devices
can handle.
Table 14. AD7143 I2C Fixed Device Address
DEV
A6
DEV
A5
DEV
A4
DEV
A3
DEV
A2
DEV
A1
DEV
A0
0
1
0
1
1
1
0
Data Transfer
Data is transferred over the I2C serial interface in 8-bit bytes.
The master initiates a data transfer by establishing a start con-
dition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCLK, remains high. This
indicates that an address/data stream follows.
When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA while SCLK remains high. If the AD7143
encounters a stop condition, it returns to its idle condition, and
the address pointer register resets to Address 0x00.
START
AD7143 DEVICE ADDRESS
REGISTER ADDRESS [A15:A8]
REGISTER ADDRESS [A7:A0]
SDA
DEV DEV DEV DEV DEV DEV DEV
A6 A5 A4 A3 A2 A1 A0
R/W ACK A15 A14
A9
A8 ACK A7
A6
A1
A0
t1
t3
SCLK
1
2
3
4
11
5
6
7
8
9
10
16
17
18
19
20
25
26
t2
STOP
START
REGISTER DATA [D15:D8]
ACK D15 D14
REGISTER DATA [D7:D0]
D6 D1
t5
38
AD7143 DEVICE ADDRESS
DEV DEV DEV
t8
ACK
ACK
45
D9
D8
t4
D7
D0
A6
A5
A4
t6
t7
1
2
3
27
28
29
34
35
36
37
43
44
46
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 1 0].
4. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X ARE DON’T CARE BITS.
5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
Figure 39. Example of I2C Timing for Single Register Write Operation
Rev. 0 | Page 28 of 56
AD7143
Writing Data over the I2C Bus
The process for writing to the AD7143 over the I2C bus is
shown in Figure 39 and Figure 41. The device address is sent
Any data written to the AD7143 after the address pointer has
reached its maximum value is discarded.
All registers on the AD7143 are 16-bit. Two consecutive 8-bit
data bytes are combined and written to the 16-bit registers. To
avoid errors, all writes to the device must contain an even
number of data bytes.
W
over the bus followed by the R/ bit set to 0. This is followed
by two bytes of data that contain the 10-bit address of the
internal data register to be written. The following bit map shows
the upper register address bytes. Note that Bit 7 to Bit 2 in the
upper address byte are don’t care bits. The address is contained
in the 10 LSBs of the register address bytes.
To finish the transaction, the master generates a stop condition
on SDA, or generates a repeat start condition if the master is to
maintain control of the bus.
MSB
7
LSB
6
5
4
3
2
1
0
Reading Data over the I2C Bus
X
X
X
X
X
X
Register Register
Address Address
To read from the AD7143, the address pointer register must first
be set to the address of the required internal register. The master
performs a write transaction, and writes to the AD7143 to set the
address pointer. The master then outputs a repeat start condition
to keep control of the bus, or, if this is not possible, ends the write
transaction with a stop condition. A read transaction is initiated,
Bit 9
Bit 8
The following bit map shows the lower register address bytes.
MSB
7
LSB
6
5
4
3
2
1
0
Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
W
with the R/ bit set to 1.
Addr. Addr. Addr. Addr. Addr. Addr. Addr. Addr.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
The AD7143 supplies the upper eight bits of data from the
addressed register in the first readback byte, followed by the
lower eight bits in the next byte. This is shown in Figure 40 and
Figure 41.
The third data byte contains the 8 MSBs of the data to be
written to the internal register. The fourth data byte contains
the 8 LSBs of data to be written to the internal register.
Because the address pointer automatically increases after each
read, the AD7143 continues to output readback data until the
master puts a no acknowledge and stop condition on the bus. If
the address pointer reaches its maximum value, and the master
continues to read from the part, the AD7143 repeatedly sends
data from the last register addressed.
The AD7143 address pointer register automatically increments
after each write. This allows the master to sequentially write to all
registers on the AD7143 in the same write transaction. However,
the address pointer register does not wrap around after the last
address.
Rev. 0 | Page 29 of 56
AD7143
START
AD7143 DEVICE ADDRESS
REGISTER ADDRESS [A15:A8]
REGISTER ADDRESS [A7:A0]
SDA
DEV DEV DEV DEV DEV DEV DEV
R/W ACK A15 A14
A9
A8 ACK A7
A6
A1
A0
ACK
27
A6
A5
A4
A3
A2
A1
A0
t1
t3
SCLK
1
2
3
4
5
6
7
8
9
10
11
16
17
18
19
20
25
26
t2
P
AD7143 DEVICE ADDRESS
REGISTER DATA [D7:D0]
D6 D1
t5
39
SR
t8
AD7143 DEVICE ADDRESS
DEV DEV DEV
DEV DEV
A6 A5
DEV DEV
A1
D7
D0
ACK
ACK
46
R/W
A6
A5
A4
A0
USING
REPEATED START
t4
t6
t7
34
35
36
37
38
44
45
1
2
3
28
29
30
AD7143 DEVICE ADDRESS
REGISTER DATA [D7:D0]
D6 D1
t5
39
P
P
S
DEV DEV
A6 A5
DEV DEV
A1
D7
D0 ACK
ACK
R/W
A0
t4
SEPARATE READ AND
WRITE TRANSACTIONS
34
35
36
37
38
44
45
46
28
29
30
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 1 0].
5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB Xs ARE DON’T CARE BITS.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY LOW ACK BITS.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
Figure 40. Example of I2C Timing for Single Register Readback Operation
WRITE
7-BIT DEVICE
REGISTER ADDR
[15:8]
REGISTER ADDR
[7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
S
P
W
ADDRESS
READ (USING REPEATED START)
7-BIT DEVICE
ADDRESS
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
P
ACK
S
W
READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS)
7-BIT DEVICE
ADDRESS
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
P
P
ACK
S
S
W
OUTPUT FROM MASTER
OUTPUT FROM AD7143
S = START BIT
P = STOP BIT
SR = REPEATED START BIT
ACK = ACKNOWLEDGE BIT
ACK = NO ACKNOWLEDGE BIT
Figure 41. Example of Sequential I2C Write and Readback Operation
Rev. 0 | Page 30 of 56
AD7143
PCB DESIGN GUIDELINES
CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS
Table 15.
Parameter
Symbol
Min
1.0
0
Typ Max Unit
Distance from Edge of Any Sensor to Edge of Metal Object
Distance Between Sensor Edges1
Distance Between Bottom of Sensor Board and Controller Board or Metal Casing2 (4-Layer,
2-Layer, and Flex Circuit)
D1
mm
mm
D2 = D3 = D4
D5
1.0
mm
1 The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user’s finger positioning and handling.
Adjacent sensors, with 0 minimum space between them, are implemented differentially.
2 The 1.0 mm specification is meant to prevent direct sensor board contact with any conductive material. This specification does not guarantee no EMI coupling from
the controller board to the sensors. Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main
controller board as shown in Figure 44.
CAPACITIVE SENSOR BOARD
D
5
METAL OBJECT
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
CAPACITIVE SENSOR
PRINTED CIRCUIT
Figure 44. Capacitive Sensor Board with Grounded Shield
8-WAY
SWITCH
CHIP SCALE PACKAGES
The lands on the chip scale package (CP-16-13) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length, and 0.05 mm wider than
the package land width. Center the land on the pad to maximize
the solder joint size.
D
4
SLIDER
BUTTONS
D
3
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. To avoid shorting, provide a
clearance of at least 0.25 mm between the thermal pad and the
inner edges of the land pattern on the printed circuit board.
D
2
D
1
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via.
Figure 42. Capacitive Sensor Board Mechanicals Top View
CAPACITIVE SENSOR BOARD
GROUNDED METAL SHIELD
D
5
Connect the printed circuit board thermal pad to GND.
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
Figure 43. Capacitive Sensor Board Mechanicals Side View
Rev. 0 | Page 31 of 56
AD7143
POWER-UP SEQUENCE
When the AD7143 is powered up, the following sequence is
recommended when initially developing the AD7143 and
Host μC serial interface:
Register values:
Address 0x000 = 0x00B2
Address 0x001 = 0x0000
Address 0x002 = 0x0690
Address 0x003 = 0x0664
Address 0x004 = 0x290F
Address 0x005 = 0x0000
Address 0x006 = 0x0000
1. Turn on the power supplies to the AD7143.
2. Write to the Bank 2 registers at Address 0x080 through
Address 0x0DF. These registers are contiguous, so a
sequential register write sequence can be applied.
Note: The Bank 2 register values are unique for each
application. Register values are provided by Analog
Devices after the sensor board has been developed.
3. Write to the Bank 1 registers at Address 0x000 through
Address 0x007 as outlined below. These registers are
contiguous so a sequential register write sequence can be
applied
Address 0x007 = 0x0001 (The AD7143 interrupt is asserted
approximately every 25 ms.)
4. Write to the Bank 1 register, Address 0x001 = 0x0FFF.
Caution: At this time, Address 0x001 must remain set to
default value 0x0000 during this contiguous write
operation.
5. Read back the corresponding interrupt status register at
Address 0x008, Address 0x009, or Address 0x00A. This is
determined by the interrupt output configuration as
explained in the Interrupt Output section.
Note: The specific registers required to be readback depend
on each application. Analog Devices provides this
information after the sensor board has been developed.
INT
6. Repeat Step 5 each time
is asserted.
POWER
HOST
SERIAL
INTERFACE
CONVERSION
1
2
3
4
5
6
7
8
9
10 11
0
1
2
9
10 11
0
1
2
9
10 11
0
1
CONVERSION STAGES DISABLED
0
STAGE
AD7143 INT
SECOND CONVERSION
SEQUENCE
THIRD CONVERSION
SEQUENCE
FIRST CONVERSION SEQUENCE
Figure 45. Recommended Start-Up Sequence
Rev. 0 | Page 32 of 56
AD7143
TYPICAL APPLICATION CIRCUITS
VDRIVE
2.2kΩ
2.2kΩ
2.2kΩ
INT
SCLK
HOST WITH
2
I C
INTERFACE
V
HOST
SDA 12
VDRIVE 11
GND 10
1 CIN2
2 CIN3
3 CIN4
4 CIN5
SDA
SCROLL
WHEEL
AD7143
OPTIONAL
2
I C INTERFACE
VOLTAGE
VCC
2.7V TO 3.6V
VCC
9
(1.65V TO 3.6V)
0.1µF
1µF TO 10µF
(OPTIONAL)
SENSOR PCB
10nF
Figure 46. Typical Application Circuit with I2C Interface
Rev. 0 | Page 33 of 56
AD7143
REGISTER MAP
The AD7143 address space is divided into three different
register banks, referred to as Bank 1, Bank 2, and Bank 3.
Figure 47 illustrates the division of these three banks.
Bank 3 registers contains the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7143 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.
Bank 1 registers contain control registers, CDC conversion
control registers, interrupt enable registers, interrupt status
registers, CDC 16-bit conversion data registers, device ID
registers, and proximity status registers.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power up and configuration of the Bank 2
registers.
Bank 2 registers contain the configuration registers used for
uniquely configuring the CIN inputs for each conversion stage.
Initialize the Bank 2 configuration registers immediately after
power-up to obtain valid CDC conversion result data.
REGISTER BANK 1
REGISTER BANK 2
REGISTER BANK 3
ADDR 0x000
ADDR 0x001
ADDR 0x080
ADDR 0x088
ADDR 0x0E0
ADDR 0x088
STAGE0 CONFIGURATION
(8 REGISTERS)
STAGE0 RESULTS
(36 REGISTERS)
SET UP CONTROL
(1 REGISTER)
STAGE1 CONFIGURATION
(8 REGISTERS)
STAGE1 RESULTS
(36 REGISTERS)
CALIBRATION AND SET UP
(4 REGISTERS)
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x090
ADDR 0x098
STAGE2 RESULTS
(36 REGISTERS)
STAGE2 CONFIGURATION
(8 REGISTERS)
ADDR 0x005
STAGE3 CONFIGURATION
(8 REGISTERS)
STAGE3 RESULTS
(36 REGISTERS)
INTERRUPT ENABLE
(3 REGISTERS)
ADDR 0x0A0
ADDR 0x0A8
STAGE4 RESULTS
(36 REGISTERS)
STAGE4 CONFIGURATION
(8 REGISTERS)
ADDR 0x008
ADDR 0x00B
INTERRUPT STATUS
(3 REGISTERS)
STAGE5 RESULTS
(36 REGISTERS)
STAGE5 CONFIGURATION
(8 REGISTERS)
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x0B0
ADDR 0x0B8
CDC 16-BIT CONVERSION DATA
(8 REGISTERS)
STAGE6 RESULTS
(36 REGISTERS)
STAGE6 CONFIGURATION
(8 REGISTERS)
ADDR 0x013
ADDR 0x017
ADDR 0x018
ADDR 0x042
ADDR 0x043
STAGE7 RESULTS
(36 REGISTERS)
STAGE7 CONFIGURATION
(8 REGISTERS)
UNUSED (4 REGISTERS)
DEVICE ID REGISTER
INVALID DO NOT ACCESS
PROXIMITY STATUS REGISTER
INVALID DO NOT ACCESS
ADDR 0x7F0
Figure 47. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers
Rev. 0 | Page 34 of 56
AD7143
DETAILED REGISTER DESCRIPTIONS
BANK 1 REGISTERS
All addresses and default values are expressed in hexadecimal format.
Table 16. PWR_CONTROL Register
Address Data Bit
Default Type Name
Description
0x000
[1:0]
0
R/W
POWER_MODE
Operating modes
00 = full power mode (normal operation, CDC conversions
approximately every 25 ms)
01 = full shutdown mode (no CDC conversions)
10 = low power mode (automatic wake-up operation)
11 = full shutdown mode (no CDC conversions)
[3:2]
[7:4]
[9:8]
0
0
0
LP_CONV_DELAY
Low power mode conversion delay
00 = 200 ms
01 = 400 ms
10 = 600 ms
11 = 800 ms
SEQUENCE_STAGE_NUM Number of stages in sequence (N + 1)
0000 = 1 conversion stage in sequence
0001 = 2 conversion stages in sequence
……
Maximum value = 1011 = 12 conversion stages per sequence
DECIMATION
ADC decimation factor
00 = decimate by 256
01 = decimate by 128
10 = do not use this setting
11 = do not use this setting
[10]
[11]
0
0
SW_RESET
INT_POL
Software reset control (self-clearing)
1 = resets all registers to default values
Interrupt polarity control
0 = active low
1 = active high
[12]
0
EXCITATION_SOURCE
Excitation source control for Pin 15
0 = enable output
1 = disable output
[13]
[15:14]
0
0
Unused
CDC_BIAS
Set unused register bits = 0
CDC bias current control
00 = normal operation
01 = normal operation + 20%
10 = normal operation + 35%
11 = normal operation + 50%
Rev. 0 | Page 35 of 56
AD7143
Table 17. STAGE_CAL_EN Register
Address
Data Bit Default
Type
Name
Description
0x001
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
0
0
0
0
0
0
0
0
R/W
STAGE0_CAL_EN
STAGE0 calibration enable
0 = disable
1 = enable
STAGE1_CAL_EN
STAGE2_CAL_EN
STAGE3_CAL_EN
STAGE4_CAL_EN
STAGE5_CAL_EN
STAGE6_CAL_EN
STAGE7_CAL_EN
STAGE1 calibration enable
0 = disable
1 = enable
STAGE2 calibration enable
0 = disable
1 = enable
STAGE3 calibration enable
0 = disable
1 = enable
STAGE4 calibration enable
0 = disable
1 = enable
STAGE5 calibration enable
0 = disable
1 = enable
STAGE6 calibration enable
0 = disable
1 = enable
STAGE7 calibration enable
0 = disable
1 = enable
[11:8]
0
0
Unused
Set unused register bits = 0
[13:12]
AVG_FP_SKIP
Full power mode skip control
00 = skip 3 samples
01 = skip 7 samples
10 = skip 15 samples
11 = skip 31 samples
[15:14]
0
AVG_LP_SKIP
Low power mode skip control
00 = use all samples
01 = skip 1 sample
10 = skip 2 samples
11 = skip 3 samples
Rev. 0 | Page 36 of 56
AD7143
Table 18. AMB_COMP_CTRL0 Register
Address
Data Bit Default
Type
Name
Description
0x002
[3:0]
0
R/W
FF_SKIP_CNT
Fast filter skip control (N+1)
0000 = no sequence of results are skipped
0001 = one sequence of results is skipped for every one
allowed into Fast FIFO
0010 = two sequences of results are skipped for every
one allowed into Fast FIFO
1011 = maximum value = 12 sequences of results are
skipped for every one allowed into Fast FIFO
[7:4]
[11:8]
[13:12]
F
F
0
FP_PROXIMITY_CNT
LP_PROXIMITY_CNT
PWR_DOWN_TIMEOUT
Full power mode proximity period
Low power mode proximity period
Full power to low power mode time out control
00 = 1.25 × (FP_PROXIMITY_CNT)
01 = 1.50 × (FP_PROXIMITY_CNT)
10 = 1.75 × (FP_PROXIMITY_CNT)
11 = 2.00 × (FP_PROXIMITY_CNT)
[14]
[15]
0
0
FORCED_CAL
CONV_RESET
Forced calibration control
0 = normal operation
1 = forces all conversion stages to recalibrate
Conversion reset control (self-clearing)
0 = normal operation
1 = resets the conversion sequence back to STAGE0
Table 19. AMB_COMP_CTRL1 Register
Address
Data Bit Default
Type
Name
Description
0x003
[7:0]
[13:8]
[15:14]
64
1
0
R/W
PROXIMITY_RECAL_LVL
PROXIMITY_DETECTION_RATE
SLOW_FILTER_UPDATE_LVL
Proximity recalibration level
Proximity detection rate
Slow filter update level
Table 20. AMB_COMP_CTRL2 Register
Address
Data Bit Default
Type
Name
Description
0x004
[9:0]
[15:10]
3FF
3F
R/W
FP_PROXIMITY_RECAL
LP_PROXIMITY_RECAL
Full power mode proximity recalibration time control
Low power mode proximity recalibration time control
Rev. 0 | Page 37 of 56
AD7143
Table 21. STAGE_LOW_INT_EN Register
Address Data Bit
Default
Type
Name
Description
0x005
[0]
0
R/W
STAGE0_LOW_INT_EN
STAGE0 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
[1]
0
0
0
0
0
STAGE1_LOW_INT_EN
STAGE2_LOW_INT_EN
STAGE3_LOW_INT_EN
STAGE4_LOW_INT_EN
STAGE5_LOW_INT_EN
STAGE1 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
[2]
[3]
[4]
[5]
STAGE2 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
STAGE3 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
STAGE4 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
STAGE5 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
[6]
[7]
0
0
STAGE6_LOW_INT_EN
STAGE7_LOW_INT_EN
STAGE6 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
STAGE7 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
[11:8]
[15:12]
0
0
Unused
TESTMODE
Set unused register bits = 0
Set test mode register bits = 0 (at all times)
Rev. 0 | Page 38 of 56
AD7143
Table 22. STAGE_HIGH_INT_EN Register
Address Data Bit
Default
Type
Name
Description
0x006
[0]
[1]
[2]
[3]
0
R/W
STAGE0_HIGH_INT_EN
STAGE0 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
0
0
0
STAGE1_HIGH_INT_EN
STAGE2_HIGH_INT_EN
STAGE3_HIGH_INT_EN
STAGE1 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
STAGE2 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
STAGE3 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[4]
0
0
0
0
STAGE4_HIGH_INT_EN
STAGE5_HIGH_INT_EN
STAGE6_HIGH_INT_EN
STAGE7_HIGH_INT_EN
Unused
STAGE4 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[5]
STAGE5 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[6]
STAGE6 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[7]
STAGE7 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[15:8]
Set unused register bits = 0
Rev. 0 | Page 39 of 56
AD7143
Table 23. STAGE_COMPLETE_INT_EN Register
Address Data Bit
Default
Type
Name
Description
0x007
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
0
R/W
STAGE0_COMPLETE_EN
STAGE0 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE0 conversion
STAGE1 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE1 conversion
STAGE2 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE2 conversion
STAGE3 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE3 conversion
STAGE4 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE4 conversion
STAGE5 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE5 conversion
STAGE6 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE6 conversion
STAGE7 conversion interrupt control
0 = interrupt source disabled
0
0
0
0
0
0
0
STAGE1_COMPLETE_EN
STAGE2_COMPLETE_EN
STAGE3_COMPLETE_EN
STAGE4_COMPLETE_EN
STAGE5_COMPLETE_EN
STAGE6_COMPLETE_EN
STAGE7_COMPLETE_EN
1 = INT asserted at completion of STAGE7 conversion
Set unused register bits = 0
Set test mode register bits = 0 at all times
Set unused register bits = 0
[11:8]
[12]
[15:13]
0
0
Unused
TESTMODE
Unused
Table 24. STAGE_LOW_LIMIT_INT Register1
Address Data Bit
Default Type
Name
Description
0x008
[0]
0
0
0
0
0
0
0
0
R
STAGE0_LOW_LIMIT_INT
STAGE0 CDC conversion low limit interrupt result
1 indicates STAGE0_LOW_THRESHOLD value exceeded
STAGE1 CDC conversion low limit interrupt result
1 indicates STAGE1_LOW_THRESHOLD value exceeded
STAGE2 CDC conversion low limit interrupt result
1 indicates STAGE2_LOW_THRESHOLD value exceeded
STAGE3 CDC conversion low limit interrupt result
1 indicates STAGE3_LOW_THRESHOLD value exceeded
STAGE4 CDC conversion low limit interrupt result
1 indicates STAGE4_LOW_THRESHOLD value exceeded
STAGE5 CDC conversion low limit interrupt result
1 indicates STAGE5_LOW_THRESHOLD value exceeded
STAGE6 CDC conversion low limit interrupt result
1 indicates STAGE6_LOW_THRESHOLD value exceeded
STAGE7 CDC conversion low limit interrupt result
1 indicates STAGE7_LOW_THRESHOLD value exceeded
Set unused register bits = 0
[1]
STAGE1_LOW_LIMIT_INT
STAGE2_LOW_LIMIT_INT
STAGE3_LOW_LIMIT_INT
STAGE4_LOW_LIMIT_INT
STAGE5_LOW_LIMIT_INT
STAGE6_LOW_LIMIT_INT
STAGE7_LOW_LIMIT_INT
Unused
[2]
[3]
[4]
[5]
[6]
[7]
[15:8]
1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Rev. 0 | Page 40 of 56
AD7143
Table 25. STAGE_HIGH_LIMIT_INT Register1
Address Data Bit
Default Type
Name
Description
0x009
[0]
0
0
0
0
0
0
0
0
R
STAGE0_HIGH_LIMIT_INT
STAGE0 CDC conversion high limit interrupt result
1 indicates STAGE0_HIGH_THRESHOLD value exceeded
STAGE1 CDC conversion high limit interrupt result
1 indicates STAGE1_HIGH_THRESHOLD value exceeded
Stage2 CDC conversion high limit interrupt result
1 indicates STAGE2_HIGH_THRESHOLD value exceeded
STAGE3 CDC conversion high limit interrupt result
1 indicates STAGE3_HIGH_THRESHOLD value exceeded
STAGE4 CDC conversion high limit interrupt result
1 indicates STAGE4_HIGH_THRESHOLD value exceeded
STAGE5 CDC conversion high limit interrupt result
1 indicates STAGE5_HIGH_THRESHOLD value exceeded
STAGE6 CDC conversion high limit interrupt result
1 indicates STAGE6_HIGH_THRESHOLD value exceeded
STAGE7 CDC conversion high limit interrupt result
1 indicates STAGE7_HIGH_THRESHOLD value exceeded
Set unused register bits = 0
[1]
STAGE1_HIGH_LIMIT_INT
STAGE2_HIGH_LIMIT_INT
STAGE3_HIGH_LIMIT_INT
STAGE4_HIGH_LIMIT_INT
STAGE5_HIGH_LIMIT_INT
STAGE6_HIGH_LIMIT_INT
STAGE7_HIGH_LIMIT_INT
Unused
[2]
[3]
[4]
[5]
[6]
[7]
[15:8]
1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Table 26. STAGE_COMPLETE_LIMIT_INT Register1
Address Data Bit
Default Type
Name
Description
0x00A
[0]
0
0
0
0
0
0
0
0
0
R
STAGE0_COMPLETE_STATUS_INT STAGE0 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
STAGE1_COMPLETE_STATUS_INT STAGE1 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
STAGE2_COMPLETE_STATUS_INT STAGE2 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
STAGE3_COMPLETE_STATUS_INT STAGE3 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
STAGE4_COMPLETE_STATUS_INT STAGE4 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
STAGE5_COMPLETE_STATUS_INT STAGE5 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
STAGE6_COMPLETE_STATUS_INT STAGE6 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
STAGE7_COMPLETE_STATUS_INT STAGE7 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[15:8]
Unused
1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Rev. 0 | Page 41 of 56
AD7143
Table 27. CDC 16-Bit Conversion Data Registers
Address Data Bit
Default
Type
Name
Description
0x00B
0x00C
0x00D
0x00E
0x00F
0x010
0x011
0x012
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
ADC_RESULT_S0
ADC_RESULT_S1
ADC_RESULT_S2
ADC_RESULT_S3
ADC_RESULT_S4
ADC_RESULT_S5
ADC_RESULT_S6
ADC_RESULT_S7
STAGE0 CDC 16-bit conversion data
STAGE1 CDC 16-bit conversion data
STAGE2 CDC 16-bit conversion data
STAGE3 CDC 16-bit conversion data
STAGE4 CDC 16-bit conversion data
STAGE5 CDC 16-bit conversion data
STAGE6 CDC 16-bit conversion data
STAGE7 CDC 16-bit conversion data
Table 28. Device ID Register
Address Data Bit Default
Type
Name
Description
0x017
[3:0]
[15:4]
0
E63
R
REVISION_CODE
DEVID
AD7143 revision code
AD7143 device ID = 0xE63
Table 29. Proximity Status Register
Address Data Bit
Default
Type
Name
Description
0x042
[0]
0
R
STAGE0_PROXIMITY_STATUS
STAGE0 proximity status register
1 indicates proximity detected on STAGE0
STAGE1 proximity status register
1 indicates proximity detected on STAGE1
STAGE2 proximity status register
1 indicates proximity detected on STAGE2
STAGE3 proximity status register
1 indicates proximity detected on STAGE3
STAGE4 proximity status register
1 indicates proximity detected on STAGE4
STAGE5 proximity status register
1 indicates proximity detected on STAGE5
STAGE6 proximity status register
1 indicates proximity detected on STAGE6
STAGE7 proximity status register
1 indicates proximity detected on STAGE7
Set unused register bits = 0
[1]
0
0
0
0
0
0
0
R
R
R
R
R
R
R
STAGE1_PROXIMITY_STATUS
STAGE2_PROXIMITY_STATUS
STAGE3_PROXIMITY_STATUS
STAGE4_PROXIMITY_STATUS
STAGE5_PROXIMITY_STATUS
STAGE6_PROXIMITY_STATUS
STAGE7_PROXIMITY_STATUS
Unused
[2]
[3]
[4]
[5]
[6]
[7]
[15:8]
Rev. 0 | Page 42 of 56
AD7143
BANK 2 REGISTERS
All address values are expressed in hexadecimal format.
Table 30. STAGE0 Configuration Registers
Address
0x080
0x081
0x082
0x083
0x084
0x085
0x086
0x087
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
X
X
X
X
X
X
X
X
STAGE0_CONNECTION[6:0]
STAGE0_CONNECTION 7
STAGE0_AFE_OFFSET
STAGE0_SENSITIVITY
STAGE0_OFFSET_LOW
STAGE0_OFFSET_HIGH
STAGE0_OFFSET_HIGH_CLAMP
STAGE0_OFFSET_LOW_CLAMP
STAGE0 CIN(6:0) connection setup (see Table 38)
STAGE0 CIN7 connection setup (see Table 39)
STAGE0 AFE offset control (see Table 40)
STAGE0 sensitivity control (see Table 41)
STAGE0 initial offset low value
STAGE0 initial offset high value
STAGE0 offset high clamp value
STAGE0 offset low clamp value
Table 31. STAGE1 Configuration Registers
Address
0x088
0x089
0x08A
0x08B
0x08C
0x08D
0x08E
0x08F
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
X
X
X
X
X
X
X
X
STAGE1_CONNECTION[6:0]
STAGE1_CONNECTION 7
STAGE1_AFE_OFFSET
STAGE1_SENSITIVITY
STAGE1_OFFSET_LOW
STAGE1_OFFSET_HIGH
STAGE1_OFFSET_HIGH_CLAMP
STAGE1_OFFSET_LOW_CLAMP
STAGE1 CIN(6:0) connection setup (see Table 38)
STAGE1 CIN7 connection setup (see Table 39)
STAGE1 AFE offset control (see Table 40)
STAGE1 sensitivity control (see Table 41)
STAGE1 initial offset low value
STAGE1 initial offset high value
STAGE1 offset high clamp value
STAGE1 offset low clamp value
Table 32. STAGE2 Configuration Registers
Address
0x090
0x091
0x092
0x093
0x094
0x095
0x096
0x097
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
X
X
X
X
X
X
X
X
STAGE2_CONNECTION[6:0]
STAGE2_CONNECTION 7
STAGE2_AFE_OFFSET
STAGE2_SENSITIVITY
STAGE2_OFFSET_LOW
STAGE2_OFFSET_HIGH
STAGE2_OFFSET_HIGH_CLAMP
STAGE2_OFFSET_LOW_CLAMP
STAGE2 CIN(6:0) connection setup (see Table 38)
STAGE2 CIN7 connection setup (see Table 39)
STAGE2 AFE offset control (see Table 40)
STAGE2 sensitivity control (see Table 41)
STAGE2 initial offset low value
STAGE2 initial offset high value
STAGE2 offset high clamp value
STAGE2 offset low clamp value
Rev. 0 | Page 43 of 56
AD7143
Table 33. STAGE3 Configuration Registers
Address Data Bit
Default
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
0x098
0x099
0x09A
0x09B
0x09C
0x09D
0x09E
0x09F
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
STAGE3_CONNECTION[6:0]
STAGE3_CONNECTION 7
STAGE3_AFE_OFFSET
STAGE3_SENSITIVITY
STAGE3_OFFSET_LOW
STAGE3_OFFSET_HIGH
STAGE3_OFFSET_HIGH_CLAMP
STAGE3_OFFSET_LOW_CLAMP
STAGE3 CIN(6:0) connection setup (see Table 38)
STAGE3 CIN7 connection setup (see Table 39)
STAGE3 AFE offset control (see Table 40)
STAGE3 sensitivity control (see Table 41)
STAGE3 initial offset low value
STAGE3 initial offset high value
STAGE3 offset high clamp value
STAGE3 offset low clamp value
Table 34. STAGE4 Configuration Registers
Address Data Bit
Default
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
0x0A0
0x0A1
0x0A2
0x0A3
0x0A4
0x0A5
0x0A6
0x0A7
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
STAGE4_CONNECTION[6:0]
STAGE4_CONNECTION 7
STAGE4_AFE_OFFSET
STAGE4_SENSITIVITY
STAGE4_OFFSET_LOW
STAGE4_OFFSET_HIGH
STAGE4_OFFSET_HIGH_CLAMP
STAGE4_OFFSET_LOW_CLAMP
STAGE4 CIN(6:0) connection setup (see Table 38)
STAGE4 CIN7 connection setup (see Table 39)
STAGE4 AFE offset control (see Table 40)
STAGE4 sensitivity control (see Table 41)
STAGE4 initial offset low value
STAGE4 initial offset high value
STAGE4 offset high clamp value
STAGE4 offset low clamp value
Table 35. STAGE5 Configuration Registers
Address Data Bit
Default
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
0x0A8
0x0A9
0x0AA
0x0AB
0x0AC
0x0AD
0x0AE
0x0AF
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
STAGE5_CONNECTION[6:0]
STAGE5_CONNECTION 7
STAGE5_AFE_OFFSET
STAGE5_SENSITIVITY
STAGE5_OFFSET_LOW
STAGE5_OFFSET_HIGH
STAGE5_OFFSET_HIGH_CLAMP
STAGE5_OFFSET_LOW_CLAMP
STAGE5 CIN(6:0) connection setup (see Table 38)
STAGE5 CIN7 connection setup (see Table 39)
STAGE5 AFE offset control (see Table 40)
STAGE5 sensitivity control (see Table 41)
STAGE5 initial offset low value
STAGE5 initial offset high value
STAGE5 offset high clamp value
STAGE5 offset low clamp value
Table 36. STAGE6 Configuration Registers
Address Data Bit
Default
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
0x0B0
0x0B1
0x0B2
0x0B3
0x0B4
0x0B5
0x0B6
0x0B7
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
STAGE6_CONNECTION[6:0]
STAGE6_CONNECTION 7
STAGE6_AFE_OFFSET
STAGE6_SENSITIVITY
STAGE6_OFFSET_LOW
STAGE6_OFFSET_HIGH
STAGE6_OFFSET_HIGH_CLAMP
STAGE6_OFFSET_LOW_CLAMP
STAGE6 CIN(6:0) connection setup (see Table 38)
STAGE6 CIN7 connection setup (see Table 39)
STAGE6 AFE offset control (see Table 40)
STAGE6 sensitivity control (see Table 41)
STAGE6 initial offset low value
STAGE6 initial offset high value
STAGE6 offset high clamp value
STAGE6 offset low clamp value
Rev. 0 | Page 44 of 56
AD7143
Table 37. STAGE7 Configuration Registers
Address Data Bit
Default
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
0x0B8
0x0B9
0x0BA
0x0BB
0x0BC
0x0BD
0x0BE
0x0BF
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
STAGE7_CONNECTION[6:0]
STAGE7_CONNECTION 7
STAGE7_AFE_OFFSET
STAGE7_SENSITIVITY
STAGE7_OFFSET_LOW
STAGE7_OFFSET_HIGH
STAGE7_OFFSET_HIGH_CLAMP
STAGE7_OFFSET_LOW_CLAMP
STAGE7 CIN(6:0) connection setup (see Table 38)
STAGE7 CIN7 connection setup (see Table 39)
STAGE7 AFE offset control (see Table 40)
STAGE7 sensitivity control (see Table 41)
STAGE7 initial offset low value
STAGE7 initial offset high value
STAGE7 offset high clamp value
STAGE7 offset low clamp value
Table 38. STAGEX Detailed CIN (0:6) Connection Setup Description (X = 0 to 6)
Data Bit
Default
Type
Name
Description
[1:0]
X
R/W
CIN0_CONNECTION_SETUP
CIN0 connection setup
00 = CIN0 not connected to CDC inputs
01 = CIN0 connected to CDC negative input
10 = CIN0 connected to CDC positive input
11 = CIN0 connected to BIAS (connect unused CIN inputs)
CIN1 connection setup
00 = CIN1 not connected to CDC inputs
01 = CIN1 connected to CDC negative input
10 = CIN1 connected to CDC positive input
11 = CIN1 connected to BIAS (connect unused CIN inputs)
CIN2 connection setup
00 = CIN2 not connected to CDC inputs
01 = CIN2 connected to CDC negative input
10 = CIN2 connected to CDC positive input
11 = CIN2 connected to BIAS (connect unused CIN inputs)
CIN3 connection setup
00 = CIN3 not connected to CDC inputs
01 = CIN3 connected to CDC negative input
10 = CIN3 connected to CDC positive input
11 = CIN3 connected to BIAS (connect unused CIN inputs)
CIN4 connection setup
00 = CIN4 not connected to CDC inputs
01 = CIN4 connected to CDC negative input
10 = CIN4 connected to CDC positive input
11 = CIN4 connected to BIAS (connect unused CIN inputs)
CIN5 connection setup
00 = CIN5 not connected to CDC inputs
01 = CIN5 connected to CDC negative input
10 = CIN5 connected to CDC positive input
11 = CIN5 connected to BIAS (connect unused CIN inputs)
CIN6 connection setup
[3:2]
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
CIN1_CONNECTION_SETUP
CIN2_CONNECTION_SETUP
CIN3_CONNECTION_SETUP
CIN4_CONNECTION_SETUP
CIN5_CONNECTION_SETUP
CIN6_CONNECTION_SETUP
Unused
[5:4]
[7:6]
[9:8]
[11:10]
[13:12]
[15:14]
00 = CIN6 not connected to CDC inputs
01 = CIN6 connected to CDC negative input
10 = CIN6 connected to CDC positive input
11 = CIN6 connected to BIAS (connect unused CIN inputs)
Rev. 0 | Page 45 of 56
AD7143
Table 39. STAGEX Detailed CIN7 Connection Setup Description
Data Bit
Default
Type
Name
Description
[1:0]
X
R/W
CIN7_CONNECTION_SETUP
CIN7 connection setup
00 = CIN7 not connected to CDC inputs
01 = CIN7 connected to CDC negative input
10 = CIN7 connected to CDC positive input
11 = CIN7 connected to BIAS (connect unused CIN inputs)
[13:2]
[14]
X
X
R/W
R/W
Unused
NEG_AFE_OFFSET_DISABLE
Negative AFE offset enable control
0 = enable
1 = disable
[15]
X
R/W
POS_AFE_OFFSET_DISABLE
Positive AFE offset enable control
0 = enable
1 = disable
Table 40. STAGEX Detailed Offset Control Description (X = 0 to 7)
Data Bit
Default
Type
Name
Description
[6:0]
X
R/W
NEG_AFE_OFFSET
Negative AFE offset setting (20 pF range)
1 LSB value = 0.16 pF of offset
[7]
X
R/W
NEG_AFE_OFFSET_SWAP
Negative AFE offset swap control
0 = NEG_AFE_OFFSET applied to CDC negative input
1 = NEG_AFE_OFFSET applied to CDC positive input
Positive AFE offset setting (20 pF range)
1 LSB value = 0.16 pF of offset
[14:8]
[15]
X
X
R/W
R/W
POS_AFE_OFFSET
POS_AFE_OFFSET_SWAP
Positive AFE offset swap control
0 = POS_AFE_OFFSET applied to CDC positive input
1 = POS_AFE_OFFSET applied to CDC negative input
Table 41. STAGEX Detailed Sensitivity Control Description (X = 0 to 7)
Data Bit
Default
Type
Name
Description
[3:0]
X
R/W
NEG_THRESHOLD_SENSITIVITY
Negative threshold sensitivity control
0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08%
0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15%
0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22%
1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28%
1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32%
Negative peak detect setting
[6:4]
X
R/W
NEG_PEAK_DETECT
000 = 40% level, 001 = 50% level, 010 = 60% level
011 = 70% level, 100 = 80% level, 101 = 90% level
[7]
X
X
R/W
R/W
Unused
[11:8]
POS_THRESHOLD_SENSITIVITY
Positive threshold sensitivity control
0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08%
0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15%
0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22%
1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28%
1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32%
Positive peak detect setting
[14:12]
[15]
X
X
R/W
R/W
POS_PEAK_DETECT
Unused
000 = 40% level, 001 = 50% level, 010 = 60% level
011 = 70% level, 100 = 80% level, 101 = 90% level
Rev. 0 | Page 46 of 56
AD7143
BANK 3 REGISTERS
All address values are expressed in hexadecimal format.
Table 42. STAGE0 Results Registers
Address Data Bit
Default
Type
Name
Description
0x0E0
[15:0]
X
R/W
STAGE0_CONV_DATA
STAGE0 CDC 16-bit conversion data
(copy of data in STAGE0_CONV_DATA register)
0x0E1
0x0E2
0x0E3
0x0E4
0x0E5
0x0E6
0x0E7
0x0E8
0x0E9
0x0EA
0x0EB
0x0EC
0x0ED
0x0EE
0x0EF
0x0F0
0x0F1
0x0F2
0x0F3
0x0F4
0x0F5
0x0F6
0x0F7
0x0F8
0x0F9
0x0FA
0x0FB
0x0FC
0x0FD
0x0FE
0x0FF
0x100
0x101
0x102
0x103
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE0_FF_WORD0
STAGE0_FF_WORD1
STAGE0_FF_WORD2
STAGE0_FF_WORD3
STAGE0_FF_WORD4
STAGE0_FF_WORD5
STAGE0_FF_WORD6
STAGE0_FF_WORD7
STAGE0_SF_WORD0
STAGE0_SF_WORD1
STAGE0_SF_WORD2
STAGE0_SF_WORD3
STAGE0_SF_WORD4
STAGE0_SF_WORD5
STAGE0_SF_WORD6
STAGE0_SF_WORD7
STAGE0_SF_AMBIENT
STAGE0_FF_AVG
STAGE0_PEAK_DETECT_WORD0
STAGE0_PEAK_DETECT_WORD1
STAGE0_MAX_WORD0
STAGE0_MAX_WORD1
STAGE0_MAX_WORD2
STAGE0_MAX_WORD3
STAGE0_MAX_AVG
STAGE0_HIGH_THRESHOLD
STAGE0_MAX_TEMP
STAGE0_MIN_WORD0
STAGE0_MIN_WORD1
STAGE0_MIN_WORD2
STAGE0_MIN_WORD3
STAGE0_MIN_AVG
STAGE0 fast FIFO WORD0
STAGE0 fast FIFO WORD1
STAGE0 fast FIFO WORD2
STAGE0 fast FIFO WORD3
STAGE0 fast FIFO WORD4
STAGE0 fast FIFO WORD5
STAGE0 fast FIFO WORD6
STAGE0 fast FIFO WORD7
STAGE0 slow FIFO WORD0
STAGE0 slow FIFO WORD1
STAGE0 slow FIFO WORD2
STAGE0 slow FIFO WORD3
STAGE0 slow FIFO WORD4
STAGE0 slow FIFO WORD5
STAGE0 slow FIFO WORD6
STAGE0 slow FIFO WORD7
STAGE0 slow FIFO ambient value
STAGE0 fast FIFO average value
STAGE0 peak FIFO WORD0 value
STAGE0 peak FIFO WORD1 value
STAGE0 maximum value FIFO WORD0
STAGE0 maximum value FIFO WORD1
STAGE0 maximum value FIFO WORD2
STAGE0 maximum value FIFO WORD3
STAGE0 average maximum FIFO value
STAGE0 high threshold value
STAGE0 temporary maximum value
STAGE0 minimum value FIFO WORD0
STAGE0 minimum value FIFO WORD1
STAGE0 minimum value FIFO WORD2
STAGE0 minimum value FIFO WORD3
STAGE0 average minimum FIFO value
STAGE0 low threshold value
STAGE0_LOW_THRESHOLD
STAGE0_MIN_TEMP
Unused
STAGE0 temporary minimum value
Rev. 0 | Page 47 of 56
AD7143
Table 43. STAGE1 Results Registers
Address Data Bit
Default
Type
Name
Description
0x104
[15:0]
X
R/W
STAGE1_CONV_DATA
STAGE1 CDC 16-bit conversion data
(copy of data in STAGE1_CONV_DATA register)
0x105
0x106
0x107
0x108
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
0x112
0x113
0x114
0x115
0x116
0x117
0x118
0x119
0x11A
0x11B
0x11C
0x11D
0x11E
0x11F
0x120
0x121
0x122
0x123
0x124
0x125
0x126
0x127
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1_FF_WORD0
STAGE1_FF_WORD1
STAGE1_FF_WORD2
STAGE1_FF_WORD3
STAGE1_FF_WORD4
STAGE1_FF_WORD5
STAGE1_FF_WORD6
STAGE1_FF_WORD7
STAGE1_SF_WORD0
STAGE1_SF_WORD1
STAGE1_SF_WORD2
STAGE1_SF_WORD3
STAGE1_SF_WORD4
STAGE1_SF_WORD5
STAGE1_SF_WORD6
STAGE1_SF_WORD7
STAGE1_SF_AMBIENT
STAGE1_FF_AVG
STAGE1_CDC_WORD0
STAGE1_CDC_WORD1
STAGE1_MAX_WORD0
STAGE1_MAX_WORD1
STAGE1_MAX_WORD2
STAGE1_MAX_WORD3
STAGE1_MAX_AVG
STAGE1_HIGH_THRESHOLD
STAGE1_MAX_TEMP
STAGE1_MIN_WORD0
STAGE1_MIN_WORD1
STAGE1_MIN_WORD2
STAGE1_MIN_WORD3
STAGE1_MIN_AVG
STAGE1 fast FIFO WORD0
STAGE1 fast FIFO WORD1
STAGE1 fast FIFO WORD2
STAGE1 fast FIFO WORD3
STAGE1 fast FIFO WORD4
STAGE1 fast FIFO WORD5
STAGE1 fast FIFO WORD6
STAGE1 fast FIFO WORD7
STAGE1 slow FIFO WORD0
STAGE1 slow FIFO WORD1
STAGE1 slow FIFO WORD2
STAGE1 slow FIFO WORD3
STAGE1 slow FIFO WORD4
STAGE1 slow FIFO WORD5
STAGE1 slow FIFO WORD6
STAGE1 slow FIFO WORD7
STAGE1 slow FIFO ambient value
STAGE1 fast FIFO average value
STAGE1 CDC FIFO WORD0
STAGE1 CDC FIFO WORD1
STAGE1 maximum value FIFO WORD0
STAGE1 maximum value FIFO WORD1
STAGE1 maximum value FIFO WORD2
STAGE1 maximum value FIFO WORD3
STAGE1 average maximum FIFO value
STAGE1 high threshold value
STAGE1 temporary maximum value
STAGE1 minimum value FIFO WORD0
STAGE1 minimum value FIFO WORD1
STAGE1 minimum value FIFO WORD2
STAGE1 minimum value FIFO WORD3
STAGE1 average minimum FIFO value
STAGE1 low threshold value
STAGE1 temporary minimum value
STAGE1_LOW_THRESHOLD
STAGE1_MIN_TEMP
Unused
Rev. 0 | Page 48 of 56
AD7143
Table 44. STAGE2 Results Registers
Address Data Bit
Default
Type
Name
Description
0x128
[15:0]
X
R/W
STAGE2_CONV_DATA
STAGE2 CDC 16-bit conversion data
(copy of data in STAGE2_CONV_DATA register)
0x129
0x12A
0x12B
0x12C
0x12D
0x12E
0x12F
0x130
0x131
0x132
0x133
0x134
0x135
0x125
0x137
0x138
0x139
0x13A
0x13B
0x13C
0x13D
0x13E
0x13F
0x140
0x141
0x142
0x143
0x144
0x145
0x146
0x147
0x148
0x149
0x14A
0x14B
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE2_FF_WORD0
STAGE2_FF_WORD1
STAGE2_FF_WORD2
STAGE2_FF_WORD3
STAGE2_FF_WORD4
STAGE2_FF_WORD5
STAGE2_FF_WORD6
STAGE2_FF_WORD7
STAGE2_SF_WORD0
STAGE2_SF_WORD1
STAGE2_SF_WORD2
STAGE2_SF_WORD3
STAGE2_SF_WORD4
STAGE2_SF_WORD5
STAGE2_SF_WORD6
STAGE2_SF_WORD7
STAGE2_SF_AMBIENT
STAGE2_FF_AVG
STAGE2_CDC_WORD0
STAGE2_CDC_WORD1
STAGE2_MAX_WORD0
STAGE2_MAX_WORD1
STAGE2_MAX_WORD2
STAGE2_MAX_WORD3
STAGE2_MAX_AVG
STAGE2_HIGH_THRESHOLD
STAGE2_MAX_TEMP
STAGE2_MIN_WORD0
STAGE2_MIN_WORD1
STAGE2_MIN_WORD2
STAGE2_MIN_WORD3
STAGE2_MIN_AVG
STAGE2 fast FIFO WORD0
STAGE2 fast FIFO WORD1
STAGE2 fast FIFO WORD2
STAGE2 fast FIFO WORD3
STAGE2 fast FIFO WORD4
STAGE2 fast FIFO WORD5
STAGE2 fast FIFO WORD6
STAGE2 fast FIFO WORD7
STAGE2 slow FIFO WORD0
STAGE2 slow FIFO WORD1
STAGE2 slow FIFO WORD2
STAGE2 slow FIFO WORD3
STAGE2 slow FIFO WORD4
STAGE2 slow FIFO WORD5
STAGE2 slow FIFO WORD6
STAGE2 slow FIFO WORD7
STAGE2 slow FIFO ambient value
STAGE2 fast FIFO average value
STAGE2 CDC FIFO WORD0
STAGE2 CDC FIFO WORD1
STAGE2 maximum value FIFO WORD0
STAGE2 maximum value FIFO WORD1
STAGE2 maximum value FIFO WORD2
STAGE2 maximum value FIFO WORD3
STAGE2 average maximum FIFO value
STAGE2 high threshold value
STAGE2 temporary maximum value
STAGE2 minimum value FIFO WORD0
STAGE2 minimum value FIFO WORD1
STAGE2 minimum value FIFO WORD2
STAGE2 minimum value FIFO WORD3
STAGE2 average minimum FIFO value
STAGE2 low threshold value
STAGE2_LOW_THRESHOLD
STAGE2_MIN_TEMP
Unused
STAGE2 temporary minimum value
Rev. 0 | Page 49 of 56
AD7143
Table 45. STAGE3 Results Registers
Address Data Bit
Default
Type
Name
Description
0x14C
[15:0]
X
R/W
STAGE3_CONV_DATA
STAGE3 CDC 16-bit conversion data
(copy of data in STAGE3_CONV_DATA register)
0x14D
0x14E
0x14F
0x150
0x151
0x152
0x153
0x154
0x155
0x156
0x157
0x158
0x159
0x15A
0x15B
0x15C
0x15D
0x15E
0x15F
0x160
0x161
0x162
0x163
0x164
0x165
0x166
0x167
0x168
0x169
0x16A
0x16B
0x16C
0x16D
0x16E
0x16F
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE3_FF_WORD0
STAGE3_FF_WORD1
STAGE3_FF_WORD2
STAGE3_FF_WORD3
STAGE3_FF_WORD4
STAGE3_FF_WORD5
STAGE3_FF_WORD6
STAGE3_FF_WORD7
STAGE3_SF_WORD0
STAGE3_SF_WORD1
STAGE3_SF_WORD2
STAGE3_SF_WORD3
STAGE3_SF_WORD4
STAGE3_SF_WORD5
STAGE3_SF_WORD6
STAGE3_SF_WORD7
STAGE3_SF_AMBIENT
STAGE3_FF_AVG
STAGE3_CDC_WORD0
STAGE3_CDC_WORD1
STAGE3_MAX_WORD0
STAGE3_MAX_WORD1
STAGE3_MAX_WORD2
STAGE3_MAX_WORD3
STAGE3_MAX_AVG
STAGE3_HIGH_THRESHOLD
STAGE3_MAX_TEMP
STAGE3_MIN_WORD0
STAGE3_MIN_WORD1
STAGE3_MIN_WORD2
STAGE3_MIN_WORD3
STAGE3_MIN_AVG
STAGE3 fast FIFO WORD0
STAGE3 fast FIFO WORD1
STAGE3 fast FIFO WORD2
STAGE3 fast FIFO WORD3
STAGE3 fast FIFO WORD4
STAGE3 fast FIFO WORD5
STAGE3 fast FIFO WORD6
STAGE3 fast FIFO WORD7
STAGE3 slow FIFO WORD0
STAGE3 slow FIFO WORD1
STAGE3 slow FIFO WORD2
STAGE3 slow FIFO WORD3
STAGE3 slow FIFO WORD4
STAGE3 slow FIFO WORD5
STAGE3 slow FIFO WORD6
STAGE3 slow FIFO WORD7
STAGE3 slow FIFO ambient value
STAGE3 fast FIFO average value
STAGE3 CDC FIFO WORD0
STAGE3 CDC FIFO WORD1
STAGE3 maximum value FIFO WORD0
STAGE3 maximum value FIFO WORD1
STAGE3 maximum value FIFO WORD2
STAGE3 maximum value FIFO WORD3
STAGE3 average maximum FIFO value
STAGE3 high threshold value
STAGE3 temporary maximum value
STAGE3 minimum value FIFO WORD0
STAGE3 minimum value FIFO WORD1
STAGE3 minimum value FIFO WORD2
STAGE3 minimum value FIFO WORD3
STAGE3 average minimum FIFO value
STAGE3 low threshold value
STAGE3 temporary minimum value
STAGE3_LOW_THRESHOLD
STAGE3_MIN_TEMP
Unused
Rev. 0 | Page 50 of 56
AD7143
Table 46. STAGE4 Results Registers
Address Data Bit
Default
Type
Name
Description
0x170
[15:0]
X
R/W
STAGE4_CONV_DATA
STAGE4 CDC 16-bit conversion data
(copy of data in STAGE4_CONV_DATA register)
0x171
0x172
0x173
0x174
0x175
0x176
0x177
0x178
0x179
0x17A
0x17B
0x17C
0x17D
0x17E
0x17F
0x180
0x181
0x182
0x183
0x184
0x185
0x186
0x187
0x188
0x189
0x18A
0x18B
0x18C
0x18D
0x18E
0x18F
0x190
0x191
0x192
0x193
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE4_FF_WORD0
STAGE4_FF_WORD1
STAGE4_FF_WORD2
STAGE4_FF_WORD3
STAGE4_FF_WORD4
STAGE4_FF_WORD5
STAGE4_FF_WORD6
STAGE4_FF_WORD7
STAGE4_SF_WORD0
STAGE4_SF_WORD1
STAGE4_SF_WORD2
STAGE4_SF_WORD3
STAGE4_SF_WORD4
STAGE4_SF_WORD5
STAGE4_SF_WORD6
STAGE4_SF_WORD7
STAGE4_SF_AMBIENT
STAGE4_FF_AVG
STAGE4_CDC_WORD0
STAGE4_CDC_WORD1
STAGE4_MAX_WORD0
STAGE4_MAX_WORD1
STAGE4_MAX_WORD2
STAGE4_MAX_WORD3
STAGE4_MAX_AVG
STAGE4_HIGH_THRESHOLD
STAGE4_MAX_TEMP
STAGE4_MIN_WORD0
STAGE4_MIN_WORD1
STAGE4_MIN_WORD2
STAGE4_MIN_WORD3
STAGE4_MIN_AVG
STAGE4 fast FIFO WORD0
STAGE4 fast FIFO WORD1
STAGE4 fast FIFO WORD2
STAGE4 fast FIFO WORD3
STAGE4 fast FIFO WORD4
STAGE4 fast FIFO WORD5
STAGE4 fast FIFO WORD6
STAGE4 fast FIFO WORD7
STAGE4 slow FIFO WORD0
STAGE4 slow FIFO WORD1
STAGE4 slow FIFO WORD2
STAGE4 slow FIFO WORD3
STAGE4 slow FIFO WORD4
STAGE4 slow FIFO WORD5
STAGE4 slow FIFO WORD6
STAGE4 slow FIFO WORD7
STAGE4 slow FIFO ambient value
STAGE4 fast FIFO average value
STAGE4 CDC FIFO WORD0
STAGE4 CDC FIFO WORD1
STAGE4 maximum value FIFO WORD0
STAGE4 maximum value FIFO WORD1
STAGE4 maximum value FIFO WORD2
STAGE4 maximum value FIFO WORD3
STAGE4 average maximum FIFO value
STAGE4 high threshold value
STAGE4 temporary maximum value
STAGE4 minimum value FIFO WORD0
STAGE4 minimum value FIFO WORD1
STAGE4 minimum value FIFO WORD2
STAGE4 minimum value FIFO WORD3
STAGE4 average minimum FIFO value
STAGE4 low threshold value
STAGE4_LOW_THRESHOLD
STAGE4_MIN_TEMP
Unused
STAGE4 temporary minimum value
Rev. 0 | Page 51 of 56
AD7143
Table 47. STAGE5 Results Registers
Address Data Bit
Default
Type
Name
Description
0x194
[15:0]
X
R/W
STAGE5_CONV_DATA
STAGE5 CDC 16-bit conversion data
(copy of data in STAGE5_CONV_DATA register)
0x195
0x196
0x197
0x198
0x199
0x19A
0x19B
0x19C
0x19D
0x19E
0x19F
0x1A0
0x1A1
0x1A2
0x1A3
0x1A4
0x1A5
0x1A6
0x1A7
0x1A8
0x1A9
0x1AA
0x1AB
0x1AC
0x1AD
0x1AE
0x1AF
0x1B0
0x1B1
0x1B2
0x1B3
0x1B4
0x1B5
0x1B6
0x1B7
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE5_FF_WORD0
STAGE5_FF_WORD1
STAGE5_FF_WORD2
STAGE5_FF_WORD3
STAGE5_FF_WORD4
STAGE5_FF_WORD5
STAGE5_FF_WORD6
STAGE5_FF_WORD7
STAGE5_SF_WORD0
STAGE5_SF_WORD1
STAGE5_SF_WORD2
STAGE5_SF_WORD3
STAGE5_SF_WORD4
STAGE5_SF_WORD5
STAGE5_SF_WORD6
STAGE5_SF_WORD7
STAGE5_SF_AMBIENT
STAGE5_FF_AVG
STAGE5_CDC_WORD0
STAGE5_CDC_WORD1
STAGE5_MAX_WORD0
STAGE5_MAX_WORD1
STAGE5_MAX_WORD2
STAGE5_MAX_WORD3
STAGE5_MAX_AVG
STAGE5_HIGH_THRESHOLD
STAGE5_MAX_TEMP
STAGE5_MIN_WORD0
STAGE5_MIN_WORD1
STAGE5_MIN_WORD2
STAGE5_MIN_WORD3
STAGE5_MIN_AVG
STAGE5 fast FIFO WORD0
STAGE5 fast FIFO WORD1
STAGE5 fast FIFO WORD2
STAGE5 fast FIFO WORD3
STAGE5 fast FIFO WORD4
STAGE5 fast FIFO WORD5
STAGE5 fast FIFO WORD6
STAGE5 fast FIFO WORD7
STAGE5 slow FIFO WORD0
STAGE5 slow FIFO WORD1
STAGE5 slow FIFO WORD2
STAGE5 slow FIFO WORD3
STAGE5 slow FIFO WORD4
STAGE5 slow FIFO WORD5
STAGE5 slow FIFO WORD6
STAGE5 slow FIFO WORD7
STAGE5 slow FIFO ambient value
STAGE5 fast FIFO average value
STAGE5 CDC FIFO WORD0
STAGE5 CDC FIFO WORD1
STAGE5 maximum value FIFO WORD0
STAGE5 maximum value FIFO WORD1
STAGE5 maximum value FIFO WORD2
STAGE5 maximum value FIFO WORD3
STAGE5 average maximum FIFO value
STAGE5 high threshold value
STAGE5 temporary maximum value
STAGE5 minimum value FIFO WORD0
STAGE5 minimum value FIFO WORD1
STAGE5 minimum value FIFO WORD2
STAGE5 minimum value FIFO WORD3
STAGE5 average minimum FIFO value
STAGE5 low threshold value
STAGE5 temporary minimum value
STAGE5_LOW_THRESHOLD
STAGE5_MIN_TEMP
Unused
Rev. 0 | Page 52 of 56
AD7143
Table 48. STAGE6 Results Registers
Address Data Bit
Default
Type
Name
Description
0x1B8
[15:0]
X
R/W
STAGE6_CONV_DATA
STAGE6 CDC 16-bit conversion data
(copy of data in STAGE6_CONV_DATA register)
0x1B9
0x1BA
0x1BB
0x1BC
0x1BD
0x1BE
0x1BF
0x1C0
0x1C1
0x1C2
0x1C3
0x1C4
0x1C5
0x1C6
0x1C7
0x1C8
0x1C9
0x1CA
0x1CB
0x1CC
0x1CD
0x1CE
0x1CF
0x1D0
0x1D1
0x1D2
0x1D3
0x1D4
0x1D5
0x1D6
0x1D7
0x1D8
0x1D9
0x1DA
0x1DB
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE6_FF_WORD0
STAGE6_FF_WORD1
STAGE6_FF_WORD2
STAGE6_FF_WORD3
STAGE6_FF_WORD4
STAGE6_FF_WORD5
STAGE6_FF_WORD6
STAGE6_FF_WORD7
STAGE6_SF_WORD0
STAGE6_SF_WORD1
STAGE6_SF_WORD2
STAGE6_SF_WORD3
STAGE6_SF_WORD4
STAGE6_SF_WORD5
STAGE6_SF_WORD6
STAGE6_SF_WORD7
STAGE6_SF_AMBIENT
STAGE6_FF_AVG
STAGE6_CDC_WORD0
STAGE6_CDC_WORD1
STAGE6_MAX_WORD0
STAGE6_MAX_WORD1
STAGE6_MAX_WORD2
STAGE6_MAX_WORD3
STAGE6_MAX_AVG
STAGE6_HIGH_THRESHOLD
STAGE6_MAX_TEMP
STAGE6_MIN_WORD0
STAGE6_MIN_WORD1
STAGE6_MIN_WORD2
STAGE6_MIN_WORD3
STAGE6_MIN_AVG
STAGE6 fast FIFO WORD0
STAGE6 fast FIFO WORD1
STAGE6 fast FIFO WORD2
STAGE6 fast FIFO WORD3
STAGE6 fast FIFO WORD4
STAGE6 fast FIFO WORD5
STAGE6 fast FIFO WORD6
STAGE6 fast FIFO WORD7
STAGE6 slow FIFO WORD0
STAGE6 slow FIFO WORD1
STAGE6 slow FIFO WORD2
STAGE6 slow FIFO WORD3
STAGE6 slow FIFO WORD4
STAGE6 slow FIFO WORD5
STAGE6 slow FIFO WORD6
STAGE6 slow FIFO WORD7
STAGE6 slow FIFO ambient value
STAGE6 fast FIFO average value
STAGE0 CDC FIFO WORD0
STAGE6 CDC FIFO WORD1
STAGE6 maximum value FIFO WORD0
STAGE6 maximum value FIFO WORD1
STAGE6 maximum value FIFO WORD2
STAGE6 maximum value FIFO WORD3
STAGE6 average maximum FIFO value
STAGE6 high threshold value
STAGE6 temporary maximum value
STAGE6 minimum value FIFO WORD0
STAGE6 minimum value FIFO WORD1
STAGE6 minimum value FIFO WORD2
STAGE6 minimum value FIFO WORD3
STAGE6 average minimum FIFO value
STAGE6 low threshold value
STAGE6_LOW_THRESHOLD
STAGE6_MIN_TEMP
Unused
STAGE6 temporary minimum value
Rev. 0 | Page 53 of 56
AD7143
Table 49. STAGE7 Results Registers
Address Data Bit
Default
Type
Name
Description
0x1DC
[15:0]
X
R/W
STAGE7_CONV_DATA
STAGE7 CDC 16-bit conversion data
(copy of data in STAGE7_CONV_DATA register)
0x1DD
0x1DE
0x1DF
0x1E0
0x1E1
0x1E2
0x1E3
0x1E4
0x1E5
0x1E6
0x1E7
0x1E8
0x1E9
0x1EA
0x1EB
0x1EC
0x1ED
0x1EE
0x1EF
0x1F0
0x1F1
0x1F2
0x1F3
0x1F4
0x1F5
0x1F6
0x1F7
0x1F8
0x1F9
0x1FA
0x1FB
0x1FC
0x1FD
0x1FE
0x1FF
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE7_FF_WORD0
STAGE7_FF_WORD1
STAGE7_FF_WORD2
STAGE7_FF_WORD3
STAGE7_FF_WORD4
STAGE7_FF_WORD5
STAGE7_FF_WORD6
STAGE7_FF_WORD7
STAGE7_SF_WORD0
STAGE7_SF_WORD1
STAGE7_SF_WORD2
STAGE7_SF_WORD3
STAGE7_SF_WORD4
STAGE7_SF_WORD5
STAGE7_SF_WORD6
STAGE7_SF_WORD7
STAGE7_SF_AMBIENT
STAGE7_FF_AVG
STAGE7_CDC_WORD0
STAGE7_CDC_WORD1
STAGE7_MAX_WORD0
STAGE7_MAX_WORD1
STAGE7_MAX_WORD2
STAGE7_MAX_WORD3
STAGE7_MAX_AVG
STAGE7_HIGH_THRESHOLD
STAGE7_MAX_TEMP
STAGE7_MIN_WORD0
STAGE7_MIN_WORD1
STAGE7_MIN_WORD2
STAGE7_MIN_WORD3
STAGE7_MIN_AVG
STAGE7 fast FIFO WORD0
STAGE7 fast FIFO WORD1
STAGE7 fast FIFO WORD2
STAGE7 fast FIFO WORD3
STAGE7 fast FIFO WORD4
STAGE7 fast FIFO WORD5
STAGE7 fast FIFO WORD6
STAGE7 fast FIFO WORD7
STAGE7 slow FIFO WORD0
STAGE7 slow FIFO WORD1
STAGE7 slow FIFO WORD2
STAGE7 slow FIFO WORD3
STAGE7 slow FIFO WORD4
STAGE7 slow FIFO WORD5
STAGE7 slow FIFO WORD6
STAGE7 slow FIFO WORD7
STAGE7 slow FIFO ambient value
STAGE7 fast FIFO average value
STAGE7 CDC FIFO WORD0
STAGE7 CDC FIFO WORD1
STAGE7 maximum value FIFO WORD0
STAGE7 maximum value FIFO WORD1
STAGE7 maximum value FIFO WORD2
STAGE7 maximum value FIFO WORD3
STAGE7 average maximum FIFO value
STAGE7 high threshold value
STAGE7 temporary maximum value
STAGE7 minimum value FIFO WORD0
STAGE7 minimum value FIFO WORD1
STAGE7 minimum value FIFO WORD2
STAGE7 minimum value FIFO WORD3
STAGE7 average minimum FIFO value
STAGE7 low threshold value
STAGE7 temporary minimum value
STAGE7_LOW_THRESHOLD
STAGE7_MIN_TEMP
Unused
Rev. 0 | Page 54 of 56
AD7143
OUTLINE DIMENSIONS
0.50
0.40
0.30
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATO
R
1
12
13
16
2.65
2.50 SQ
2.35
PIN 1
INDICATOR
3.75
BSC SQ
EXPOSED
PAD
4
8
5
0.65
BSC
9
0.25 MIN
TOP VIEW
1.95 BCS
BOTTOM VIEW
12° MAX
0.80 MAX
0.65 TYP
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC.
Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Very Thin Quad
(CP-16-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7143ACPZ-1REEL1
AD7143ACPZ-1500RL71
EVAL-AD7143-1EBZ1
Temperature Range
Serial Interface Description
I2C Interface
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Evaluation Board
Package Option
CP-16-13
CP-16-13
−40°C to +85°C
−40°C to +85°C
I2C Interface
I2C Interface
1 Z = Pb-free part.
Rev. 0 | Page 55 of 56
AD7143
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06472-0-1/07(0)
Rev. 0 | Page 56 of 56
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