AD7190BRUZ-REEL_技术文档

4.8 kHz Ultralow Noise 24-Bit

Sigma-Delta ADC with PGA

AD7190

Chromatography

FEATURES

PLC/DCS analog input modules

Data acquisition

Medical and scientific instrumentation

RMS noise: 8.5 nV @ 4.7 Hz (gain = 128)

16 noise free bits @ 2.4 kHz (gain = 128)

Up to 22.5 noise free bits (gain = 1)

Offset drift: 5 nV/°C

GENERAL DESCRIPTION

Gain drift: 1 ppm/°C

The AD7190 is a low noise, complete analog front end for high

precision measurement applications. It contains a low noise,

24-bit sigma-delta (∑-Δ) analog to digital converter (ADC).

The on-chip low noise gain stage means that signals of small

amplitude can be interfaced directly to the ADC.

Specified drift over time

2 differential/4 pseudo differential input channels

Automatic channel sequencer

Programmable gain (1 to 128)

Output data rate: 4.7 Hz to 4.8 kHz

Internal or external clock

Simultaneous 50 Hz/60 Hz rejection

4 general-purpose digital outputs

Power supply

AV_DD: 4.75 V to 5.25 V

DV_DD: 2.7 V to 5.25 V

Current: 6 mA

Temperature range: –40°C to +105°C

Interface

The device can be configured to have two differential inputs or

four pseudo differential inputs. The on-chip channel sequencer

allows several channels to be enabled, and the AD7190

sequentially converts on each enabled channel. This simplifies

communication with the part. The on-chip 4.92 MHz clock can

be used as the clock source to the ADC or, alternatively, an

external clock or crystal can be used. The output data rate from

the part can be varied from 4.7 Hz to 4.8 kHz.

The device has two digital filter options. The choice of filter

affects the rms noise/noise-free resolution at the programmed

output data rate, the settling time, and the 50 Hz/60 Hz

rejection. For applications that require all conversions to be

settled, the AD7190 includes a zero latency feature.

3-wire serial

SPI, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

APPLICATIONS

The part operates with 5 V analog power supply and a digital

power supply from 2.7 V to 5.25 V. It consumes a current of

6 mA. It is housed in a 24-lead TSSOP package.

Weigh scales

Strain gauge transducers

Pressure measurement

Temperature measurement

FUNCTIONAL BLOCK DIAGRAM

AGND AV

DV

DGND REFIN1(+) REFIN1(–)

DD

REFERENCE

DETECT

AD7190

AIN1

AIN2

AIN3

DOUT/RDY

SERIAL

INTERFACE

AND

CONTROL

LOGIC

AIN4

MUX

DIN

Σ-Δ

ADC

AINCOM

PGA

SCLK

CS

SYNC

TEMP

SENSOR

P3

P2

BPDSW

CLOCK

CIRCUITRY

AGND

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7190

TABLE OF CONTENTS

Features .............................................................................................. 1

Full-Scale Register...................................................................... 25

ADC Circuit Information.............................................................. 26

Overview ..................................................................................... 26

Filter, Output Data Rate, Settling Time................................... 26

Digital Interface.......................................................................... 29

Circuit Description......................................................................... 33

Analog Input Channel ............................................................... 33

PGA.............................................................................................. 33

Bipolar/Unipolar Configuration .............................................. 33

Data Output Coding .................................................................. 33

Clock ............................................................................................ 33

Burnout Currents ....................................................................... 34

Reference ..................................................................................... 34

Reference Detect......................................................................... 34

Reset............................................................................................. 34

System Synchronization ............................................................ 35

Temperature Sensor ................................................................... 35

Bridge Power-Down Switch...................................................... 35

Logic Outputs ............................................................................. 35

Enable Parity ............................................................................... 35

Calibration................................................................................... 36

Grounding and Layout .............................................................. 36

Applications Information.............................................................. 38

Weigh Scales................................................................................ 38

Outline Dimensions....................................................................... 39

Ordering Guide .......................................................................... 39

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 7

Circuit and Timing Diagrams..................................................... 7

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

RMS Noise and Resolution............................................................ 15

Sinc⁴Chop Disabled................................................................... 15

Sinc³Chop Disabled................................................................... 16

Sinc⁴Chop Enabled.................................................................... 17

Sinc³Chop Enabled.................................................................... 18

On-Chip Registers.......................................................................... 19

Communications Register......................................................... 19

Status Register............................................................................. 20

Mode Register ............................................................................. 20

Configuration Register .............................................................. 22

Data Register............................................................................... 24

GPOCON Register..................................................................... 24

Offset Register............................................................................. 25

REVISION HISTORY

10/08—Revision 0—Initial Version

Rev. 0 | Page 2 of 40

AD7190

SPECIFICATIONS

AV_DD= 4.75 V to 5.25 V; DV_DD= 2.7 V to 5.25 V; GND = 0 V; REFIN1(+) = AV_DD; REFIN1(−) = GND; MCLK = 4.92 MHz; all

specifications T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

AD7190B

Unit

Test Conditions/Comments¹

ADC

Output Data Rate

4.7 to 4800

1.17 to 1200

24

See the RMS Noise and

Resolution section

Hz nom

Bits min

Chop disabled.

Chop enabled.

FS > 1, sinc⁴filter.

FS > 4, sinc³filter.

No Missing Codes²

Resolution

RMS Noise and Output Data Rates See the RMS Noise and

Resolution section

Integral Nonlinearity

±±

±1±

±7±5gain

±0.±

±1005gain

±±

ppm of FSR max

μV typ

nV5°C typ

±1 ppm typical, gain = 1.

±± ppm typical, gain > 1.

Chop disabled.

Offset Error³

Chop enabled.

Offset Error Drift vs. Temperature

Gain = 1 to 16. chop disabled.

Gain = 32 to 128. chop disabled.

Chop enabled.

nV5°C typ

±±

Offset Error Drift vs. Time

Gain Error^{3, 4}

2±

nV51000 hours typ

% max

% typ

ppm5°C typ

ppm51000 hours typ

dB typ

Gain ≥ 32

±0.001 % typical, gain = 1, AV_DD= ± V.

Gain > 1, post internal-calibration.

±0.00±

±0.007±

±1

10

9±

Gain Drift vs. Temperature

Gain Drift vs. Time

Power Supply Rejection

Gain = 1.

Gain = 1, V_IN= 1 V.

9±

dB min

Gain > 1, V_IN= 1 V5gain. 110 dB typical.

Common-Mode Rejection

@ DC

100

110

120

dB min

Gain = 1, V_IN= 1 V²

Gain > 1, V_IN= 1 V5gain.

10 Hz output data rate, ±0 ± 1 Hz, 60 ± 1 Hz.

±0 ± 1 Hz (±0 Hz output data rate), 60 ± 1 Hz

(60 Hz output data rate).

@ ±0 Hz, 60 Hz²

Normal Mode Rejection²

Sinc⁴Filter

Internal Clock

@ ±0 Hz, 60 Hz

100

74

dB min

10 Hz output data rate, ±0 ± 1 Hz, 60 ± 1 Hz.

±0 Hz output data rate, REJ60^±= 1,

±0 ± 1 Hz, 60 ± 1 Hz.

@ ±0 Hz

@ 60 Hz

96

97

dB min

±0 Hz output data rate, ±0 ± 1 Hz.

60 Hz output data rate, 60 ± 1 Hz.

Rev. 0 | Page 3 of 40

AD7190

Parameter

AD7190B

Unit

Test Conditions/Comments¹

External Clock

@ ±0 Hz, 60 Hz

120

82

dB min

10 Hz output data rate, ±0 ± 1 Hz, 60 ± 1 Hz.

±0 Hz output data rate, REJ60^±= 1,

±0 ± 1 Hz, 60 ± 1 Hz.

@ ±0 Hz

@ 60 Hz

120

dB min

±0 Hz output data rate, ±0 ± 1 Hz.

60 Hz output data rate, 60 ± 1 Hz.

Sinc³Filter

Internal Clock

@ ±0 Hz, 60 Hz

7±

60

dB min

10 Hz output data rate, ±0 ± 1 Hz, 60 ± 1 Hz.

±0 Hz output data rate, REJ60^±= 1,

±0 ± 1 Hz, 60 ± 1 Hz.

@ ±0 Hz

@ 60 Hz

72

dB min

±0 Hz output data rate, ±0 ± 1 Hz.

60 Hz output data rate, 60 ± 1 Hz.

External Clock

@ ±0 Hz, 60 Hz

100

67

dB min

10 Hz output data rate, ±0 ± 1 Hz, 60 ± 1 Hz.

±0 Hz output data rate, REJ60^±= 1,

±0 ± 1 Hz, 60 ± 1 Hz.

@ ±0 Hz

@ 60 Hz

100

dB min

±0 Hz output data rate, ±0 ± 1 Hz.

60 Hz output data rate, 60 ± 1 Hz.

ANALOG INPUTS

Differential Input Voltage Ranges

±V_REF5gain

V nom

V_REF= REFINx(+) − REFINx(−),

gain = 1 to 128.

±(AV_DD– 1.2± V)5gain

V min5max

gain > 1.

Absolute AIN Voltage Limits²

Unbuffered Mode

GND − ±0 mV

AV_DD+ ±0 mV

GND + 2±0 mV

AV_DD− 2±0 mV

V min

V max

V min

V max

Buffered Mode

Analog Input Current

Buffered Mode

Input Current²

±2

±3

±±

nA max

pA5°C typ

Gain = 1.

Gain > 1.

Input Current Drift

Unbuffered Mode

Input Current

±±

μA5V typ

Gain = 1, input current varies with input

voltage.

±1

μA5V typ

Gain > 1.

Input Current Drift

±0.0±

±1.6

nA5V5°C typ

External clock.

Internal clock.

REFERENCE INPUT

REFIN Voltage

Reference Voltage Range²

AV_DD

1

AV_DD

V nom

V min

V max

REFIN = REFINx(+) − REFINx(−).

The differential input must be limited to

± (AV_DD– 1.2± V)5gain when gain > 1.

Absolute REFIN Voltage Limits²

Average Reference Input Current

Drift

GND – ±0 mV

AV_DD+ ±0 mV

7

V min

V max

μA5V typ

nA5V5°C typ

±0.03

External clock.

Internal clock.

1.3

nA5V5°C typ

Rev. 0 | Page 4 of 40

AD7190

Parameter

AD7190B

Unit

Test Conditions/Comments¹

Normal Mode Rejection²

Common-Mode Rejection

Reference Detect Levels

Same as for analog inputs

100

0.3

0.6

dB typ

V min

V max

TEMPERATURE SENSOR

Accuracy

±2

°C typ

Applies after user calibration at one

temperature.

Sensitivity

281±

Codes5°C typ

Bipolar mode.

BRIDGE POWER-DOWN SWITCH

R_ON

Allowable Current²

BURNOUT CURRENTS

AIN Current

10

30

Ω max

mA max

Continuous current.

±00

nA nom

Analog inputs must be buffered and chop

disabled.

DIGITAL OUTPUTS (P0 to P3)

Output High Voltage, VOH²

Output Low Voltage, VOL²

Floating-State Leakage Current

Floating-State Output

Capacitance

4

V min

AV_DD= ±V, I_SOURCE= 200 μA.

AV_DD= ±V, I_SINK= 800 μA.

0.4

±100

10

V max

nA max

pF typ

INTERNAL5EXTERNAL CLOCK

Internal Clock

Frequency

Duty Cycle

External Clock5Crystal²

4.92 ± 4%

±0:±0

MHz min5max

% typ

Frequency

4.91±2

2.4±765±.12

0.8

0.4

2.±

MHz nom

MHz min5max

V max

V min

Input Low Voltage, VINL

Input High Voltage, VINH

DV_DD= ± V.

DV_DD= 3 V.

DV_DD= ± V.

3.±

V min

Input Current

±10

μA max

LOGIC INPUTS

Input High Voltage, VINH²

Input Low Voltage, VINL²

Hysteresis²

2

0.8

0.150.2±

±10

V min

V max

V min5V max

μA max

Input Currents

LOGIC OUTPUT (DOUT5RDY)

Output High Voltage, VOH²

Output Low Voltage, VOL²

Output High Voltage, VOH²

Output Low Voltage, VOL²

Floating-State Leakage Current

DV_DD− 0.6

0.4

4

0.4

±10

10

V min

V max

V min

V max

μA max

pF typ

DV_DD= 3 V, I_SOURCE= 100 μA.

DV_DD= 3 V, I_SINK= 100 μA.

DV_DD= ± V, I_SOURCE= 200 μA.

DV_DD= ± V, I_SINK= 1.6 mA.

Floating-State Output

Capacitance

Data Output Coding

SYSTEM CALIBRATION²

Full-Scale Calibration Limit

Zero-Scale Calibration Limit

Input Span

Offset binary

1.0± × FS

−1.0± × FS

0.8 × FS

V max

V min

V max

2.1 × FS

Rev. 0 | Page ± of 40

AD7190

Parameter

AD7190B

Unit

Test Conditions/Comments¹

POWER REQUIREMENTS⁶

Power Supply Voltage

AV_DD− AGND

4.7±5±.2±

2.75±.2±

V min5max

DV_DD− DGND

Power Supply Currents

AI_DDCurrent

1

mA max

mA typ

0.8± mA typical, gain = 1, buffer off.

1.1 mA typical, gain = 1, buffer on.

3.± mA typical, gain = 8, buffer off.

4 mA typical, gain = 8, buffer on.

± mA typical, gain = 16 to 128, buffer off.

±.± mA typical, gain = 16 to 128, buffer on.

0.3± mA typical, DV_DD= 3 V.

1.3

4.±

4.7±

6.2

6.7±

0.4

0.6

1.±

2

DI_DDCurrent

0.± mA typical, DV_DD= ± V.

External crystal used.

I_DD(Power-Down Mode)

μA max

¹Temperature range: −40°C to +10±°C.

²Specification is not production tested but is supported by characterization data at initial product release.

³Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-

scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

⁴Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (AV_DD= ± V, gain = 1, T_A= 2±°C).

^±REJ60 is a bit in the mode register. When the output data rate is set to ±0 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous ±0 Hz560 Hz rejection.

⁶Digital inputs equal to DV_DDor GND.

Rev. 0 | Page 6 of 40

AD7190

TIMING CHARACTERISTICS

AV_DD= 4.75 V to 5.25 V; DV_DD= 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV_DD, unless otherwise noted.

Table 2.

Parameter

Limit at T_MIN, T_MAX(B Version)

Unit

Conditions/Comments^{1, 2}

SCLK high pulse width

SCLK low pulse width

t₃

t₄

100

ns min

READ OPERATION

t₁

0

ns min

ns max

ns min

ns max

ns min

ns max

ns min

CS falling edge to DOUT5RDY active time

DV_DD= 4.7± V to ±.2± V

DV_DD= 2.7 V to 3.6 V

SCLK active edge to data valid delay⁴

DV_DD= 4.7± V to ±.2± V

DV_DD= 2.7 V to 3.6 V

Bus relinquish time after CS inactive edge

60

80

0

60

80

10

80

0

3

t₂

±, 6

t_±

t₆

t₇

SCLK inactive edge to CS inactive edge

SCLK inactive edge to DOUT5RDY high

10

WRITE OPERATION

t₈

0

ns min

CS falling edge to SCLK active edge setup time⁴

Data valid to SCLK edge setup time

Data valid to SCLK edge hold time

CS rising edge to SCLK edge hold time

t₉

t₁₀

t₁₁

30

2±

0

¹Sample tested during initial release to ensure compliance. All input signals are specified with t_R= t_F= ± ns (10% to 90% of DV_DD) and timed from a voltage level of 1.6 V.

²See Figure 3 and Figure 4.

³These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V_OLor V_OHlimits.

⁴The SCLK active edge is the falling edge of SCLK.

^±These numbers are derived from the measured time taken by the data output to change 0.± V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the ±0 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

⁶RDY

RDY

returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while

is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the

digital word can be read only once.

CIRCUIT AND TIMING DIAGRAMS

I

(1.6mA WITH DV = 5V,

DD

SINK

100µA WITH DV

= 3V)

DD

TO

OUTPUT

1.6V

50pF

I

(200µA WITH DV = 5V,

DD

SOURCE

100µA WITH DV

= 3V)

DD

Figure 2. Load Circuit for Timing Characterization

Rev. 0 | Page 7 of 40

AD7190

CS (I)

t₆

t₁

t₅

MSB

LSB

t₇

DOUT/RDY (O)

t₂

t₃

SCLK (I)

t₄

I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

CS (I)

t₁₁

t₈

SCLK (I)

DIN (I)

t₉

t₁₀

MSB

LSB

I = INPUT, O = OUTPUT

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 8 of 40

AD7190

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 3.

Parameter

Rating

AV_DDto GND

−0.3 V to +6.± V

−0.3 V to AV_DD+ 0.3 V

−0.3 V to DV_DD+ 0.3 V

10 mA

Table 4. Thermal Resistance

Package Type

24-Lead TSSOP

DV_DDto GND

θ_JA

θ_JC

Unit

Analog Input Voltage to GND

Reference Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

AIN5Digital Input Current

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

Lead Temperature, Soldering

Vapor Phase (60 sec)

97.9

14

°C5W

ESD CAUTION

−40°C to +10±°C

−6±°C to +1±0°C

1±0°C

21±°C

220°C

Infrared (1± sec)

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 9 of 40

AD7190

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

MCLK1

MCLK2

SCLK

DIN

DOUT/RDY

SYNC

CS

DV

AV

DD

AD7190

TOP VIEW

(Not to Scale)

P3

P2

DGND

P1/REFIN2(+)

P0/REFIN2(–)

NC

AGND

BPDSW

REFIN1(–)

REFIN1(+)

AIN4

9

10

11

12

AINCOM

AIN1

AIN2

AIN3

NC = NO CONNECT

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

MCLK1

When the master clock for the device is provided externally by a crystal, the crystal is connected between

MCLK1 and MCLK2.

2

3

4

MCLK2

SCLK

CS

Master Clock Signal for the Device. The AD7190 has an internal 4.92 MHz clock. This internal clock can be

made available on the MCLK2 pin. The clock for the AD7190 can be provided externally also in the form of

a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the

MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected.

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be

continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncon-

tinuous clock with the information transmitted to or from the ADC in smaller batches of data.

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC

in systems with more than one device on the serial bus or as a frame synchronization signal in

communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode

with SCLK, DIN, and DOUT used to interface with the device.

±

6

7

P3

P2

Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV_DDand AGND.

Digital Output Pin5Positive Reference Input. This pin functions as a general-purpose output bit referenced

between AV_DDand AGND. When REFSEL = 1, this pin functions as REFIN2(+). An external reference can be

applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AV_DDand GND + 1 V. The

nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AV_DD, but the part functions with a reference from

1 V to AV_DD.

P15REFIN2(+)

8

P05REFIN2(−)

Digital Output Pin5Negative Reference Input. This pin functions as a general-purpose output bit referenced

between AV_DDand AGND. When REFSEL = 1, this pin functions as REFIN2(−). This reference input can lie

anywhere between GND and AV_DD− 1 V.

9

NC

No Connect. This pin should be tied to AGND.

10

AINCOM

Analog Input AIN1 to Analog Input AIN4 are referenced to this input when configured for pseudo

differential operation.

11

12

AIN1

AIN2

Analog Input. It can be configured as the positive input of a fully differential input pair when used with

AIN2 or as a pseudo differential input when used with AINCOM.

Analog Input. It can be configured as the negative input of a fully differential input pair when used with

AIN1 or as a pseudo differential input when used with AINCOM.

Rev. 0 | Page 10 of 40

AD7190

Pin No.

Mnemonic

Description

13

AIN3

Analog Input. It can be configured as the positive input of a fully differential input pair when used with

AIN4 or as a pseudo differential input when used with AINCOM.

14

1±

AIN4

Analog Input. It can be configured as the negative input of a fully differential input pair when used with

AIN3 or as a pseudo differential input when used with AINCOM.

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).

REFIN1(+) can lie anywhere between AV_DDand GND + 1 V. The nominal reference voltage, (REFIN1(+) −

REFIN1(−)), is AV_DD, but the part functions with a reference from 1 V to AV_DD.

REFIN1(+)

16

17

18

19

20

21

22

REFIN1(−)

BPDSW

AGND

DGND

AV_DD

Negative Reference Input. This reference input can lie anywhere between GND and AV_DD− 1 V.

Bridge Power-Down Switch to AGND.

Analog Ground Reference Point.

Digital Ground Reference Point.

Analog Supply Voltage, 4.7± V to ±.2± V. AV_DDis independent of DV_DD.

Digital Supply Voltage, 2.7 V to ±.2± V. DV_DDis independent of AV_DD.

Logic input that allows for synchronization of the digital filters and analog modulators when using

multiple AD7190 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the

calibration control logic are reset, and the analog modulator is held in its reset state. SYNC does not affect

the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to

DV_DD.

DV_DD

SYNC

23

24

DOUT5RDY

Serial Data Output5Data Ready Output. DOUT5RDYserves a dual purpose. It functions as a serial data

output pin to access the output shift register of the ADC. The output shift register can contain data from

any of the on-chip data or control registers. In addition, DOUT5RDY operates as a data ready pin, going low

to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high

before the next update occurs. The DOUT5RDY falling edge can be used as an interrupt to a processor,

indicating that valid data is available. With an external serial clock, the data can be read using the

DOUT5RDY pin. With CS low, the data5control word information is placed on the DOUT5RDY pin on the

SCLK falling edge and is valid on the SCLK rising edge.

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the

control registers in the ADC, with the register selection bits of the communications register identifying the

appropriate register.

Rev. 0 | Page 11 of 40

AD7190

TYPICAL PERFORMANCE CHARACTERISTICS

8,388,760

8,388,950

8,388,900

8,388,850

8,388,800

8,388,750

8,388,700

8,388,650

8,388,600

8,388,550

8,388,500

8,388,450

8,388,758

8,388,756

8,388,754

8,388,752

8,388,750

8,388,748

8,388,746

0

200

400

600

800

1000

0

100 200 300 400 500 600 700 800 900 1000

SAMPLES

SAMPLE

Figure 6. Noise (V_REF= 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop

Disabled, Sinc⁴Filter)

Figure 8. Noise (V_REF= 5 V, Output Data Rate = 4800 Hz, Gain = 128, Chop

Disabled, Sinc⁴Filter)

30

25

20

15

10

5

250

200

150

100

50

0

CODE

Figure 9. Noise Distribution Histogram (V_REF= 5 V,

Figure 7. Noise Distribution Histogram (V_REF= 5 V,

Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc⁴Filter)

Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc⁴Filter)

Rev. 0 | Page 12 of 40

AD7190

8,388,820

8,388,800

8,388,780

8,388,760

8,388,740

8,388,720

8,388,700

8,388,680

8,388,660

8,388,640

8,388,620

3.0

2.0

1.0

0

–1.0

–2.0

–3.0

0

100 200 300 400 500 600 700 800 900 1000

SAMPLES

–2.5 –2.0 –1.5 –1.0 –0.5

0

0.5

1.0

1.5

2.0

2.5

V

(V)

IN

Figure 10. Noise (V_REF= 5 V, Output Data Rate = 4800 Hz, Gain = 1, Chop

Disabled, Sinc⁴Filter)

Figure 12. INL (Gain = 1)

80

70

60

50

40

30

20

10

0

6

4

2

0

–2

–4

–6

–0.020 –0.015 –0.010 –0.005

0

0.005 0.010 0.015 0.020

V

(V)

IN

CODE

Figure 11. Noise Distribution Histogram (V_REF= 5 V,

Figure 13. INL (Gain = 128)

Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc⁴Filter)

Rev. 0 | Page 13 of 40

AD7190

66

64

62

60

58

56

54

1.000008

1.000007

1.000006

1.000005

1.000004

1.000003

1.000002

1.000001

1.000000

–60 –40 –20

0

20

40

60

80

100 120 140

–60

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 14. Offset Error (Gain = 1, Chop Disabled)

Figure 16. Gain Error (Gain = 1, Chop Disabled)

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

128.003

128.002

128.001

128.000

127.999

127.998

127.997

127.996

–0.7

–60

–40

–20

0

20

40

60

80

100

120

–60

–40

–20

0

20

40

60

80

100

120

TEMERATURE (°C)

TEMPERATURE (°C)

Figure 15. Offset Error (Gain = 128, Chop Disabled)

Figure 17. Gain Error (Gain = 128, Chop Disabled)

Rev. 0 | Page 14 of 40

AD7190

RMS NOISE AND RESOLUTION

The AD7190 has a choice of two filter types: sinc⁴and sinc³.

In addition, the AD7190 can be operated with chop enabled

or chop disabled.

on a single channel. The effective resolution is also shown, and

the output peak-to-peak (p-p) resolution, or noise-free resol-

ution, is listed in parentheses. It is important to note that the

effective resolution is calculated using the rms noise, wheras the

p-p resolution is calculated based on peak-to-peak noise. The p-

p resolution represents the resolution for which there is no code

flicker. These numbers are typical and are rounded to the

nearest ½ LSB.

The following tables show the rms noise of the AD7190 for some

of the output data rates and gain settings with chop disabled

and enabled for the sinc⁴and sinc³filters. The numbers given

are for the bipolar input range with the external 5 V reference.

These numbers are typical and are generated with a differential

input voltage of 0 V when the ADC is continuously converting

SINC⁴CHOP DISABLED

Table 6. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms)

Gain of 1

2±0

310

330

900

Gain of 8

38

4±

Gain of 16 Gain of 32

Gain of 64

Gain of 128

1023

640

480

96

80

32

16

±

4.7

7.±

10

±0

8±2.±

±33

400

21

12

10

12

14

33

36

±±

7±

140

220

380

8.±

10.±

11.±

28

31

48

2±

16

±0

30

18

800

12±

140

21±

28±

480

780

1920

78

4±

60

66.7

26.7

13.3

4.17

1.67

0.83

970

88

±2

1±0

300

960

2400

4800

1460

1900

3000

±000

14,300

12±

170

280

440

1000

7±

100

17±

280

±±0

67

121

198

29±

2

1

Table 7. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word Output Data

Settling

Time (ms)

(Decimal)

Rate (Hz)

Gain of 1¹

24 (22.±)

24 (22)

Gain of 8¹

24 (22)

23.± (20.±)

23 (20.±)

22.± (19.±)

22 (19.±)

21.± (18.±)

20.± (18)

19.± (16.±)

Gain of 16¹

24 (22)

24 (21.±)

23 (20)

22.± (20)

22.± (19.±)

22 (19)

21 (18.±)

20.± (17.±)

19.± (16.±)

Gain of 32¹

Gain of 64¹

24 (21)

Gain of 128¹

23 (20.±)

23 (20)

1023

640

480

96

80

32

16

±

4.7

7.±

10

±0

8±2.±

±33

400

24 (22)

24 (21.±)

22.± (20)

22 (19.±)

21.± (19)

21 (18)

23.± (21)

23.± (20.±)

22 (19.±)

21.± (18.±)

21 (18.±)

20 (17.±)

19.± (16.±)

18.± (16)

24 (22)

22.± (20)

21.± (18.±)

20.± (18)

20 (17.±)

19.± (16.±)

18.± (16)

18 (1±.±)

800

23.± (20.±)

22.± (20)

22.± (19.±)

21.± (19)

21 (18)

60

66.7

26.7

13.3

4.17

1.67

0.83

1±0

300

960

2400

4800

2

1

20 (17.±)

19 (16.±)

19.± (16.±)

¹The output peak-to-peak (p-p) resolution is listed in parentheses.

Rev. 0 | Page 1± of 40

AD7190

SINC³CHOP DISABLED

Table 8. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data Settling

Rate (Hz)

Time (ms)

639.4

400

Gain of 1

270

320

3±0

1000

10±0

1±00

19±0

4000

Gain of 8

42

±0

60

134

14±

22±

308

±90

Gain of 16

23

27

3±

86

9±

130

17±

330

Gain of 32

13.±

17

19

±0

±±

80

110

200

Gain of 64

10.±

13

1±

3±

40

±8

83

Gain of 128

1023

640

480

96

80

32

16

±

4.7

7.±

9

11.±

12.±

29

32

±0

10

300

±0

60

±0

1±0

300

960

2400

4800

20

10

3.12±

1.2±

0.62±

73

1±0

900

7000

133

490

34±0

2

1

±6,600

442,000

7000

±±,000

3±00

28,000

1800

14,000

Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms)

Gain of 1¹

24 (22.±)

24 (22)

Gain of 8¹

24 (22)

Gain of 16¹

24 (22)

24 (21.±)

23 (20)

22.± (20)

22 (19.±)

22 (19)

Gain of 32¹Gain of 64¹

Gain of 128¹

23 (20.±)

22.± (20)

21.± (18.±)

21 (18.±)

20.± (18)

20 (17.±)

19 (16.±)

1023

640

480

96

80

32

16

±

4.7

7.±

10

±0

639.4

400

300

60

±0

20

24 (21.±)

24 (21)

22.± (20)

22.± (19.±)

22 (19)

21.± (18.±)

20.± (18)

17.± (14.±)

14.± (11.±)

24 (21)

24 (22)

23.± (21)

23.± (20.±)

22 (19.±)

22 (19)

21.± (18.±)

21 (18)

24 (22)

24 (21.±)

23 (20.±)

22.± (19.±)

22 (19)

21 (18.±)

17.± (14.±)

14.± (11.±)

23.± (20.±)

23 (20.±)

22.± (20)

22.± (19.±)

21.± (18.±)

17.± (14.±)

14.± (11.±)

60

1±0

300

960

2400

4800

10

3.12±

1.2±

0.62±

21 (18)

17.± (14.±)

14.± (11.±)

20 (17.±)

17.± (14.±)

14.± (11.±)

2

1

17.± (14.±)

14.± (11.±)

¹The output peak-to-peak (p-p) resolution is listed in parentheses.

Rev. 0 | Page 16 of 40

AD7190

SINC⁴CHOP ENABLED

Table 10. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word Output Data Settling Time

(Decimal)

Rate (Hz)

1.17±

1.87±

2.±

12.±

1±

37.±

7±

240

(ms)

1702

1067

800

160

133

Gain of 1

177

219

234

637

Gain of 8

27

32

36

89

Gain of 16

1±

18

21

±±

63

89

120

198

311

707

Gain of 32

8.±

11.±

13

32

37

±3

71

124

198

389

Gain of 64

Gain of 128

1023

640

480

96

80

32

16

±

7

6

8.±

10

24

26

39

±3

99

1±6

26

7.±

8.±

20

22

34

48

86

140

209

686

99

±3

1033

1343

2121

3±36

10,200

1±2

202

340

±±2

1360

26.7

8.33

3.33

1.67

2

600

1

1200

Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data Settling

Rate (Hz)

1.17±

1.87±

2.±

Time (ms)

1702

1067

800

Gain of 1¹

24 (23)

24 (22.±)

24 (21)

23 (20.±)

23 (20)

Gain of 8¹

24 (22.±)

24 (21)

23.± (21)

23 (20)

22.± (20)

22 (19)

Gain of 16¹

24 (22.±)

24 (22)

23.± (20.±)

23 (20)

Gain of 32¹

24 (22.±)

24 (22)

Gain of 64¹

24 (21.±)

24 (21)

22.± (20)

22 (19)

Gain of 128¹

23.± (21)

23.± (20.±)

23 (20.±)

22 (19)

1023

640

480

96

80

32

16

±

24 (22)

12.±

1±

160

133

23 (20.±)

22.± (20)

22 (19.±)

21.± (18.±)

20.± (18)

19.± (17)

22 (19)

37.±

7±

240

600

1200

±3

21 (18.±)

20.± (18)

20 (17)

19 (16.±)

18.± (16)

26.7

8.33

3.33

1.67

22.± (19.±)

21.± (19)

21 (18)

21.± (19)

20.± (18)

20 (17)

22 (19.±)

21.± (18.±)

20 (17)

2

1

21 (18.±)

20 (17)

19 (16.±)

¹The output peak-to-peak (p-p) resolution is listed in parentheses.

Rev. 0 | Page 17 of 40

AD7190

SINC³CHOP ENABLED

Table 12. RMS Noise (nV) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data

Rate (Hz)

Settling

Time (ms)

Gain of 1

191

226

248

708

Gain of 8

30

36

43

9±

103

1±9

218

418

Gain of 16

16.±

19

2±

61

68

92

124

234

Gain of 32

10

12

14

36

39

±7

78

Gain of 64

Gain of 128

1023

640

480

96

80

32

16

±

1.±6

2.±

3.33

16.6

20

1282

800

600

120

100

40

20

6.2±

2.±

8

9

11

2±

29

41

±9

106

637

49±0

6.±

8.±

9

21

23

36

±2

94

347

2440

743

±0

1061

1380

2829

40,100

312,±±0

100

320

800

1600

142

1273

9900

2

1

49±0

38,±40

247±

19,800

1.2±

Table 13. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate

Filter Word

(Decimal)

Output Data Settling

Rate (Hz)

1.±6

2.±

Time (ms)

1282

800

Gain of 1¹

24 (23)

24 (22.±)

24 (21)

23.± (21)

23 (20.±)

23 (20)

Gain of 8¹

24 (22.±)

24 (22)

23.± (21)

23 (20)

Gain of 16¹Gain of 32¹Gain of 64¹Gain of 128¹

1023

640

480

96

80

32

16

±

24 (22.±)

24 (22)

23.± (20.±)

23 (20.±)

22.± (20)

22.± (19.±)

21.± (18.±)

18 (1±)

24 (22)

24 (21.±)

23 (20.±)

23 (20)

24 (21.±)

24 (21)

22.± (20)

22.± (19.±)

22 (19)

23.± (21)

23 (20.±)

22 (19)

3.33

16.6

20

600

120

100

21.± (19)

21 (18.±)

20.± (18)

19.± (17)

18 (1±)

±0

40

22.± (19.±)

22 (19)

21 (18.±)

18 (1±)

100

20

22.± (19.±)

21.± (19)

18 (1±)

21.± (18.±)

20.± (18)

18 (1±)

320

800

6.2±

2.±

22 (19)

18 (1±)

2

1

1600

1.2±

1± (12)

1± (12.±)

1± (12)

¹The output peak-to-peak (p-p) resolution is listed in parentheses.

Rev. 0 | Page 18 of 40

AD7190

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip

registers, which are described in the following sections. In the

descriptions, set implies a Logic 1 state and cleared implies a

Logic 0 state, unless otherwise noted.

interface returns to where it expects a write operation to the

communications register. This is the default state of the

interface and, on power-up or after a reset, the ADC is in this

default state waiting for a write operation to the communi-

cations register. In situations where the interface sequence is

lost, a write operation of at least 40 serial clock cycles with DIN

high returns the ADC to this default state by resetting the entire

part. Table 14 outlines the bit designations for the

communications register. CR0 through CR7 indicate the bit

locations, CR denoting that the bits are in the communications

register. CR7 denotes the first bit of the data stream. The

number in parentheses indicates the power-on/reset default

status of that bit.

COMMUNICATIONS REGISTER

(RS2, RS1, RS0 = 0, 0, 0)

The communications register is an 8-bit write-only register. All

communications to the part must start with a write operation to

the communications register. The data written to the communi-

cations register determines whether the next operation is a read

or write operation and in which register this operation takes

place. For read or write operations, when the subsequent read

or write operation to the selected register is complete, the

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

WEN(0)

R5W(0)

RS2(0)

RS1(0)

RS0(0)

CREAD(0)

0(0)

Table 14. Communications Register Bit Designations

Bit Location

Bit Name

Description

CR7

WEN

Write enable bit. A 0 must be written to this bit for a write to the communications register to occur. If a 1 is

the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location

until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the

communications register.

CR6

R5W

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

indicates that the next operation is a read from the designated register.

CR± to CR3

CR2

RS2 to RS0

CREAD

Register address bits. These address bits are used to select which registers of the ADC are selected during

the serial interface communication. See Table 1±.

Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read; that is, the contents of the data

register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin

goes low to indicate that a conversion is complete. The communications register does not have to be

written to for subsequent data reads. To enable continuous read, the instruction 01011100 must be written

to the communications register. To disable continuous read, the instruction 01011000 must be written to

the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors

activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset

occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction is to be

written to the device.

CR1 to CR0

These bits must be programmed to Logic 0 for correct operation.

Table 15. Register Selection

RS2

RS1

RS0

Register

Register Size

8 bits

0

1

Communications register during a write operation

Status register during a read operation

Mode register

24 bits

0

1

0

Configuration register

24 bits

0

1

0

1

0

Data register5data register plus status information

ID register

24 bits532 bits

8 bits

1

0

1

GPOCON register

8 bits

1

0

Offset register

24 bits

1

Full-scale register

24 bits

Rev. 0 | Page 19 of 40

AD7190

STATUS REGISTER

(RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80)

The status register is an 8-bit, read-only register. To access the ADC status register, the user must write to the communications register,

select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status

register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data

stream. The number in parentheses indicates the power-on/reset default status of that bit.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RDY(1)

ERR(0)

NOREF(0)

Parity(0)

CHD3(0)

CHD2(0)

CHD1(0)

CHD0(0)

Table 16. Status Register Bit Designations

Bit Location

Bit Name

Description

SR7

RDY

Ready bit for the ADC. Cleared when data is written to the ADC data register. The RDY bit is set

automatically after the ADC data register is read, or after a period of time before the data register is

updated, with a new conversion result to indicate to the user that the conversion data should not be read.

It is also set when the part is placed in power-down mode or idle mode or when SYNC is taken low.

The end of a conversion is also indicated by the DOUT5RDY pin. This pin can be used as an alternative to

the status register for monitoring the ADC for conversion data.

SR6

SR±

ERR

ADC error bit. This bit is written to at the same time as the RDY bit. The ERR bit is set to indicate that the

result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or

underrange or the absence of a reference voltage. The bit is cleared by a write operation to start a conversion.

NOREF

No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a

voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is

cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled

by setting the REFDET bit in the configuration register to 1. The ERR bit is also set if the voltage applied to

the selected reference input is invalid.

SR4

Parity

Parity check of the data register. If the ENPAR bit in the mode register is set, the parity bit is set if there is an

odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The

DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set,

the contents of the status register are transmitted along with the data for each data register read.

SR3 to SR0

CHD3 to

CHD0

These bits indicate which channel corresponds to the data register contents. They do not indicate which

channel is presently being converted but indicate which channel was selected when the conversion

contained in the data register was generated.

MODE REGISTER

(RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060)

The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the

operating mode, the output data rate, and the clock source. Table 17 outlines the bit designations for the mode register. MR0 through

MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The

number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and

RDY

filter and sets the

bit.

MR23

MD2(0)

MR15

Sinc3(0)

MR7

MR22

MD1(0)

MR14

0

MR21

MD0(0)

MR13

ENPAR(0)

MR5

MR20

DAT_STA(0)

MR12

0

MR19

CLK1(1)

MR11

Single(0)

MR3

MR18

CLK0(0)

MR10

REJ60(0)

MR2

MR17

0

MR16

0

MR9

FS9(0)

MR1

FS1(0)

MR8

FS8(0)

MR0

FS0(0)

MR6

MR4

FS7(0)

FS6(1)

FS±(1)

FS4(0)

FS3(0)

FS2(0)

Rev. 0 | Page 20 of 40

AD7190

Table 17. Mode Register Bit Designations

Bit Location

MR23 to MR21

MR20

Bit Name

MD2 to MD0

DAT_STA

Description

Mode select bits. These bits select the operating mode of the AD7190 (see Table 18).

This bit enables the transmission of status register contents after each data register read. When

DAT_STA is set, the contents of the status register are transmitted along with each data register read.

This function is useful when several channels are selected because the status register identifies the

channel to which the data register value corresponds.

MR19 to MR18

CLK1 to CLK0

These bits are used to select the clock source for the AD7190. Either the on-chip 4.92 MHz clock or an

external clock can be used. The ability to use an external clock allows several AD7190 devices to be

synchronized. Also, ±0 Hz560 Hz rejection is improved when an accurate external clock drives the

AD7190.

CLK1

CLK0

ADC Clock Source

0

1

0

External crystal used. The external crystal is connected from MCLK1 to MCLK2.

External clock used. The external clock is applied to the MCLK2 pin.

Internal 4.92 MHz clock. Pin MCLK2 is tristated.

1

0

1

Internal 4.92 MHz clock. The internal clock is available on MCLK2.

MR17 to MR16

MR1±

These bits must be programmed with a Logic 0 for correct operation.

SINC3

Sinc³filter select bit. When this bit is cleared, the sinc⁴filter is used (default value). When this bit is set,

the sinc³filter is used. The benefit of the sinc³filter compared to the sinc⁴filter is its lower settling time

when chop is disabled. For a given output data rate, f_ADC, the sinc³filter has a settling time of f_ADC53

while the sinc⁴filter has a settling time of f_ADC54. The sinc⁴filter, due to its deeper notches, gives better

±0 Hz560 Hz rejection. At low output data rates, both filters give similar rms noise and similar no

missing codes for a given output data rate. At higher output data rates (FS values less than ±), the sinc⁴

filter gives better performance than the sinc³filter for rms noise and no missing codes.

MR14

MR13

This bit must be programmed with a Logic 0 for correct operation.

ENPAR

Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit

in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the

contents of the status register are transmitted along with the data for each data register read.

MR12

MR11

This bit must be programmed with a Logic 0 for correct operation.

Single

Single cycle conversion enable bit. When this bit is set, the AD7190 settles in one conversion cycle so

that it functions as a zero latency ADC. This bit has no affect when multiple analog input channels are

enabled or when the single conversion mode is selected.

MR10

REJ60

This bit enables a notch at 60 Hz when the output data rate is equal to ±0 Hz. The bit should only be

set when chop is disabled and when the device is operating with the zero latency function disabled.

This bit allows simultaneous ±0 Hz560 Hz rejection.

MR9 to MR0

FS9 to FS0

Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter

cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In

association with the gain selection, it also determines the output noise (and, therefore, the effective

resolution) of the device. When chop is disabled and continuous conversion mode is selected, the first

notch of the filter occurs at a frequency determined by the relationship:

Filter First Notch Frequency = (f_MOD564)5FS

where FS is the decimal equivalent of the code in the FS0 to FS9 bits and is in the range 1 to 1023, and

fmod is the modulator frequency, which is equal to MCLK516. With a nominal MCLK of 4.92 MHz, this

results in a first notch frequency range from 4.69 Hz to 4.8 kHz.

Changing the filter notch frequency or changing the gain impacts resolution. Table 6 through Table

13 show the effect of the filter notch frequency and gain on the effective resolution of the AD7190.

The output data rate (or effective conversion time) for the device is equal to the frequency selected for

the first notch of the filter. For example, if the first notch of the filter is selected at ±0 Hz, a new word is

available at a ±0 Hz rate or every 20 ms. When chop is enabled, the output data rate equals

Output Data Rate = (f_MOD564)5(N x FS)

where FS is the decimal equivalent of the code in the FS0 to FS9 bits and is in the range 1 to 1023, and

fmod is the modulator frequency, which is equal to MCLK516. With a nominal MCLK of 4.92 MHz, this

results in a conversion rate from 4.695N Hz to 4.85N kHz, where N is the order of the sinc filter.

Rev. 0 | Page 21 of 40

AD7190

Table 18. Operating Modes

MD2 MD1 MD0 Mode

0

Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions

and places the result in the data register. The DOUT5 RDY pin and the RDY bit in the status register go low when a

conversion is complete. The user can read these conversions by setting the CREAD bit in the communications

register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically

placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each

conversion by writing to the communications register. After power-on, a reset, or a recon-figuration of the ADC, the

complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are

available at the selected output data rate, which is dependent on filter choice.

0

1

Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single

conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then

performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in

the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data

register and RDY remains active (low) until the data is read or another conversion is performed.

0

1

0

1

Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are

still provided.

Power-down mode. In power-down mode, all AD7190 circuitry, except the bridge power-down switch, is powered

down. The bridge power-down switch remains active because the user may need to power up the sensor prior to

powering up the AD7190 for settling reasons. The external crystal, if selected, remains active.

1

0

1

Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the

calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a

calibration. The measured offset coefficient is placed in the offset register of the selected channel.

Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed

in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the

selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-

scale error.

1

0

1

System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as

selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and

returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required

each time the gain of a channel is changed.

System full-scale calibration. The user should connect the system full-scale input to the channel input pins as

selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and

returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required

each time the gain of a channel is changed.

CONFIGURATION REGISTER

(RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117)

The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to

configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the

gain, and to select the analog input channel.

Table 19 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits

are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset

default status of that bit.

Rev. 0 | Page 22 of 40

AD7190

CON23

Chop(0)

CON15

CH7(0)

CON7

CON22

0(0)

CON21

0(0)

CON20

REFSEL(0)

CON12

CH4(0)

CON4

CON19

0(0)

CON18

0(0)

CON17

0(0)

CON16

(0)

CON14

CH6(0)

CON6

CON13

CH±(0)

CON5

0(0)

CON11

CH3(0)

CON3

U5B (0)

CON10

CH2(0)

CON2

G2(1)

CON9

CH1(0)

CON1

G1(1)

CON8

CH0(1)

CON0

G0(1)

Burn(0)

REFDET(0)

BUF(1)

Table 19. Configuration Register Bit Designations

Bit Location

Bit Name

Description

CON23

Chop

Chop enable bit. When the chop bit is cleared, chop is disabled. When the chop bit is set, chop is

enabled. When chop is enabled, the offset and offset drift of the ADC are continuously minimized.

However, this increases the conversion time and settling time of the ADC. For example, when FS = 96

decimal and the sinc⁴filter is selected, the conversion time with chop enabled equals 80 ms and the

settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of

96 decimal and the sinc⁴filter selected, the conversion time is 20 ms and the settling time is 80 ms.

However, at low gains, periodic calibrations may be required to remove the offset and offset drift.

CON22, CON21

CON20

These bits must be programmed with a Logic 0 for correct operation.

REFSEL

Reference select bits. The reference source for the ADC is selected using these bits.

REFSEL

Reference Voltage

0

1

External reference applied between REFIN1(+) and REFIN1(−).

External reference applied between the P1 and P0 pins.

CON19 to CON16

These bits must be programmed with a Logic 0 for correct operation.

CON1± to CON8 CH7 to CH0

Channel select bits. These bits are used to select which channels are enabled on the AD7190. See Table 20.

Several channels can be selected, and the AD7190 automatically sequences them. The conversion on

each channel requires the complete settling time.

CON7

CON6

Burn

When this bit is set to 1 by the user, the ±00 nA current sources in the signal path are enabled. When

burn = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer

is active and when chop is disabled.

REFDET

Enables the reference detect function. When set, the NOREF bit in the status register indicates when the

external reference being used by the ADC is open circuit or less than 0.± V typically. The reference detect

circuitry only operates when the ADC is active.

CON±

CON4

This bit must be programmed with a Logic 0 for correct operation.

BUF

Configures the ADC for a buffered or an unbuffered mode of operation. If cleared, the ADC operates in

unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered

mode, allowing the user to place source impedances on the front end without contributing gain errors

to the system. With the buffer disabled, the voltage on the analog input pins can be from ±0 mV below

GND to ±0 mV above AV_DD. When the buffer is enabled, it requires some headroom; therefore, the

voltage on any input pin must be limited to 2±0 mV within the power supply rails.

CON3

U5B

Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar

operation is selected.

CON2 to CON0

G2 to G0

Gain select bits. Written by the user to select the ADC input range as follows:

G2

0

G1

0

G0

0

Gain

ADC Input Range (5 V Reference, Bipolar Mode)

1

+± V

0

1

Reserved

0

1

0

Reserved

0

1

8

+62± mV

1

0

16

32

64

128

+312.± mV

+1±6.2 mV

+78.12± mV

+39.06 mV

1

0

1

0

1

Rev. 0 | Page 23 of 40

AD7190

Table 20. Channel Selection

Channel Enable Bits in the Configuration Register

Status Register Bits

CHD[3:0]

Calibration Register

Pair

CH7

CH6 CH5 CH4 CH3

CH2 CH1 CH0

Channel Enabled

AIN1 to AIN2

AIN3 to AIN4

Temperature sensor

AIN2 to AIN2

AIN1 to AINCOM

AIN2 to AINCOM

AIN3 to AINCOM

AIN4 to AINCOM

1

0000

0001

0010

0011

0100

0101

0110

0111

0

1

None

1

0

1

2

3

1

GPOCON REGISTER

DATA REGISTER

(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)

(RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000)

The GPOCON register is an 8-bit register from which data can

be read or to which data can be written. This register is used to

enable the general-purpose digital outputs.

The conversion result from the ADC is stored in this data

register. This is a read-only, 24-bit register. On completion of a

RDY

read operation from this register, the

pin/bit is set. When

the DAT_STA bit in the mode register is set to 1, the contents of

the status register are appended to each 24-bit conversion. This

is required when several analog input channels are enabled

because the four LSBs of the status register (CHD3 to CHD0)

identify the channel from which the conversion originated.

Table 21 outlines the bit designations for the GPOCON register.

GP0 through GP7 indicate the bit locations. GP denotes that the

bits are in the GPOCON register. GP7 denotes the first bit of

the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Rev. 0 | Page 24 of 40

AD7190

GP7

GP6

GP5

GP4

GP3

GP2

GP1

GP0

P0DAT(0)

0(0)

BPDSW(0)

GP32EN(0)

GP10EN(0)

P3DAT(0)

P2DAT(0)

P1DAT(0)

Table 21. Register Bit Designations

Bit Location

Bit Name

Description

GP7

0

This bit must be programmed with a Logic 0 for correct operation.

GP 6

BPDSW

Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch

BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power-

down switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active.

GP±

GP4

GP32EN

GP10EN

Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the digital outputs, P3 and P2, are

active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored.

Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the digital outputs, P1 and P0, are

active. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are

ignored. The P1 and P0 pins can be used as a reference input REFIN2 when the REFSEL bit in the

configuration register is set to 1.

GP3

GP2

GP1

GP0

P3DAT

P2DAT

P1DAT

P0DAT

Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin.

When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the

GPOCON register is read, the P3DAT bit reflects the status of the P3 pin; that is, a fault condition on the P3

pin is detected.

Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin.

When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the

GPOCON register is read, the P2DAT bit reflects the status of the P2 pin; that is, a fault condition on the P2

pin is detected.

Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin.

When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the

GPOCON register is read, the P1DAT bit reflects the status of the P1 pin; that is, a fault condition on the P1

pin is detected.

Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin.

When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the

GPOCON register is read, the P0DAT bit reflects the status of the P0 pin; that is, a fault condition on the P0

pin is detected.

OFFSET REGISTER

FULL-SCALE REGISTER

(RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000)

(RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0)

The offset register holds the offset calibration coefficient for the

ADC. The power-on reset value of the offset register is 0x800000.

The AD7190 has four offset registers; therefore, each channel

has a dedicated offset register. Each of these registers is a 24-bit

read/write register. This register is used in conjunction with its

associated full-scale register to form a register pair. The power-

on reset value is automatically overwritten if an internal or

system zero-scale calibration is initiated by the user. The AD7190

must be placed in power-down mode or idle mode when writing

to the offset register.

The full-scale register is a 24-bit register that holds the full-scale

calibration coefficient for the ADC. The AD7190 has four full-

scale registers; therefore, each channel has a dedicated full-scale

register. The full-scale registers are read/write registers. However,

when writing to the full-scale registers, the ADC must be placed

in power-down mode or idle mode. These registers are configured

at power-on with factory-calibrated, full-scale calibration coef-

ficients, the calibration being performed at gain = 1. Therefore,

every device has different default coefficients. The default value

is automatically overwritten if an internal or system full-scale

calibration is initiated by the user or if the full-scale register is

written to.

Rev. 0 | Page 2± of 40

AD7190

ADC CIRCUIT INFORMATION

5V

AGND AV

DV

DGND

DD

REFIN1(+)

REFERENCE

DETECT

IN+

IN–

AV

DD

AIN1

AIN2

AIN3

AIN4

AINCOM

OUT+

OUT–

DOUT/RDY

SERIAL

INTERFACE

AND

CONTROL

LOGIC

MUX

DIN

Σ-Δ

ADC

PGA

SCLK

CS

SYNC

AGND

TEMP

SENSOR

P3

P2

REFIN1(–)

BPDSW

CLOCK

CIRCUITRY

AD7190

AGND

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

Figure 18. Basic Connection Diagram

where:

OVERVIEW

f

_ADCis the output data rate.

The AD7190 is an ultralow noise ADC that incorporates a

∑-Δ modulator, a buffer, PGA, and on-chip digital filtering

intended for the measurement of wide dynamic range signals

such as those in pressure transducers, weigh scales, and strain

gauge applications.

f

_CLK= master clock (4.92 MHz nominal).

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

The output data rate can be programmed from 4.7 Hz to 4800 Hz;

that is, FS[9:0] can have a value from 1 to 1023.

The part can be configured to have two differential inputs or four

pseudo differential inputs that can be buffered or unbuffered.

Figure 18 shows the basic connections required to operate the part.

The above equation is valid for both the sinc³and sinc⁴filters.

The settling time for the sinc⁴filter is equal to

t

_SETTLE= 4/f_ADC

Whereas the settling time for the sinc³filter is equal to

_SETTLE= 3/f_ADC

FILTER, OUTPUT DATA RATE, SETTLING TIME

A ∑-Δ ADC consists of a modulator followed by a digital filter.

The AD7190 has two filter options: a sinc³filter and a sinc⁴

filter. The filter is selected using the sinc3 bit in the mode

register. When sinc3 is set to 0 (default value), the sinc⁴filter is

selected. The sinc³filter is selected when sinc3 is set to 1.

t

Figure 19 and Figure 20 show the frequency response of the sinc⁴

and sinc³filters, respectively, for an output data rate of 50 Hz.

0

At low update rates (<1 kHz), the noise-free resolution is

comparable for the two filter types. However, at the higher

update rates, the sinc⁴filter gives better noise free resolution.

The sinc⁴filter also leads to better 50 Hz and 60 Hz rejection.

While the notch positions are not affected by the order of the

filter, the higher order filter has wider notches, which leads to

better rejection in the band ( 1 Hz) around the notches. It also

gives better stop-band attenuation. The benefit of the sinc³filter

is its lower settling time for the same output data rate.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Chop Disabled

The output data rate (the rate at which conversions are available

on a single channel when the ADC is continuously converting)

is equal to

0

25

50

75

100

125

150

FREQUENCY (Hz)

Figure 19. Sinc⁴Filter Response (50 Hz Output Data Rate)

f

_ADC= f_CLK/(1024 × FS[9:0])

Rev. 0 | Page 26 of 40

AD7190

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

The value of FS[9:0] can be varied from 1 to 1023. This results

in an output data rate of 1.173 Hz to 1200 Hz for the sinc⁴filter

and 1.56 Hz to 1600 Hz for the sinc³filter. The settling time for

the sinc³or sinc⁴filter is equal to

t

_SETTLE= 2/f_ADC

Therefore, with chop enabled, the settling time is reduced for a

given output data rate compared to the chop disabled mode. For

either the sinc³or the sinc⁴filter, the cutoff frequency f_3dBis

equal to

f

_3dB= 0.24 × f_ADC

Figure 21 and Figure 22 show the filter response for the sinc⁴

and sinc³filters, respectively, when chop is enabled. As shown

in the plots, the stop-band attenuation is less compared with the

chop disabled modes.

0

25

50

75

100

125

150

FREQUENCY (Hz)

Figure 20. Sinc³Filter Response (50 Hz Output Data Rate)

As shown in the plots, the sinc⁴filter provides 50 Hz ( 1 Hz)

rejection in excess of 120 dB, assuming a stable master clock,

while the sinc³filter gives a rejection of 100 dB. The stop-band

attenuation is typically 53 dB for the sinc⁴filter but equal to

40 dB for the sinc³filter.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

The 3 dB frequency for the sinc⁴filter is equal to

f

_3dB= 0.23 × f_ADC

and for the sinc³filter is equal to

_3dB= 0.272 × f_ADC

f

Chop Enabled

With chop enabled, the analog input offset and offset drift are

minimized. When chop is enabled, the analog input pins are

continuously swapped. Therefore, with the analog input pins

connected in one direction, the settling time of the sinc filter is

allowed to elapse until a valid conversion is available. The analog

input pins are then inverted and another valid conversion is

obtained. Subsequent conversions are then averaged so that the

offset is minimized. This continuous swapping of the analog

input pins and the averaging of subsequent conversions means

that the offset drift is also minimized.

0

25

50

75

100

125

150

FREQUENCY (Hz)

Figure 21. Sinc⁴Filter Response (Output Data Rate = 12.5 Hz, Chop Enabled)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Chopping affects the output data rate and settling time of the

ADC. For the sinc⁴filter, the output data rate is equal to

f

_ADC= f_CLK/(4 x 1024 × FS[9:0])

For sinc³filter, the output data rate is equal to

_ADC= f_CLK/(3 x 1024 × FS[9:0])

where:

f

0

25

50

75

100

125

150

FREQUENCY (Hz)

Figure 22. Sinc³Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled)

f

_ADCis the output data rate.

f

_CLK= master clock (4.92 MHz nominal).

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the

mode register.

Rev. 0 | Page 27 of 40

AD7190

50 Hz/60 Hz Rejection

REJ60 bit at these output data rates further improves the

rejection at 60 Hz. Figure 25 and Figure 26 show the filter

response for both output data rates when REJ60 is set to 1.

0

Normal mode rejection is one of the main functions of the

digital filter. With chop disabled, 50 Hz rejection is obtained

when the output data rate is set to 50 Hz, whereas 60 Hz

rejection is achieved when the output data rate is set to 60 Hz.

Simul-taneous 50 Hz and 60 Hz rejection is obtained when the

output data rate is set to 10 Hz. Simultaneous 50 Hz/60 Hz

rejection can also be achieved using the REJ60 bit in the mode

register. When the output data rate is programmed to 50 Hz and

the REJ60 bit is set to 1, notches are placed at both 50 Hz and 60

Hz.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Figure 23 and Figure 24 show the frequency response of the

sinc⁴and sinc³filters, respectively, when the output data rate is

programmed to 50 Hz and REJ60 is set to 1.

0

25

50

75

100

125

150

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

FREQUENCY (Hz)

Figure 25. Sinc⁴Filter Response (12.5 Hz Output Data Rate,

Chop Enabled, REJ60 = 1)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

25

50

75

100

125

150

FREQUENCY (Hz)

Figure 23. Sinc⁴Filter Response (50 Hz Output Data Rate, REJ60 = 1)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

25

50

75

100

125

150

FREQUENCY (Hz)

Figure 26. Sinc³Filter Response (16.7 Hz Output Data Rate,

Chop Enabled, REJ60 = 1)

Channel Sequencer

The AD7190 includes a channel sequencer, which simplifies

communications with the device in multichannel applications.

Bis CH0 to Bit CH7 in the configuration register are used to

enable the required channels. In continuous conversion mode,

the ADC selects each of the enabled channels in sequence and

performs a conversion on the channel. The

pin goes low

RDY

0

25

50

75

100

125

150

when a valid conversion is available on each channel. When

several channels are enabled, the contents of the status register

should be attached to the 24-bit word so that the user can

identify the channel that corresponds to each conversion. To

attach the status register value to the conversion, Bit DAT_STA

in the mode register should be set to 1.

FREQUENCY (Hz)

Figure 24. Sinc³Filter Response (50 Hz Output Data Rate, REJ60 = 1)

Again, the sinc⁴filter provides better 50 Hz/60 Hz rejection

than the sinc³filter. In addition, better stop-band attenuation is

achieved with the sinc⁴filter.

When chop is enabled, lower output data rates must be used to

achieve 50 Hz and 60 Hz rejection. An output data rate of 12.5 Hz

gives simultaneous 50 Hz/60 Hz rejection when the sinc⁴filter is

selected, whereas an output data rate of 16.7 Hz gives simultaneous

50 Hz/ 60 Hz rejection when the sinc³filter is used. Setting the

When several channels are enabled, the ADC must allow the

complete settling time to generate a valid conversion each time

that the channel is changed. The AD7190 takes care of this:

when a channel is selected, the modulator and filter are reset

Rev. 0 | Page 28 of 40

AD7190

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

and the

pin is taken high. The AD7190 then allows the

RDY

complete settling time to generate the first conversion.

only goes low when a valid conversion is available. The

RDY

AD7190 then selects the next enabled channel and converts on

that channel. The user can then read the data register while the

ADC is performing the conversion on the next channel.

The frequency at which all enabled channels are converted is

equal to

t

_SETTLE× Number of Enabled Channels

For example, if the sinc⁴filter is selected, chop is disabled and

zero latency is disabled, conversions are available at 1/f_ADCwhen

converting on a single channel, where f_ADCis equal to the output

data rate. The settling time is equal to

0

50 100 150 200 250 300 350 400 450 500 550 600

FREQUENCY (Hz)

Figure 28. Sinc⁴Filter Response (50 Hz Output Data Rate, Zero Latency)

t

_SETTLE= 4/f_ADC

DIGITAL INTERFACE

The time required to sample N channels is

As indicated in the On-Chip Registers section, the programmable

functions of the AD7190 are controlled using a set of on-chip

registers. Data is written to these registers via the serial interface

of the part. Read access to the on-chip registers is also provided

by this interface. All communication with the part must start with

a write to the communications register. After power-on or reset,

the device expects a write to its communications register. The data

written to this register determines whether the next operation is a

read operation or a write operation and also determines which

register this read or write operation affects. Therefore, write

access to any of the other registers on the part begins with a write

operation to the communications register, followed by a write to

the selected register. A read operation from any other register

(except when continuous read mode is selected) starts with a write

to the communications register, followed by a read operation from

the selected register.

4/(f_ADC× N)

RDY

CONVERSIONS

CHANNEL A

CHANNEL B

CHANNEL C

1/f

ADC

Figure 27. Channel Sequencer

Zero Latency

Zero latency is enabled by setting the SINGLE bit in the mode

register to 1. With zero latency, the complete settling time is

allowed for each conversion. Therefore,

f

_ADC= 1/t_SETTLE

Zero latency means that the output data rate is constant

irrespective of the number of analog input channels enabled;

the user does not need to consider the effects of channel

changes on the output data rate. The disadvantages of zero

latency are the increased noise for a given output data rate

compared with the nonzero latency mode. For example, when

zero latency is not enabled, the AD7190 has a noise-free

resolution of 18.5 bits when the output data rate is 50 Hz and

the gain is set to 128. When zero latency is enabled, the ADC

has a resolution of 17.5 bits peak-to-peak when the output data

rate is 50 Hz. The filter response also changes. Figure 19 shows

the filter response for the sinc⁴filter when the output data rate

is 50 Hz (zero latency disabled). Figure 28 shows the filter

response when zero latency is enabled and the output data rate

is 50 Hz (sinc⁴filter); 50 Hz rejection is no longer achieved. The

ADC needs to operate with an output data rate of 12.5 Hz to

obtain 50 Hz rejection when zero latency is enabled. To obtain

simultaneous 50 Hz/60 Hz rejection, the REJ60 bit in the mode

register can be set when the output data rate is equal to 12.5 Hz.

The stop-band attenuation is considerably reduced also (3 dB

compared with 53 dB in the nonzero latency mode).

CS

The serial interface of the AD7190 consists of four signals:

,

RDY

DIN, SCLK, and DOUT/ . The DIN line is used to transfer

RDY

data into the on-chip registers, whereas DOUT/

is used for

accessing data from the on-chip registers. SCLK is the serial clock

input for the device, and all data transfers (either on DIN or

RDY

DOUT/ ) occur with respect to the SCLK signal.

RDY

The DOUT/

pin functions as a data ready signal also, the

line going low when a new data-word is available in the output

register. It is reset high when a read operation from the data

register is complete. It also goes high prior to the updating of the

data register to indicate when not to read from the device, to

ensure that a data read is not attempted while the register is being

CS

updated.

is used to select a device. It can be used to decode the

AD7190 in systems where several components are connected to

the serial bus.

Rev. 0 | Page 29 of 40

AD7190

Figure 3 and Figure 4 show timing diagrams for interfacing to the

The AD7190 can be configured to continuously convert or to

perform a single conversion. See Figure 29 through Figure 31.

CS

AD7190, with

being used to decode the part. Figure 3 shows

the timing for a read operation from the output shift register of

the AD7190, and Figure 4 shows the timing for a write operation

to the input shift register. It is possible to read the same word

Single Conversion Mode

In single conversion mode, the AD7190 is placed in power-

down mode after conversions. When a single conversion is

initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively,

in the mode register, the AD7190 powers up, performs a single

conversion, and then returns to power-down mode. The on-

chip oscillator requires 1 ms approximately to power up.

RDY

from the data register several times even though the DOUT/

line returns high after the first read operation. However, care

must be taken to ensure that the read operations have been com-

pleted before the next output update occurs. In continuous read

mode, the data register can be read only once.

RDY

DOUT/

When the data word has been read from the data register,

RDY CS RDY

remains high

goes low to indicate the completion of a conversion.

CS

The serial interface can operate in 3-wire mode by tying

low.

lines are used to

RDY

In this case, the SCLK, DIN, and DOUT/

communicate with the AD7190. The end of the conversion can be

RDY

DOUT/

goes high. If

is low, DOUT/

until another conversion is initiated and completed. The data

register can be read several times, if required, even when

monitored using the

interfacing to microcontrollers.

CS

bit or pin. This scheme is suitable for

RDY

DOUT/

has gone high.

If

is required as a decoding signal, it can be generated from a

If several channels are enabled, the ADC sequences through

the enabled channels and performs a conversion on each

port pin. For microcontroller interfaces, it is recommended that

SCLK idle high between data transfers.

channel. When a conversion is started, DOUT/

goes high

RDY

and remains high until a valid conversion is available. As soon

as the conversion is available, DOUT/ goes low. The ADC

CS

The AD7190 can be operated with

ization signal. This scheme is useful for DSP interfaces. In this

CS

used as a frame synchron-

RDY

case, the first bit (MSB) is effectively clocked out by because

normally occurs after the falling edge of SCLK in DSPs. The

then selects the next channel and begins a conversion. The user

can read the present conversion while the next conversion is

being performed. As soon as the next conversion is complete,

the data register is updated; therefore, the user has a limited

period in which to read the conversion. When the ADC has

performed a single conversion on each of the selected channels,

it returns to power-down mode.

CS

SCLK can continue to run between data transfers, provided the

timing numbers are obeyed.

The serial interface can be reset by writing a series of 1s to the

DIN input. If a Logic 1 is written to the AD7190 DIN line for at

least 40 serial clock cycles, the serial interface is reset. This ensures

that the interface can be reset to a known state if the interface gets

lost due to a software error or some glitch in the system. Reset

returns the interface to the state in which it is expecting a write to

the communications register. This operation resets the contents of

all registers to their power-on values. Following a reset, the user

should allow a period of 500 μs before addressing the serial

interface.

If the DAT_STA bit in the mode register is set to 1, the contents

of the status register are output along with the conversion each

time that the data read is performed. The four LSBs of the status

register indicate the channel to which the conversion corresponds.

CS

0x08

0x280060

0x58

DIN

DATA

DOUT/RDY

SCLK

Figure 29. Single Conversion

Rev. 0 | Page 30 of 40

AD7190

Continuous Conversion Mode

accessed at the completion of the next conversion or else the

new conversion word is lost.

Continuous conversion is the default power-up mode. The

RDY

AD7190 converts continuously, the

register going low each time a conversion is complete. If

RDY

bit in the status

When several channels are enabled, the ADC continuously

loops through the enabled channels, performing one conversion

on each channel per loop. The data register is updated as soon

CS

is

line also goes low when a conversion is

completed. To read a conversion, the user writes to the com-

munications register, indicating that the next operation is a read

of the data register. The digital conversion is placed on the

low, the DOUT/

RDY

as each conversion is available. The DOUT/

pin pulses low

each time a conversion is available. The user can then read the

conversion while the ADC converts on the next enabled channel.

RDY

ADC. DOUT/

DOUT/

pin as soon as SCLK pulses are applied to the

RDY

If the DAT_STA bit in the mode register is set to 1, the contents

of the status register are output along with the conversion each

time that the data read is performed. The status register indicates

the channel to which the conversion corresponds.

returns high when the conversion is read.

The user can read this register additional times, if required.

However, the user must ensure that the data register is not being

CS

0x58

DIN

DATA

DOUT/RDY

SCLK

Figure 30. Continuous Conversion

Rev. 0 | Page 31 of 40

AD7190

Continuous Read

conversion is complete and the new conversion is placed in

the output serial register.

Rather than write to the communications register each time a

conversion is complete to access the data, the AD7190 can be

configured so that the conversions are placed on the DOUT/

To exit the continuous read mode, the instruction 01011000

must be written to the communications register while the

RDY

line automatically. By writing 01011100 to the commun-

RDY

pin is low. While in the continuous read mode, the ADC

ications register, the user need only apply the appropriate

number of SCLK cycles to the ADC, and the conversion word

monitors activity on the DIN line so that it can receive the

instruction to exit the continuous read mode. Additionally, a

reset occurs if 40 consecutive 1s are seen on DIN. Therefore,

DIN should be held low in continuous read mode until an

instruction is to be written to the device.

RDY

is automatically placed on the DOUT/

line when a

conversion is complete. The ADC should be configured for

continuous conversion mode.

When several channels are enabled, the ADC continuously

steps through the enabled channels and performs one con-

version on each channel each time that it is selected. DOUT/

RDY

When DOUT/

sufficient SCLK cycles must be applied to the ADC; the data

RDY

goes low to indicate the end of a conversion,

conversion is then placed on the DOUT/

conversion is read, DOUT/

line. When the

returns high until the next

RDY

pulses low when a conversion is available. When the user

applies sufficient SCLK pulses, the data is automatically placed

RDY

conversion is available. In this mode, the data can be read only

once. Also, the user must ensure that the data-word is read

before the next conversion is complete. If the user has not read

the conversion before the completion of the next conversion,

or if insufficient serial clocks are applied to the AD7190 to

read the word, the serial output register is reset when the next

on the DOUT/

pin. If the DAT_STA bit in the mode

register is set to 1, the contents of the status register are output

along with the conversion. The status register indicates the

channel to which the conversion corresponds.

CS

0x5C

DIN

DATA

DOUT/RDY

SCLK

Figure 31. Continuous Read

Rev. 0 | Page 32 of 40

AD7190

CIRCUIT DESCRIPTION

ANALOG INPUT CHANNEL

The analog input range must be limited to (AV_DD− 1.25 V)/gain

because the PGA requires some headroom. Therefore, if V_REF

=

The AD7190 has two differential/four pseudo differential analog

input channels which can be buffered or unbuffered. In buffered

mode (the BUF bit in the configuration register is set to 1), the

input channel feeds into a high impedance input stage of the

buffer amplifier. Therefore, the input can tolerate significant

source impedances and is tailored for direct connection to

external resistive-type sensors such as strain gauges or resistance

temperature detectors (RTDs).

AV_DD= 5 V, the maximum analog input that can be applied to

the AD7190 is 0 to 3.75 V/gain in unipolar mode or 3.75 V/

gain in bipolar mode.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7190 can accept either unipolar or

bipolar input voltage ranges. A bipolar input range does not

imply that the part can tolerate negative voltages with respect to

system GND. Unipolar and bipolar signals on the AIN(+) input

are referenced to the voltage on the AIN(−) input. For example,

if AIN(−) is 2.5 V and the ADC is configured for unipolar mode

with a gain of 1, the input voltage range on the AIN(+) pin is

2.5 V to 5 V when a 2.5 V reference is used.

When BUF = 0, the part is operated in unbuffered mode. This

results in a higher analog input current. Note that this unbuffered

input path provides a dynamic load to the driving source.

Therefore, resistor/capacitor combinations on the input pins

can cause gain errors, depending on the output impedance of

the source that is driving the ADC input. Table 22 shows the

allowable external resistance/capacitance values for unbuffered

mode at a gain of 1 such that no gain error at the 20-bit level is

introduced.

If the ADC is configured for bipolar mode, the analog input

range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar

B

option is chosen by programming the U/ bit in the configur-

ation register.

Table 22. External R-C Combination for No 20-Bit Gain Error

DATA OUTPUT CODING

C (pF)

±0

R (Ω)

1.4 k

8±0

300

230

30

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage resulting in a code of 00...00, a midscale voltage resulting

in a code of 100...000, and a full-scale input voltage resulting in

a code of 111...111. The output code for any analog input voltage

can be represented as

100

±00

1000

±000

Code = (2^N× AIN × gain)/V_REF

The absolute input voltage range in buffered mode is restricted

to a range between AGND + 250 mV and AV_DD– 250 mV. Care

must be taken in setting up the common-mode voltage so that

these limits are not exceeded. Otherwise, there is degradation in

linearity and noise performance.

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000...000, a zero differential input voltage resulting

in a code of 100...000, and a positive full-scale input voltage

resulting in a code of 111...111. The output code for any analog

input voltage can be represented as

The absolute input voltage in unbuffered mode includes the

range between AGND – 50 mV and AV_DD+ 50 mV. The

negative absolute input voltage limit does allow the possibility

of monitoring small true bipolar signals with respect to GND.

Code = 2^{N – 1}× [(AIN × gain/V_REF) + 1]

where AIN is the analog input voltage, gain is the PGA setting

(1 to 128), and N = 24.

PGA

When the gain stage is enabled, the output from the buffer is

applied to the input of the programmable gain array (PGA).

The presence of the PGA means that signals of small amplitude

can be gained within the AD7190 while still maintaining excel-

lent noise performance. For example, when the gain is set to

128, the rms noise is 8.5 nV, typically, when the output data rate

is 4.7 Hz, which is equivalent to 23 bits of effective resolution or

20.5 bits of noise-free resolution.

CLOCK

The AD7190 includes an internal 4.92 MHz clock on-chip. This

internal clock has a tolerance of 4%. Either the internal clock

or an external crystal/clock can be used as the clock source to

the AD7190. The clock source is selected using the CLK1 and

CLK0 bits in the mode register. When an external crystal is

used, it must be connected across the MCLK1 and MCLK2

pins. The crystal manufacturer recommends the load capaci-

tances required for the crystal. The MCLK1 and MCLK2 pins of

the AD7190 have a capacitance of 15 pF, typically. If an external

clock source is used, the clock source must be connected to the

MCLK2 pin and the MCLK1 pin must be left floating.

The AD7190 can be programmed to have a gain of 1, 8, 16, 32,

64, and 128 using Bit G2 to Bit G0 in the configuration register.

Therefore, with an external 2.5 V reference, the unipolar ranges

are from 0 mV to 19.53 mV to 0 V to 2.5 V, and the bipolar

ranges are from 19.53 mV to 2.5 V.

Rev. 0 | Page 33 of 40

AD7190

The internal clock can also be made available at the MCLK2

pin. This is useful when several ADCs are used in an application

and the devices need to be synchronized. The internal clock

from one device can be used as the clock source for all ADCs

in the system. Using a common clock, the devices can be syn-

chronized by applying a common reset to all devices, or the

Recommended 2.5 V reference voltage sources for the AD7190

include the ADR421 and ADR431, which are low noise

references. Also note that the reference inputs provide a high

impedance, dynamic load. Because the input impedance of each

reference input is dynamic, resistor/capacitor combinations on

these inputs can cause dc gain errors, depending on the output

impedance of the source driving the reference inputs.

pin can be pulsed.

SYNC

Reference voltage sources like those recommended above (for

example, ADR431) typically have low output impedances and

are, therefore, tolerant to having decoupling capacitors on

REFINx(+) without introducing gain errors in the system.

Deriving the reference input voltage across an external resistor

means that the reference input sees a significant external source

impedance. External decoupling on the REFINx pins is not

recommended in this type of circuit configuration.

BURNOUT CURRENTS

The AD7190 contains two 500 nA constant current generators,

one sourcing current from AV_DDto AIN(+) and one sinking

current from AIN(−) to GND. The currents are switched to the

selected analog input pair. Both currents are either on or off,

depending on the burnout current enable (burn) bit in the

configuration register. These currents can be used to verify that

an external transducer remains operational before attempting to

take measurements on that channel. After the burnout currents

are turned on, they flow in the external transducer circuit, and a

measurement of the input voltage on the analog input channel

can be taken. If the resultant voltage measured is full scale, the

user needs to verify why this is the case. A full-scale reading

could mean that the front-end sensor is open circuit. It could

also mean that the front-end sensor is overloaded and is

justified in outputting full scale, or the reference may be absent

and the NOREF bit in the status register is set, thus clamping

the data to all 1s.

REFERENCE DETECT

The AD7190 includes on-chip circuitry to detect whether the

part has a valid reference for conversions or calibrations. This

feature is enabled when the REFDET bit in the configuration

register is set to 1. If the voltage between the selected REFINx(+)

and REFINx(–) pins goes below 0.3 V or either the REFINx(+)

or REFINx(–) input is open circuit, the AD7190 detects that it

no longer has a valid reference. In this case, the NOREF bit of

the status register is set to 1. If the AD7190 is performing normal

conversions and the NOREF bit becomes active, the conversion

results is all 1s. Therefore, it is not necessary to continuously

monitor the status of the NOREF bit when performing

conversions. It is only necessary to verify its status if the con-

version result read from the ADC data register is all 1s. If the

AD7190 is performing either an offset or full-scale calibration

and the NOREF bit becomes active, the updating of the

respective calibration registers is inhibited to avoid loading

incorrect coefficients to these registers, and the ERR bit in the

status register is set. If the user is concerned about verifying

that a valid reference is in place every time a calibration is

performed, the status of the ERR bit should be checked at the

end of the calibration cycle.

When reading all 1s from the output, the user needs to check

these three cases before making a judgment. If the voltage

measured is 0 V, it may indicate that the transducer has short

circuited. The current sources work over the normal absolute

input voltage range specifications when the analog inputs are

buffered and chop is disabled.

REFERENCE

The ADC has a fully differential input capability for the refer-

ence channel. In addition, the user has the option of selecting

one of two external reference options (REFIN1(x) or REFIN2(x)).

The reference source for the AD7190 is selected using the

REFSEL bit in the configuration register. The REFIN2(x) pins

are dual purpose: they can function as two general-purpose

output pins or as reference pins. When the REFSEL bit is set

to 1, these pins automatically function as reference pins.

RESET

The circuitry and serial interface of the AD7190 can be reset by

writing consecutive 1s to the device; 40 consecutive 1s are

required to perform the reset. This resets the logic, the digital

filter, and the analog modulator, whereas all on-chip registers

are reset to their default values. A reset is automatically

performed on power-up. When a reset is initiated, the user

must allow a period of 500 μs before accessing any of the on-

chip registers. A reset is useful if the serial interface becomes

asynchronous due to noise on the SCLK line.

The common-mode range for these differential inputs is from

GND to AV_DD. The reference input is unbuffered; therefore,

excessive R-C source impedances introduce gain errors. The

reference voltage REFIN (REFINx(+) − REFINx(−)) is AV_DD

nominal, but the AD7190 is functional with reference voltages

from 1 V to AV_DD. In applications where the excitation (voltage

or current) for the transducer on the analog input also drives

the reference voltage for the part, the effect of the low frequency

noise in the excitation source is removed because the application is

ratiometric. If the AD7190 is used in a nonratiometric applica-

tion, use a low noise reference.

Rev. 0 | Page 34 of 40

AD7190

Temp (K) = (Conversion – 0x800000)/2815 K

Temp (°C) = Temp (K) – 273

SYSTEM SYNCHRONIZATION

SYNC

The

input allows the user to reset the modulator and the

digital filter without affecting any of the setup conditions on the

part. This allows the user to start gathering samples of the analog

input from a known point in time, that is, the rising edge of

Following the one point calibration, the internal temperature

sensor has an accuracy of 2 °C, typically.

BRIDGE POWER-DOWN SWITCH

SYNC SYNC

.

needs to be taken low for four master clock cycles

In bridge applications such as strain gauges and load cells, the

bridge itself consumes the majority of the current in the system.

For example, a 350 Ω load cell requires 15 mA of current when

excited with a 5 V supply. To minimize the current consumption

of the system, the bridge can be disconnected (when it is not

being used) using the bridge power-down switch. Figure 18

shows how the bridge power-down switch is used. The switch

can withstand 30 mA of continuous current, and it has an on

resistance of 10 Ω maximum.

to implement the synchronization function.

If multiple AD7190 devices are operated from a common master

clock, they can be synchronized so that their data registers are

SYNC

updated simultaneously. A falling edge on the

the digital filter and the analog modulator and places the AD7190

SYNC

pin resets

into a consistent, known state. While the

AD7190 is maintained in this state. On the

pin is low, the

SYNC

rising edge,

the modulator and filter are taken out of this reset state and, on

the next clock edge, the part starts to gather input samples again.

In a system using multiple AD7190 devices, a common signal to

LOGIC OUTPUTS

The AD7190 has four general-purpose digital outputs, P0, P1,

P2, and P3. These are enabled using the GP32EN and GP10EN

bits in the GPOCON register. The pins can be pulled high or

low using the P0DAT to P3DAT bits in the GPOCON register;

that is, the value at the pin is determined by the setting of the

P0DAT to P3DAT bits. The logic levels for these pins are

determined by AV_DDrather than by DV_DD. When the GPOCON

register is read, the bits P0DAT to P3DAT reflect the actual

value at the pins. This is useful for short-circuit detection.

SYNC

their

pins synchronizes their operation. This is normally

done after each AD7190 has performed its own calibration or

has had calibration coefficients loaded into its calibration

registers. The conversions from the AD7190s are then

synchronized.

The part is taken out of reset on the master clock falling edge

following the

multiple devices are being synchronized, the

be taken high on the master clock rising edge to ensure that all

devices begin sampling on the master clock falling edge. If the

SYNC

low to high transition. Therefore, when

SYNC

pin should

These pins can be used to drive external circuitry, for example,

an external multiplexer. If an external multiplexer is used to

increase the channel count, the multiplexer logic pins can be

controlled via the AD7190 general-purpose output pins. The

general-purpose output pins can be used to select the active

multiplexer pin. Because the operation of the multiplexer is

independent of the AD7190, the AD7190 modulator and filter

SYNC

pin is not taken high in sufficient time, it is possible to

have a difference of one master clock cycle between the devices;

that is, the instant at which conversions are available differs

from part to part by a maximum of one master clock cycle.

SYNC

The

In this mode, the rising edge of

RDY

pin can also be used as a start conversion command.

SYNC

starts conversion, and the

indicates when the conversion is complete.

SYNC

should be reset using the

pin each time that the multi-

falling edge of

plexer channel is changed.

The disadvantage of this scheme is that the settling time of the

filter has to be allowed for each data register update. This means

that the rate at which the data register is updated is reduced. For

example, if the ADC is configured to use the sinc⁴filter, zero

latency is disabled and chop is disabled, the data register update

takes four times longer.

ENABLE PARITY

The AD7190 also has a parity check function on-chip that

detects 1-bit errors in the serial communications between the

ADC and the microprocessor. When the ENPAR bit in the

mode register is set to 1, parity is enabled. The contents of the

status register must be transmitted along with each 24-bit

conversion when the parity function is enabled. To append the

contents of the status register to each conversion read, the

DAT_STA bit in the mode register should be set to 1. For each

conversion read, the parity bit in the status register is

programmed so that the overall number of 1s transmitted in the

24-bit data-word is even. Therefore, for example, if the 24-bit

conversion contains eleven 1s (binary format), the parity bit is

set to 1 so that the total number of 1s in the serial transmission is

even. If the microprocessor receives an odd number of 1s, it

knows that the data received has been corrupted.

TEMPERATURE SENSOR

Embedded in the AD7190 is a temperature sensor. This is

selected using the CH2 bit in the configuration register. When

the CH2 bit is set to 1, the temperature sensor is enabled. When

the temperature sensor is selected and bipolar mode is selected,

the device should return a code of 0x800000 when the temper-

ature is 0 K. A one-point calibration is needed to get the opti-

mum performance from the sensor. Therefore, a conversion at a

known temperature should be recorded. Using this point along

with the 0 K point, the gain error can be calculated. The

sensitivity is 2815 codes/°C, typically. The equation for the

temperature sensor is

Rev. 0 | Page 3± of 40

AD7190

The parity function only detects 1-bit errors. For example, two

bits of corrupt data can result in the microprocessor receiving an

even number of 1s. Therefore, an error condition is not detected.

A system full-scale calibration requires a time of t_SETTLE. With

chop disabled, the zero-scale calibration (internal or system

zero-scale) should be performed before the system full-scale

calibration is initiated.

CALIBRATION

An internal zero-scale calibration, system zero-scale calibration

and system full-scale calibration can be performed at any output

data rate. An internal full-scale calibration can be performed at

any output data rate for which the filter word FS[9:0] is divisible

by 16, FS[9:0] being the decimal equivalent of the 10-bit word

written to Bit FS9 to Bit FS0 in the mode register. Therefore,

internal full-scale calibrations can be performed at output data

rates such as 300 Hz, 150 Hz, and 100 Hz. Using these lower

output data rates results in better calibration accuracy.

The AD7190 provides four calibration modes that can be pro-

grammed via the mode bits in the mode register. These modes

are internal zero-scale calibration, internal full-scale calibration,

system zero-scale calibration, and system full-scale calibration.

A calibration can be performed at any time by setting the MD2

to MD0 bits in the mode register appropriately. A calibration

should be performed when the gain is changed. After each

conversion, the ADC conversion result is scaled using the ADC

calibration registers before being written to the data register.

The offset calibration coefficient is subtracted from the result

prior to multiplication by the full-scale coefficient.

The gain error of the AD7190 is factory calibrated at a gain of 1

with a 5 V power supply at ambient temperature. Following this

calibration, the gain error is 0.001%, typically, at 5 V. The offset

error is, typically, 100 μV/gain. If the gain is changed, it is

advisable to perform a calibration. A zero-scale calibration (an

internal zero-scale calibration or system zero-scale calibration)

reduces the offset error to the order of the noise. Table 23 shows

the uncalibrated gain error for the different gain settings. An

internal full-scale calibration reduces the gain error to 0.001%,

typically, when the gain is equal to 1. For higher gains, the gain

error post internal full-scale calibration is 0.0075%, typically.

A system full-sale calibration reduces the gain error to the order

of the noise.

To start a calibration, write the relevant value to the MD2 to

RDY

MD0 bits. The DOUT/

pin and the

bit in the status

register go high when the calibration is initiated. When the

calibration is complete, the contents of the corresponding

RDY

calibration registers are updated, the

bit in the status

RDY

CS

is low),

register is reset, the DOUT/

pin returns low (if

and the AD7190 reverts to idle mode.

During an internal zero-scale or full-scale calibration, the res-

pective zero input and full-scale input are automatically connected

internally to the ADC input pins. A system calibration, however,

expects the system zero-scale and system full-scale voltages to

be applied to the ADC pins before initiating the calibration

mode. In this way, external ADC errors are removed.

Table 23. Precalibration Gain Error vs. Gain

Gain

Precalibration Gain Error (%)

8

16

32

64

−0.11

−0.20

−0.23

−0.29

−0.39

From an operational point of view, treat a calibration like

another ADC conversion. A zero-scale calibration, if required,

must always be performed before a full-scale calibration. Set the

RDY

system software to monitor the

bit in the status register or

128

RDY

the DOUT/

pin to determine the end of calibration via a

The AD7190 gives the user access to the on-chip calibration

registers, allowing the microprocessor to read the calibration

coefficients of the device and also to write its own calibration

coefficients from prestored values in the EEPROM. A read of

the registers can be performed at any time. However, the ADC

must be placed in power-down or idle mode when writing to

the registers. The values in the calibration registers are 24-bits

wide. The span and offset of the part can also be manipulated

using the registers.

polling sequence or an interrupt-driven routine.

With chop disabled, both an internal zero-scale calibration and

a system zero-scale calibration require a time equal to the

settling time, t_SETTLE, (4/f_ADCfor the sinc⁴filter and 3/f_ADCfor the

sinc³filter).

With chop enabled, an internal zero-scale calibration is not

needed because the ADC itself minimizes the offset continuously.

However, if an internal zero-scale calibration is performed, the

settling time, t_SETTLE,(2/f_ADC) is required to perform the calibra-

tion. Similarly, a system zero-scale calibration requires a time of

GROUNDING AND LAYOUT

Because the analog inputs and reference inputs are differential,

most of the voltages in the analog modulator are common-

mode voltages. The high common-mode rejection of the part

removes common-mode noise on these inputs. The analog and

digital supplies to the AD7190 are independent and separately

pinned out to minimize coupling between the analog and

digital sections of the device. The digital filter provides

t

_SETTLEto complete.

To perform an internal full-scale calibration, a full-scale input

voltage is automatically connected to the selected analog input

for this calibration. For a gain of 1, the time required for an

internal full-scale calibration is equal to t_SETTLE. For higher gains,

the internal full-scale calibration requires a time of 2 × t_SETTLE

A full-scale calibration is required each time the gain of a

channel is changed to minimize the full-scale error.

.

rejection of broadband noise on the power supplies, except at

Rev. 0 | Page 36 of 40

AD7190

integer multiples of the modulator sampling frequency.

Connect an R-C filter to each analog input pin to provide

rejection at the modulator sampling frequency. A 100 ꢀ

resistor in series with each analog input (a 0.1 ꢁF capacitor

from AINx(+) to AINx(−) along with a 0.01 ꢁF capacitor from

each analog input to AGND) is advised. The digital filter also

removes noise from the analog and reference inputs provided

these noise sources do not saturate the analog modulator. As a

result, the AD7190 is more immune to noise interference than a

conventional high resolution converter. However, because the

resolution of the AD7190 is so high and the noise levels from

the converter so low, care must be taken with regard to grounding

and layout.

In any layout, the user must keep in mind the flow of currents

in the system, ensuring that the paths for all currents are as close

as possible to the paths the currents took to reach their destin-

ations. Avoid forcing digital currents to flow through the AGND.

Avoid running digital lines under the device because this

couples noise onto the die, and allow the analog ground plane

to run under the AD7190 to prevent noise coupling. The power

supply lines to the AD7190 must use as wide a trace as possible

to provide low impedance paths and reduce the effects of

glitches on the power supply line. Shield fast switching signals

like clocks with digital ground to prevent radiating noise to

other sections of the board, and never run clock signals near the

analog inputs. Avoid crossover of digital and analog signals.

Run traces on opposite sides of the board at right angles to each

other. This reduces the effects of feedthrough through the

board. A microstrip technique is by far the best but is not

always possible with a double-sided board. In this technique,

the component side of the board is dedicated to ground planes,

whereas signals are placed on the solder side.

The printed circuit board (PCB) that houses the ADC must be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be easily separated. A minimum

etch technique is generally best for ground planes because it

gives the best shielding.

Although the AD7190 has separate pins for analog and digital

ground, the AGND and DGND pins are tied together internally

via the substrate. Therefore, the user must not tie these two

pins to separate ground planes unless the ground planes are

connected together near the AD7190.

Good decoupling is important when using high resolution ADCs.

Decouple all analog supplies with 10 ꢁF tantalum in parallel with

0.1 ꢁF capacitors to AGND. To achieve the best from these

decoupling components, place them as close as possible to the

device, ideally right up against the device. Decouple all logic chips

with 0.1 ꢁF ceramic capacitors to DGND. In systems in which a

common supply voltage is used to drive both the AV^DDand DVDD

of the AD7190, it is recommended that the system AVDD supply

be used. For this supply, place the recommended analog supply

decoupling capacitors between the AV^DDpin of the AD7190

and AGND and the recommended digital supply decoupling

capacitor between the DV^DDpin of the AD7190 and DGND.

In systems in which the AGND and DGND are connected

somewhere else in the system (that is, the power supply of the

system), they should not be connected again at the AD7190

because a ground loop results. In these situations, it is

recommended that ground pins of the AD7190 be tied to the

AGND plane.

Rev. 0 | Page 37 of 40

AD7190

APPLICATIONS INFORMATION

The AD7190 provides a low-cost, high resolution analog-to-

digital function. Because the analog-to-digital function is

provided by a ∑-Δ architecture, it makes the part more

immune to noisy environments, making it ideal for use in

sensor measurement and industrial and process control

applications.

bridge power-down switch is connected in series with the cold

side of the bridge. In normal operation, the switch is closed and

measurements can be taken. In applications in which current

consumption is being minimized, the AD7190 can be placed in

standby mode, thus significantly reducing the power consumed

in the application. In addition, the bridge power-down switch

can be opened while in standby mode, thus avoiding unnecessary

power consumption by the front-end transducer. When the part

is taken out of standby mode and the bridge power-down switch

is closed, the user should ensure that the front-end circuitry is

fully settled before attempting a read from the AD7190.

WEIGH SCALES

Figure 32 shows the AD7190 being used in a weigh scale

application. The load cell is arranged in a bridge network and

gives a differential output voltage between its OUT+ and OUT–

terminals. Assuming a 5 V excitation voltage, the full-scale

output range from the transducer is 10 mV when the sensitivity

is 2 mV/V. The excitation voltage for the bridge can be used to

directly provide the reference for the ADC because the reference

input range includes the supply voltage.

For simplicity, external filters are not included in Figure 32.

However, an R-C antialias filter should be included on each

analog input. This is required because the on-chip digital filter

does not provide any rejection around the modulator sampling

frequency or multiples of this frequency. Suitable values are a

100 Ω resistor in series with each analog input, a 0.1 ꢁF capa-

citor from AINx(+) to AINx(−), and 0.01 ꢁF capacitors from

AINx(+)/AINx(−) to AGND.

A second advantage of using the AD7190 in transducer-based

applications is that the bridge power-down switch can be fully

utilized to minimize the power consumption of the system. The

5V

AGND AV

DV

DGND

DD

REFIN1(+)

REFERENCE

DETECT

IN+

IN–

AV

DD

AIN1

AIN2

AIN3

AIN4

AINCOM

OUT+

OUT–

DOUT/RDY

SERIAL

INTERFACE

AND

CONTROL

LOGIC

MUX

DIN

Σ-Δ

ADC

PGA

SCLK

CS

SYNC

AGND

TEMP

SENSOR

P3

P2

REFIN1(–)

BPDSW

CLOCK

CIRCUITRY

AD7190

AGND

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

Figure 32. Typical Application (Weigh Scale)

Rev. 0 | Page 38 of 40

AD7190

OUTLINE DIMENSIONS

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8°

0°

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Models

Temperature Range

Package Description

24-Lead TSSOP

Package Option

RU-24

AD7190BRUZ¹

–40°C to +10±°C

AD7190BRUZ-REEL¹

¹Z = RoHS Compliant Part.

Rev. 0 | Page 39 of 40

AD7190

NOTES

registered trademarks are the property of their respective owners.

D07640-0-10/08(0)

Rev. 0 | Page 40 of 40


型号：	AD7190BRUZ-REEL
厂家：	ADI
描述：	4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA 4.8千赫兹超低噪声， 24位Σ- Δ型ADC PGA 转换器模数转换器光电二极管
文件：	总40页 (文件大小：744K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7190BRUZ-REEL [ADI]

相关型号：

AD7190WBRUZ

AD7190WBRUZ-RL

AD7190_08

AD7191

AD7191BRUZ

AD7191BRUZ

AD7191BRUZ-REEL

AD7191BRUZ-REEL

AD7192

AD7192BRUZ

AD7192BRUZ-REEL

AD7193