AD721JP [ADI]
RGB to NTSC/PAL Encoders; RGB转NTSC / PAL编码器
| 型号： | AD721JP |
| 厂家： | 
ADI |
| 描述： | RGB to NTSC/PAL Encoders |
| 文件： | 总8页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
RGB to NTSC/PAL Encoders
AD720/AD721
FEATURES
Com posite Video Output
(subcarrier amplitude and phase) signals in accordance with
either NT SC or PAL standards. T hese two outputs are also
combined to provide a composite video output. All three out-
puts are available separately at voltages of twice the standard
signal levels as required for driving 75 Ω reverse terminated
cables. T he AD721 also features a bypass mode, in which the
RGB inputs may bypass the encoder section of the IC via three
gain-of-two amplifiers suitable for driving 75 Ω reverse termi-
nated cables.
Chrom inance and Lum inance (S-Video) Outputs
No External Filters or Delay Lines Required
Drives 75 Ω Reverse-Term inated Loads
Com pact 28-Pin PLCC
Logic Selectable NTSC or PAL Encoding Modes
Autom atically Selects Proper Chrom inance Filter
Cutoff Frequency for Encoding Standard
Logic Selectable Encode or Pow er-Dow n Mode (AD720
Only)
T he AD720 and AD721 provide a complete, fully calibrated
function, requiring only termination resistors, bypass capacitors,
a clock input at four times the subcarrier frequency, and a com-
posite sync pulse. T here are two control inputs: one input
selects the T V standard (NT SC/PAL) and the other (ENCD)
powers down most sections of the chip when the encoding func-
tion is not in use (AD720) or activates the triple bypass buffer to
drive the RGB signals when RGB encoding is not required
(AD721). All logical inputs are CMOS compatible. T he chip
operates from ±5 V supplies.
Logic Selectable Encode or Bypass Mode (AD721 Only)
Low Pow er: 200 m W typical
APPLICATIONS
RGB to NTSC or PAL Encoding
Drive RGB Signals into 75 Ω Load (AD721 Only)
P RO D UCT D ESCRIP TIO N
T he AD720 and AD721 RGB to NT SC/PAL Encoders convert
red, green and blue color component signals into their corre-
sponding luminance (baseband amplitude) and chrominance
(continued on page 5)
FUNCTIO NAL BLO CK D IAGRAM
NTSC/PAL
ASNC
DELAYED C-SYNC
C-SYNC
DELAY
POWER AND GROUNDS
SYNC
DECODER
NTSC/PAL
LOGIC
+5V
+5V
C-SYNC
BURST
ANALOG
ANALOG ONLY
ANALOG
LOGIC
–5V
AGND
DGND
±180
°
SC 90
°
/270
NTSC/PAL
CLOCK
AT 8FSC
°
(PAL ONLY)
SC 90
°
4FSC
ENCD
QUADRATURE
DECODER
SC 0
Y
°
BURST
5MHz
DC
LUMINANCE OUTPUT*
–0.572V TO 1.43V NTSC
–0.6V TO 1.4V PAL
5MHz
4-POLE LP
SAMPLED-
DATA
DELAY LINE
2-POLE
LP POST-
FILTER
RESTORE
AND C-SYNC
INSERTION
X2
RED
PRE-FILTER
COMPOSITE OUTPUT*
–0.572V TO 2V NTSC
–0.6V TO 2V PAL
RGB-TO-YUV
ENCODING
MATRIX
1.2MHz
4-POLE
LPF
NTSC/PAL
∑
X2
X2
U
V
GREEN
BLUE
3.6MHz (NTSC)
4.4MHz (PAL)
3-POLE LPF
BALANCED
MODULATORS
CHROMINANCE OUTPUT*
572mVp-p NTSC
600mVp-p PAL
∑
1.2MHz
4-POLE
LPF
*NOTE:
ROUT
1.5Vp-p
X2
X2
X2
THE LUMINANCE, COMPOSITE, AND CHROMINANCE
OUTPUTS ARE AT TWICE NORMAL LEVELS FOR
DRIVING 75Ω REVERSE-TERMINATED LINES.
AD721
(ONLY)
GOUT
1.5Vp-p
BOUT
1.5Vp-p
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
(T = +25°C and supplies = ±5 V unless otherwise noted)
AD720/AD721–SPECIFICATIONS
A
P aram eter
Conditions
Min
Typ Max
Unit
SIGNAL INPUT S (RDIN, GRIN, BLIN)
Input Amplitude
NT SC
PAL
714
700
mV
mV
Input Resistances1
RDIN with Respect to AGND
GRIN with Respect to AGND
BLIN with Respect to AGND
Input Capacitance
2.3
4.2
4.2
5
kΩ
kΩ
kΩ
pF
LOGIC INPUT S (C-SYNC, 4FSC, ENCD, NT SC)
Logic LO Input Voltage
1
V
Logic HI Input Voltage
4
V
Logic LO Input Current (DC)
Logic HI Input Current (DC)
<1
<1
µA
µA
BYPASS AMPLIFIERS (AD721 Only)
Gain Error
Nominal Gain of ×22
–5
+5
%
Small Signal –3 dB Bandwidth
Output Offset Voltage (Active State)
Output Voltage (Inactive State)
100
–50
–50
MHz
mV
mV
+50
+50
VIDEO OUT PUT S3 (LUMA, CRMA, CMPS)
Luminance (LUMA) Output
Bandwidth
Gain Error
5
±1
MHz
%
–5
+5
Linearity
Sync Level
±0.1
286
300
%
mV
mV
NT SC
PAL
252
320
Chrominance (CRMA) Output
Bandwidth
NT SC
PAL
NT SC
PAL
3.6
4.4
286
300
±5
MHz
MHz
mV p-p
mV p-p
%
Color Burst Amplitude
257
–15
315
+15
Absolute Gain Error
Absolute Phase Error
Chroma/Luma T ime Alignment4
Composite Output
±3
–170
Degrees
ns
NT SC
Absolute Gain Error
Differential Gain
Differential Phase
Output Offset Voltage
Chroma Feedthrough
–5
±1
0.1
0.1
50
+5
%
%
With Respect to Chroma Channel
With Respect to Chroma Channel
Chroma, Luma, or Composite Outputs
Monochrome Input
Degrees
mV
mV p-p
100
55
20
POWER SUPPLIES (APOS, DPOS, VNEG)
Recommended Supply Range
Full Output Current5
Dual Supply
–5 V Supply
+5 V Supply
–5 V Supply
+5 V Supply
–5 V Supply
+5 V Supply
±4.75
±5.25
V
35
67
20
20
14
14
mA
mA
mA
mA
mA
mA
Zero Signal Quiescent Current
10
10
35
35
20
20
Bypass Mode Quiescent Current
(AD721 Only)
NOT ES
1Input scaling resistors provide best scaling accuracy when source resistance is 37.5 Ω (75 Ω reverse-terminated input).
2Required for driving a 75 Ω double reverse terminated load.
3All outputs are measured at a reverse-terminated load; voltages at IC pins are twice those specified here.
4T his is a predistortion (per FCC specifications) that compensates for the chroma/luma delay in the low-pass filter that separates the luminance and chrominance
signals in a television receiver.
5CRMA, LUMA, and CMPS outputs are all connected to 75 Ω reverse-terminated loads; full-white signal for entire field.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
–2–
REV. 0
AD720/AD721
ABSO LUTE MAXIMUM RATINGS*
P IN D ESCRIP TIO NS
Supply Voltage ±VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 600 mW
Operating T emperature Range . . . . . . . . . . . . . . 0°C to +70°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature, Soldering 60 sec . . . . . . . . . . . . . . +300°C
NOT E
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended rating conditions for extended periods
may affect device reliability.
P in Mnem onic* D escription*
1
2
3
4
5
(NC) GOUT (No Connection) Green Bypass Buffer
(NC) APOS
(NC) ROUT
AGND
(No Connection) Analog Positive Supply; +5 V ± 5%
(No Connection) Red Bypass Buffer
Analog Ground Connection
ENCD
A Logical High Enables the NT SC/PAL Encode
Mode (A Logical Low Powers Down the Chip)
A Logical Low Enables the RGB Bypass Mode
Red Component Video Input
0 mV to 714 mV for NT SC
6
RDIN
0 mV to 700 mV for PAL
T hermal characteristics: 28-pin plastic package: θJA = 100°C.
7
8
AGND
GRIN
Analog Ground Connection
Green Component Video Input
0 mV to 714 mV for NT SC
O RD ERING GUID E
0 mV to 700 mV for PAL
9
AGND
Analog Ground Connection
Blue Component Video Input
0 mV to 714 mV for NT SC
Tem perature
Range
P ackage
O ption
10 BLIN
Model
P ackage
0 mV to 700 mV for PAL
AD720JP
AD721JP
0°C to +70°C
0°C to +70°C
28-Pin PLCC
28-Pin PLCC
P-28A
P-28A
11 ST ND
A Logical High Input Selects NT SC Encoding
A Logical Low Input Selects PAL Encoding
CMOS Logic Levels
12 AGND
13 CRMA
Analog Ground Connection
P IN CO NNECTIO NS
28-Lead P lastic Leaded Chip Car r ier (P LCC) P ackage
P -28A
Chrominance Output; Subcarrier Only**
572 mV Peak-to-Peak for NT SC
600 mV Peak-to-Peak for PAL
Analog Positive Supply; +5 V ± 5%
Composite Video Output**
14 APOS
15 CMPS
–572 mV to 2 V for NT SC
–600 mV to 2 V for PAL
16 APOS
17 LUMA
Analog Positive Supply; +5 V ± 5%
Luminance Plus SYNC Output**
–572 mV to 1.43 V for NT SC
–600 mV to 1.4 V for PAL
System Negative Supply; –5 V ± 5%
Digital Ground Connection
Clock Input at Four T imes the Subcarrier Frequency
14.318 180 MHz for NT SC
17.734 480 MHz for PAL
1
26
4
3
2
28 27
5
6
25
24
23
22
21
20
19
DGND
SYNC
DPOS
ASNC
DPOS
4FSC
ENCD
RDIN
18 VNEG
19 DGND
20 4FSC
7
AGND
GRIN
AGND
BLIN
AD720/AD721
RGB TO NTSC/PAL
ENCODER
8
CMOS Logic Levels
9
21 DPOS
22 ASNC
Digital Positive Supply; +5 V ± 5%
A Logical High Input Resets the Subcarrier Phase
Every Frame
10
STND 11
DGND
A Logical Low Input Resets the Subcarrier Phase
Every Fourth Frame
CMOS Logic Levels
12
13 14 15 16 17 18
23 DPOS
24 SYNC
Digital Positive Supply; +5 V ± 5%
Input for Composite T elevision
Synchronization Pulses
NOTE:
CONNECTIONS IN ( ) PERTAIN ONLY TO AD720
Negative Sync Pulses
CMOS Logic Levels
25 DGND
26 VNEG
27 (NC) BOUT
28 APOS
Digital Ground Connections (One of T wo)
System Negative Supply; –5 V ± 5%
(No Connection) Blue Bypass Buffer
Analog Positive Supply; +5 V ± 5%
*( ) pertain only to AD720.
**T he luminance, chrominance, and composite outputs are at twice normal
levels for driving 75 Ω reverse-terminated lines.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD720/AD721 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD720/AD721–Typical Characteristics
COMPOSITE VIDEO
VOLTS
IRE:FLT
100.0
%
G
µs
FF
COMPOSITE
SYNC
TEKTRONIX TSG 300
COMPONENT VIDEO
WAVEFORM GENERATOR
AD720/AD721
RGB TO NTSC/PAL
ENCODER
SONY
MONITOR
MODEL 1342
CE
RGB
3
75Ω
75Ω
GENLOCK
0.5
50.0
0.0
4FSC
TEKTRONIX 1910
COMPOSITE VIDEO
WAVEFORM GENERATOR
FSC
TEKTRONIX VM700A
WAVEFORM MONITOR
PIXEL-CLOCK
GENERATOR
Figure 1. AD720/AD721 Evaluation Setup
DG DP(NTSC) (SYNC = EXT)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
FIELD = 1 LINE = 21
DIFFERENTIAL GAIN (%) MIN = –0.10; MAX = 0.00; p-p/MAX = 0.10
MICROSECONDS
–0.04
–0.10
0.00
–0.04
0.00
–0.01
0.10
0.05
Figure 4. 100% Color Bars, NTSC
0.00
–0.05
–0.10
VOLTS
IRE:FLT
FRAMES SELECTED: 1 2; APL = 11.3%
525 LINE NTSC; NO FILTERING
SLOW CLAMP TO 0.00V AT 6.63µs
PRECISION MODE OFF
SYNC = SOURCE
DIFFERENTIAL PHASE (°) MIN = 0.00; MAX = 0.07; p-p = 0.07
0.07 0.01
100.0
0.00
0.05
0.05
0.04
0.10
0.05
0.00
0.5
–0.05
–0.10
1ST
5TH
6TH
2ND
3RD
4TH
Figure 2. Com posite Output Differential Phase and Gain,
NTSC (Nulled to Chrom a Output)
VOLTS
IRE:FLT
NOISE REDUCTION: 15.05dB
APL = 49.6%
525 LINE NTSC; NO FILTERING
SLOW CLAMP TO 0.00V AT 6.63µs
SYNC = SOURCE
Figure 5. Multipulse, NTSC
FRAMES SELECTED: 1 2
100.0
H TIMING MEASUREMENT RS-170A (NTSC)
FIELD = 1 LINE = 22
0.5
8.0
CYCLES
50.0
0.0
5.35µs
4.82µs
85ns
39.4 IRE
39.2 IRE
73ns
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
AVERAGE 32 TO 32
MICROSECONDS/PRECISION MODE OFF
Figure 3. Modulated Pulse and Bar, NTSC
Figure 6. Horizontal Tim ing, NTSC
H TIMING (PAL)
LINE = 17
1.98µs
5.52µs
4.82µs
81ns
302.2mV
292.1mV
82ns
AVERAGE 32 TO 32
Figure 7. Horizontal Tim ing, PAL
–4–
REV. 0
AD720/AD721
(continued from page 1)
Y = 0.299R + 0.587G + 0.114B
U = 0.493 (B-Y)
V = 0.877 (R-Y)
All required low-pass filters are on chip. After the input signals
pass through a precision RGB to YUV encoding matrix, two on-
chip low-pass filters limit the bandwidth of the U and V color
difference signals to 1.2 MHz prior to quadrature modulation of
the color subcarrier; a third low-pass filter at 3.6 MHz (NT SC)
or 4.4 MHz (PAL) follows the modulators to limit the harmonic
content of the output.
For NTSC operation, the chroma amplitude is increased by the
factor 1.06 prior to summation with the luminance output. The
burst signal is inserted into the Y channel in the encoding matrix.
The three outputs of the encoding matrix, now transformed into Y,
U, and V components, take two paths. The Y (luminance) signal is
passed through a delay line consisting of a prefilter, a sampled-data
delay line, and a post filter. The pre- and post-filters prevent
aliasing of harmonics back into the baseband video. The overall de-
lay is a nominal –170 ns relative to the chrominance signal, in
keeping with broadcast requirements to compensate for delays in-
troduced by the filters in the decoding process.
Delays in the U and V chroma filters are matched by an on-chip
sampled data delay line in the Y signal path; to prevent aliasing,
prefilter at 5 MHz is included ahead of the delay line and a post
filter at 5 MHz is added after the delay line to suppress harmon-
ics in the output. T hese low-pass filters are optimized for mini-
mum pulse overshoot. T he overall delay is about 170 ns, which
precompensates for delays in the filters used to decode the
NT SC or PAL signal in a television receiver. (T his precompen-
sation delay is already present in T V broadcasts.)
T he U and V components pass through 4-pole modified Bessel
low-pass filters with a 1.2 MHz –3 dB frequency to prevent
aliasing in the balanced modulators, where they modulate a
3.579 545 000 MHz (NT SC) or 4.433 618 750 MHz (PAL)
signal via a pair of balanced modulators driven in quadrature by
the color subcarrier.
The AD720 and AD721 are available in a 28-pin plastic leaded
chip carrier for the 0°C to +70°C commercial temperature range.
TH EO RY O F O P ERATIO N
T he AD720/AD721 4FSC input drives a digital divide-by-4 cir-
cuit (two flip-flops) to create the quadrature signal. T he refer-
ence phase 0° is used for the U signal. In the NT SC mode, the
V signal is modulated at 90°, but in the PAL mode, the V
modulation input alternates between 90° and 270° at half the
line rate as required by the PAL standard. T he outputs of the
balanced modulators are summed and low-pass filtered to re-
move harmonics.
Referring to the AD720/AD721 block diagram (Figure 8), the
RGB inputs (each 0 mV to 714 mV in NT SC or 0 mV to
700 mV in PAL) are first encoded into luminance and color
difference signals. T he luminance signal is called the “Y”
signal and the color-difference signals are called U and V. T he
RGB inputs are encoded into the YUV format using the
transformation
NTSC/PAL
ASNC
DELAYED C-SYNC
C-SYNC
DELAY
POWER AND GROUNDS
SYNC
DECODER
NTSC/PAL
LOGIC
+5V
+5V
C-SYNC
BURST
ANALOG
ANALOG ONLY
ANALOG
LOGIC
–5V
AGND
DGND
±180
°
SC 90
°
/270
NTSC/PAL
CLOCK
AT 8FSC
°
(PAL ONLY)
SC 90
°
4FSC
ENCD
QUADRATURE
DECODER
SC 0
Y
°
BURST
5MHz
DC
LUMINANCE OUTPUT*
–0.572V TO 1.43V NTSC
–0.6V TO 1.4V PAL
5MHz
4-POLE LP
SAMPLED-
DATA
DELAY LINE
2-POLE
LP POST-
FILTER
RESTORE
AND C-SYNC
INSERTION
X2
RED
PRE-FILTER
COMPOSITE OUTPUT*
–0.572V TO 2V NTSC
–0.6V TO 2V PAL
RGB-TO-YUV
ENCODING
MATRIX
1.2MHz
4-POLE
LPF
NTSC/PAL
∑
X2
X2
U
V
GREEN
BLUE
3.6MHz (NTSC)
4.4MHz (PAL)
3-POLE LPF
BALANCED
MODULATORS
CHROMINANCE OUTPUT*
572mVp-p NTSC
600mVp-p PAL
∑
1.2MHz
4-POLE
LPF
*NOTE:
ROUT
1.5Vp-p
X2
X2
X2
THE LUMINANCE, COMPOSITE, AND CHROMINANCE
OUTPUTS ARE AT TWICE NORMAL LEVELS FOR
DRIVING 75Ω REVERSE-TERMINATED LINES.
AD721
(ONLY)
GOUT
1.5Vp-p
BOUT
1.5Vp-p
Figure 8. AD720/AD721 Functional Block Diagram
REV. 0
–5–
AD720/AD721
T he filtered output is summed with the luminance signal to cre-
ate a composite video signal. T he separate luminance, chromi-
nance, and composite video signals are amplified by gain-of-two
amplifiers for driving 75 Ω reverse-terminated lines. T he sepa-
rate luminance and chrominance outputs together are known as
“S-Video.”
Asserting the ENCD pin to a logical low routes the AD721’s
RGB inputs through three gain-of-two bypass buffers for driving
75 Ω reverse-terminated lines, bypassing the encoder section of
the AD721. T he triple bypass amplifier is utilized to overcome
the loading effects of a “T V-out” connection on the RGB moni-
tor output. When a video encoder is connected to outputs of a
current-out video RAMDAC or VGA controller, the R, G, and
B signals to the monitor are loaded-down. T his requires the use
of a gain block to properly drive the monitor.
T he digital section of the AD720/AD721 is clocked by the
4FSC input. It measures the width of pulses in the composite
sync input to separate vertical, horizontal, and serration pulses
and to insert the subcarrier burst only after a valid horizontal
sync pulse.
+5V FROM
ANALOG SUPPLY
–5V FROM
ANALOG SUPPLY
0.1µF
0.1µF
4
3
2
1
28
27 26
VNEG
ENCODE INPUT
ENCODE = CMOS HIGH
AGND
ENCD
POWER DOWN = CMOS LOW
25
5
6
7
DGND
COMPOSITE SYNC INPUT
CMOS LOGIC LEVEL
NEGATIVE SYNC TIPS
IOR
24
23
SYNC
DPOS
RDIN
75Ω
75Ω
75Ω
75Ω
+5V FROM
AGND
VIDEO
DIGITAL SUPPLY
0.1µF
0.1µF
RAM-DAC
AD720
ADV47X IOG
ASNC 22
8
9
GRIN
RGB TO NTSC/PAL
ENCODER
ADV71XX
75Ω
+5V FROM
DIGITAL SUPPLY
21
20
19
DPOS
4FSC
AGND
IOB
10
11
BLIN
75Ω
4 X SUBCARRIER INPUT
CMOS LOGIC LEVELS
NTCS = 14.318 180MHz
PAL = 17.734 480MHz
STND
AGND
DGND
0.1µF
VIDEO STANDARD
SELECTION INPUT
NTSC = CMOS HIGH
PAL = CMOS LOW
VNEG
12 13 14 15 16 17 18
–5V FROM ANALOG SUPPLY
LUMINANCE OUTPUT
75Ω
75Ω
75Ω
+5V FROM
ANALOG SUPPLY
COMPOSITE OUTPUT
0.1µF
CHROMINANCE OUTPUT
Figure 9. AD720 Application
75Ω
RED OUTPUT
75Ω
75Ω
GREEN OUTPUT
BLUE OUTPUT
+5V FROM
0.1µF
ANALOG SUPPLY
–5V FROM
ANALOG SUPPLY
0.1µF
4
3
2
1
28
27 26
VNEG
DGND
ENCODE INPUT
ENCODE = CMOS HIGH
BYPASS = CMOS LOW
AGND
ENCD
25
5
6
7
COMPOSITE SYNC INPUT
CMOS LOGIC LEVEL
NEGATIVE SYNC TIPS
IOR
24
23
SYNC
DPOS
RDIN
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
+5V FROM
AGND
VIDEO
DIGITAL SUPPLY
0.1µF
0.1µF
RAM-DAC
AD721
RGB TO NTSC/PAL
ENCODER
ADV47X IOG
ADV71XX
ASNC 22
8
9
GRIN
+5V FROM
DIGITAL SUPPLY
21
20
19
DPOS
4FSC
AGND
IOB
10
11
BLIN
4 X SUBCARRIER INPUT
CMOS LOGIC LEVELS
NTCS = 14.318 180MHz
PAL = 17.734 480MHz
STND
AGND
DGND
0.1µF
VIDEO STANDARD
SELECTION INPUT
NTSC = CMOS HIGH
PAL = CMOS LOW
VNEG
12 13 14 15 16 17 18
–5V FROM ANALOG SUPPLY
LUMINANCE OUTPUT
75Ω
75Ω
75Ω
+5V FROM
ANALOG SUPPLY
COMPOSITE OUTPUT
0.1µF
CHROMINANCE OUTPUT
Figure 10. AD721 Application
–6–
REV. 0
AD720/AD721
AP P LYING TH E AD 720/AD 721
separator in the AD720/AD721 ignores horizontal sync pulses
that are too long or too short. Figure 11 shows the timing win-
dows for valid NT SC and PAL horizontal sync pulses.
Figure 9 shows the application of the AD720 and Figure 10
shows the application of the AD721. Note that the AD720 and
AD721 differ from other analog encoders because they are dc
coupled. T his means that, for example, the expected RGB
inputs are 0 mV to 714 mV in NT SC and 0 mV to 700 mV in
PAL. T he luminance, chrominance, and composite outputs
are also dc coupled. T hese outputs can drive a 75 Ω reverse-
terminated load. Unused outputs should be terminated with
150 Ω resistors.
NTSC: 5.30µs
PAL: 5.46µs
COLOR BURST
COMPOSITE SYNC PULSE
T he RGB data must be supplied to the AD720/AD721 at
NT SC or PAL rates, interlaced format. Various VGA chip set
vendors support this mode of operation. Most computers supply
RGB outputs in noninterlaced format at higher data rates than
NT SC and PAL, which means that “outboard” encoders must
supply some form of timing conversion before the RGB data
reaches the AD720/AD721.
NTSC: 2.51µs
PAL: 2.25µs
NTSC: 2.79µs
PAL: 3.21µs
NTSC: 2.51µs
PAL: 2.25µs
IF THE TRAILING EDGE OF A COMPOSITE SYNC PULSE IS WITHIN
THIS WINDOW, THE PULSE IS TREATED AS A HORIZONTAL SYNC PULSE.
IF THE TRAILING EDGE IS OUTSIDE THIS WINDOW, THE PULSE IS TREATED
AS AN EQUALIZING OR BLANKING PULSE.
Note also that the AD720/AD721 does not have internal dc res-
toration and does not accept sync on green. T he composite sync
input is a separate, CMOS logical-level input and must be syn-
chronized with the 4FSC input, which serves as the master clock
for the AD720/AD721.
Figure 11. NTSC and PAL Tim ing for Valid Horizontal
Sync Pulses
When the horizontal sync pulses are too long or too short, a dc
offset voltage (due to charge storage) increases on the output of
the sampled data delay line’s auto-zero amplifier. Normally, this
offset voltage is removed at the beginning of every line, as signi-
fied by the horizontal sync pulse. Without the horizontal sync
pulse, the dc offset on the auto-zero amplifier increases over
time (usually about three to five minutes) until it overrides the
luminance information. T he end result is a slow fade to black or
white.
T he AD720/AD721 does not implement two elements of the
PAL and NT SC standards. In NT SC operation, it does not
support the 7.5 IRE unit setup (1 IRE unit = 7.14 mV)—this
must be added via software using the RGB inputs. Many RAM-
DACs, such as the Analog Devices ADV471 and ADV478, offer
a logic-selectable setup mode. In PAL operation, the AD720/
AD721 does not implement a 25 Hz subcarrier offset.
D ecoupling and Gr ounding
Color Flicker ing—Asynchr onous O per ation
Referring to the pin descriptions, the AD720/AD721 uses mul-
tiple analog grounds, digital grounds, digital positive supply in-
puts, analog positive supply inputs, and analog negative supply
inputs in order to maximize isolation between analog and digital
signal paths.
T he AD720/AD721 requires that its 4FSC and composite sync
signals be synchronized. In most systems, when the two signals
are synchronized, the composite sync signal is generated using a
4FSC signal as the reference. After every four frames, the
AD720/AD721 resets the phase quadrature generator. When the
CSYNC and 4FSC are synchronized, this reset is transparent to
the system because the reference phase does not change. When
the CSYNC and 4FSC are not synchronized, the difference
between the reference phase and its new value upon reset causes
an instantaneous color shift, which appears as a flickering in the
color.
T he most sensitive input of the AD720/AD721 is the 4FSC pin:
any noise on this pin directly affects the subcarrier and causes
degradation of the picture. Digital and analog grounds should
be kept separate and brought together at a single point.
All power supply pins should be decoupled using 0.1 µF ceramic
capacitors located as close to the AD720/AD721 as possible. In
addition, ferrite beads may be slipped over the power supply
leads to reduce high frequency noise.
Adding NTSC Setup
T he easiest way to add the 7.5 IRE unit1 setup is to use a
ADV471/478 or ADV477/475 or ADV473 type RAM-DAC,
which have a logic-selectable setup (called “pedestal” on some
data sheets and “setup” on others).
If a high speed RAM-DAC is used (e.g., capable of 80 MHz op-
eration with subnanosecond rise times), care must be taken to
properly terminate the input printed-circuit-board traces to the
AD720/AD721. Otherwise, ringing on these traces may occur
and cause degradation of the picture.
Color Fidelity
A source impedance other than 37.5 Ω (75 Ωʈ75 Ω—a
reverse-terminated 75 Ω input) can cause errors in the YUV
encoding matrix, which is basically resistive and depends on the
correct source impedance for accuracy. Figures 9 and 10 show
the correct interface between a RAM-DAC and the AD720 and
AD721 respectively, using 75 Ω reverse-terminated connections.
AP P LICATIO NS H INTS
In applying the AD720/AD721, problems may arise due to in-
correct input signals. A few common situations follow.
Fade to Black or White—Invalid H or izontal Sync P ulses
Some systems produce sync pulses that are longer or shorter
than the NT SC and PAL standards specify. T he digital sync
NOT E
1IRE unit = 7.14 mV.
REV. 0
–7–
AD720/AD721
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-Lead P lastic Leaded Chip Car r ier (P LCC) P ackage
P -28A
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
4
26
25
PIN 1
IDENTIFIER
5
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
0.430 (10.92)
0.390 (9.91)
TOP
VIEW
0.032 (0.81)
0.026 (0.66)
19
18
11
12
0.020
0.040 (1.01)
0.025 (0.64)
(0.50)
R
0.456 (11.58)
SQ
0.450 (11.43)
0.110 (2.79)
0.085 (2.16)
0.495 (12.57)
0.485 (12.32)
SQ
–8–
REV. 0
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