AD7225CQ [ADI]
LC2MOS Quad 8-Bit DAC with Separate Reference Inputs; LC2MOS四通道8位DAC ，具有独立的基准输入
| 型号： | AD7225CQ |
| 厂家： | 
ADI |
| 描述： | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
| 文件： | 总12页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS Quad 8-Bit DAC
with Separate Reference Inputs
a
AD7225
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Four 8-Bit DACs w ith Output Am plifiers
Separate Reference Input for Each DAC
P Com patible w ith Double-Buffered Inputs
Sim ultaneous Update of All Four Outputs
Operates w ith Single or Dual Supplies
Extended Tem perature Range Operation
No User Trim s Required
Skinny 24-Pin DIP, SOIC and 28-Term inal Surface
Mount Packages
GENERAL D ESCRIP TIO N
T he AD7225 contains four 8-bit voltage output digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. Each D/A converter has a
separate reference input terminal. No external trims are re-
quired to achieve full specified performance for the part.
P RO D UCT H IGH LIGH TS
1. DACs and Amplifiers on CMOS Chip
T he single-chip design of four 8-bit DACs and amplifiers al-
lows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple convert-
ers. Its pinout is aimed at optimizing board layout with all
analog inputs and outputs at one end of the package and all
digital inputs at the other.
T he double-buffered interface logic consists of two 8-bit regis-
ters per channel–an input register and a DAC register. Control
inputs A0 and A1 determine which input register is loaded when
WR goes low. Only the data held in the DAC registers deter-
mines the analog outputs of the converters. T he double-
buffering allows simultaneous update of all four outputs under
control of LDAC. All logic inputs are T T L and CMOS (5 V)
level compatible and the control logic is speed compatible with
most 8-bit microprocessors.
2. Single or Dual Supply Operation
T he voltage-mode configuration of the AD7225 allows single
supply operation. T he part can also be operated with dual
supplies giving enhanced performance for some parameters.
Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V when using dual supplies. T he part is also
specified for single supply operation using a reference of +10 V.
Each output buffer amplifier is capable of developing +10 V
across a 2 kΩ load.
3. Versatile Interface Logic
T he AD7225 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. T he double-buffered in-
terface allows simultaneous update of the four outputs.
T he AD7225 is fabricated on an all ion-implanted high-speed
Linear Compatible CMOS (LC2MOS) process which has been
specifically developed to integrate high speed digital logic cir-
cuits and precision analog circuitry on the same chip.
4. Separate Reference Input for Each DAC
T he AD7225 offers great flexibility in dealing with input sig-
nals with a separate reference input provided for each DAC
and each reference having variable input voltage capability.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD7225–SPECIFICATIONS
(V = 11.4 V to 16.5 V, V = –5 V ؎ 10%; AGND = DGND = O V; V = +2 V to (V – 4 V)1 unless otherwise noted.
DD
SS
REF
DD
DUAL SUPPLY
All specifications TMIN to TMAX unless otherwise noted.)
K, B
L, C
P aram eter
Versions2
Versions2
T Version
U Version
Units
Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
8
8
8
8
Bits
T otal Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale T emp. Coeff.
Zero Code Error @ 25°C
T MIN to T MAX
±2
±1
±1
±1
±5
±25
±30
±30
±1
±1/2
±1
±1/2
±5
±15
±20
±30
±2
±1
±1
±1
±5
±25
±30
±30
±1
±1/2
±1
±1/2
±5
±15
±20
±30
LSB max
LSB max
LSB max
LSB max
ppm/°C typ
mV max
mV max
µV/°C typ
VDD = +15 V ± 5%, VREF = +10 V
Guaranteed Monotonic
VDD = 14 V to 16.5 V, VREF = +10 V
Zero Code Error T emp Coeff.
REFERENCE INPUT
Voltage Range
2 to (VDD – 4) 2 to (VDD – 4) 2 to (VDD – 4) 2 to (VDD – 4) V min to V max
Input Resistance
11
100
11
100
60
11
100
60
11
100
60
kΩ min
pF max
dB min
dB max
Input Capacitance3
Occurs when each DAC is loaded with all 1s.
VREF = 10 V p-p Sine Wave @ 10 kHz
VREF = 10 V p-p Sine Wave @ 10 kHz
Channel-to-Channel Isolation3 60
AC Feedthrough3
–70
–70
–70
–70
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance3
Input Coding
2.4
0.8
±1
2.4
0.8
±1
2.4
0.8
±1
2.4
0.8
±1
V min
V max
µA max
pF max
VIN = 0 V or VDD
8
8
8
8
Binary
Binary
Binary
Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate3
Voltage Output Settling T ime3
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough3
2.5
2.5
2.5
2.5
V/µs min
5
5
50
50
2
5
5
50
50
2
5
5
50
50
2
5
5
50
50
2
µs max
µs max
nV secs typ
nV secs typ
kΩ min
VREF = +10 V; Settling T ime to ±1/2 LSB
VREF = +10 V; Settling T ime to ±1/2 LSB
Code transition all 0s to all 1s.
Code transition all 0s to all 1s.
VOUT = +10 V
Digital Crosstalk3
Minimum Load Resistance
POWER SUPPLIES
VDD Range
11.4/16.5
11.4/16.5
11.4/16.5
11.4/16.5
V min to V max For Specified Performance
IDD
ISS
10
9
10
9
12
10
12
10
mA max
mA max
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; VIN = VINL or VINH
SWIT CHING CHARACT ERIST ICS3, 4
t1
@ 25°C
T MIN to T MAX
95
120
95
120
95
150
95
150
ns min
ns min
Write Pulse Width
t2
t3
t4
t5
t6
@ 25°C
T MIN to T MAX
0
0
0
0
0
0
0
0
ns min
ns min
Address to Write Setup T ime
Address to Write Hold T ime
Data Valid to Write Setup T ime
Data Valid to Write Hold T ime
Load DAC Pulse Width
@ 25°C
T MIN to T MAX
0
0
0
0
0
0
0
0
ns min
ns min
@ 25°C
T MIN to T MAX
70
90
70
90
70
90
70
90
ns min
ns min
@ 25°C
T MIN to T MAX
10
10
10
10
10
10
10
10
ns min
ns min
@ 25°C
95
95
95
95
ns min
ns min
T MIN to T MAX
120
120
150
150
NOT ES
1Maximum possible reference voltage.
2T emperature ranges are as follows:
K, L Versions: –40°C to +85°C
B, C Versions: –40°C to +85°C
T , U Versions: –55°C to +125°C
3Sample T ested at 25°C to ensure compliance.
4Switching characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
–2–
REV. B
AD7225
1
(V = +15 V ؎ 5%; V = AGND = DGND = O V; V = +10 V unless otherwise noted.
DD
SS
REF
SINGLE SUPPLY
All specifications TMIN to TMAX unless otherwise noted.)
K, B
L, C
P aram eter
Versions2
Versions2
T Version
U Version
Units
Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
8
±2
±1
8
±1
±1
8
±2
±1
8
±1
±1
Bits
LSB max
LSB max
T otal Unadjusted Error3
Differential Nonlinearity3
Guaranteed Monotonic
REFERENCE INPUT
Input Resistance
11
100
60
11
100
60
11
100
60
11
100
60
kΩ min
pF max
dB min
dB max
Input Capacitance4
Occurs when each DAC is loaded with all 1s.
VREF = 10 V p-p Sine Wave @ 10 kHz
VREF = 10 V p-p Sine Wave @ 10 kHz
Channel-to-Channel Isolation3, 4
AC Feedthrough3, 4, 5
–70
–70
–70
–70
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance4
Input Coding
2.4
0.8
±1
2.4
0.8
±1
2.4
0.8
±1
2.4
0.8
±1
V min
V max
µA max
pF max
VIN = 0 V or VDD
8
8
8
8
Binary
Binary
Binary
Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate4
Voltage Output Settling T ime4
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough3, 4
2
2
2
2
V/µs min
5
7
50
50
2
5
7
50
50
2
5
7
50
50
2
5
7
50
50
2
µs max
µs max
nV secs typ
nV secs typ
kΩ min
Settling T ime to ±1/2 LSB
Settling T ime to ±1/2 LSB
Code transition all 0s to all 1s.
Code transition all 0s to all 1s.
VOUT = +10 V
Digital Crosstalk3, 4
Minimum Load Resistance
POWER SUPPLIES
VDD Range
IDD
14.25/15.75
10
14.25/15.75
10
14.25/15.75
12
14.25/15.75
12
V min to V max For Specified Performance
mA max
Outputs Unloaded; VIN = VINL or VINH
SWIT CHING CHARACT ERIST ICS4
t1
@ 25°C
T MIN to T MAX
t2
95
120
95
120
95
150
95
150
ns min
ns min
Write Pulse Width
@ 25°C
T MIN to T MAX
t3
@ 25°C
T MIN to T MAX
t4
@ 25°C
T MIN to T MAX
t5
@ 25°C
T MIN to T MAX
t6
0
0
0
0
0
0
0
0
ns min
ns min
Address to Write Setup T ime
Address to Write Hold T ime
Data Valid to Write Setup T ime
Data Valid to Write Hold T ime
Load DAC Pulse Width
0
0
0
0
0
0
0
0
ns min
ns min
70
90
70
90
70
90
70
90
ns min
ns min
10
10
10
10
10
10
10
10
ns min
ns min
@ 25°C
95
95
95
95
ns min
ns min
T MIN to T MAX
120
120
150
150
NOT ES
3Sample T ested at 25°C to ensure compliance.
1Maximum possible reference voltage.
2T emperature ranges are as follows:
K, L Versions: –40°C to +85°C
B, C Versions: –40°C to +85°C
T , U Versions: –55°C to +125°C
4Switching characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
O RD ERING GUID E
Total
Total
Tem perature
Range
Unadjusted
Error
P ackage
Tem perature
Range
Unadjusted
Error
P ackage
O ption2
Model1
Model1
O ption2
AD7225T Q
AD7225UQ
AD7225T E
AD7225UE
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
±2 LSB
±1 LSB
±2 LSB
±1 LSB
Q-24
Q-24
E-28A
E-28A
AD7225KN
AD7225LN
AD7225KP
AD7225LP
AD7225KR
AD7225LR
AD7225BQ
AD7225CQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±2 LSB
±1 LSB
±2 LSB
±1 LSB
±2 LSB
±1 LSB
±2 LSB
±1 LSB
N-24
N-24
P-28A
P-28A
R-24
R-24
Q-24
Q-24
NOT ES
1T o order MIL-ST D-883 processed parts, add /883B to part number. Contact your
local sales office for military data sheet.
2E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
–3–
REV. B
AD7225
ABSO LUTE MAXIMUM RATINGS1
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (T , U Versions) . . . . . . . . . . . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Power Dissipation (Any Package) to +75°C . . . . . . . . 500 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/°C
Operating T emperature
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Outputs may be shorted to any voltage in the range VSS to VDD provided that the
power dissipation of the package is not exceeded. T ypical short circuit current for
a short to AGND or VSS is 50 mA.
Commercial (K, L Versions) . . . . . . . . . . . –40°C to +85°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7225 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN CO NFIGURATIO NS
D IP and SO IC
LCCC
P LCC
TERMINO LO GY
D IGITAL FEED TH RO UGH
TO TAL UNAD JUSTED ERRO R
Digital Feedthrough is the glitch impulse transferred to the out-
put of the DAC due to a change in its digital input code. It is
specified in nV secs and is measured at VREF = 0 V.
T otal Unadjusted Error is a comprehensive specification which
includes full-scale error, relative accuracy, and zero code error.
Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB
(ideal) is VREF/256. T he LSB size will vary over the VREF range.
Hence the zero code error will, relative to the LSB size, increase
as VREF decreases. Accordingly, the total unadjusted error,
which includes the zero code error, will also vary in terms of
LSBs over the VREF range. As a result, total unadjusted error is
specified for a fixed reference voltage of +10 V.
D IGITAL CRO SSTALK
Digital Crosstalk is the glitch impulse transferred to the output
of one converter (not addressed) due to a change in the digital
input code to another addressed converter. It is specified in
nV secs and is measured at VREF = 0 V.
AC FEED TH RO UGH
AC Feedthrough is the proportion of reference input signal
which appears at the output of a converter when that DAC is
loaded with all 0s.
RELATIVE ACCURACY
Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after al-
lowing for zero code error and full-scale error and is normally
expressed in LSBs or as a percentage of full-scale reading.
CH ANNEL-TO -CH ANNEL ISO LATIO N
Channel-to-channel isolation is the proportion of input signal
from the reference of one DAC (loaded with all 1s) which ap-
pears at the output of one of the other three DACs (loaded with
all 0s) T he figure given is the worst case for the three other out-
puts and is expressed as a ratio in dBs.
D IFFERENTIAL NO NLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
FULL-SCALE ERRO R
Full-Scale Error is defined as:
Measured Value – Zero Code Error – Ideal Value
–4–
REV. B
Typical Performance Characteristics–AD7225
T = 25؇C, V = +15 V, V = –5 V unless otherwise noted.
A
DD
SS
Figure 1. Channel-to-Channel Matching
Figure 2. Relative Accuracy vs. VREF
Figure 4. Power Supply Current vs. Tem perature
Figure 3. Differential Nonlinearity vs. VREF
Figure 5. Zero Code Error vs. Tem perature
Figure 6. Broadband Noise
–5–
REV. B
AD7225
CIRCUIT INFO RMATIO N
D /A SECTIO N
T he AD7225 contains four, identical, 8-bit voltage mode
digital-to-analog converters. Each D/A converter has a separate
reference input. T he output voltages from the converters have
the same polarity as the reference voltages, allowing single sup-
ply operation. A novel DAC switch pair arrangement on the
AD7225 allows a reference voltage range from +2 V to +12.5 V
on each reference input.
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high speed NMOS, single-pole, double-throw
switches. T he simplified circuit diagram for channel A is shown
in Figure 7. Note that AGND (Pin 6) is common to all four
DACs.
Figure 8. Variation of ISINK with VOUT
Figure 7. D/A Sim plified Circuit Diagram
Additionally, the negative VSS gives more headroom to the out-
put amplifiers which results in better zero code performance and
improved slew rate at the output, than can be obtained in the
single supply mode.
T he input impedance at any of the reference inputs is code de-
pendent and can vary from 11 kΩ minimum to infinity. T he
lowest input impedance at any reference input occurs when that
DAC is loaded with the digital code 01010101. T herefore, it is
important that the reference presents a low output impedance
under changing load conditions. T he nodal capacitance at the
reference terminals is also code dependent and typically varies
from 15 pF to 35 pF.
D IGITAL SECTIO N
T he AD7225 digital inputs are compatible with either T T L or
5 V CMOS levels. All logic inputs are static protected MOS
gates with typical input currents of less than 1 nA. Internal in-
put protection is achieved by an on-chip distributed diode be-
tween DGND and each MOS gate. T o minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (VDD and DGND) as practi-
cally possible.
Each VOUT pin can be considered as a digitally programmable
voltage source with an output voltage of:
VOUT X = DX • VREFX
where DX is fractional representation of the digital input code
and can vary from 0 to 255/256.
INTERFACE LO GIC INFO RMATIO N
T he output impedance is that of the output buffer amplifier.
T he AD7225 contains two registers per DAC, an input register
and a DAC register. Address lines A0 and A1 select which input
register will accept data from the input port. When the WR sig-
nal is LOW, the input latches of the selected DAC are transpar-
ent. T he data is latched into the addressed input register on the
rising edge of WR. T able I shows the addressing for the input
registers on the AD7225.
O P -AMP SECTIO N
Each voltage mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. T his buffer amplifier is ca-
pable of developing +10 V across a 2 kΩ load and can drive ca-
pacitive loads of 3300 pF.
T he AD7225 can be operated single or dual supply; operating
with dual supplies results in enhanced performance in some pa-
rameters which cannot be achieved with single supply operation.
In single supply operation (VSS = 0 V = AGND) the sink capa-
bility of the amplifier, which is normally 400 µA, is reduced as
the output voltage nears AGND. T he full sink capability of
400 µA is maintained over the full output voltage range by tying
VSS to –5 V. T his is indicated in Figure 8.
Table I. AD 7225 Addressing
A1
A0
Selected Input Register
L
L
H
H
L
H
L
H
DAC A Input Register
DAC B Input Register
DAC C Input Register
DAC D Input Register
Settling-time for negative-going output signals approaching
AGND is similarly affected by VSS. Negative-going settling-time
for single supply operation is longer than for dual supply opera-
tion. Positive-going settling-time is not affected by VSS.
–6–
REV. B
AD7225
Only the data held in the DAC register determines the analog
output of the converter. T he LDAC signal is common to all four
DACs and controls the transfer of information from the input
registers to the DAC registers. Data is latched into all four DAC
registers simultaneously on the rising edge of LDAC. T he
LDAC signal is level triggered and therefore the DAC registers
may be made transparent by tying LDAC LOW (in this case the
outputs of the converters will respond to the data held in their
respective input latches). LDAC is an asynchronous signal and
is independent of WR. T his is useful in many applications.
However, in systems where the asynchronous LDAC can occur
during a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. In other
words, if LDAC is activated prior to the rising edge of WR (or
WR occurs during LDAC), then LDAC must stay LOW for t6
or longer after WR goes HIGH to ensure correct data is latched
through to the output. Table II shows the truth table for AD7225
operation. Figure 9 shows the input control logic for the part
and the write cycle timing diagram is given in Figure 10.
Figure 9. Input Control Logic
Table II. AD 7225 Truth Table
WR LDAC Function
H
L
g
H
H
H
L
No Operation. Device not selected
Input Register of Selected DAC T ransparent
Input Register of Selected DAC Latched
All Four DAC Registers T ransparent
(i.e. Outputs respond to data held in respective
input registers)
H
Input Registers are Latched
H
L
g
L
All Four DAC Registers Latched
DAC Registers and Selected Input Register
T ransparent Output follows Input Data for
Selected Channel.
Figure 10. Write Cycle Tim ing Diagram
GRO UND MANAGEMENT AND LAYO UT
Since the AD7225 contains four reference inputs which can be
driven from ac sources (see AC REFERENCE SIGNAL sec-
tion) careful layout and grounding is important to minimize
analog crosstalk between the four channels. T he dynamic per-
formance of the four DACs depends upon the optimum choice
of board layout. Figure 11 shows the relationship between input
Figure 12. Suggested PCB Layout for AD7225.
Layout Shows Com ponent Side (Top View)
frequency and channel-to-channel isolation. Figure 12 shows a
printed circuit board layout which is aimed at minimizing
crosstalk and feedthrough. T he four input signals are screened
by AGND. VREF was limited to between 2 V and 3.24 V to
avoid slew rate limiting effects from the output amplifier during
measurements.
Figure 11. Channel-to-Channel Isolation
–7–
REV. B
AD7225
SP ECIFICATIO N RANGES
Table III. Unipolar Code Table
For the AD7225 to operate to rated specifications, its input ref-
erence voltage must be at least 4 V below the VDD power supply
voltage. T his voltage differential is the overhead voltage re-
quired by the output amplifiers.
D AC Latch Contents
MSB LSB
Analog O utput
255
+VREF
T he AD7225 is specified to operate over a VDD range from
+12 V ± 5% to +15 V ±10% (i.e., from +11.4 V to +16.5 V)
with a VSS of –5 V ±10%. Operation is also specified for a single
+15 V ± 5% VDD supply. Applying a VSS of –5 V results in im-
proved zero code error, improved output sink capability with
outputs near AGND and improved negative going settling time.
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
256
129
+VREF
256
128
256
VREF
+VREF
= +
1 0 0 0 0 0 0 0
2
Performance is specified over a wide range of reference voltages
from 2 V to (VDD – 4 V) with dual supplies. T his allows a range
of standard reference generators to be used such as the AD580,
a +2.5 V bandgap reference and the AD584, a precision +10 V
reference. Note that an output voltage range of 0 V to +10 V re-
quires a nominal +15 V ± 5% power supply voltage.
127
256
+VREF
+VREF
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1
256
0 V
UNIP O LAR O UTP UT O P ERATIO N
T his is the basic mode of operation for each channel of the
AD7225, with the output voltage having the same positive
polarity as VREF. T he AD7225 can be operated single supply
(VSS = AGND) or with positive/negative supplies (see op-amp
section which outlines the advantages of having negative VSS).
Connections for the unipolar output operation are shown in Fig-
ure 13. T he voltage at any of the reference inputs must never be
negative with respect to DGND. Failure to observe this precau-
tion may cause parasitic transistor action and possible device de-
struction. T he code table for unipolar output operation is shown
in T able III.
1
256
Note: 1 LSB = V
2−8 = V
(
)
(
)
REF
REF
BIP O LAR O UTP UT O P ERATIO N
Each of the DACs of the AD7225 can be individually config-
ured to provide bipolar output operation. T his is possible using
one external amplifier and two resistors per channel. Figure 14
shows a circuit used to implement offset binary coding (bipolar
operation) with DAC A of the AD7225. In this case
R2
R1
R2
R1
VOUT = 1 +
D V
–
V
(
REF
(
)
)
A
REF
With R1 = R2
VOUT = (2 DA – 1) • VREF
where DA is a fractional representation of the digital word in
latch A. (0 ≤ DA ≤ 255/256)
Mismatch between R1 and R2 causes gain and offset errors and,
therefore, these resistors must match and track over tempera-
ture. Once again the AD7225 can be operated in single supply
or from positive/negative supplies. T able IV shows the digital
code versus output voltage relationship for the circuit of Figure
14 with R1 = R2.
Figure 13. Unipolar Output Circuit
–8–
REV. B
AD7225
For a given VIN, increasing AGND above system GND will re-
duce the effective VDD–VREF which must be at least 4 V to en-
sure specified operation. Note that because the AGND pin is
common to all four DACs, this method biases up the output
voltages of all the DACs in the AD7225. Note that VDD and VSS
of the AD7225 should be referenced to DGND.
AC REFERENCE SIGNAL
In some applications it may be desirable to have ac reference
signals. T he AD7225 has multiplying capability within the up-
per (VDD – 4 V) and lower (2 V) limits of reference voltage when
operated with dual supplies. T herefore ac signals need to be ac
coupled and biased up before being applied to the reference in-
puts. Figure 16 shows a sine wave signal applied to VREF A. For
input signal frequencies up to 50 kHz the output distortion typi-
cally remains less than 0.1%. T he typical 3 dB bandwidth figure
for small signal inputs is 800 kHz.
Figure 14. AD7225 Bipolar Output Circuit
Table IV. Bipolar (O ffset Binary) Code Table
D AC Latch Contents
MSB
LSB
Analog O utput
127
+VREF
1 1 1 1
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
128
1
+VREF
128
0 V
1
–VREF
128
127
–VREF
128
128
128
–VREF
= –VREF
Figure 16. Applying an AC Signal to the AD7225
AP P LICATIO NS
AGND BIAS
P RO GRAMMABLE TRANSVERSAL FILTER
A discrete-time filter may be described by either multiplication
in the frequency domain or convolution in the time domain i.e.
T he AD7225 AGND pin can be biased above system GND
(AD7225 DGND) to provide an offset “zero” analog output
voltage level. Figure 15 shows a circuit configuration to achieve
this for channel A of the AD7225. T he output voltage, VOUT A,
can be expressed as:
N
Y ω = H ω X ω or yn = ∑ hkXn –k+1
(
)
( ) ( )
k=1
T he convolution sum may be implemented using the special
structure known as the transversal filter (Figure 17). Basically, it
consists of an N-stage delay line with N taps weighted by N co-
efficients, the resulting products being accumulated to form the
output. T he tap weights or coefficients hk are actually the non-
zero elements of the impulse response and therefore determine
the filter transfer function. A particular filter frequency response
is realized by setting the coefficients to the appropriate values.
T his property leads to the implementation of transversal filters
whose frequency response is programmable.
VOUT A = VBIAS + DA (VIN
)
where DA is a fractional representation of the digital word in
DAC latch A. (0 ≤ DA ≤ 255/256).
Figure 15. AGND Bias Circuit
Figure 17. Transversal Filter
–9–
REV. B
AD7225
ACCUMULATOR
O/P
V
OUT
V
OUT
V
OUT
V
OUT
A
B
C
D
DELAYED
I/P
I/P
FILTER
I/P
FILTER
O/P
AD7820
ADC
Am29520
TLD
AD7225
QUAD DAC
AD585
+
SHA
SAMPLES
SAMPLES
V
V
A
V
A
h
V
A
V
V
A
REF
REF
REF
REF
X
X
X
X
n–3
n
n–1
n–2
h
1
h
2
h
4
3
FILTER
I/P
T
T
3
T
4
A
V
OUT
A
V
A
A
OUT
OUT
OUT
1
2
3
4
h
h
h
h
1
2
AD584
REF
Am7224
DAC
AD7226
+10V
V
OUT
QUAD DAC
V
V
REF
REF
+
FILTER
O/P
Y
n
GAIN SET
TAP WEIGHTS
Figure 18. Program m able Transversal Filter
A 4-tap programmable transversal filter may be implemented
using the AD7225 (Figure 18). T he input signal is first sampled
and converted to allow the tapped delay line function to be pro-
vided by the Am29520. T he multiplication of delayed input
samples by fixed, programmable up weights is accomplished by
the AD7225, the four coefficients or reference inputs being set
by the digital codes stored in the AD7226. T he resultant prod-
ucts are accumulated to yield the convolution sum output
sample which is held by the AD585.
filter with the coefficients indicated. Although the theoretical
prediction does not take into account the quantization of the in-
put samples and the truncation of the coefficients, nevertheless,
there exists a good correlation with the actual performance of
the transversal filter (Figure 20).
D IGITAL WO RD MULTIP LICATIO N
Since each DAC of the AD7225 has a separate reference input,
the output of one DAC can be used as the reference input for
another. T his means that multiplication of digital words can be
performed (with the result given in analog form). For example,
if the output from DACA is applied to VREF B then the output
from DACB, VOUT B, can be expressed as:
0
–10
–20
–30
VOUT B = DA • DB • VREF
A
–40
–50
–60
–70
–80
–90
–100
h
h
h
h
= 0.117
= 0.417
= 0.417
= 0.417
1
2
3
4
where DA and DB are the fractional representations of the
digital words in DAC latches A and B respectively.
If DA = DB = D then the result is D2 • VREF
A
In this manner, the four DACs can be used on their own or in
conjunction with an external summing amplifier to generate
complex waveforms. Figure 21 shows one such application. In
this case the output waveform, Y, is represented by:
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
NORMALIZED FREQUENCY – f/fs
0
Y = –(x4 + 2x3 + 3x2 + 2x + 4) • VIN
Figure 19. Predicted (Theoretical) Response
where x is the digital code which is applied to all four DAC
latches.
+15V
25kΩ
100kΩ
V
DD
50kΩ
V
V
V
V
V
A
V
OUT
A
B
C
D
IN
REF
REF
REF
REF
Y
AD7225*
33kΩ
50kΩ
B
C
D
V
V
V
OUT
OUT
100kΩ
OUT
V
Figure 20. Actual Response
SS
AGND DGND
*DIGITAL INPUTS OMITTED
FOR CLARITY
Low pass, bandpass and high pass filters may be synthesized us-
ing this arrangement. T he particular up weights needed for any
desired transfer function may be obtained using the standard
Remez Exchange Algorithm. Figure 19 shows the theoretical
low pass frequency response produced by a 4-tap transversal
Figure 21. Com plex Waveform Generation
–10–
REV. B
AD7225
MICRO P RO CESSO R INTERFACE
A23
A1
A15
ADDRESS BUS
ADDRESS BUS
A8
A0
A1
LDAC
A0
A1
8085A/
ADDRESS
DECODE
ADDRESS
DECODE
8088
68008
AD7225*
AD7225*
WR
AS
EN
WR
WR
R/W
LATCH
EN
LDAC
DB7
DB0
DTACK
ALE
DB7
DB0
AD7
AD0
ADDRESS DATA BUS
LINEAR CIRCUITRY OMITTED FOR CLARITY
D7
D0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
*
Figure 22. AD7225 to 8085A/8088 Interface,
Double-Buffered Mode
Figure 25. AD7225 to 68008 Interface,
Single-Buffered Mode
VSS GENERATIO N
A15
ADDRESS BUS
A0
Operating the AD7225 from dual supplies results in enhanced
performance over single supply operation on a number of pa-
rameters as previously outlined. Some applications may require
this enhanced performance, but may only have a single power
supply rail available. T he circuit of Figure 26 shows a method of
generating a negative voltage using one CD4049, operated from
a VDD of +15 V. T wo inverters of the hex inverter chip are used
as an oscillator. T he other four inverters are in parallel and used
as buffers for higher output current. T he square-wave output is
level translated to a negative-going signal, then rectified and fil-
tered. T he circuit configuration shown will provide an output
voltage of –5.1 V for current loadings in the range 0.5 mA to
9 mA. T his will satisfy the AD7225 ISS requirement over the
commercial operating temperature range.
A0
A1
6809/
6502
ADDRESS
DECODE
LDAC
AD7225*
WR
EN
R/W
E OR φ2
DB7
DB0
D7
D0
DATA BUS
LINEAR CIRCUITRY OMITTED FOR CLARITY
*
Figure 23. AD7225 to 6809/6502 Interface,
Single-Buffered Mode
A15
ADDRESS BUS
A8
1/6
CD4049AE
A0
A1
Z-80
1/6
CD4049AE
ADDRESS
DECODE
1/6
1/6
LDAC
CD4049AE CD4049AE
AD7225*
EN
MREQ
WR
1/6
CD4049AE
WR
510k
5.1k
DB7
DB0
1/6
CD4049AE
+
D7
D0
0.02µF
510Ω
47µF
47µF
DATA BUS
LINEAR CIRCUITRY OMITTED FOR CLARITY
–VOUT
5V1
*
1N4001
1N4001
+
Figure 24. AD7225 to Z-80 Interface,
Double-Buffered Mode
Figure 26. VSS Generation Circuit
–11–
REV. B
AD7225
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
24-P in P lastic (N-24)
24-Lead SO IC (R-24)
24-P in Cer dip (Q -24)
28-Ter m inal Leadless
Cer am ic Chip Car r ier (E-28A)
28-Lead P LCC (P -28A)
–12–
REV. B
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