AD7233_技术文档

LC²MOS

a

12-Bit Serial Mini-DIP DACPORT

AD7233

FUNCTIONAL BLOCK DIAGRAM

FEATURES

12-Bit CMOS DAC with

On-Chip Voltage Reference

Output Amplifier

–5 V to +5 V Output Range

Serial Interface

V

DD

2R

300 kHz DAC Update Rate

Small Size: 8-Pin Mini-DIP

Nonlinearity: ؎1/2 LSB T_MINto T_MAX

Low Power Dissipation: 100 mW typ

V

OUT

12-BIT

DAC

12

APPLICATIONS

Process Control

Industrial Automation

Digital Signal Processing Systems

Input/Output Ports

GND

DAC

LATCH

AD7233

12

INPUT SHIFT

REGISTER

V

SS

SDIN

SCLK

SYNC LDAC

GENERAL DESCRIPTION

The AD7233 is a complete 12-bit, voltage-output, digital-to-

analog converter with output amplifier and Zener voltage refer-

ence all in an 8-lead package. No external trims are required to

achieve full specified performance. The data format is two’s

complement, and the output range is –5 V to +5 V.

PRODUCT HIGHLIGHTS

1. Complete 12-Bit DACPORT^®.

The AD7233 features a fast, versatile serial interface which al-

lows easy connection to both microcomputers and 16-bit digital

signal processors with serial ports. When the SYNC input is

taken low, data on the SDIN pin is clocked into the input shift

register on each falling edge of SCLK. On completion of the

16-bit data transfer, bringing LDAC low updates the DAC latch

with the lower 12 bits of data and updates the output. Alterna-

tively, LDAC can be tied permanently low, and in this case the

DAC register is automatically updated with the contents of the

shift register when all sixteen data bits have been clocked in.

The serial data may be applied at rates up to 5 MHz allowing a

DAC update rate of 300 kHz.

2. The AD7233 is a complete, voltage output, 12-bit DAC on a

single chip. This single-chip design is inherently more reli-

able than multichip designs.

3. Simple 3-wire interface to most microcontrollers and DSP

processors.

4. DAC Update Rate—300 kHz.

5. Space Saving 8-Lead Package.

For applications which require greater flexibility and unipolar

output ranges with single supply operation, please refer to the

AD7243 data sheet.

The AD7233 is fabricated on Linear Compatible CMOS

(LC²MOS), an advanced, mixed-technology process. It is pack-

aged in an 8-lead DIP package.

DACPORT is a registered trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(V_DD= +12 V to +15 V,²V_SS= –12 V to –15 V,²GND = 0 V, R_L= 2 k⍀,

C_L= 100 pF to GND. All specifications T_MINto T_MAXunless otherwise noted.)

AD7233–SPECIFICATIONS¹

Parameter

A, B

Unit

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

12

1

0.9

6

8

30

Bits

Relative Accuracy³

LSB max

ppm of FSR/°C typ

Differential Nonlinearity³

Bipolar Zero Error³

Guaranteed Monotonic

DAC Latch Contents 0000 0000 0000

Full-Scale Error³

Full-Scale Temperature Coefficient⁴

Guaranteed By Process

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

2.4

0.8

V min

V max

I_IN

1

8

µA max

pF max

V_IN= 0 V to V_DD

Input Capacitance⁴

ANALOG OUTPUTS

Output Voltage Range

DC Output Impedance⁴

5

0.5

V

Ω typ

AC CHARACTERISTICS⁴

Voltage Output Settling Time

Positive Full-Scale Change

Negative Full-Scale Change

Digital-to-Analog Glitch Impulse³

Digital Feedthrough³

Settling Time to Within 1/2 LSB of Final Value

Typically 4 µs; DAC Latch 100. . .000 to 011. . .111

Typically 5 µs; DAC Latch 011. . .111 to 100. . .000

DAC Latch Contents Toggled Between All 0s and all 1s

LDAC = High

10

30

10

µs max

nV secs typ

POWER REQUIREMENTS

V_DDRange

V_SSRange

I_DD

+10.8/+16.5

–10.8/–16.5

10

2

V min/V max

mA max

For Specified Performance Unless Otherwise Stated

Output Unloaded; Typically 7 mA at Thresholds

Output Unloaded; Typically 1 mA at Thresholds

I_SS

mA max

NOTES

¹Temperature Ranges are as follows: A, B Versions: –40°C to +85°C.

²Power Supply Tolerance: A, B Versions: 10%.

³See Terminology.

⁴Guaranteed by design and characterization, not production tested.

Specifications subject to change without notice.

(V_DD= +10.8 V to +16.5 V, V_SS= –10.8 V to –16.5 V, GND = O V, R_L= 2 k⍀,

C_L= 100 pF. All Specifications T_MINto T_MAXunless otherwise noted.)

TIMING CHARACTERISTICS^{1, 2}

Limit at +25؇C, T_MIN, T_MAX

Parameter

(All Versions)

Unit

Conditions/Comments

3

t₁

200

15

70

0

40

0

ns min

SCLK Cycle Time

t₂

t₃

t₄

t₅

t₆

t₇

t₈

SYNC to SCLK Falling Edge Setup Time

SYNC to SCLK Hold Time

Data Setup Time

Data Hold Time

SYNC High to LDAC Low

LDAC Pulsewidth

20

0

LDAC High to SYNC Low

NOTES

¹Sample tested at +25°C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

²See Figure 3.

³SCLK Mark/Space Ratio range is 40/60 to 60/40.

–2–

REV. A

AD7233

ABSOLUTE MAXIMUM RATINGS¹

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

(T_A= +25°C unless otherwise noted)

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V

_SSto GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V

V_OUT²to GND . . . . . . . . . . . . . . . . . . . . –6 V to V_DD+0.3 V

Digital Inputs to GND . . . . . . . . . . . . . –0.3 V to V_DD+0.3 V

Operating Temperature Range

²The output may be shorted to voltages in this range provided the power dissipation

of the package is not exceeded. Short circuit current is typically 80 mA.

Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C

Power Dissipation to +75°C . . . . . . . . . . . . . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V

ORDERING GUIDE

Temperature

Range

Relative

Accuracy

Package

Option*

Model

AD7233AN

AD7233BN

–40°C to +85°C

1 LSB

1/2 LSB

N-8

*N = Plastic DIP.

TERMINOLOGY

FULL-SCALE ERROR

RELATIVE ACCURACY (LINEARITY)

Full-scale error is a measure of the output error when the am-

plifier output is at full scale (full scale is either positive or nega-

tive full scale).

Relative accuracy, or endpoint linearity, is a measure of the

maximum deviation of the DAC transfer function from a straight

line passing through the endpoints of the transfer function. It is

measured after allowing for zero and full-scale errors and is ex-

pressed in LSBs or as a percentage of full-scale reading.

DIGITAL-TO-ANALOG GLITCH IMPULSE

This is the voltage spike that appears at the output of the DAC

when the digital code in the DAC latch changes before the out-

put settles to its final value. The energy in the glitch is specified

in nV secs, and is measured for an all codes change (0000 0000

0000 to 1111 1111 1111).

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB or less

over the operating temperature range ensures monotonicity.

DIGITAL FEEDTHROUGH

This is a measure of the voltage spike that appears on V_OUTas a

result of feedthrough from the digital inputs on the AD7233. It

is measured with LDAC held high.

BIPOLAR ZERO ERROR

Bipolar zero error is the voltage measured at V_OUTwhen the

DAC is loaded with all 0s. It is due to a combination of offset

errors in the DAC, amplifier and mismatch between the internal

gain resistors around the amplifier.

REV. A

–3–

AD7233

PIN FUNCTION DESCRIPTION

Mnemonic

Description

1

2

3

4

V_DD

Positive Supply (+12 V to +15 V).

Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.

Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.

Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in

readiness for a new data word.

SCLK

SDIN

SYNC

5

LDAC

Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of

this signal, or alternatively if this line in permanently low, an automatic update mode is selected whereby

the DAC is updated on the 16th falling SCLK pulse.

6

7

8

GND

V_OUT

V_SS

Ground Pin = 0 V.

Analog Output Voltage. This is the buffered DAC output voltage (–5 V to +5 V).

Negative Supply (–12 V to –15 V).

V

1

2

3

4

8

7

6

5

DD

SS

AD7233

V

SCLK

SDIN

OUT

TOP VIEW

(Not to Scale)

GND

SYNC

LDAC

CIRCUIT INFORMATION

D/A Section

The AD7233 contains a 12-bit voltage-mode D/A converter

consisting of highly stable thin-film resistors and high speed

NMOS single-pole, double-throw switches.

DIGITAL INTERFACE

The AD7233 contains an input serial to parallel shift register

and a DAC latch. A simplified diagram of the input loading cir-

cuitry is shown in Figure 2. Serial data on the SDIN input is

loaded to the input register under control of SYNC and SCLK.

When a complete word is held in the shift register it may then be

loaded into the DAC latch under control of LDAC. Only the

data in the DAC latch determines the analog output on the

AD7233.

Op Amp Section

The output of the voltage-mode D/A converter is buffered by a

noninverting CMOS amplifier. The buffer amplifier is capable

of developing 5 V across a 2 kΩ load to GND.

A low SYNC input provides the frame synchronization signal

which tells the AD7233 that valid serial data on the SDIN input

will be available for the next 16 falling edges of SCLK. An inter-

nal counter/decoder circuit provides a low gating signal so that

only 16 data bits are clocked into the input shift register. After

16 SCLK pulses the internal gating signal goes inactive (high)

thus locking out any further clock pulses. Therefore, either a

continuous clock or a burst clock source may be used to clock in

the data.

R

V

OUT

2R

INTERNAL

REFERENCE

DB0 DB1

DB9 DB10

DB11

5V

GND

Figure 1. Simplified D/A Converter

The SYNC input should be taken high after the complete 16-bit

word is loaded in.

Although 16 bits of data are clocked into the input register, only

the latter 12 bits get transferred into the DAC latch. The first 4

bits in the 16-bit stream are don’t cares since their value does

not affect the DAC latch data. Therefore the data format is 4

don’t cares followed by the 12-bit data word with the LSB as the

last bit in the serial stream.

–4–

REV. A

AD7233

There are two ways in which the DAC latch and hence the ana-

log output may be updated. The status of the LDAC input is

examined after SYNC is taken low. Depending on its status, one

of two update modes is selected.

If LDAC = 1 then the automatic update is disabled and the

DAC latch is updated by taking LDAC low any time after the

16-bit data transfer is complete. The update now occurs on the

falling edge of LDAC. This facility is useful for simultaneous

update in multi-DAC systems. Note that the LDAC input must

be taken back high again before the next data transfer is initiated.

If LDAC = 0 then the automatic update mode is selected. In

this mode the DAC latch and analog output are updated auto-

matically when the last bit in the serial data stream is clocked in.

The update thus takes place on the sixteenth falling SCLK edge.

SYNC

RESET

GATING

SIGNAL

–16

COUNTER/

DECODER

GATED

SCLK

SDIN

INPUT SHIFT REGISTER (16 BITS)

AUTO-UPDATE

CIRCUITRY

DAC LATCH (12 BITS)

LDAC

Figure 2. Simplified Loading Structure

t₁

SCLK

t₂

t₃

SYNC

SDIN

t₄

t₅

DB15

DB14

DB13

DB12

DB11

MSB

DB0

LSB

DB1

DON'T CARE DON'T CARE DON'T CARE DON'T CARE

t₆

t₇

t₈

LDAC

Figure 3. Timing Diagram

REV. A

–5–

AD7233–Typical Performance Graphs

100

0.50

500

200

OUTPUT WITH ALL

0s ON DAC

90

DECOUPLING

NO DECOUPLING

DECOUPLING

V

= +15V

= – 15V

DD

0.40

80

70

60

SS

OUTPUT WITH ALL

1s ON DAC

T

= +25 C

A

0.30

0.20

0.10

0

100

50

40

30

20

10

0

NO DECOUPLING

T

= +25 C

A

20

0

OUTPUT WITH ALL

V

= +15V WITH

DD

0s ON DAC

100mV p–p SIGNAL

10

100

1k

FREQUENCY – Hz

10k

100k

10.5 11

12

13

14

15

16

100 200 500

2k

5k

10k

20k

100k

50

1k

50k

V

/V – Volts

FREQUENCY – Hz

SS

DD

*

POWER SUPPLY DECOUPLING CAPACITORS

ARE 10µF AND 0.1µF.

Linearity vs. Power Supply Voltage

Noise Spectral Density

vs. Frequency

Power Supply Rejection Ratio

vs. Frequency

APPLYING THE AD7233

Bipolar (؎5 V) Configuration

Table I. AD7233 Bipolar Code Table

The AD7233 provides an output voltage range from –5 V to

+5 V without any external components. This configuration is

shown in Figure 4. The data format is two's complement. The

output code table is shown in Table I. If offset binary coding is

required, then this can be done by inverting the MSB in soft-

ware before the data is loaded to the AD7233.

Input Data Word

MSB

LSB

Analog Output, V_OUT

XXXX 0111 1111 1111

XXXX 0000 0000 0001

XXXX 0000 0000 0000

XXXX 1111 1111 1111

XXXX 1000 0000 0001

XXXX 1000 0000 0000

+5 V • (2047/2048)

+5 V • (1/2048)

0 V

–5 V • (1/2048)

–5 V • (2047/2048)

–5 V • (2048/2048) = –5 V

+12V TO

+15V

V

DD

2R

X = Don’t Care

AD7233

Note: 1 LSB = 5 V/2048 ≈ 2.4 mV

V

OUT

12-BIT

DAC

+5V

V

GND

SS

–12V TO

–15V

Figure 4. Circuit Configuration

Power Supply Decoupling

To achieve optimum performance when using the AD7233, the

V_DDand V_SSlines should each be decoupled to GND using

0.1 µF capacitors. In very noisy environments it is recom-

mended that 10 µF capacitors be connected in parallel with the

0.1 µF capacitors.

–6–

REV. A

AD7233

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD7233 is via a serial bus

which uses standard protocol compatible with DSP processors

and microcontrollers. The communications channel requires a

three-wire interface consisting of a clock signal, a data signal and

a synchronization signal. The AD7233 requires a 16-bit data

word with data valid on the falling edge of SCLK. For all of the

interfaces, the DAC update may be done automatically when all

the data is clocked in or it may done under control of LDAC.

LDAC

DSP56000

AD7233*

SCK

SCLK

SDIN

STD

SC2

Figures 5 to 8 show the AD7233 configured for interfacing to a

number of popular DSP processors and microcontrollers.

SYNC

AD7233–ADSP-2101/ADSP-2102 Interface

Figure 5 shows a serial interface between the AD7233 and the

ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/

ADSP-2102 contains two serial ports, and either port may be

used in the interface. The data transfer is initiated by TFS going

low. Data from the ADSP-2101/ADSP-2102 is clocked into the

AD7233 on the falling edge of SCLK. When the data transfer is

complete TFS is taken high. In the interface shown the DAC is

updated using an external timer which generates an LDAC

pulse. This could also be done using a control or decoded ad-

dress line from the processor. Alternatively, the LDAC input

could be hardwired low, and in this case the automatic update

mode is selected whereby the DAC update takes place automati-

cally on the 16th falling edge of SCLK.

* ADDITIONAL PINS OMITTED FOR CLARITY

Figure 6. AD7233 to DSP56000 Interface

AD7233–87C51 Interface

A serial interface between the AD7233 and the 87C51 micro-

controller is shown in Figure 7. TXD of the 87C51 drives

SCLK of the AD7233 while RXD drives the serial data line of

the part. The SYNC signal is derived from the port line P3.3.

The 87C51 provides the LSB of its SBUF register as the first bit

in the serial data stream. Therefore, the user will have to ensure

that the data in the SBUF register is arranged correctly so that

the don’t care bits are the first to be transmitted to the AD7233

and the last bit to be sent is the LSB of the word to be loaded to

the AD7233. When data is to be transmitted to the part, P3.3 is

taken low. Data on RXD is valid on the falling edge of TXD.

The 87C51 transmits its serial data in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. To load data

to the AD7233, P3.3 is kept low after the first eight bits are

transferred and a second byte of data is then transferred serially

to the AD7233. When the second serial transfer is complete, the

P3.3 line is taken high.

TIMER

LDAC

ADSP-2101/

ADSP-2102*

AD7233*

Figure 7 shows the LDAC input of the AD7233 hardwired low.

As a result, the DAC latch and the analog output will be up-

dated on the sixteenth falling edge of TXD after the SYNC sig-

nal for the DAC has gone low. Alternatively, the scheme used in

previous interfaces, whereby the LDAC input is driven from a

timer, can be used.

TFS

SCLK

DT

SYNC

SCLK

SDIN

* ADDITIONAL PINS OMITTED FOR CLARITY

Figure 5. AD7233 to ADSP-2101/ADSP-2102 Interface

LDAC

AD7233-DSP56000 Interface

A serial interface between the AD7233 and the DSP56000 is

shown in Figure 6. The DSP56000 is configured for Normal

Mode Asynchronous operation with Gated Clock. It is also set

up for a 16-bit word with SCK and SC2 as outputs and the FSL

control bit set to a 0. SCK is internally generated on the

DSP56000 and applied to the AD7233 SCLK input. Data from

the DSP56000 is valid on the falling edge of SCK. The SC2

output provides the framing pulse for valid data. This line must

be inverted before being applied to the SYNC input of the

AD7233.

87C51*

AD7233*

P3.3

SYNC

TXD

RXD

SCLK

SDIN

* ADDITIONAL PINS OMITTED FOR CLARITY

The LDAC input of the AD7233 is connected to GND so the

update of the DAC latch takes place automatically on the 16th

falling edge of SCLK. An external timer could also be used as in

the previous interface if an external update is required.

Figure 7. AD7233 to 87C51 Interface

REV. A

–7–

AD7233

AD7233-68HC11 Interface

Figure 8 shows a serial interface between the AD7233 and the

68HC11 microcontroller. SCK of the 68HC11 drives SCLK of

the AD7233 while the MOSI output drives the serial data line.

The SYNC signal is derived from a port line (PC7 shown).

LDAC

AD7233*

68HC11*

For correct operation of this interface, the 68HC11 should be

configured such that its CPOL bit is a 0 and its CPHA bit is a

1. When data is to be transmitted to the part, PC7 is taken low.

When the 68HC11 is configured like this, data on MOSI is

valid on the falling edge of SCK. The 68HC11 transmits its se-

rial data in 8-bit bytes with only eight falling clock edges occur-

ring in the transmit cycle. To load data to the AD7233, PC7 is

kept low after the first eight bits are transferred and a second

byte of data is then transferred serially to the AD7233. When

the second serial transfer is complete, the PC7 line is taken

high. Figure 8 shows the LDAC input of the AD7233 hard-

wired low. As a result, the DAC latch and the analog output of

the DAC will be updated on the sixteenth falling edge of SCK

after the respective SYNC signal has gone low. Alternatively,

the scheme used in previous interfaces, whereby the LDAC in-

put is driven from a timer, can be used.

PC7

SCK

SYNC

SCLK

SDIN

MOSI

* ADDITIONAL PINS OMITTED FOR CLARITY

Figure 8. AD7233 to 68HC11 Interface

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic DIP (N-8) Package

8

1

5

0.280 (7.11)

0.240 (6.10)

4

0.430 (10.92)

0.348 (8.84)

0.325 (8.25)

0.300 (7.62)

0.060 (1.52)

0.015 (0.38)

0.210

(5.33)

MAX

0.195 (4.95) MAX

0.015 (0.381)

0.008 (0.204)

0.150

(3.81)

MIN

0.022 (0.558)

0.014 (0.356)

0.100 BSC

(2.54 BSC)

0.70 (1.77)

0.045 (1.15)

–8–

REV. A


型号：	AD7233
厂家：	ADI
描述：	LC2MOS 12-Bit Serial Mini-DIP DACPORT LC2MOS 12位串行的Mini- DIP DACPORT
文件：	总8页 (文件大小：101K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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