AD7243BR [ADI]
LC2MOS 12-Bit Serial DACPORT; LC2MOS 12位串行DACPORT
| 型号： | AD7243BR |
| 厂家： | 
ADI |
| 描述： | LC2MOS 12-Bit Serial DACPORT |
| 文件： | 总12页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
12-Bit Serial DACPORT
a
AD7243
FEATURES
12-Bit CMOS DAC with
On-Chip Voltage Reference
Output Amplifier
FUNCTIONAL BLOCK DIAGRAM
V
DD
Three Selectable Output Ranges
–5 V to +5 V, 0 V to +5 V, 0 V to +10 V
Serial Interface
300 kHz DAC Update Rate
Small Size: 16-Lead DIP or SOIC
Nonlinearity: ؎1/2 LSB TMIN to TMAX
Low Power Dissipation: 100 mW Typical
2R
REFOUT
REFIN
R
OFS
2R
V
OUT
12 - BIT DAC
12
AGND
DGND
DAC LATCH
12
AD7243
APPLICATIONS
Process Control
INPUT SHIFT REGISTER
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports
V
SS
SDIN CLR
SCLK SYNC
LDAC
BIN/
DCEN SDO
COMP
The AD7243 is fabricated on Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process. It is pack-
aged in 16-lead DIP and 16-lead SOIC packages.
GENERAL DESCRIPTION
The AD7243 is a complete 12-bit, voltage output, digital-to-
analog converter with output amplifier and Zener voltage refer-
ence on a monolithic CMOS chip. No external trims are
required to achieve full specified performance.
PRODUCT HIGHLIGHTS
1. Complete 12-Bit DACPORT®
The output amplifier is capable of developing +10 V across a
2 kΩ load. The output voltage ranges with single supply opera-
tion are 0 V to +5 V or 0 V to +10 V, while an additional bipo-
lar 5 V output range is available with dual supplies. The ranges
are selected using the internal gain resistor.
The AD7243 is a complete, voltage output, 12-bit DAC on
a single chip. The single chip design is inherently more
reliable than multichip designs.
2. Single or Dual Supply Operation.
3. Minimum 3-wire interface to most DSP processors.
4. DAC Update Rate–300 kHz.
The data format is natural binary in both unipolar ranges, while
either offset binary or two’s complement format may be selected
in the bipolar range. A CLR function is provided which sets the
output to 0 V in both unipolar ranges and in the two’s comple-
ment bipolar range, while with offset binary data format, the
output is set to –REFIN. This function is useful as a power-on
reset as it allows the output to be set to a known voltage level.
5. Serial Data Output allows easy daisy-chaining in multiple
DAC systems.
The AD7243 features a fast versatile serial interface which
allows easy connection to both microcomputers and 16-bit digi-
tal signal processors with serial ports. The serial data may be
applied at rates up to 5 MHz allowing a DAC update rate of
300 kHz. A serial data output capability is also provided which
allows daisy chaining in multi-DAC systems. This feature allows
any number of DACs to be used in a system with a simple
4-wire interface. All DACs may be updated simultaneously
using LDAC.
DACPORT is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(VDD = +12 V to +15 V,1 VSS = 0 V or –12 V to –15 V,1 AGND = DGND = O V, REFIN = +5 V,
RL = 2 k⍀, CL = 100 pF to AGND. All Specifications TMIN to TMAX unless otherwise noted.)
AD7243–SPECIFICATIONS
Parameter
A2
B2
S2
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
1
0.9
12
1/2
0.9
4
12
1
0.9
Bits
Relative Accuracy3
LSB max
LSB max
LSB max
Differential Nonlinearity3
Unipolar Offset Error3
Guaranteed Monotonic
4
5
VSS = 0 V or –12 V to –15 V1; DAC Latch
Contents All 0s
Bipolar Zero Error3
5
6
5
5
6
5
6
7
5
LSB max
LSB max
VSS = –12 V to –15 V1; DAC Latch Contents All 0s
Full-Scale Error3, 4
Full-Scale Temperature Coefficient5
ppm of FSR/ Guaranteed By Process
°C typ
REFERENCE OUTPUT
Reference Output Range, REFOUT
Reference Temperature Coefficient5
Reference Load Change
4.95/5.05
25
4.95/5.05
25
4.95/5.05
30
V min/V max
ppm/°C typ
Guaranteed By Process
(∆REFOUT VS. IL)
–1
–1
–1
mV max
Reference Load Current (IL) Change (0–100 µA)
REFERENCE INPUT
Reference Input Range, REFIN
Input Current
4.95/5.05
5
4.95/5.05
5
4.95/5.05
5
V min/V max 5 V 1% for Specified Performance
µA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
1
2.4
0.8
1
2.4
0.8
1
V min
V max
µA max
pF max
VIN = 0 V to VDD
Input Capacitance5
8
8
8
DIGITAL OUTPUT
Serial Data Out (SDO)
Output Low Voltage, VOL
Output High Voltage, VOH
0.4
4.0
0.4
4.0
0.4
4.0
V max
V min
ISINK = 1.6 mA
ISOURCE = 400 µA
ANALOG OUTPUT
Output Range Resistor, ROFS
Output Voltage Ranges6
Output Voltage Ranges6
DC Output Impedance5
15/30
15/30
15/30
kΩ min/max
Typically 20 k⍀. Guaranteed By Process
Single Supply; VSS = 0 V
Dual Supply; VSS = –12 V to –15 V
+5, +10
+5, +10,
0.5
+5, +10
+5, +10,
0.5
+5, +10
+5, +10,
0.5
V
5
5
5
V
Ω typ
AC CHARACTERISTICS5
Voltage Output Settling-Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse3
Settling Time to Within 1/2 LSB of Final Value
10
10
30
10
10
30
10
10
30
µs max
Typically 4 µs
Typically 5 µs
DAC Latch Contents Toggled Between All 0s
µs max
nV secs typ
and All 1s
LDAC = High
Digital Feedthrough3
10
10
10
nV secs typ
POWER REQUIREMENTS
VDD Range
VSS Range (Dual Supplies)
IDD
+10.8/+16.5 +10.8/+16.5 +11.4/+15.75 V min/V max For Specified Performance Unless Otherwise Stated
–10.8/–16.5 –10.8/–16.5 –11.4/–15.75 V min/V max For Specified Performance Unless Otherwise Stated
10
10
10
mA max
Output Unloaded; Typically 7 mA
ISS (Dual Supplies)
2
2
2
mA max
Output Unloaded; Typically 1 mA
NOTES
1Power Supply Tolerance A, B Versions: 10%; S Version: 5%.
2Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
3See terminology.
4Measured with respect to REFIN and includes unipolar/bipolar offset error.
5Guaranteed by design and characterization, not production tested.
60 V to +10 V output range is available only with VDD ≥ +14.25 V.
Specifications subject to change without notice.
REV. A
–2–
AD7243
(VDD = +10.8 V to +16.5 V, VSS = 0 V or –10.8 V to –16.5 V, AGND = DGND = 0 V,
TIMING CHARACTERISTICS1, 2
RL = 2 k⍀, CL = 100 pF. All Specifications TMIN to TMAX unless otherwise noted.)
Limit at +25؇C, TMIN, TMAX
Parameter
(All Versions)
Units
Conditions/Comments
3
t1
200
15
70
0
40
0
20
0
20
160
>t5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
SCLK Cycle Time
t2
t3
t4
t5
t6
t7
t8
t9
SYNC to SCLK Falling Edge Setup Time
SYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
SYNC High to LDAC Low
LDAC Pulsewidth
LDAC High to SYNC Low
CLR Pulsewidth
SCLK Falling Edge to SDO Valid
SCLK Falling Edge to SDO Invalid
4, 5
t10
4, 6
t11
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 7 & 8.
3SCLK mark/space ratio range is 40/60 to 60/40.
4SDO load capacitance is no greater than 50 pF.
5At 25°C t10 is 130 ns max.
6Guaranteed by design.
ABSOLUTE MAXIMUM RATINGS1
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
(TA = +25°C unless otherwise noted)
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
VDD to AGND, DGND . . . . . . . . . . . . . . . . . –0.3 V to +17 V
SS to AGND, DGND . . . . . . . . . . . . . . . . . +0.3 V to –17 V
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VOUT2 to AGND . . . . . . . . . . . . . . . . . . . –6 V to VDD + 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD
REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
SDO to DGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.
2The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. Short circuit current is typically 80 mA.
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
ORDERING GUIDE
Temperature Range
Model
Relative Accuracy
Package Option1
AD7243AN
AD7243BN
AD7243AR
AD7243BR
AD7243AQ
AD7243BQ
AD7243SQ2
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
1/2 LSB
N-16
N-16
R-16
R-16
Q-16
Q-16
Q-16
1 LSB
NOTES
1N = Plastic DIP; R = SOIC; Q = Cerdip.
2Available to /883B processing only. Contact your local sales office for military data sheet.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7243 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD7243
TERMINOLOGY
Bipolar Zero Error
Relative Accuracy (Linearity)
Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func-
tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.
Bipolar Zero Error is the voltage measured at VOUT when the
DAC is configured for bipolar output and loaded with all 0s
(Two’s Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis-
tors around the amplifier.
Single Supply Linearity and Gain Error
The output amplifier on the AD7243 can have true negative off-
sets even when the part is operated from a single +15 V supply.
However, because the negative supply rail (VSS) is 0 V, the out-
put cannot actually go negative. Instead, when the output offset
voltage is negative, the output voltage sits at 0 V, resulting in the
transfer function shown in Figure 1.
Full-Scale Error
Full-Scale Error is a measure of the output error when the am-
plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.
Digital-to-Analog Glitch Impulse
This is the voltage spike that appears at VOUT when the digital
code in the DAC latch changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs, and
is measured for an all codes change from 0000 0000 0000 to
1111 1111 1111 and vice versa.
OUTPUT
VOLTAGE
0V
DAC CODE
Digital Feedthrough
NEGATIVE
OFFSET
{
This is a measure of the voltage spike that appears on VOUT as a
result of feedthrough from the digital inputs on the AD7243. It
is measured with LDAC held high.
Figure 1. Effect of Negative Offset (Single Supply)
AD7243 PIN FUNCTION DESCRIPTIONS (DIP and SOIC PIN NUMBERS)
Description
Pin Mnemonic
1
2
3
4
REFIN
Voltage Reference Input. It is internally buffered before being applied to the DAC. The nominal reference
voltage for specified operation of the AD7243 is 5 V.
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part -
using its internal reference, REFOUT should be connected to REFIN.
Clear, Logic Input. Taking this input low sets VOUT to 0 V in both unipolar ranges and the two’s complement
bipolar range and to –REFIN in the offset binary bipolar range.
Logic Input. This input selects the data format to be either binary or two’s complement. In both unipolar
ranges, natural binary format is selected by connecting this input to a Logic “0.” In the bipolar configuration,
offset binary format is selected with a Logic “0” while a Logic “1” selects two’s complement format.
REFOUT
CLR
BIN/COMP
5
6
7
SCLK
SDIN
SYNC
Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readiness for a
new data word.
8
9
DGND
LDAC
Digital Ground. Ground reference for all digital circuitry.
Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of this
signal or alternatively if this line is permanently low, an automatic update mode is selected whereby the DAC
is updated on the 16th falling SCLK pulse.
10 DCEN
11 SDO
Daisy-Chain Enable, Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise
this pin must be connected low.
Serial Data Out, Logic Output. With DCEN at Logic “1” this output is enabled, and the serial data in the
input shift register is clocked out on each falling SCLK edge.
12 AGND
13 ROFS
Analog Ground. Ground reference for all analog circuitry.
Output Offset Resistor for the amplifier. It is connected to VOUT for the +5 V range, to AGND for the +10 V
range and to REFIN for the –5 V to +5 V range.
14 VOUT
15 VSS
16 VDD
Analog Output Voltage. This is the buffer amplifier output voltage. Three different output voltage ranges can
be chosen: 0 V to +5 V, 0 to +10 V and –5 V to +5 V.
Negative Power Supply (used for the output amplifier only, may be connected to 0 V for single supply
operation or to –12 V to –15 V for dual supplies).
Positive Power Supply (+12 V to +15 V).
REV. A
–4–
AD7243
TERMINOLOGY (Continued)
Internal Reference
This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the out-
put voltage could have gone negative.
The AD7243 has an on-chip temperature compensated buried
Zener reference which is factory trimmed to 5 V 50 mV. The
reference voltage is provided at the REFOUT pin. This refer-
ence can be used to provide the reference voltage for the D/A
converter (by connecting the REFOUT pin to the REFIN pin.)
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7243 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500 µA to an ex-
ternal load. The maximum recommended capacitance on
REFOUT for normal operation is 50 pF. If the reference is re-
quired for external use with capacitive loads greater than 50 pF
then it should be decoupled to AGND with a 200 Ω resistor in
series with a parallel combination of a 10 µF tantalum capacitor
and a 0.1 µF ceramic capacitor.
Differential Nonlinearity
200⍀
EXT
LOAD
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB or less
over the operating temperature range ensures monotonicity.
REFOUT
0.1F
10F
Figure 3. Reference Decoupling Scheme
External Reference
Unipolar Offset Error
Unipolar Offset Error is the measured output voltage from
V
OUT with all zeros loaded into the DAC latch when the DAC is
In some applications, the user may require a system reference or
some other external reference to drive the AD7243. References
such as the AD586 provide an ideal external reference source
(see Figure 10). The REFIN voltage is internally buffered by a
unity gain amplifier before being applied to the D/A converter.
The D/A converter is scaled for a 5 V reference and the device is
tested with 5 V applied to REFIN. Other reference voltages may
be used with degraded performance. Figure 4 shows the typical
degradation in linearity vs. REFIN.
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
PIN CONFIGURATION
DIP and SOIC
1
2
16
REFIN
V
V
DD
15
14
13
REFOUT
CLR
SS
V
AD7243
OUT
3
4
1.0
BIN/COMP
R
OFS
V
V
= +15V
= –15V
= +25؇C
TOP VIEW
DD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
(Not to Scale)
SS
AGND
12
5
6
SCLK
SDIN
T
A
11 SDO
10
9
SYNC
7
8
DCEN
LDAC
DGND
INL
CIRCUIT INFORMATION
D/A Section
The AD7243 contains a 12-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. The output voltage
from the converter has the same polarity as the reference volt-
age, REFIN, allowing single supply operation.
DNL
2
3
4
5
6
7
8
9
REFIN – Volts
Figure 4. Typical Linearity vs. REFIN Voltage
Op Amp Section
The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The ROFS input allows three out-
put voltage ranges to be selected. The buffer amplifier is capable
of developing +10 V across a 2 kΩ load to AGND.
2R
2R
R
OFS
R
R
R
R
R
V
OUT
2R
2R
2R
2R
2R
2R
DB0
DB9
DB10
DB11
DB1
The output amplifier can be operated from a single +12 V to
+15 V supply by tying VSS = 0 V.
SHOWN FOR ALL 1S
ON DAC
REFIN*
The amplifier can also be operated from dual supplies to allow
an additional bipolar output range of –5 V to +5 V. Dual supplies are
necessary for the bipolar output range but can also be used for
the unipolar ranges to give faster settling time to voltages near
AGND
*BUFFERED REFIN VOLTAGE
Figure 2. D/A Simplified Circuit Diagram
REV. A
–5–
AD7243
0 V, to allow full sink capability of 2.5 mA over the entire
output range and to eliminate the effects of negative offsets on
the transfer characteristic (outlined previously). A plot of the
output sink capability of the amplifier is shown in Figure 5.
circuitry is shown in Figure 6. Serial data on the SDIN input is
loaded to the input register under control of DCEN, SYNC and
SCLK. When a complete word is held in the shift register, it
may then be loaded into the DAC latch under control of
LDAC. Only the data in the DAC latch determines the analog
output on the AD7243.
3
The DCEN (daisy-chain enable) input is used to select either a
standalone mode or a daisy-chain mode. The loading format is
slightly different depending on which mode is selected.
V
= –15V
SS
2
V
= 0V
SS
Serial Data Loading Format (Standalone Mode)
With DCEN at Logic 0 the standalone mode is selected. In this
mode a low SYNC input provides the frame synchronization
signal which tells the AD7243 that valid serial data on the SDIN
input will be available for the next 16 falling edges of SCLK. An
internal counter/decoder circuit provides a low gating signal so
that only 16 data bits are clocked into the input shift register.
After 16 SCLK pulses the internal gating signal goes inactive
(high) thus locking out any further clock pulses. Therefore, ei-
ther a continuous clock or a burst clock source may be used to
clock in the data.
1
0
4
2
6
8
10
0
OUTPUT VOLTAGE – Volts
Figure 5. Amplifier Sink Current
DIGITAL INTERFACE
The AD7243 contains an input serial to parallel shift register
and a DAC latch. A simplified diagram of the input loading
The SYNC input should be taken high after the complete 16-bit
word is loaded in.
DCEN
SYNC
RESET
EN
÷
16
GATING
SIGNAL
COUNTER/
DECODER
GATED
INPUT SHIFT REGISTER (16 BITS)
SCLK
SCLK
SDIN
SDO
AUTO – UPDATE
CIRCUITRY
LDAC
CLR
DAC LATCH (12 BITS)
Figure 6. Simplified Loading Structure
t1
SCLK
SYNC
t2
t3
t4
t5
DB11
MSB
DB0
LSB
DB15
*
DB14
*
DB13
*
DB12*
SDIN
t6
t7
t8
LDAC
t9
CLR
*
= DON'T CARE
Figure 7. Timing Diagram (Standalone Mode)
–6–
REV. A
AD7243
Although 16 bits of data are clocked into the input register, only
the latter 12 bits get transferred into the DAC latch. The first 4
bits in the 16 bit stream are don’t cares since their value does
not affect the DAC latch data. Therefore, the data format is 4
don’t cares followed by the 12-bit data word with the LSB as
the last bit in the serial stream.
SYNC is low. The data is clocked into the register on each fall-
ing SCLK edge after SYNC going low. If more than 16 clock
pulses are applied, the data ripples out of the shift register and
appears on the SDO line. By connecting this line to the SDIN
input on the next AD7243 in the chain, a multi-DAC interface
may be constructed. Sixteen SCLK pulses are required for each
DAC in the system. Therefore, the total number of clock cycles
must equal 16N where N is the total number of devices in the
chain. When the serial transfer to all devices is complete, SYNC
should be taken high. This prevents any further data being
clocked into the input register.
There are two ways in which the DAC latch and hence the ana-
log output may be updated. The status of the LDAC input is
examined after SYNC is taken low. Depending on its status, one
of two update modes is selected.
If LDAC = 0, then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated auto-
matically when the last bit in the serial data stream is clocked in.
The update thus takes place on the sixteenth falling SCLK edge.
A continuous SCLK source may be used if it can be arranged
that SYNC is held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of clock
cycles may be used and SYNC taken high some time later.
If LDAC = 1, then the automatic update is disabled and the
DAC latch is updated by taking LDAC low any time after the
16-bit data transfer is complete. The update now occurs on the
falling edge of LDAC. Note that the LDAC input must be taken
back high again before the next data transfer is initiated.
When the transfer to all input registers is complete, a common
LDAC signal updates all DAC latches with the lower 12 bits of
data in each input register. All analog outputs are therefore up-
dated simultaneously on the falling edge of LDAC.
Clear Function (CLR)
Serial Data Loading Format (Daisy-Chain Mode)
The clear function bypasses the input shift register and loads the
DAC Latch with all 0s. It is activated by taking CLR low. In all
ranges except the Offset Binary bipolar range (–5 V to +5 V) the
output voltage is reset to 0 V. In the offset binary bipolar range
the output is set to –REFIN. The clear function is especially
useful at power-up as it enables the output to be reset to a
known state.
By connecting DCEN high the daisy-chain mode is enabled.
This mode of operation is designed for multi-DAC systems
where several AD7243s may be connected in cascade (see Fig-
ure 16). In this mode the internal gating circuitry on SCLK is
disabled, and a serial data output facility is enabled. The inter-
nal gating signal is permanently active (low) so that the SCLK
signal is continuously applied to the input shift register when
t1
SCLK
t2
t3
SYNC
t4
t5
DB11 (N)
MSB
DB0 (N)
LSB
DB15*
(N + 1)
DB11 (N + 1)
MSB
DB0 (N + 1)
LSB
DB15 (N)*
SDIN
t10
t11
DB11 (N)
MSB
DB0 (N)
LSB
DB15 (N)*
SDO
t6
t7
t8
UNDEFINED
LDAC
t9
CLR
* = DON'T CARE
Figure 8. Timing Diagram (Daisy-Chain Mode)
REV. A
–7–
AD7243
APPLYING THE AD7243
Power Supply Decoupling
Unipolar (0 V to +5 V) Configuration
The 0 V to +5 V output voltage range is achieved by connecting
To achieve optimum performance when using the AD7243, the
VDD and VSS lines should each be decoupled to DGND using
0.1 µF capacitors. In noisy environments it is recommended
that 10 µF capacitors be connected in parallel with the 0.1 µF
capacitors.
R
OFS to VOUT. Once again, the AD7243 can be operated using
either single or dual supplies. The table for output voltage vs.
digital code is as in Table I, with 2REFIN replaced by REFIN.
Note, for this range, 1 LSB = REFIN • (2–12 ) = (REFIN/4096).
Bipolar (؎5 V) Configuration
The internal scaling resistors provided on the AD7243 allow
several output voltage ranges. The part can produce unipolar
output ranges of 0 V to +5 V or 0 V to +10 V and a bipolar out-
put range of 5 V. Connections for the various ranges are out-
lined below.
The bipolar configuration for the AD7243, which gives an out-
put range of –5 V to +5 V, is achieved by connecting ROFS to
REFIN. The AD7243 must be operated from dual supplies to
achieve this output voltage range. Either offset binary or two’s
complement data format may be selected. Figure 10 shows the
connection diagram for bipolar operation. An AD586 provides
the reference voltage for the DAC but this could be provided by
the on-chip reference by connecting REFOUT to REFIN.
Unipolar (0 V to +10 V) Configuration
The first of the configurations provides an output voltage range
of 0 V to +10 V. This is achieved by connecting the output off-
set resistor ROFS (Pin 13) to AGND. Natural Binary data format
is selected by connecting BIN/COMP (Pin 4) to DGND. In this
configuration, the AD7243 can be operated using either single
or dual supplies. Note that the VDD supply must be ≥+14.25 V
for this range in order to maintain sufficient amplifier head-
room. Dual supplies may be used to improve settling time and
give increased current sink capability for the amplifier. Figure 9
shows the connection diagram for unipolar operation of the
AD7243. Table I shows the digital code vs. analog output for
this configuration.
V
DD
V
DD
R
OFS
2R
2R
+V
IN
V
OUT
AD586
V
OUT
REFIN
DAC
–5V TO + 5V
AD7243*
GND
V
BIN/ COMP
V
DD
AGND
DGND
SS
V
DD
V
V
SS
DD
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7243*
REFOUT
REFIN
2R
2R
R
OFS
Figure 10. Bipolar Configuration with External Reference
Bipolar Operation (Two’s Complement Data Format)
The AD7243 is configured for two’s complement data format
by connecting BIN/COMP (Pin 4) high. The analog output vs.
digital code is shown in Table II.
V
OUT
DAC
0V TO + 10V
BIN/
COMP
Table II. Two’s Complement Bipolar Code Table
Input Data Word
V
SS
AGND
DGND
0V OR V
SS
MSB
LSB Analog Output, VOUT
*ADDITIONAL PINS OMITTED FOR CLARITY
XXXX 0111 1111 1111
XXXX 0000 0000 0001
XXXX 0000 0000 0000
XXXX 1111 1111 1111
XXXX 1000 0000 0001
XXXX 1000 0000 0000
+REFIN × (2047/2048)
+REFIN × (1/2048)
0 V
–REFIN × (1/2048)
–REFIN × (2047/2048)
–REFIN × (2048/2048) = –REFIN
Figure 9. Unipolar (0 V to +10 V) Configuration
Table I. Unipolar Code Table (0 V to +10 V Range)
Input Data Word
MSB
LSB Analog Output, VOUT
X = Don’t Care.
Note: 1 LSB = REFIN/2048.
XXXX 1111 1111 1111 +2 REFIN × (4095/4096)
XXXX 1000 0000 0001 +2 REFIN × (2049/4096)
XXXX 1000 0000 0000 +2 REFIN × (2048/4096)= +REFIN
XXXX 0111 1111 1111 +2 REFIN × (2047/4096)
XXXX 0000 0000 0001 +2 REFIN × (1/4096)
XXXX 0000 0000 0000 0 V
Bipolar Operation (Offset Binary Data Format)
The AD7243 is configured for Offset Binary data format by
connecting BIN/COMP (Pin 4) low. The analog output vs. digi-
tal code may be obtained by inverting the MSB in Table II.
X = Don’t Care.
Note: 1 LSB = 2 REFIN/4096.
REV. A
–8–
AD7243
MICROPROCESSOR INTERFACING
AD7243–DSP56000 Interface
Microprocessor interfacing to the AD7243 is via a serial bus
which uses standard protocol compatible with DSP processors
and microcontrollers. The communications channel requires a
three-wire interface consisting of a clock signal, a data signal
and a synchronization signal. The AD7243 requires a 16-bit
data word with data valid on the falling edge of SCLK. For all
the interfaces, the DAC update may be done automatically
when all the data is clocked in or it may be done under control
of LDAC.
A serial interface between the AD7243 and the DSP56000 is
shown in Figure 12. The DSP56000 is configured for Normal
Mode Asynchronous operation with Gated Clock. It is also set
up for a 16-bit word with SCK and SC2 as outputs and the FSL
control bit set to a “0.” SCK is internally generated on the
DSP56000 and applied to the AD7243 SCLK input. Data from
the DSP56000 is valid on the falling edge of SCK. The SC2
output provides the framing pulse for valid data. This line must
be inverted before being applied to the SYNC input of the
AD7243.
Figures 11 to 16 show the AD7243 configured for interfacing to
a number of popular DSP processors and microcontrollers.
The LDAC input of the AD7243 is connected to DGND so the
update of the DAC latch takes place automatically on the six-
teenth falling edge of SCLK. An external timer could also be
used as in the previous interface if an external update is
required.
AD7243–ADSP-2101/ADSP-2102 Interface
Figure 11 shows a serial interface between the AD7243 and the
ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/
ADSP-2102 contains two serial ports, and either port may be
used in the interface. The data transfer is initiated by TFS going
low. Data from the ADSP-2101/ADSP-2102 is clocked into the
AD7243 on the falling edge of SCLK. When the data transfer is
complete, TFS is taken high. In the interface shown the DAC is
updated using an external timer which generates an LDAC
pulse. This could also be done using a control or decoded ad-
dress line from the processor. Alternatively, the LDAC input
could be hard wired low and in this case the update takes place
automatically on the sixteenth falling edge of SCLK.
LDAC
DSP56000
AD7243*
SCK
STD
SC2
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
TIMER
Figure 12. AD7243–DSP56000 Interface
AD7243–TMS32020 Interface
ADSP - 2101/
LDAC
Figure 13 shows a serial interface between the AD7243 and the
TMS32020 DSP processor. In this interface, the CLKX and
FSX signals for the TMS32020 should be generated using ex-
ternal clock/timer circuitry. The FSX pin of the TMS32020
must be configured as an input. Data from the TMS32020 is
valid on the falling edge of CLKX.
ADSP - 2102*
AD7243*
TFS
SCLK
DT
SYNC
SCLK
SDIN
The clock/timer circuitry generates the LDAC signal for the
AD7243 to synchronize the update of the output with the serial
transmission. Alternatively, the automatic update mode may be
selected by connecting LDAC to DGND.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. AD7243–ADSP-2101/ADSP-2102 Interface
CLOCK/
TIMER
LDAC
TMS32020
AD7243*
FSX
SYNC
SCLK
SDIN
CLKX
DX
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. AD7243–TMS32020 Interface
REV. A
–9–
AD7243
AD7243–87C51 Interface
Figure 15 shows the LDAC input of the AD7243 hardwired
low. As a result, the DAC latch and the analog output of the
DAC will be updated on the sixteenth falling edge of SCK after
the respective SYNC signal has gone low. Alternatively, the
scheme used in previous interfaces, whereby the LDAC input is
driven from a timer, can be used.
A serial interface between the AD7243 and the 87C51
microcontroller is shown in Figure 14. TXD of the 87C51 drives
SCLK of the AD7243, while RXD drives the serial data line of
the part. The SYNC signal is derived from the port line P3.3.
The 87C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
the don’t care bits are the first to be transmitted to the AD7243
and the last bit to be sent is the LSB of the word to be loaded to
the AD7243. When data is to be transmitted to the part, P3.3 is
taken low. Data on RXD is valid on the falling edge of TXD.
The 87C51 transmits its serial data in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. To load data
to the AD7243, P3.3 is left low after the first eight bits are trans-
ferred and a second byte of data is then transferred serially to the
AD7243. When the second serial transfer is complete, the P3.3
line is taken high.
LDAC
68HC11*
AD7243*
PC7
SYNC
SCLK
SDIN
SCK
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. AD7243–68HC11 Interface
Multiple DAC Daisy-Chain Interface
Figure 14 shows the LDAC input of the AD7243 hard wired
low. As a result, the DAC latch and the analog output will be up-
dated on the sixteenth falling edge of TXD after the SYNC sig-
nal for the DAC has gone low. Alternatively, the scheme used in
previous interfaces, whereby the LDAC input is driven from a
timer, can be used.
A multi-DAC serial interface is shown in Figure 16. This
scheme may be used with all of the interfaces previously dis-
cussed if more than one DAC is required in a system. To enable
the facility the DCEN pin must be connected high on all de-
vices, including the last device in the chain.
PA0
MICROCONTROLLER
SDIN
LDAC
87C51*
AD7243*
AD7243*
PA1
PA2
PA3
SCLK
V
DD
P3.3
SYNC
SYNC
LDAC
SCLK
SDIN
DCEN
SDO
TXD
RXD
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7243*
Figure 14. AD7243–87C51 Interface
SCLK
V
AD7243–68HC11 Interface
DD
SYNC
LDAC
Figure 15 shows a serial interface between the AD7243 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7243 while the MOSI output drives the serial data line of
the AD7243. The SYNC signal is derived from a port line (PC7
shown).
DCEN
SDO
SDIN
AD7243*
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial data
in 8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. To load data to the AD7243, PC7 is left low after
the first eight bits are transferred and a second byte of data is
then transferred serially to the AD7243. When the second serial
transfer is complete, the PC7 line is taken high.
SCLK
V
DD
SYNC
LDAC
DCEN
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD7243 Daisy-Chain Configuration
REV. A
–10–
AD7243
Common clock, data, and synchronization signals are applied to
all DACs in the chain. The loading sequence starts by taking
SYNC low. The data is then clocked into the input registers on
the falling edge of SCLK. Sixteen clock pulses are required for
each DAC in the chain. The data ripples through the input reg-
isters with the first 16-bit word filling the last register in the
chain after 16N clock pulses where N = the total number of
DACs in the chain.
Figure 17 shows a 4-channel isolated interface using the
AD7243. The DCEN pin must be connected high to enable the
daisy-chain facility. Four channels with 12-bit resolution are
provided in the circuit shown, but this may be expanded to ac-
commodate any number of DAC channels without any extra
isolation circuitry.
The sequence of events to program the output channels is as
follows:
When valid data has been loaded into all the registers, the
SYNC input should be taken high and a common LDAC pulse
used to update all the DACs simultaneously.
1. Take the SYNC line low.
2. Transmit the data as four 16-bit words. A total of 64 clock
pulses is required to clock the data through the chain.
APPLICATIONS
3. Take the SYNC line high.
OPTO-ISOLATED INTERFACE
4. Pulse the LDAC line low. This updates all output channels
simultaneously on the falling edge of LDAC.
In many process control type applications it is necessary to pro-
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD7243
makes it ideal for opto-isolated interfaces as the number of in-
terface lines is kept to a minimum.
To reduce the number of opto-couplers, the LDAC line could
be driven from a one shot which is triggered by the rising edge
on the SYNC line. A low level pulse of 50 ns duration or greater
is all that is required to update the outputs.
V
DD
DATA OUT
SDIN
V
DD
CONTROLLER
AD7243*
V
OUT
SCLK
SYNC
LDAC
CLOCK OUT
V
(A)
V
V
V
OUT
DD
DD
DD
V
DD
DCEN
SDO
SYNC OUT
V
DD
SDIN
AD7243*
CONTROL OUT
V
SCLK
SYNC
LDAC
OUT
V
(B)
OUT
DCEN
SDO
QUAD OPTO-COUPLER
SDIN
AD7243*
V
SCLK
SYNC
LDAC
OUT
V
(C)
OUT
DCEN
SDO
SDIN
AD7243*
V
OUT
SCLK
V
(D)
V
OUT
DD
SYNC
LDAC
DCEN
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. Four-Channel Opto-lsolated Interface
REV. A
–11–
AD7243
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-16)
16
1
9
0.25
(6.35)
0.31
(7.87)
8
0.87 (22.1) MAX
0.18
(4.57)
MAX
0.035
(0.89)
0.125
(3.18)
MIN
0.18
(4.57)
0.011
(0.28)
0.3 (7.62)
0.033 (0.84)
0.1 (2.54)
0.018 (0.46)
Cerdip (Q-16)
9
16
1
0.310 (7.87)
TOP VIEW
(Not to Scale)
0.220 (5.59)
8
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150 (3.81) MIN
0.015 (0.381)
0.008 (0.204)
0.100 BSC
(2.54 BSC)
0.022 (0.558)
0.014 (0.356)
0.070 (1.78)
0.30 (0.76)
SOIC (R-16)
0.413 (10.49)
0.398 (10.11)
16
9
0.419 (10.64)
0.394 (10.01)
0.300 (7.62)
0.292 (7.42)
1
8
0.02 (0.508)
45oC
✕
CHAMP
0.350 (8.89)
0.011 (0.279)
0.004 (0.102)
STANDOFF
0.104 (2.64)
0.093 (2.36)
0.019 (0.483)
0.014 (0.356)
0.050 (1.27) REF
0.050 (1.27)
0.01 (0.254)
REV. A
–12–
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