AD7248A_15 [ADI]
LC MOS 12-Bit DACPORTs;
| 型号： | AD7248A_15 |
| 厂家： | 
ADI |
| 描述： | LC MOS 12-Bit DACPORTs |
| 文件： | 总16页 (文件大小：703K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
12-Bit DACPORTs
a
AD7245A/AD7248A
FEATURES
AD7245A FUNCTIONAL BLOCK DIAGRAM
12-Bit CMOS DAC with Output Amplifier and
Reference
Improved AD7245/AD7248:
V
R
OFS
DD
REF OUT
2R
2R
R
FB
12 V to 15 V Operation
؎1/2 LSB Linearity Grade
V
OUT
Faster Interface—30 ns Typ Data Setup Time
Extended Plastic Temperature Range (–40؇C to +85؇C)
Single or Dual Supply Operation
Low Power—65 mW Typ in Single Supply
Parallel Loading Structure: AD7245A
(8+4) Loading Structure: AD7248A
V
REF
DAC
V
SS
AGND
CS
WR
DAC LATCH
INPUT LATCH
DB0 DB11
CLR
CONTROL
LOGIC
AD7245A
GENERAL DESCRIPTION
LDAC
The AD7245A/AD7248A is an enhanced version of the industry
standard AD7245/AD7248. Improvements include operation
from 12 V to 15 V supplies, a 1/2 LSB linearity grade, faster
interface times and better full scale and reference variations with
VDD. Additional features include extended temperature range
operation for commercial and industrial grades.
DGND
AD7248A FUNCTIONAL BLOCK DIAGRAM
The AD7245A/AD7248A is a complete, 12-bit, voltage output,
digital-to-analog converter with output amplifier and Zener voltage
reference on a monolithic CMOS chip. No external user trims
are required to achieve full specified performance.
V
R
OFS
DD
REF OUT
2R
2R
R
FB
Both parts are microprocessor compatible, with high speed data
latches and double-buffered interface logic. The AD7245A accepts
12-bit parallel data that is loaded into the input latch on the
rising edge of CS or WR. The AD7248A has an 8-bit-wide data
bus with data loaded to the input latch in two write operations.
For both parts, an asynchronous LDAC signal transfers data
from the input latch to the DAC latch and updates the analog
output. The AD7245A also has a CLR signal on the DAC latch
which allows features such as power-on reset to be implemented.
V
OUT
V
REF
DAC
V
SS
AGND
LDAC
DAC LATCH
WR
CONTROL
LOGIC
AD7248A
CSLSB
4-BIT
8-BIT
INPUT
LATCH
INPUT
CSMSB
LATCH
The on-chip 5 V buried Zener diode provides a low noise, tem-
perature compensated reference for the DAC. For single supply
operation, two output ranges of 0 V to 5 V and 0 V to 10 V are
available, while these two ranges plus an additional 5 V range
are available with dual supplies. The output amplifiers are capa-
ble of developing 10 V across a 2 kΩ load to GND.
DB7 DB0
DGND
PRODUCT HIGHLIGHTS
1. The AD7245A/AD7248A is a 12-bit DACPORT® on a single
chip. This single chip design and small package size offer
considerable space saving and increased reliability over
multichip designs.
The AD7245A/AD7248A is fabricated in linear compatible CMOS
(LC2MOS), an advanced, mixed technology process that combines
precision bipolar circuits with low power CMOS logic. The
AD7245A is available in a small, 0.3" wide, 24-lead DIP and
SOIC and in 28-terminal surface mount packages. The AD7248A
is packaged in a small, 0.3" wide, 20-lead DIP and SOIC and in
20-terminal surface mount packages.
2. The improved interface times on the part allows easy, direct
interfacing to most modern microprocessors.
3. The AD7245A/AD7248A features a wide power supply range
allowing operation from 12 V supplies.
DACPORT is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2001
(V = +12 V to +15 V,1 V = O V or –12 V to –15 V,1
AGND = DGND = O V, RL = 2 k⍀, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
AD7245A/AD7248A–SPECIFICATIONS
DD
SS
A2
B2
T2
Parameter
Version Version
Version Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
3/4
1
12
1/2
3/4
1/2
1
3
5
2
4
12
1/2
3/4
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
% of FSR max
% of FSR/V max
% of FSR/V max
Relative Accuracy @ 25°C3
TMIN to TMAX
T
MIN to TMAX
VDD = 15 V 10%
Differential Nonlinearity3
Unipolar Offset Error @ 25°C3
TMIN to TMAX
1
3
5
3
5
2
0.2
0.06
0.01
40
1
3
5
2
4
2
0.2
0.06
0.01
40
Guaranteed Monotonic
VSS = 0 V or –12 V to –15 V4
Typical Tempco is 3 ppm of FSR5/°C.
ROFS connected to REF OUT; VSS = –12 V to –15 V4
Typical Tempco is 3 ppm of FSR5/°C.
Bipolar Zero Error @ 25°C3
TMIN to TMAX
DAC Gain Error3, 6
2
Full-Scale Output Voltage Error7 @ 25°C
∆Full Scale/∆VDD
0.2
0.06
0.01
30
VDD = 15 V
VDD = +12 V to +15 V4
VSS = –12 V to –15 V4
∆Full Scale/∆VSS
Full-Scale Temperature Coefficient8
ppm of FSR/°C max VDD = 15 V
REFERENCE OUTPUT
REF OUT @ 25°C
4.99/5.01 4.99/5.01 4.99/5.01 V min/V max
VDD = 15 V
∆REF OUT/∆VDD
2
2
2
mV/V max
VDD = 12 V to 15 V4
Reference Temperature Coefficient
Reference Load Change
(∆REF OUT vs. ∆I)
25
25
35
ppm/°C typ
–1
–1
–1
mV max
Reference Load Current Change (0–100 µA)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
10
2.4
0.8
10
2.4
0.8
10
V min
V max
µA max
pF max
VIN = 0 V to VDD
Input Capacitance9
8
8
8
ANALOG OUTPUTS
Output Range Resistors
Output Voltage Ranges10
15/30
5, 10
5, 10,
5
15/30
5, 10
5, 10,
5
15/30
5, 10
5, 10,
5
kΩ min/kΩ max
V
VSS = 0 V; Pin Strappable
VSS = –12 V to –15 V;4 Pin Strappable
V
DC Output Impedance
0.5
0.5
0.5
Ω typ
AC CHARACTERISTICS9
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Output Voltage Slew Rate
Digital Feedthrough3
Settling Time to Within 1/2 LSB of Final Value
DAC Latch All 0s to All 1s
7
7
2
10
30
7
7
2
10
30
10
10
1.5
10
30
µs max
µs max
DAC Latch All 1s to All 0s; VSS = –12 V to –15 V4
V/µs min
nV-s typ
nV-s typ
Digital-to-Analog Glitch Impulse
POWER REQUIREMENTS
VDD
+10.8/
+16.5
–10.8/
–16.5
9
+10.8/
+16.5
–10.8/
–16.5
9
+10.8/
+16.5
–10.8/
–16.5
9
V min/
V max
V min/
V max
mA max
mA max
mA max
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
VSS
IDD @ 25°C
TMlN to TMAX
ISS (Dual Supplies)
Output Unloaded; Typically 5 mA
Output Unloaded
Output Unloaded; Typically 2 mA
10
3
10
3
12
5
NOTES
1Power supply tolerance is 10%.
2Temperature ranges are as follows: A/B Versions; –40°C to +85°C; T Version; –55°C to +125°C.
3See Terminology.
4With appropriate power supply tolerances.
5FSR means Full-Scale Range and is 5 V for the 0 V to 5 V output range and 10 V for both the 0 V to 10 V and 5 V output ranges.
6This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.
7This error is calculated with respect to an ideal 4.9988 V on the 0 V to 5 V and 5 V ranges; it is calculated with respect to an ideal 9.9976 V on the 0 V to 10 V
range. It includes the effects of internal voltage reference, gain and offset errors.
8Full-Scale TC = ∆FS/∆T, where ∆FS is the full-scale change from TA = 25°C to TMIN or TMAX
9Guaranteed by design and characterization, not production tested.
.
100 V to 10 V output range is available only when VDD ≥ +14.25 V.
Specifications subject to change without notice.
–2–
REV. B
AD7245A/AD7248A
SWITCHING CHARACTERISTICS1 (VDD = +12 V to +15 V;2 VSS = 0 V to –12 V to –15 V;2 See Figures 5 and 7.)
Parameter
A, B Versions
T Version
Unit
Conditions
t1
@ 25°C
TMIN to TMAX
55
80
55
100
ns typ
ns min
Chip Select Pulsewidth
t2
@ 25°C
TMIN to TMAX
40
80
40
100
ns typ
ns min
Write Pulsewidth
t3
@ 25°C
0
0
0
0
ns min
ns min
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Data Valid to Write Setup Time
Data Valid to Write Hold Time
Load DAC Pulsewidth
T
MIN to TMAX
t4
t5
t6
t7
@ 25°C
TMIN to TMAX
0
0
0
0
ns min
ns min
@ 25°C
TMIN to TMAX
40
80
40
80
ns typ
ns min
@ 25°C
10
10
10
10
ns min
ns min
TMIN to TMAX
@ 25°C
MIN to TMAX
40
80
40
100
ns typ
ns min
T
t8 (AD7245A Only)
@ 25°C
TMIN to TMAX
40
80
40
100
ns typ
ns min
Clear Pulsewidth
NOTES
1Sample tested at 25°C to ensure compliance.
2Power supply tolerance is 10%.
ABSOLUTE MAXIMUM RATINGS1
Operating Temperature
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
V
DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
DD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2The output may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. VOUT short circuit current is typically
80 mA.
V
OUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
2
VOUT to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 24 V
2
VOUT to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –32 V, 0 V
REF OUT2 to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD7245A/AD7248A
AD7245A ORDERING GUIDE
DAC GAIN ERROR
DAC Gain Error is a measure of the output error between an
ideal DAC and the actual device output with all 1s loaded after
offset error has been allowed for. It is, therefore defined as:
Temperature
Range
Relative
Accuracy
Package
Option2
Model1
AD7245AAN
AD7245ABN
AD7245AAQ
AD7245ATQ3
AD7245AAP
AD7245AAR
AD7245ABR
AD7245ATE3
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
3/4 LSB
1/2 LSB
3/4 LSB
3/4 LSB
3/4 LSB
3/4 LSB
1/2 LSB
3/4 LSB
N-24
N-24
Q-24
Q-24
P-28A
R-24
R-24
E-28A
Measured Value—Offset—Ideal Value
where the ideal value is calculated relative to the actual refer-
ence value.
UNIPOLAR OFFSET ERROR
Unipolar Offset Error is a combination of the offset errors of the
voltage mode DAC and the output amplifier and is measured
when the part is configured for unipolar outputs. It is present
for all codes and is measured with all 0s in the DAC register.
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact our local sales office for military data sheet and availability.
2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.
BIPOLAR ZERO OFFSET ERROR
Bipolar Zero Offset Error is measured when the part is config-
ured for bipolar output and is a combination of errors from the
DAC and output amplifier. It is present for all codes and is
measured with a code of 2048 (decimal) in the DAC register.
3This grade will be available to /883B processing only.
AD7248A ORDERING GUIDE
SINGLE SUPPLY LINEARITY AND GAIN ERROR
The output amplifier of the AD7245A/AD7248A can have a
true negative offset even when the part is operated from a single
positive power supply. However, because the lower supply rail
to the part is 0 V, the output voltage cannot actually go nega-
tive. Instead the output voltage sits on the lower rail and this
results in the transfer function shown. This is an offset effect
and the transfer function would have followed the dotted line if
the output voltage could have gone negative. Normally, linearity
is measured after offset and full scale have been adjusted or
allowed for. On the AD7245A/AD7248A the negative offset is
allowed for by calculating the linearity from the code which the
amplifier comes off the lower rail. This code is given by the
negative offset specification. For example, the single supply
linearity specification applies between Code 3 and Code 4095
for the 25°C specification and between Code 5 and Code 4095
over the TMIN to TMAX temperature range. Since gain error is
also measured after offset has been allowed for, it is calculated
between the same codes as the linearity error. Bipolar linearity and
gain error are measured between Code 0 and Code 4095.
Temperature
Range
Relative
Accuracy
Package
Option2
Model1
AD7248AAN
AD7248ABN
AD7248AAQ
AD7248ATQ3
AD7248AAP
AD7248AAR
AD7248ABR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
3/4 LSB
1/2 LSB
3/4 LSB
3/4 LSB
3/4 LSB
3/4 LSB
1/2 LSB
N-20
N-20
Q-20
Q-20
P-20A
R-20
R-20
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact our local sales office for military data sheet and availability.
2N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
3This grade will be available to /883B processing only.
TERMINOLOGY
RELATIVE ACCURACY
Relative Accuracy, or endpoint nonlinearity, is a measure of the
actual deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after allowing for
zero and full scale and is normally expressed in LSBs or as a
percentage of full-scale reading.
OUTPUT
VOLTAGE
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB max over
the operating temperature range ensures monotonicity.
0V
NEGATIVE
OFFSET
DAC CODE
DIGITAL FEEDTHROUGH
Digital Feedthrough is the glitch impulse injected from the digital
inputs to the analog output when the inputs change state. It is
measured with LDAC high and is specified in nV-s.
–4–
REV. B
AD7245A/AD7248A
AD7245A PIN FUNCTION DESCRIPTIONS
(DIP PIN NUMBERS)
Pin Mnemonic Description
Pin
Mnemonic Description
19
WR
Write Input (Active LOW). This is used in
conjunction with CS to write data into the
input latch of the AD7245A.
l
VSS
Negative Supply Voltage (0 V for single
supply operation).
2
3
ROFS
Bipolar Offset Resistor. This provides
access to the on-chip application resistors
and allows different output voltage ranges.
20
LDAC
Load DAC Input (Active LOW). This is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.
REF OUT Reference Output. The on-chip reference
is provided at this pin and is used when
configuring the part for bipolar outputs.
21
CLR
Clear Input (Active LOW). When this
input is active the contents of the DAC
latch are reset to all 0s.
4
5
AGND
DB11
Analog Ground.
Data Bit 11. Most Significant Bit (MSB).
22
23
VDD
RFB
Positive Supply Voltage.
6–11 DB10–DB5 Data Bit 10 to Data Bit 5.
12 DGND Digital Ground.
13–16 DB4–DB1 Data Bit 4 to Data Bit 1.
Feedback Resistor. This allows access to
the amplifier’s feedback loop.
24
VOUT
Output Voltage. Three different output
voltage ranges can be chosen: 0 V to 5 V,
0 V to 10 V or –5 V to +5 V.
17
18
DB0
Data Bit 0. Least Significant Bit (LSB).
CS
Chip Select Input (Active LOW). The
device is selected when this input is active.
AD7245A PIN CONFIGURATIONS
PLCC
LCCC
DIP and SOIC
V
24
V
OUT
1
SS
23
22
21
20
19
18
R
FB
R
2
3
OFS
4
28 27 26
3
2
1
4
3
2
1 28 27 26
V
REF OUT
DD
4
AGND
CLR
LDAC
WR
5
6
25 CLR
AGND
DB11
DB10
NC
25
24
23
CLR
LDAC
WR
AGND
DB11
DB10
NC
5
6
AD7245A
TOPVIEW
(NOTTO SCALE)
(MSB) DB11
DB10
24
23
22
21
20
19
5
LDAC
WR
7
6
AD7245A
TOPVIEW
7
AD7245A
TOPVIEW
(NOTTO SCALE)
NC
8
7
DB9
DB8
DB7
DB6
CS
22 NC
(NOTTO SCALE)
8
9
CS
DB9
17 DB0 (LSB)
DB1
8
21 CS
DB9
9
DB0
DB1
10
11
DB8
16
9
DB0
20
19
DB8
10
11
DB7
15 DB2
14 DB3
10
DB1
DB7
DB5 11
12 13 14 15 16 17 18
12 13 14 15 16 17 18
13
DGND 12
DB4
NC = NO CONNECT
NC = NO CONNECT
REV. B
–5–
AD7245A/AD7248A
AD7248A PIN FUNCTION DESCRIPTIONS
(ANY PACKAGE)
Pin Mnemonic Description
Pin Mnemonic Description
l
VSS
Negative Supply Voltage (0 V for single
supply operation).
14
15
16
17
CSMSB
CSLSB
WR
Chip Select Input for MS Nibble. (Active
LOW). This selects the upper 4 bits of the
input latch. Input data is right justified.
2
ROFS
Bipolar Offset Resistor. This provides
access to the on-chip application resistors
and allows different output voltage ranges.
Chip Select Input for LS byte. (Active
LOW). This selects the lower 8 bits of the
input latch.
3
REF OUT
Reference Output. The on-chip reference
is provided at this pin and is used when
configuring the part for bipolar outputs.
Write Input. This is used in conjunction
with CSMSB and CSLSB to load data
into the input latch of the AD7248A.
4
5
AGND
DB7
Analog Ground.
Data Bit 7.
LDAC
Load DAC Input (Active LOW). This is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.
6
DB6
Data Bit 6.
7
DB5
Data Bit 5.
8
DB4
Data Bit 4.
18
19
VDD
RFB
Positive Supply Voltage.
9
DB3
Data Bit 3.
Feedback Resistor. This allows access to
the amplifier’s feedback loop.
10
11
12
13
DGND
DB2
Digital Ground.
Data Bit 2/Data Bit 10.
Data Bit 1/Data Bit 9.
Data Bit 0 (LSB)/Data Bit 8.
20
VOUT
Output Voltage. Three different output
voltage ranges can be chosen: 0 V to 5 V,
0 V to 10 V or –5 V to +5 V.
DB1
DB0
AD7248A PIN CONFIGURATIONS
PLCC
DIP and SOIC
LCCC
V
V
1
2
20
19
18
SS
OUT
R
R
FB
OFS
3
2
1
20 19
3
2
1
20 19
V
3
REF OUT
DD
PIN 1
IDENTIFIER
4
5
6
7
8
18
17
16
15
14
V
DD
AGND
(MSB) DB7
DB6
18
17
16
15
14
AGND
(MSB) DB7
DB6
4
5
6
7
8
V
4
17 LDAC
16
AGND
(MSB) DB7
DB6
DD
LDAC
WR
AD7248A
TOPVIEW
(NOTTO SCALE)
LDAC
WR
5
WR
15 CSLSB
AD7248A
TOP VIEW
AD7248A
TOP VIEW
(NOT TO SCALE)
6
(NOT TO SCALE)
DB5
CSLSB
CSMSB
DB5
CSLSB
7
14
13
12
11
DB5
DB4
CSMSB
DB0 (LSB)
DB1
DB4
DB4
CSMSB
8
9
10 11 12 13
9
10 11 12 13
9
DB3
DB2
DGND
10
–6–
REV. B
Typical Performance Characteristics– AD7245A/AD7248A
7
6
5
4
3
2
1
4.995
I
(V = –15V, V =V
ORV
)
V
= +15V
DD
SS
IN
INL
INH
DD
I
(V = –15V, V = 0V ORV
)
DD
DD
SS
IN
5.000
5.005
5.010
I
(V = 0V,V = 0V ORV
)
DD
SS
IN
DD
I
(V = –15V)
SS
SS
0
–55
–25
0
25
TEMPERATURE – ؇C
70 85
125
–55
–25
0
25
70 85
125
TEMPERATURE – ؇C
TPC 1. Power Supply Current vs. Temperature
TPC 4. Reference Voltage vs. Temperature
500
V
= 15V
= 0V
= 25؇C
DD
OUTPUTWITH ALL
DECOUPLING*
0s ON DAC
V
SS
T
A
80
200
100
NO
REFERENCE (NO DECOUPLING)
DECOUPLING
60
REFERENCE (DECOUPLED*)
OUTPUTWITH ALL
DECOUPLING
1s ON DAC
50
40
NO DECOUPLING
20
20
10
OUTPUT WITH
ALL 0s ON DAC
V
= 15VWITH
DD
100mV p-p SIGNAL
0
50 100 200
500
1k
2k
5k
10k 20k
50k
50
100
1k
FREQUENCY – Hz
20k
10k
100k
200
2k
FREQUENCY – Hz
*REFERENCE DECOUPLING COMPONENTS AS PER FIGURE 8
*POWER SUPPLY DECOUPLING CAPACITORS ARE 10F AND 0.1F
TPC 2. Noise Spectral Density vs. Frequency
TPC 5. Power Supply Rejection Ration vs. Frequency
1mV
1mV
100
90
100
90
10
10
0%
0%
1s
2V
1s
2V
TPC 3. Positive-Going Settling Time
(VDD = +15 V, VSS = –15 V)
TPC 6. Negative Going Settling Time
(VDD = +15 V, VSS = –15 V)
REV. B
–7–
AD7245A/AD7248A
CIRCUIT INFORMATION
The small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the ampli-
fier is low with a figure of 25 nV/√Hz at a frequency of 1 kHz.
The broadband noise from the amplifier has a typical peak-to-
peak figure of 150 µV for a 1 MHz output bandwidth. There is
no significant difference in the output noise between single and
dual supply operation.
D/A SECTION
The AD7245A/AD7248A contains a 12-bit voltage mode digi-
tal-to-analog converter. The output voltage from the converter
has the same positive polarity as the reference voltage allowing
single supply operation. The reference voltage for the DAC is
provided by an on-chip buried Zener diode.
VOLTAGE REFERENCE
The DAC consists of a highly stable, thin-film, R–2R ladder and
twelve high-speed NMOS single-pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in Figure 1.
The AD7245A/AD7248A contains an internal low noise buried
Zener diode reference which is trimmed for absolute accuracy
and temperature coefficient. The reference is internally connected
to the DAC. Since the DAC has a variable input impedance at
its reference input the Zener diode reference is buffered. This
buffered reference is available to the user to drive the circuitry
required for bipolar output ranges. It can be used as a reference
for other parts in the system provided it is externally buffered.
The reference will give long-term stability comparable with the
best discrete Zener reference diodes. The performance of the
AD7245A/AD7248A is specified with internal reference, and all
the testing and trimming is done with this reference. The reference
should be decoupled at the REF OUT pin and recommended
decoupling components are 10 µF and 0.1 µF capacitors in
series with a 10 Ω resistor. A simplified schematic of the refer-
ence circuitry is shown in Figure 3.
2R
2R
R
R
OFS
FB
V
R
OUT
R
R
R
R
2R
2R
2R
2R
2R
2R
DB9
DB11
DB1
DB0
DB10
V
REF
AGND
SHOWN FOR ALL 1s ON DAC
Figure 1. D/A Simplified Circuit Diagram
The input impedance of the DAC is code dependent and can
vary from 8 kΩ to infinity. The input capacitance also varies
with code, typically from 50 pF to 200 pF.
V
DD
OP AMP SECTION
I
C
The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The user has access to two gain
setting resistors which can be connected to allow different out-
put voltage ranges (discussed later). The buffer amplifier is
capable of developing up to 10 V across a 2 kΩ load to GND.
TO DAC
V-TO-I
The output amplifier can be operated from a single positive
power supply by tying VSS = AGND = 0 V. The amplifier can
also be operated from dual supplies to allow a bipolar output
range of –5 V to +5 V. The advantages of having dual supplies
for the unipolar output ranges are faster settling time to voltages
near 0 V, full sink capability of 2.5 mA maintained over the entire
output range and elimination of the effects of negative offset on
the transfer characteristic (outlined previously). Figure 2 shows
the sink capability of the amplifier for single supply operation.
AGND
REF OUT
ISTEMPERATURE
I
C
COMPENSATION CURRENT
Figure 3. Internal Reference
DIGITAL SECTION
The AD7245A/AD7248A digital inputs are compatible with
either TTL or 5 V CMOS levels. All data inputs are static pro-
tected MOS gates with typical input currents of less than 1 nA.
The control inputs sink higher currents (150 µA max) as a result
of the fast digital interfacing. Internal input protection of all
logic inputs is achieved by on-chip distributed diodes.
5
4
3
2
1
The AD7245A/AD7248A features a very low digital feedthrough
figure of 10 nV-s in a 5 V output range. This is due to the volt-
age mode configuration of the DAC. Most of the impulse is
actually as a result of feedthrough across the package.
INTERFACE LOGIC INFORMATION—AD7245A
Table I shows the truth table for AD7245A operation. The part
contains two 12-bit latches, an input latch and a DAC latch. CS
and WR control the loading of the input latch while LDAC
controls the transfer of information from the input latch to the
DAC latch. All control signals are level triggered; and therefore,
either or both latches may be made transparent, the input latch
by keeping CS and WR “LOW”, the DAC latch by keeping
LDAC “LOW.” Input data is latched on the rising edge of WR.
T
=T
TO T
MIN
A
MAX
9
0
0
1
2
3
4
5
6
7
8
10
OUTPUTVOLTAGE –Volts
Figure 2. Typical Single Supply Sink Current vs.
Output Voltage
–8–
REV. B
AD7245A/AD7248A
The data held in the DAC latch determines the analog output of
the converter. Data is latched into the DAC latch on the rising
edge of LDAC. This LDAC signal is an asynchronous signal
and is independent of WR. This is useful in many applications.
However, in systems where the asynchronous LDAC can occur
during a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. For
example, if LDAC goes LOW while WR is “LOW,” then the
LDAC signal must stay LOW for t7 or longer after WR goes
high to ensure correct data is latched through to the output.
t1
5V
0V
CS
t3
t4
t2
5V
0V
5V
0V
WR
t7
LDAC
t6
t5
5V
0V
VALID
DATA
HIGH IMPEDANCE
BUS
DATA
Table I. AD7245A Truth Table
NOTES
1. SEETIMING SPECIFICATIONS.
2. ALL INPUT RISE AND FALLTIMES MEASURES FROM 10%TO
90% OF 5V, tr tf = 5ns.
CLR LDAC WR
CS
Function
=
H
H
H
H
H
H
H
L
L
L
L
Both Latches are Transparent
Both Latches are Latched
Both Latches are Latched
Input Latches Transparent
Input Latches Latched
DAC Latches Transparent
DAC Latches Latched
DAC Latches Loaded with all 0s
DAC Latches Latched with All
0s and Output Remains at
0 V or –5 V
3.TIMING MEASUREMENT REFERENCE LEVEL IS
V
+V
2
INH
INL
H
H
H
H
L
H
X
L
X
H
L
4. IF LDAC IS ACTIVATEDWHILE WR IS LOW, LDAC MUST STAY
LOW FOR t7 OR LONGER AFTER WR GOES HIGH.
g
L
Figure 5. AD7245A Write Cycle Timing Diagram
H
H
X
H
H
H
X
H
g
INTERFACE LOGIC INFORMATION—AD7248A
X
H
The input loading structure on the AD7248A is configured for
interfacing to microprocessors with an 8-bit wide data bus. The
part contains two 12-bit latches—an input latch and a DAC
latch. Only the data held in the DAC latch determines the ana-
log output from the converter. The truth table for AD7248A
operation is shown in Table II, while the input control logic
diagram is shown in Figure 6.
g
g
L
L
L
Both Latches are Transparent
and Output Follows Input Data
H = High State, L = Low State, X = Don’t Care
DAC LATCH
12
LDAC
The contents of the DAC latch are reset to all 0s by a low level
on the CLR line. With both latches transparent, the CLR line
functions like a zero override with the output brought to 0 V in
the unipolar mode and –5 V in the bipolar mode for the dura-
tion of the CLR pulse. If both latches are latched, a “LOW”
pulse on the CLR input latches all 0s into the DAC latch and the
output remains at 0 V (or –5 V) after the CLR line has returned
“HIGH.” The CLR line can be used to ensure power-up to 0 V
on the AD7245A output in unipolar operation and is also use-
ful, when used as a zero override, in system calibration cycles.
4
UPPER
4 BITS
CSMSB
OF INPUT
LATCH
8
LOWER
8 BITS
CSLSB
WR
OF INPUT
LATCH
Figure 4 shows the input control logic for the AD7245A and the
write cycle timing for the part is shown in Figure 5.
8
DB7 – DB0
Figure 6. AD7248A Input Control Logic
LDAC
DAC LATCH
CSMSB, CSLSB and WR control the loading of data from the
external data bus to the input latch. The eight data inputs on
the AD7248A accept right justified data. This data is loaded to
the input latch in two separate write operations. CSLSB and
WR control the loading of the lower 8-bits into the 12-bit wide
latch. The loading of the upper 4-bit nibble is controlled by
CSMSB and WR. All control inputs are level triggered, and
input data for either the lower byte or upper 4-bit nibble is
latched into the input latches on the rising edge of WR (or
either CSMSB or CSLSB). The order in which the data is
loaded to the input latch (i.e., lower byte or upper 4-bit nibble
first) is not important.
CLR
WR
INPUT LATCH
CS
INPUT DATA
Figure 4. AD7245A Input Control Logic
REV. B
–9–
AD7245A/AD7248A
The LDAC input controls the transfer of 12-bit data from the
input latch to the DAC latch. This LDAC signal is also level
triggered, and data is latched into the DAC latch on the rising
edge of LDAC. The LDAC input is asynchronous and indepen-
dent of WR. This is useful in many applications especially in
the simultaneous updating of multiple AD7248A outputs. How-
ever, in systems where the asynchronous LDAC can occur during
a write cycle (or vice versa) care must be taken to ensure that
incorrect data is not latched through to the output. In other words,
if LDAC goes low while WR and either CS input are low (or
WR and either CS go low while LDAC is low), then the LDAC
signal must stay low for t7 or longer after WR returns high to
ensure correct data is latched through to the output. The write
cycle timing diagram for the AD7248A is shown in Figure 7.
APPLYING THE AD7245A/AD7248A
The internal scaling resistors provided on the AD7245A/
AD7248A allow several output voltage ranges. The part can
produce unipolar output ranges of 0 V to 5 V or 0 V to 10 V
and a bipolar output range of –5 V to +5 V. Connections for
the various ranges are outlined below.
UNIPOLAR (0 V TO 10 V) CONFIGURATION
The first of the configurations provides an output voltage range
of 0 V to 10 V. This is achieved by connecting the bipolar offset
resistor, ROFS, to AGND and connecting RFB to VOUT. In this
configuration the AD7245A/AD7248A can be operated single
supply (VSS = 0 V = AGND). If dual supply performance is
required, a VSS of –12 V to –15 V should be applied. Figure 8
shows the connection diagram for unipolar operation while the
table for output voltage versus the digital code in the DAC latch
is shown in Table III.
t1
5V
CSLSB
t1
0V
5V
10⍀
0.1F
10F
CSMSB
t3
t2
t4
t3
0V
5V
t4
V
R
DD
REF OUT
OFS
t2
R
2R
2R
FB
WR
t7
0V
5V
LDAC
V
t5
t5
REF
V
DAC
OUT
0V
REF
t6
t6
AD7245A/AD7248A*
AGND
5V
0V
VALID
DATA
VALID
DATA
DATA
IN
DGND
V
SS
*DIGITAL CIRCUITRY
OMITTED FOR CLARITY
Figure 7. AD7248A Write Cycle Timing Diagram
Figure 8. Unipolar (0 to 10 V) Configuration
An alternate scheme for writing data to the AD7248A is to tie
the CSMSB and LDAC inputs together. In this case exercising
CSLSB and WR latches the lower 8 bits into the input latch.
The second write, which exercises CSMSB, WR and LDAC
loads the upper 4-bit nibble to the input latch and at the same
time transfers the 12-bit data to the DAC latch. This automatic
transfer mode updates the output of the AD7248A in two write
operations. This scheme works equally well for CSLSB and
LDAC tied together provided the upper 4-bit nibble is loaded
to the input latch followed by a write to the lower 8 bits of
the input latch.
Table III. Unipolar Code Table (0 V to 10 V Range)
DAC Latch Contents
MSB
LSB
Analog Output, VOUT
4095
4096
1 1 1 1
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
+2 VREF
+2 VREF
+2 VREF
+2 VREF
+2 VREF
؋
؋
؋
؋
؋
2049
4096
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
Table II. AD7248A Truth Table
2048
4096
= +VREF
CSLSB CSMSB WR LDAC Function
L
L
H
H
H
L
L
g
L
g
H
H
H
H
H
H
L
Load LS Byte into Input Latch
2047
4096
Latches LS Byte into Input Latch
Latches LS Byte into Input Latch
Loads MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Loads Input Latch into DAC Latch
Latches Input Latch into DAC Latch
Loads MS Nibble into Input Latch and
Loads Input Latch into DAC Latch
No Data Transfer Operation
g
L
L
g
H
H
H
H
H
H
1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
L
H
H
L
4096
H
H
L
0 V
g
L
1
NOTE: 1 LSB = 2
؋
VREF(2–12) = VREF
H
H
H
H
2048
H = High State, L = Low State
–10–
REV. B
AD7245A/AD7248A
UNIPOLAR (0 V TO 5 V) CONFIGURATION
The 0 V to 5 V output voltage range is achieved by tying ROFS
RFB and VOUT together. For this output range the AD7245A/
AD7248A can be operated single supply (VSS = 0 V) or dual sup-
ply. The table for output voltage versus digital code is as in Table
III, with 2 × VREF replaced by VREF. Note that for this range
In this case care must be taken to ensure that the maximum
output voltage is not greater than VDD –3 V. The VDD–VOUT
overhead must be greater than 3 V to ensure correct operation
of the part. Note that VDD and VSS for the AD7245A/AD7248A
must be referenced to DGND (system GND). The entire circuit
can be operated in single supply with the VSS pin of the
AD7245A/AD7248A connected to system GND.
,
1
.
1 LSB = VREF(2–12) = VREF
؋
4096
10⍀
+
10F
0.1F
BIPOLAR CONFIGURATION
The bipolar configuration for the AD7245A/AD7248A, which
gives an output voltage range from –5 V to +5 V, is achieved by
connecting the ROFS input to REF OUT and connecting RFB
and VOUT. The AD7245A/AD7248A must be operated from
dual supplies to achieve this output voltage range. The code
table for bipolar operation is shown in Table IV.
V
R
DD
OFS
REF OUT
15V
2R
2R
R
FB
27k⍀
AGND
V
DAC
OUT
REF
V
V
REF
Table IV. Bipolar Code Table
DAC Latch Contents
BIAS
AD7245A/AD7248A*
+
V
DGND
SS
MSB
LSB
Analog Output, VOUT
AD589
–
SYSTEM
GND
*DIGITAL CIRCUITRY
OMITTED FOR CLARITY.
2047
2048
1 1 1 1
1 1 1 1
1 1 1 1
+VREF
+VREF
×
Figure 9. AGND Bias Circuit
1
1 0 0 0
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
×
PROGRAMMABLE CURRENT SINK
2048
Figure 10 shows how the AD7245A/AD7248A can be config-
ured with a power MOSFET transistor, the VN0300M, to
0 V
1
provide a programmable current sink from VDD or VSOURCE
The VN0300M is placed in the feedback of the AD7245A/
.
0 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
–VREF
–VREF
–VREF
×
×
×
2048
AD7248A amplifier. The entire circuit can be operated in single
supply by tying the VSS of the AD7245A/AD7248A to AGND.
The sink current, ISINK, can be expressed as:
2047
2048
D ×VREF
2048
2048
ISINK
=
= –VREF
R1
10⍀
V
SOURCE
+
1
NOTE: 1 LSB = 2 × VREF(2–11) = VREF
10F
0.1F
2048
V
R
DD
LOAD
OFS
REF OUT
AGND BIAS
The AD7245A/AD7248A AGND pin can be biased above sys-
tem GND (AD7245A/AD7248A DGND) to provide an offset
“zero” analog output voltage level. With unity gain on the
amplifier (ROFS = VOUT = RFB) the output voltage, VOUT is
expressed as:
2R
2R
R
FB
I
SINK
VN0300M
R1
V
DAC
OUT
REF
V
REF
VOUT = VBIAS + D
؋
VREF AD7245A/AD7248A*
where D is a fractional representation of the digital word in the
DAC latch and VBIAS is the voltage applied to the AD7245A/
AD7248A AGND pin.
V
DGND
AGND
SS
*DIGITAL CIRCUITRY
OMITTED FOR CLARITY.
Because the current flowing out of the AGND pin varies with
digital code, the AGND pin should be driven from a low imped-
ance source. A circuit configuration is outlined for AGND bias
in Figure 9 using the AD589, a +1.23 V bandgap reference.
Figure 10. Programmable Current Sink
Using the VN0300M, the voltage drop across the load can typi-
cally be as large as VSOURCE –6 V) with VOUT of the DAC at
5 V. Therefore, for a current of 50 mA flowing in the R1 (with
all 1s in the DAC register) the maximum load is 200 Ω with
VSOURCE = 15 V. The VN0300M can actually handle currents
up to 500 mA and still function correctly in the circuit, but in
practice the circuit must be used with larger values of VSOURCE
otherwise it requires a very small load.
If a gain of 2 is used on the buffer amplifier the output voltage,
V
OUT is expressed as
VOUT = 2(VBIAS + D
؋
VREF )
REV. B
–11–
AD7245A/AD7248A
Since the tolerance value on the reference voltage of the AD7245A/
AD7248A is 0.2%, then the absolute value of ISINK can vary by
0.2% from device to device for a fixed value of R1.
Adjusting the triwave applied to the AD639 adjust the distortion
performance of the sine wave output, (10 V in configuration
shown). Amplitude, offset and symmetry of the triwave can affect
the distortion. By adjusting these, via VR1 and VR2, an output
sine wave with harmonic distortion of better than –50 dB can be
achieved at low and intermediate frequencies.
Because the input bias current of the AD7245A/AD7248A’s op
amp is only of the order of picoamps, its effect on the sink cur-
rent is negligible. Tying the ROFS input to RFB input reduces this
effect even further and prevents noise pickup which could occur
if the ROFS pin was left unconnected.
Using the capacitor value shown in Figure 11 for CF (i.e., 680 pF)
the output frequency range is 0 to 100 kHz over the digital input
code range. The step size for frequency increments is 25 Hz.
The accuracy of the output frequency is limited to 8 or 9 bits by
the AD537, but is guaranteed monotonic to 12 bits.
The circuit of Figure 10 can be modified to provide a pro-
grammable current source to AGND or –VSINK (for –VSINK
,
dual supplies are required on the AD7245A/AD7248A). The
AD7245A/AD7248A is configured as before. The current through
R1 is mirrored with a current mirror circuit to provide the pro-
grammable source current (see CMOS DAC Application Guide,
Publication No. G872-30-10/84, for suitable current mirror
circuit). As before the absolute value of the source current will
be affected by the 0.2% tolerance on VREF. In this case the perfor-
mance of the current mirror will also affect the value of the
source current.
MICROPROCESSOR INTERFACING—AD7245
AD7245A—8086 INTERFACE
Figure 12 shows the 8086 16-bit processor interfacing to the
AD7245A. In the setup shown in Figure 12, the double buffer-
ing feature of the DAC is not used and the LDAC input is tied
LOW. AD0–AD11 of the 16-bit data bus are connected to the
AD7245A data bus (DB0–DB11). The 12-bit word is written
to the AD7245A in one MOV instruction and the analog output
responds immediately. In this example the DAC address is
D000. A software routine for Figure 12 is given in Table V.
FUNCTION GENERATOR WITH PROGRAMMABLE
FREQUENCY
Figure 11 shows how the AD7245A/AD7248A with the AD537,
voltage-to-frequency converter and the AD639, trigonometric
function generator to provide a complete function generator
with programmable frequency. The circuit provides square wave,
triwave and sine wave outputs, each output of 10 V amplitude.
ADDRESS BUS
8086
16-BIT
LATCH
ADDRESS
DECODE
CS
ALE
The AD7245A/AD7248A provides a programmable voltage to
the AD537 input. Since both the AD7245A/AD7248A and
AD537 are guaranteed monotonic, the output frequency will
always increase with increasing digital code. The AD537 pro-
vides a square wave output which is conditioned for 10 V by
amplifier A1. The AD537 also provides a differential triwave
output. This is conditioned by amplifiers A2 and A3 to provide the
1.8 V triwave required at the input of the AD639. The triwave is
further scaled by amplifier A4 to provide a 10 V output.
LDAC
AD7245A*
WR
WR
DB11
DB0
AD15
AD0
ADDRESS/DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 12. AD7245A to 8086 Interface
+15V
33k⍀
؎10V
SQUARE
WAVE
15k⍀
A1
82k⍀
A2
20k⍀
+15V +15V
+15V
+V
+
S
22k⍀
4.12k⍀
V
56k⍀
DD
3.9k⍀
3.9k⍀
4.7k⍀
5k⍀
GND O/P
+V
VR2
؎10V
TRIWAVE
AD7245A/
AD7248A
10k⍀
VR1
A4
DEC
S
5.6k⍀
56k⍀
22k⍀
R
4.12k⍀
FB
C
C
C
V
F
OUT
+15V
AD537
680pF
A3
+V
X1
X2
U1
U2
S
R
OFS
؎1V
SINEWAVE
REF
OUT
W
Z1
Z2
V
V
OS
SS
20k⍀
DGND
AGND
10⍀
–V
S
COM
AD639
UP
–V
+
A1, A2, A3, A4 – 2
؋
AD712 0.1F
10F
–15V
–15V
Y2
S
Figure 11. Programmable Function Generator
–12–
REV. B
AD7245A/AD7248A
Table V. Sample Program for Loading AD7245A from 8086
ADDRESS BUS
ASSUME DS: DACLOAD, CS: DACLOAD
DACLOAD SEGMENT AT 000
MC68000
ADDRESS
DECODE
AS
CS
00 8CC9
MOV CS,
CS
: DEFINE DATA SEGMENT
REGISTER
LDAC
DTACK
AD7245A*
02 8ED9
MOV DS,
CX
: EQUAL TO CODE
SEGMENT REGISTER
WR
R/W
DB11
DB0
04 BF00D0 0MOV DI, : LOAD DI WITH D000
#D000
D0–D15
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
07 C705
MOV MEM, : DAC LOADED WITH WXYZ
“YZWX” #YZWX
0B EA00 00
0E 00 FF
: CONTROL IS RETURNED TO
THE MONITOR PROGRAM
Figure 14. AD7245A to MC68000 Interface
Table VI. Sample Routine for Loading AD7245A from 68000
In a multiple DAC system the double buffering of the AD7245A
allows the user to simultaneously update all DACs. In Figure
13, a 12-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri-
ate address, CS4 (i.e., LDAC) is brought LOW, updating all the
DACs simultaneously.
01000 MOVE.W
#X,D0
The desired DAC data,
X, is loaded into Data
Register 0. X may be any
value between 0 and 4094
(decimal) or 0 and OFFF
(hexadecimal).
MOVE.W
D0,$E000 The Data X is transferred
between D0 and the
ADDRESS BUS
8086
CS1
DAC Latch.
16-BIT
LATCH
ADDRESS
DECODE
ALE
CS
AD7245A*
AD7245A*
AD7245A*
MOVE.B
TRAP
#228,D7
#14
Control is returned to
the System Monitor
Program using these two
instructions.
CS4
LDAC
WR
WR
AD15
AD0
DB11
DB0
DATA BUS
MICROPROCESSOR INTERFACE—AD7248A
CS
Figure 15 shows the connection diagram for interfacing the
AD7248A to both the 8085A and 8088 microprocessors. This
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demultiplexed. Data to be
loaded to the AD7248A is right justified. The AD7248A is
memory mapped with a separate memory address for the input
latch high byte, the input latch low byte and the DAC latch.
Data is first written to the AD7248A input latch in two write
operations. Either the high byte or the low byte data can be
written first to the AD7248A input latch. A write to the AD7248A
DAC latch address transfers the input latch data to the DAC
latch and updates the output voltage. Alternatively, the LDAC
input can be asynchronous or can be common to a number
of AD7248As for simultaneous updating of a number of volt-
age channels.
LDAC
WR
DB11
DB0
CS
LDAC
WR
DB11
DB0
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 13. AD7245A to 8086 Multiple DAC Interface
AD7245A—MC68000 INTERFACE
ADDRESS BUS
A8–A15
Interfacing between the MC68000 and the AD7245A is accom-
plished using the circuit of Figure 14. Once again the AD7245A
is used in the single buffered mode. A software routine for load-
ing data to the AD7245A is given in Table VI. In this example
the AD7245A is located at address E000, and the 12-bit word is
written to the DAC in one MOVE instruction.
CSLSB
CSMSB
LDAC
OCTAL
LATCH
ADDRESS
DECODE
ALE
8085A/8088
AD7248A*
WR
WR
DB0–DB7
AD0–AD7
ADDRESS/DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 15. AD7248A to 8085A/8088 Interface
REV. B
–13–
AD7245A/AD7248A
Figure 18 shows a connection diagram between the AD7248A
and the 8051 microprocessor. The AD7248A is port mapped in
this interface and is configured in the automatic transfer mode.
Data to be loaded to the input latch low byte is output to Port 1.
Output Line P3.0, which is connected to CSLSB of the AD7248A,
is pulsed to load data into the low byte of the input latch. Puls-
ing the P3.1 line, after the high byte data has been set up on
Port 1, updates the output of the AD7248A. The WR input of the
AD7248A can be hardwired low in this application because
spurious address strobes on CSLSB and CSMSB do not occur.
A connection diagram for the interface between the AD7248A
and 68008 microprocessor is shown in Figure 16. Once again
the AD7248A acts as a memory mapped device and data is right
justified. In this case the AD7248A is configured in the auto-
matic transfer mode which means that the high byte of the input
latch has the same address as the DAC latch. Data is written to
the AD7248A by first writing data to the AD7248A low byte.
Writing data to the high byte of the input latch also transfers the
input latch contents to the DAC latch and updates the output.
A0–A19
ADDRESS BUS
P3.0
P3.1
CSLSB
CSMSB
LDAC
WR
CSLSB
CSMSB
ADDRESS
DECODE
AS
68008
LDAC
WR
8051
AD7248A*
R/W
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
AD7248A*
DB0–DB7
DTACK
D0–D7
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 16. AD7248A to 68008 Interface
An interface circuit for connections to the 6502 or 6809 micro-
processors is shown in Figure 17. Once again, the AD7248A is
memory mapped and data is right justified. The procedure for
writing data to the AD7248A is as outlined for the 8085A/8088.
For the 6502 microprocessor the φ2 clock is used to generate
the WR, while for the 6809 the E signal is used.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 18. AD7248A to MCS-51 Interface
A0–A15
ADDRESS BUS
CSLSB
ADDRESS
DECODE
CSMSB
LDAC
EN
R/W
6502/6809
2 OR E
WR
AD7248A*
DB0–DB7
D0–D7
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 17. AD7248A to 6502/6809 Interface
–14–
REV. B
AD7245A/AD7248A
MECHANICAL INFORMATION—AD7245A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Plastic DIP
(N-24)
1.228 (31.19)
1.126 (31.14)
24
13
12
0.260 ؎ 0.001
(6.61 ؎ 0.03)
1
PIN 1
0.32 (8.128)
0.30 (7.62)
0.11 (2.79)
0.09 (2.28)
0.060 (1.52)
0.015 (0.38)
0.130 (3.30)
0.128 (3.25)
0.015 (0.381)
0.008 (0.204)
0.02 (0.5)
0.09 (2.28)
SEATING
PLANE
0.07 (1.78)
0.05 (1.27)
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN LEAD PLATED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
24-Lead Cerdip
(Q-24)
24-Lead SOIC
(R-24)
0.614 (15.6)
0.598 (15.2)
24
13
12
0.295
(7.493)
MAX
1
24
1
13
0.299 (7.6)
0.291 (7.4)
0.419 (10.65)
0.394 (10.00)
PIN 1
0.070 (1.78)
0.030 (0.76)
0.320 (8.128)
0.290 (7.366)
1.290 (32.77) MAX
12
0.180
(4.572)
MAX
0.225
(5.715)
MAX
SEATING
PLANE
PIN 1
0.125
(3.175)
MIN
0.104 (2.65)
0.093 (2.35)
0.070 (1.778)
0.020 (0.508)
0.012 (0.305)
0.008 (0.203)
0.110 (2.794)
0.090 (2.286)
TYP
0.021 (0.533)
0.015 (0.381)
TYP
15؇
0؇
8؇
0؇
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
0.050
(1.27)
BSC
0.019 (0.49) SEATING
0.012 (0.30)
0.004 (0.10)
0.005 (0.13)
0.016 (0.40)
CERDIP LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
0.013 (0.32)
0.009 (0.23)
PLANE
0.014 (0.35)
28-Terminal
Leadless Ceramic Chip Carrier
(E-28A)
28-Terminal
Plastic Leaded Chip Carrier
(P-28A)
2
0.300 (7.62)
0.180 (4.51)
0.165 (4.20)
0.032 (0.812)
0.026 (0.661)
BSC
0.075
(1.91)
REF
1
0.100 (2.54)
0.064 (1.63)
0.150
(3.51)
BSC
4
26
25
0.095 (2.41)
0.075 (1.90)
4
26
5
PIN 1
0.021 (0.533)
0.013 (0.331)
28
25
5
IDENTIFIER
0.028 (0.71)
0.022 (0.56)
0.458 (11.63)
0.442 (11.23)
SQ
1
0.430 (10.5)
0.390 (9.9)
0.458
TOP VIEW
(PINS DOWN)
0.011 (0.28)
0.007 (0.18)
R TYP
BOTTOM
VIEW
(11.63)
MAX
SQ
0.050 ؎ 0.005
(1.27 ؎ 0.13)
0.050
(1.27)
BSC
11
12
19
18
0.075
(1.91)
REF
19
11
18
12
0.456 (11.58)
0.450 (11.43)
0.495 (12.57)
45؇ TYP
0.200
(5.08)
BSC
SQ
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
0.110 (2.79)
0.085 (2.16)
SQ
0.485 (12.32)
NOTES
1
THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS.
APPLIES TO ALL FOUR SIDES.
2
ALL TERMINALS ARE GOLD PLATED
REV. B
–15–
AD7245A/AD7248A
MECHANICAL INFORMATION —AD7248A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Cerdip
(Q-20)
20-Lead Plastic DIP
(N-20)
0.11 (2.79)
0.09 (2.28)
1.07 (27.18) MAX
20
11
20
1
11
10
0.255 (6.477)
0.245 (6.223)
0.310 (7.87)
0.220 (5.59)
1
10
PIN 1
0.32 (8.128)
0.29 (7.366)
0.320 (8.13)
0.290 (7.37)
0.021 (0.533)
0.015 (0.381)
PIN 1
0.20 (5.0)
0.97 (24.64)
0.935 (23.75)
0.060 (1.52)
0.015 (0.38)
0.145
(3.683)
MIN
0.18 (4.57)
0.125 (3.18)
0.125
(3.175)
MIN
0.14 (3.18)
0.150
(3.81)
MIN
0.15 (3.8)
0.125 (3.18)
0.011 (0.28)
0.009 (0.23)
0.015 (0.38)
0.008 (0.20)
0.021 (0.533)
0.015 (0.381)
0.070 (1.77)
0.045 (1.15)
15؇
0
SEATING
PLANE
0.02 (0.5)
0.016 (0.41)
0.070 (1.78)
0.030 (0.76)
15°
0°
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
20-Lead SOIC
(R-20)
20-Terminal
Plastic Leaded Chip Carrier
(P-20A)
0.5118 (13.00)
0.4961 (12.60)
0.173 ؎ 0.008
(4.385 ؎ 0.185)
0.105 ؎ 0.015
20
1
11
SQ
(2.665 ؎ 0.375)
0.020
0.299 (7.60)
0.291 (7.40)
(0.51) MIN
0.045 ؎ 0.003
3
19
0.017 ؎ 0.004
(0.432 ؎ 0.101)
(1.143 ؎ 0.076)
0.419 (10.65)
0.404 (10.00)
4
8
18
14
PIN 1
0.050
(1.27)
BSC
10
IDENTIFIER
TOP VIEW
(PINS DOWN)
0.029 ؎ 0.003
(0.737 ؎ 0.076)
PIN 1
0.0500
(1.27)
BSC
9
13
0.020
(0.51)
MAX
0.107 (2.72)
0.089 (2.26)
0.025
(0.64) MIN
0.390 ؎ 0.005
(9.905 ؎ 0.125)
SQ
0.105 ؎ 0.015
(2.665 ؎ 0.375)
8؇
0؇
0.022 (0.56)
0.014 (0.36)
0.011 (0.275)
0.005 (0.125)
SEATING
PLANE
0.034 (0.86)
0.018 (0.46)
0.015 (0.38)
0.007 (0.18)
Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
Changed VDD = 15 V 5% to VDD = 15 V 10% in Static Performance section in Test Conditions/Comments column . . . . . . . . 2
Changed A Version of Full-Scale Temperature Coefficient from 30 to 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changed B and T Versions of VDD Power Requirements from +11.4/+15.75 to +10.8/+16.5 for V min.
Changed B and T Versions of VSS Power Requirements from –11.4/–15.75 to –10.8/–16.5 for V max . . . . . . . . . . . . . . . . . . . . . 2
Change to Note 1 and Note 9 of Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to Note 2 in Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to R-24 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–16–
REV. B
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