AD7262BSTZ-5_技术文档

1 MSPS, 12-Bit, Simultaneous Sampling

SAR ADC with PGA and Four Comparators

AD7262

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AV

V

A

REF

CC

Dual simultaneous sampling 12-bit, 2-channel ADC

True differential analog inputs

Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,

×24, ×32, ×48, ×64, ×96, ×128

REF

AD7262

BUF

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

V

+

A

OUTPUT

DRIVERS

D

A

PGA

T/H

OUT

Throughput rate per ADC

V

–

A

1 MSPS for AD7262

500 kSPS for AD7262-5

Analog input impedance: >1 GΩ

Wide input bandwidth

SCLK

CAL

CS

REFSEL

G0

CONTROL

LOGIC

G1

G2

G3

−3 dB bandwidth: 1.7 MHz at gain = 2

4 on-chip comparators

SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32

Device offset calibration, system gain calibration

On-chip reference: 2.5 V

V

DRIVE

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

V

+

B

OUTPUT

DRIVERS

D

B

T/H

PGA

OUT

V

–

B

PD0/D

PD1

PD2

IN

–40°C to +105°C operation

High speed serial interface

BUF

V

B

REF

SPI/QSPI™/MICROWIRE™/DSP compatible

48-lead LFCSP and LQFP packages

C

_C

V

C

A

B

CC

+

A

OUTPUT

C

A

OUT

DRIVERS

–

COMP

GENERAL DESCRIPTION

+

B

OUTPUT

DRIVERS

B

OUT

–

B

COMP

The AD7262/AD7262-5 are dual, 12-bit, high speed, low power,

successive approximation ADCs that operate from a single 5 V

power supply. The AD7262 features throughput rates of up to

1 MSPS per on-chip ADC. The AD7262-5 features throughput

rates of up to 500 kSPS. Two complete ADC functions allow

simultaneous sampling and conversion of two channels. Each

ADC is preceded by a true differential analog input with a PGA.

There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12,

×16, ×24, ×32, ×48, ×64, ×96, and ×128.

C

_C _GND

A

B

C

_C

V

C

D

CC

+

C

OUTPUT

DRIVERS

C

D

OUT

C

–

COMP

+

D

OUTPUT

DRIVERS

OUT

–

D

COMP

AGND

_C _GND

C

D

DGND

Figure 1.

The AD7262/AD7262-5 contain four comparators. Comparator A

and Comparator B are optimized for low power, while Compara-

tor C and Comparator D have fast propagation delays. The

AD7262/AD7262-5 feature a calibration function to remove any

device offset error and programmable gain adjust registers to

allow for input path (for example, sensor) offset and gain

compensation. The AD7262/AD7262-5 have an on-chip 2.5 V

reference that can be disabled if an external reference is preferred.

PRODUCT HIGHLIGHTS

1. Integrated PGA with a variety of flexible gain settings to

allow detection and conversion of low level analog signals.

2. Each PGA is followed by a dual simultaneous sampling

ADC, featuring throughput rates of 1 MSPS per ADC for

the AD7262. The conversion results of both ADCs are

simultaneously available on separate data lines or in succes-

sion on one data line if only one serial port is available.

3. Four integrated comparators that can be used to count

signals from pole sensors in motor control applications.

4. Internal 2.5 V reference.

The AD7262/AD7262-5 are ideally suited for monitoring small

amplitude signals from a variety of sensors. They include all the

functionality needed for monitoring the position feedback

signals from a variety of analog encoders used in motor control

systems.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7262

TABLE OF CONTENTS

Features .............................................................................................. 1

Application Details..................................................................... 20

Modes of Operation ....................................................................... 22

Pin-Driven Mode ....................................................................... 22

Gain Selection............................................................................. 22

Power-Down Modes .................................................................. 22

Control Register ......................................................................... 23

On-Chip Registers...................................................................... 24

Serial Interface ................................................................................ 25

Calibration....................................................................................... 27

Internal Offset Calibration........................................................ 27

Adjusting the Offset Calibration Registers................................. 28

System Gain Calibration............................................................ 28

Microprocessor Interfacing........................................................... 29

AD7262/AD7262-5 to ADSP-BF53x....................................... 29

Application Hints ........................................................................... 30

Grounding and Layout .............................................................. 30

PCB Design Guidelines for LFCSP.......................................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 6

Timing Diagram ........................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

Circuit Information.................................................................... 15

Comparators................................................................................ 15

Operation..................................................................................... 15

Analog Inputs.............................................................................. 15

V_DRIVE............................................................................................ 16

Reference ..................................................................................... 17

Typical Connection Diagrams.................................................. 17

REVISION HISTORY

7/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7262

SPECIFICATIONS

AV_CC= 4.75 V to 5.25 V, C_A_C_BV_CC= C_C_C_DV_CC= 2.7 V to 5.25 V, V_DRIVE= 2.7 V to 5.25 V, f_SAMPLE= 1 MSPS and f_SCLK= 40 MHz

for AD7262, f_SAMPLE= 500 kSPS and f_SCLK= 20 MHz for AD7262-5, V_REF= 2.5 V internal/external; T_A= −40°C to +105°C, unless

otherwise noted.

Table 1.

Parameter

DYNAMIC PERFORMANCE¹

Signal-to-Noise Ratio (SNR)²

Min

Typ

Max

Unit

Test Conditions/Comments

f_IN= 100 kHz sine wave

PGA gain setting = 2

70

73

72

dB

Signal-to-(Noise + Distortion) Ratio

(SINAD)²

Total Harmonic Distortion (THD)²

−85

−97

−76

−77

dB

Spurious-Free Dynamic Range (SFDR)²

Common-Mode Rejection Ratio (CMRR)³

For PGA gain setting = 2, ripple

frequency of 50 Hz/60 Hz; see Figure 17

and Figure 18

ADC-to-ADC Isolation³

Bandwidth³

−90

1.2

1.7

dB

MHz

@ −3 dB; PGA gain setting = 128

@ −3 dB; PGA gain setting = 2

DC ACCURACY

Resolution

12

1

0.99

0.305

0.2ꢀꢀ

0.305

Bits

LSB

Integral Nonlinearity²

Differential Nonlinearity²

Positive Full-Scale Error²

0.5

0.122

Guaranteed no missed codes to 12 bits

Pregain calibration

Postgain calibration

% FSR

μV/°C

0.018

0.061

0.092

0.012

0.061

0.122

0.018

0.061

Positive Full-Scale Error Match

Zero Code Error²

Preoffset and pregain calibration

Postoffset and postgain calibration

Zero Code Error Match

Negative Full-Scale Error²

Pregain calibration

Postgain calibration

Negative Full-Scale Error Match

Zero Code Error Drift

2.5

ANALOG INPUT

Input Voltage Range, V_IN+ and V_IN−

V

V_CM= AV_CC/2; PGA gain setting ≥ 2

V_REF

2 × Gain

V_CM

±

Common-Mode Voltage Range, V_CM

V_CM− 100 mV

V_CM+ 100 mV

V_CM= 2; PGA gain setting = 1;

see Figure 19^ꢀ

(V_CC/2) − 0.ꢀ

(V_CC/2) − 0.6

(V_CC/2) + 0.2

(V_CC/2) + 0.ꢀ

(V_CC/2) + 0.8

1

V

μA

pF

GΩ

V_CM= AV_CC/2; PGA gain setting = 2

V_CM= AV_CC/2; 3 ≤ PGA gain setting ≤ 32

V_CM= AV_CC/2; PGA gain setting ≥ ꢀ8

DC Leakage Current

Input Capacitance³

Input Impedance³

0.001

5

1

REFERENCE INPUT/OUTPUT

Reference Output Voltage⁵

Reference Input Voltage Range

DC Leakage Current

2.ꢀ95

2.5

0.3

2.505

1

V

μA

2.5 V 5 mV maꢁ @ 25°C

Eꢁternal reference applied to

Pin V_REFA/Pin V_REF

B

Input Capacitance³

20

ꢀ

20

pF

Ω

ppm/°C

μV rms

V_REFA, V_REFB Output Impedance³

Reference Temperature Coefficient

V_REFNoise³

Rev. 0 | Page 3 of 32

AD7262

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

0.7 × V_DRIVE

V

μA

pF

0.8

1

V_IN= 0 V or V_DRIVE

3

Input Capacitance, C_IN

ꢀ

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating State Leakage Current

Floating State Output Capacitance³

Output Coding

V_DRIVE− 0.2

V

μA

pF

0.ꢀ

1

5

Twos complement

19 × t_SCLK

CONVERSION RATE

Conversion Time

ns

Track-and-Hold Acquisition Time

Throughput Rate

ꢀ00

ns

MSPS

kSPS

1

500

AD7262

AD7262-5

COMPARATORS

Input Offset

Comparator A and Comparator B

Comparator C and Comparator D

Offset Voltage Drift

2

0.5

0 to ꢀ

0 to 1.7

ꢀ

mV

ꢂV/°C

V

pF

T_A= 25°C to 105°C only

All comparators

C_A_C_BV_CC= 5 V

C_A_C_BV_CC= 2.7 V

Input Common-Mode Range³

Input Capacitance³

Input Impedance³

I_DDNormal Mode (Static)⁶

1

GΩ

25 pF load, C_OUTꢁ = 0 V, V_CM= AV_CC/2,

V

_OVERDRIVE= 200 mV differential

Comparator A and Comparator B

Comparator C and Comparator D

Propagation Delay Time

3

6

60

120

μA

C_A_C_BV_CC= 3.3 V

C_A_C_BV_CC= 5.25 V

C_C_C_DV_CC= 3.3 V

C_C_C_DV_CC= 5.25 V

V_CM= AV_CC/2, V_OVERDRIVE= 200 mV

differential

8.5

170

High to Low, t_PHL

Comparator A and Comparator B

1.ꢀ

3.5

μs

C_A_C_BV_CC= 2.7 V

C_A_C_BV_CC= 5 V

C_C_C_DV_CC= 2.7 V

C_C_C_DV_CC= 5 V

0.95

0.20

0.13

Comparator C and Comparator D

0.32

Low to High, t_PLH

Comparator A and Comparator B

2

ꢀ

μs

C_A_C_BV_CC= 2.7 V

C_A_C_BV_CC= 5 V

C_C_C_DV_CC= 2.7 V

C_C_C_DV_CC= 5 V

V_CM= AV_CC2, V_OVERDRIVE= 200 mV

differential

0.93

0.18

0.12

Comparator C and Comparator D

Delay Matching

0.28

Comparator A and Comparator B

Comparator C and Comparator D

250

10

ns

Rev. 0 | Page ꢀ of 32

AD7262

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

AV_CC

C_A_C_BV_CC, C_C_C_DV_CC

V_DRIVE

Digital inputs = 0 V or V_DRIVE

ꢀ.75

2.7

5.25

V

I_DD

ADC Normal Mode (Static)

ADC Normal Mode (Dynamic)

Shutdown Mode

20

23

0.5

31.5

33.3

1

mA

ꢂA

AV_CC= 5.25 V

AV_CC= 5.25 V, ADCs and comparators

powered down

Power Dissipation

ADC Normal Mode (Static)

ADC Normal Mode (Dynamic)

Shutdown Mode

105

120

2.625

165

175

5.25

mW

μW

¹These specifications were determined without the use of the gain calibration feature.

²See the Terminology section.

³Samples tested during initial release to ensure compliance; they are not subject to production testing.

^ꢀFor PGA gain = 1; to use the full analog input range (V_CMV_REF/2) of the AD7262, the V_CMvoltage should be dropped to lie within a range from 1.95 V to 2.05 V.

⁵Refers to Pin V_REFA or Pin V_REFB.

⁶This specification includes the I_DDfor both comparators. The I_DDper comparator is the specified value divided by two.

Rev. 0 | Page 5 of 32

AD7262

TIMING SPECIFICATIONS

AV_CC= 4.75 V to 5.25 V, C_A_C_BV_CC= C_C_C_DV_CC= 2.7 V to 5.25 V, V_REF= 2.5 V internal/external; T_A= T_MINto T_MAX, unless otherwise noted.¹

Table 2.

Limit at T_MIN, T_MAX

Parameter 2.7 V ≤ V_DRIVE≤ 3.6 V

4.75 V ≤ V_DRIVE≤ 5.25 V

Unit

Description

f_SCLK

200

ꢀ0

32

200

ꢀ0

32

kHz min

MHz maꢁ

MHz typ

MHz maꢁ

ns maꢁ

ns min

AD7262²

AD7262-5

t_SCLK= 1/f_SCLK

AD7262

20

t_CONVERT

19 × t_SCLK

ꢀ75

950

13

19 × t_SCLK

ꢀ75

950

13

AD7262-5

t_QUIET

t₂

Minimum time between end of serial read/bus relinquish

and neꢁt falling edge of CS

10

15

10

15

ns min

ns maꢁ

CS to SCLK setup time

Delay from 19^thSCLK falling edge until D_OUTA and D_OUTB are

3

t₃

three-state disabled

t_ꢀ

t₅

t₆

t₇

t₈

t₉

29

15

0.ꢀ × t_SCLK

13

23

13

0.ꢀ × t_SCLK

13

ns maꢁ

ns min

ns maꢁ

Data access time after SCLK falling edge

SCLK to data valid hold time

SCLK high pulse width

SCLK low pulse width

CS rising edge to falling edge pulse width

13

CS rising edge to D_OUTA, D_OUTB, high impedance/bus

relinquish

t₁₀

5

35

2

5

35

2

ns min

ns maꢁ

ꢂs min

SCLK falling edge to D_OUTA, D_OUTB, high impedance

t₁₁

t₁₂

Minimum CAL pin high time

2

Minimum time between the CAL pin high and the CS

falling edge

t₁₃

t_1ꢀ

t_POWER-UP

3

2ꢀ0

15

3

2ꢀ0

15

ns min

ꢂs maꢁ

D_INsetup time prior to SCLK falling edge

D_INhold time after SCLK falling edge

Internal reference, with a 1 ꢂF decoupling capacitor

With an eꢁternal reference, 10 ꢂs typical

¹Sample tested during initial release to ensure compliance. All input signals are specified with t_R= t_F= 5 ns (10% to 90% of AV_CC) and timed from a voltage level of 1.6 V.

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the

Terminology section.

²See the Serial Interface section.

³The time required for the output to cross 0.ꢀ V or 2.ꢀ V.

TIMING DIAGRAM

CS

t₈

t₂

t₆

21

1

2

3

4

5

18

19

20

t₇

29

30

31

t₉

SCLK

t₅

t₃

t₄

t_QUIET

DB11

DB10

DB9

DB1

DB0

D

A

B

A

B

A

B

A

B

A

B

A

B

OUT

THREE-STATE

THREE-

STATE

DB10

DB0

D

OUT

THREE-

STATE

Figure 2. Serial Interface Timing Diagram

Rev. 0 | Page 6 of 32

AD7262

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

V_DRIVEto DGND

V_DRIVEto AGND

−0.3 V to AV_CC

−0.3 V to +7 V

−0.3 V to +0.3 V

AV_CCto AGND/DGND

C_A_C_BV_CCto C_A_C_B_GND

C_C_C_DV_CCto C_C_C_D_GND

AGND to DGND

C_A_C_B_GND/C_C_C_D_GND to DGND −0.3 V to +0.3 V

ESD CAUTION

Analog Input Voltage to AGND

Digital Input Voltage to DGND

Digital Output Voltage to GND

V_REFA/V_REFB Input to AGND

−0.3 V to AV_CC+ 0.3 V

−0.3 V to +7 V

−0.3 V to V_DRIVE+ 0.3 V

−0.3 V to AV_CC+ 0.3 V

−0.3 V to V_DRIVE+ 0.3 V

C_OUTA/C_OUTB/C_OUTC/C_OUTD to GND

C_A/C_B/C_C/C_Dto

C_A_C_B_GND/C_C_C_D_GND

−0.3 V to

C_A_C_BV_CC/C_C_C_DV_CC+ 0.3 V

Operating Temperature Range

Storage Temperature Range

Junction Temperature

LFCSP Package

−ꢀ0°C to +105°C

−65°C to +150°C

150°C

θ_JAThermal Impedance

θ_JCThermal Impedance

LQFP Package

30°C/W

3°C/W

θ_JAThermal Impedance

θ_JCThermal Impedance

Pb-Free Temperature, Soldering

Reflow

55°C/W

16°C/W

255°C

2 kV

ESD

Rev. 0 | Page 7 of 32

AD7262

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

48 47 46 45 44 43 42 41 40 39 38 37

36 CAL

35 CS

1

2

C

_C V

B

A

CC

PIN 1

INDICATOR

AV

V

CAL

CS

C

_C

V

1

2

36

35

34

33

32

31

30

29

A

B

CC

34 SCLK

–

3

A

PIN 1

AV

V

INDICATOR

V

+

4

33 AV

CC

A

SCLK

AV

CC

–

A

3

32

31

30

29

D

C

A

5

AGND

AV

CC

OUT

V

+

A

4

AD7262

6

B

A

B

D

C

A

TOP VIEW

5

AGND

AV

CC

OUT

7

AD7262

(Not to Scale)

B

A

B

6

TOP VIEW

8

AGND

7

(Not to Scale)

28 DGND

9

V

+

B

AGND

8

27

26

25

V

DRIVE

10

11

V

–

B

V

+

–

9

28 DGND

B

AV

C

D

CC

OUT

V

DRIVE

10

11

12

27

26

25

B

C

_C V

D CC 12

C

AV

C

D

CC

OUT

C

_C V

D

13 14 15 16 17 18 19 20 21 22 23 24

C

NOTES

1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST

BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR

NOISE AND MECHANICAL STRENGTH BENEFITS.

Figure 3. 48-Lead LQFP Pin Configuration

Figure 4. 48-Lead LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

2, 7, 11, 20, 33, ꢀ1

AV_CC

Analog Supply Voltage, ꢀ.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the

AD7262/AD7262-5. All AV_CCpins can be tied together. This supply should be decoupled to AGND

with a 100 nF ceramic capacitor per supply and a 10 ꢂF tantalum capacitor.

1

C_A_C_BV_CC

C_C_C_DV_CC

Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and

Comparator B. This supply should be decoupled to C_A_C_B_GND. AV_CC, C_C_C_DV_CC, and C_A_C_BV_CCcan be

tied together.

Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and

Comparator D. This supply should be decoupled to C_C_C_D_GND. AV_CC, C_C_C_DV_CC, and C_A_C_BV_CCcan be

tied together.

12

ꢀ, 3

9, 10

ꢀ3, 18

V_A+, V_A−

V_B+, V_B−

Analog Inputs of ADC A. True differential input pair.

Analog Inputs of ADC B. True differential input pair.

Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the

internal reference buffer for each respective ADC. Typically, 1 ꢂF capacitors are required to decouple

the reference. Provided the output is buffered, the on-chip reference can be taken from these pins

and applied eꢁternally to the rest of a system.

V

_REFA, V_REF

B

3ꢀ

SCLK

Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the

AD7262/AD7262-5. This clock is also used as the clock source for the conversion process. A

minimum of 31 clocks is required to perform the conversion and access the 12-bit result.

36

21

CAL

PD2

Logic Input. Initiates an internal offset calibration.

Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD1

and PD0 pins (see Table 7).

22

PD1

Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2

and PD0 pins (see Table 7).

Rev. 0 | Page 8 of 32

AD7262

Pin No.

Mnemonic

Description

23

PD0/D_IN

Logic Input/Data Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction

with the PD2 and PD1 pins (see Table 7). If all gain selection pins, G0 to G3, are tied low, this pin acts

as the data input pin, and all programming is via the control register (see Table 8). Data to be written

to the AD7262/AD7262-5 control register is provided on this input and is clocked into the register

on the falling edge of SCLK.

35

CS

Chip Select. Active low logic input. This input initiates conversions on the AD7262/AD7262-5.

ꢀ8, ꢀ7, ꢀ6, ꢀ5

C_A+, C_A−,

C_B+, C_B−

Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A

and Comparator B. These two comparators have very low power consumption.

13, 1ꢀ, 15, 16

5, 6, 8, 19, ꢀ2

C_C+, C_C−,

C_D+, C_D−

AGND

Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C

and Comparator D. This pair of comparators offers very fast propagation delays.

Analog Ground. Ground reference point for all analog circuitry on the AD7262/AD7262-5. All

analog input signals and any eꢁternal reference signal should be referred to this AGND voltage.

All AGND pins should connect to the AGND plane of a system. The AGND, DGND, C_A_C_B_GND, and

C_C_C_D_GND voltages ideally should be at the same potential and must not be more than 0.3 V apart,

even on a transient basis. C_A_C_B_GND and C_C_C_D_GND can be tied to AGND.

28

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7262/AD7262-5.

The DGND pin should be connected to the DGND plane of a system. The DGND and AGND voltages

should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient

basis.

30, 29, 26, 25

32, 31

C_OUTA, C_OUTB,

Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective

comparator. These are digital output pins with logic levels determined by the V_DRIVEsupply.

C_OUTC, C_OUT

D

D_OUTA, D_OUT

B

Serial Data Outputs. The data output from the AD7262/AD7262-5 is supplied to each pin as a serial

data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK

input. A total of 31 SCLKs is required to perform the conversion and access the 12-bit data. During

the conversion process, the data output pins are in three-state and, when the conversion is

completed, the 19^thSCLK edge clocks out the MSB. The data simultaneously appears on both pins

from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for

an additional 12 SCLK cycles on either D_OUTA or D_OUTB following the initial 31 SCLKs, the data from

the other ADC follows on the D_OUTpin. This allows data from a simultaneous conversion on both

ADCs to be gathered in serial format on either D_OUTA or D_OUTB using only one serial port.

ꢀ0, 39, 38, 37

27

G0, G1, G2, G3

V_DRIVE

Logic Inputs. These pins are used to program the gain setting of the front-end amplifiers. If all four

pins are tied low, the PD0 pin acts as a data input pin, D_IN, and all programming is made via the

control register (see Table 6).

Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what

voltage the interface operates, including the comparator outputs. This pin should be decoupled to

DGND.

ꢀꢀ, 17

C_A_C_B_GND,

C_C_C_D_GND

Comparator Ground. This is the ground reference point for all comparator circuitry on the AD7262/

AD7262-5. Both the C_A_C_B_GND pin and the C_C_C_D_GND pin should connect to the GND plane of a

system and can be tied to AGND. The DGND, AGND, C_A_C_B_GND, and C_C_C_D_GND voltages should

ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

2ꢀ

REFSEL

Internal/Eꢁternal Reference Selection. Logic input. If this pin is tied to a logic high voltage, the on-

chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is

tied to GND, an eꢁternal reference can be supplied to the AD7262/AD7262-5 through the V_REF

A

and/or V_REFB pin.

Rev. 0 | Page 9 of 32

AD7262

TYPICAL PERFORMANCE CHARACTERISTICS

0.6

0.4

AV

V

= 5V

AV

V

= 5V

CC

= 5V

f_S^D=^RIV1^EMSPS

CC

= 5V

f_S^D=^RIV1^EMSPS

A

0.4

T

= 25°C

T = 25°C

A

INTERNAL REFERENCE

PGA GAIN = 2

INTERNAL REFERENCE

PGA GAIN = 32

0.2

0

–0.2

–0.4

–0.6

–0.2

–0.4

–0.6

0

500

1000 1500 2000 2500 3000 3500 4000

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

Figure 5. Typical DNL at Gain of 2

Figure 8. Typical DNL at Gain of 32

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

AV

V

= 5V

AV

V

= 5V

CC

= 5V

f_S^D=^RIV1^EMSPS

T

= 25°C

T = 25°C

A

INTERNAL REFERENCE

PGA GAIN = 2

INTERNAL REFERENCE

PGA GAIN = 32

500

1000 1500 2000 2500 3000 3500 4000

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

Figure 6. Typical INL at Gain of 2

Figure 9. Typical INL at Gain of 32

0

–20

0

–20

AV

V

= 5V

AV

V

= 5V

CC

= 5V

f_S^D=^RIV1^EMSPS

CC

= 2.7V

f_S^D=^RIV1^EMSPS

T

= 25°C

T = 25°C

f_I^A_N= 100kHz

–40

INTERNAL REFERENCE

SNR = 73dB, THD = –82.5dB

PGA GAIN = 2

INTERNAL REFERENCE

SNR = 68.38dB, THD = –82dB

PGA GAIN = 32

–60

–80

–100

–120

–140

–100

–120

–140

50k 100k 150k 200k 250k 300k 350k 400k 450k

FREQUENCY (Hz)

0

50k 100k 150k 200k 250k 300k 350k 400k 450k 500k

FREQUENCY (Hz)

Figure 7. 3 dB Typical FFT at Gain of 2

Figure 10. Typical FFT at Gain of 32

Rev. 0 | Page 10 of 32

AD7262

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

2.4968

2.4967

2.4966

2.4965

2.4964

2.4963

2.4962

2.4961

8839

AV

V

= 5V

= 3V

f_S^D=^RIV1^EMSPS

CC

828

333

INTERNAL REFERENCE

0

20

40

60

80

100 120 140 160 180 200

2043

2044

2045

CODE

CURRENT LOAD (µA)

Figure 11. Histogram of Codes for 10k Samples at Gain of 2

Figure 14. V_REFvs. Reference Output Current Load

8000

1900

1800

1700

1600

1500

1400

1300

1200

1100

1000

900

6967

7000

6000

5000

4000

3000

2000

1000

0

1732

2047

AV

V

= 5V

f_S^D=^RIV1^EMSPS

1297

2045

CC

800

700

INTERNAL REFERENCE

0

4

0

600

1

2

3

4

6

8

12 16 24 32 48 64 96 128

GAIN

2044

2046

2048

2049

CODE

Figure 12. Histogram of Codes for 10k Samples at Gain of 32

Figure 15. 3 dB Bandwidth vs. Gain

80

75

70

65

60

55

50

45

40

35

30

–50

AV

V

= 5V

f_S^D=^RIV1^EMSPS

CC

–55

–60

–65

–70

–75

–70

–85

–90

INTERNAL REFERENCE

GAIN = 32

GAIN = 2

AV

V

= 5V

f_S^D=^RIV1^EMSPS

CC

INTERNAL REFERENCE

F

= 100kHz

IN

1

2

3

4

6

8

12 16 24 32 48 64 96 128

PGA GAIN

10

110 210 310 410 510 610 710 810 910

ANALOG INPUT FREQUENCY (kHz)

Figure 16. SNR vs. PGA Gain for an Analog Input Tone of 100 kHz

Figure 13. THD vs. Analog Input Frequency up to 1 MHz at Gain of 2 and 32

Rev. 0 | Page 11 of 32

AD7262

–90

–88

–86

–84

–82

–80

–78

–76

–74

–72

10

9

8

7

6

5

4

3

2

1

0

AV

V

= 5V

CC

= 3.3V

DRIVE

T

= 25°C

A

H TO L, C _C

V

= 3.6V

= 4.5V

= 2.7V

= 5V

A

B

CC

H TO L, C _C

A

H TO L, C _C

A

H TO L, C _C

A

L TO H, C _C

= 2.7V

= 3.6V

= 4.5V

= 5V

A

L TO H, C _C

A

L TO H, C _C

A

L TO H, C _C

A

AV

V

= 5V

f_S^D=^RIV1^EMSPS

CC

INTERNAL REFERENCE

f_RIPPLE= 50kHz

–70

1

2

3

4

6

8

12 16 24 32 48 64 96 128

GAIN

0

10

20

30

40

50

60

70

80

90

100

OVERDRIVE VOLTAGE (mV)

Figure 17. Common-Mode Rejection vs. Gain

Figure 20. Propagation Delay for Comparator A and Comparator B vs.

Overdrive Voltage for Various Supply Voltages

–80

–79

–78

–77

–76

–75

–74

–73

–72

–71

2.0

AV

= 5V

= 3.3V

CC

V

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

DRIVE

= 25°C

T

A

L TO H, C _C

V

= 2.7V

= 3.6V

= 4.5V

= 5V

C

D

CC

L TO H, C _C

C

L TO H, C _C

C

L TO H, C _C

C

H TO L, C _C

= 2.7V

= 3.6V

= 5V

C

H TO L, C _C

C

H TO L, C _C

C

AV

V

= 5V

f_S^D=^RIV1^EMSPS

CC

H TO L, C _C

= 4.5V

C

V

= 700mV p-p

RIPPLE

GAIN = 2

INTERNAL REFERENCE

–70

0

20

40

60

80

100 120 140 160 180 200

0

10

20

30

40

50

60

70

80

90

100

RIPPLE FREQUENCY (kHz)

OVERDRIVE VOLTAGE (mV)

Figure 18. Common-Mode Rejection vs. Common-Mode Ripple Frequency

Figure 21. Propagation Delay for Comparator C and Comparator D vs.

Overdrive Voltage for Various Supply Voltages

–10

–70

GAIN 1

AV

V

= 5V

f_S^D=^RIV1^EMSPS

V

= 5V

CC

DRIVE

GAIN = 2

= 25°C

–75

–80

–20

–30

–40

–50

–60

–70

–80

–90

–100

T

A

INTERNAL REFERENCE

f_IN= 100kHz

GAIN 2

INTERNAL REFERENCE

100mV p-p SINE WAVE ON AV

CC

AV

DECOUPLED WITH

CC

10µF AND 100nF CAPACITORS

–85

–90

–95

–100

–105

–110

–115

–120

GAIN 3

GAIN 16

GAIN 6

GAIN 8

GAIN 4

GAIN 12

GAIN 24

GAIN ≥ 32

1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

RANGE (V)

0

200

400

600

800

1000

V

SUPPLY RIPPLE FREQUENCY (kHz)

CM

Figure 19. THD vs. Common-Mode Range for Various PGA Gain Settings

Figure 22. Power Supply Rejection Ratio vs. Supply Ripple Frequency?

Rev. 0 | Page 12 of 32

AD7262

300

200

100

0

C

A/C

C/C

B SINK CURRENT

D SINK CURRENT

OUT

D

SINK CURRENT

–100

–200

–300

D

SOURCE CURRENT

OUT

C

A/C

C/C

B SOURCE CURRENT

D SOURCE CURRENT

OUT

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5

CURRENT (mA)

Figure 23. D_OUTand C_OUTSource and Sink Current

Rev. 0 | Page 13 of 32

AD7262

TERMINOLOGY

Differential Nonlinearity (DNL)

Total Harmonic Distortion (THD)

Differential nonlinearity is the difference between the measured

and the ideal 1 LSB change between any two adjacent codes in

the ADC.

Total harmonic distortion is the ratio of the rms sum of harmonics

to the fundamental. For the AD7262/AD7262-5, it is defined as

2

V₂+ V₃+ V₄+ V₅+ V₆

Integral Nonlinearity (INL)

THD(dB) = 20 log

V₁

Integral nonlinearity is the maximum deviation from a straight

line passing through the endpoints of the ADC transfer function.

The endpoints of the transfer function are zero scale, a single

(1) LSB point below the first code transition and full scale, a single

(1) LSB point above the last code transition.

where V₁is the rms amplitude of the fundamental, and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Zero Code Error

This is the deviation of the midscale transition (all 1s to all 0s)

from the ideal V_INvoltage, that is, V_CM– ½ LSB.

Peak harmonic, or spurious noise, is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2, excluding dc) to the rms value of the fun-

damental. Normally, the value of this specification is determined

by the largest harmonic in the spectrum, but for ADCs where

the harmonics are buried in the noise floor, it is a noise peak.

Positive Full-Scale Error

This is the deviation of the last code transition (011 … 110) to

(011 … 111) from the ideal, that is,

ADC-to-ADC Isolation

V_REF

2×Gain

⎛

⎜

⎝

⎞

⎟

⎠

V_CM

+

−1LSB

ADC-to-ADC isolation is a measure of the level of crosstalk

between the ADC A and ADC B. It is measured by applying a

full-scale, 100 kHz sine wave signal to all unselected input channels

and determining how much that signal is attenuated in the

selected channel with a 40 kHz signal. The figure given is the

worst case.

after the zero code error has been adjusted out.

Negative Full-Scale Error

This is the deviation of the first code transition (10 … 000) to

(10 … 001) from the ideal, that is,

PSRR (Power Supply Rejection)

V_REF

2×Gain

⎛

⎜

⎝

⎞

⎟

⎠

V_CM

−

+1LSB

Variations in power supply affect the full-scale transition but

not the linearity of the converter. Power supply rejection is the

maximum change in the full-scale transition point due to a

change in power supply voltage from the nominal value (see

Figure 22).

after the zero code error has been adjusted out.

Zero Code Error Match

This is the difference in zero code error across both ADCs.

Propagation Delay Time, Low to High (t_PLH

)

Positive Full-Scale Error Match

Propagation delay time from low to high is defined as the time

taken from the 50% point on a low to high input signal until the

digital output signal reaches 50% of its final low value.

This is the difference in positive full-scale error across both ADCs.

Negative Full-Scale Error Match

This is the difference in negative full-scale error across both ADCs.

Propagation Delay Time, High to Low (t_PHL

)

Track-and-Hold Acquisition Time

Propagation delay time from high to low is defined as the time

taken from the 50% point on a high to low input signal until the

digital output signal reaches 50% of its final high value.

The track-and-hold amplifier returns to track mode at the end

of a conversion. Track-and-hold acquisition time is the time

required for the output of the track-and-hold amplifier to reach

its final value, within 1/2 LSB, after the end of a conversion.

Comparator Offset

Comparator offset is the measure of the density of digital 1s

and 0s in the comparator output when the negative analog

terminal of the comparator input is held at a static potential

and the analog input to the positive terminal of the comparators

is varied proportionally about the static negative terminal voltage.

Signal-to-(Noise + Distortion) Ratio

This ratio is the measured ratio of signal-to-(noise + distortion)

at the output of the analog-to-digital converter. The signal is the

rms amplitude of the fundamental. Noise is the sum of all non-

fundamental signals up to half the sampling frequency (f_S/2),

excluding dc. The ratio is dependent on the number of quan-

tization levels in the digitization process; the more levels, the

smaller the quantization noise. The theoretical signal-to-(noise +

distortion) ratio for an ideal N-bit converter with a sine wave

input is given by

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 12-bit converter, this is 86 dB.

Rev. 0 | Page 1ꢀ of 32

AD7262

THEORY OF OPERATION

Each pair of comparators operates from its own independent

CIRCUIT INFORMATION

supply, C_A_C_BV_CCand C_C_C_DV_CC. The comparators are specified

for supply voltages from 2.7 V to 5.25 V. If desired, C_A_C_BV_CC

and C_C_C_DV_CCcan be tied to the AV_CCsupply. The four compa-

rators on the AD7262/AD7262-5 are functional with C_A_C_BV_CC/

C_C_C_DV_CCgreater than or equal to 1.8 V. However, no specifica-

tions are guaranteed for comparator supplies less than 2.7 V.

The wide range of supply voltages ensures that the comparators

can be used in a variety of battery backup modes.

The AD7262/AD7262-5 are fast, dual, simultaneous sampling,

differential, 12-bit, serial ADCs. The AD7262/ AD7262-5

contain two on-chip differential programmable gain amplifiers,

two track-and-hold amplifiers, and two successive approxima-

tion analog-to-digital converters with a serial interface with two

separate data output pins. The AD7262/ AD7262-5 also include

four on-chip comparators. They are housed in 48-lead LFCSP

and LQFP packages, offering the user considerable space-saving

advantages over alternative solutions. The AD7262/AD7262-5

require a low voltage 5 V 5% AV_CCto power the ADC core and

supply the digital power, a 5.25 V to 2.7 V C_A_C_BV_CC, C_C_C_DV_CC

supply for the comparators, and a 2.7 V to 5.25 V V_DRIVEsupply

for interface power.

The four on-chip comparators on the AD7262/AD7262-5 are

ideally suited for monitoring signals from pole sensors in motor

control systems. The comparators can be used to monitor

signals from Hall effect sensors or the inner tracks from an

optical encoder. One of the comparators can be used to count

the index marker or z marker, which is used on startup to place

the motor in a known position.

The on-board PGA allows the user to select from 14 program-

mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32,

×48, ×64, ×96, and ×128. The PGA accepts fully differential

analog signals. The gain can be selected either by setting the

logic state of the G0 to G3 pins or by programming the control

register.

OPERATION

The AD7262/AD7262-5 have two successive approximation

ADCs, each based around two capacitive DACs and two

programmable gate amplifiers.

The serial clock input accesses data from the part while also

providing the clock source for each successive approximation

ADC. The AD7262/AD7262-5 have an on-chip 2.5 V reference

that can be disabled when an external reference is preferred. If

the internal reference is used elsewhere in a system, the output

from V_REFA and V_REFB must first be buffered. If the internal

reference is the preferred option, the user must tie the

REFSEL pin to a logic high voltage. Alternatively, if REFSEL

is tied to GND, an external reference can be supplied to both

ADCs through the V_REFA and V_REFB pins (see the Reference

section).

The ADC itself comprises control logic, a SAR, and two capacitive

DACs. The control logic and the charge redistribution DACs are

used to add and subtract fixed amounts of charge from the sam-

pling capacitor amplifiers to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code.

Each ADC is preceded by its own programmable gain stage. The

PGA features high analog input impedance, true differential analog

inputs that allow the output from any source or sensor to be

connected directly to the PGA inputs without any requirement for

additional external buffering. The variable gain settings ensure

that the device can be used for amplifying signals from a variety

of sources. The AD7262/AD7262-5 offer the flexibility to choose

the most appropriate gain setting to use the wide dynamic range

of the device.

The AD7262/AD7262-5 also feature a range of power-down

options to allow the user great flexibility with the independent

circuit components while allowing for power savings between

conversions. The power-down feature is implemented via the

control register or the PD0 to PD2 pins, as described in the

Control Register section.

ANALOG INPUTS

COMPARATORS

Each ADC in the AD7262/AD7262-5 has two high impedance

differential analog inputs. Figure 24 shows the equivalent circuit

of the analog input structure of the AD7262/AD7262-5. It consists

of a fully differential input amplifier that buffers the analog input

signal and provides the gain selected by using the gain pins or

the control register.

The AD7262/AD7262-5 have four on-chip comparators. Com-

parator A and Comparator B have ultralow power consumption,

with static power consumption typically less than 10 μW with a

3.3 V supply. Comparator C and Comparator D feature very fast

propagation delays of 130 ns for a 200 mV differential overdrive.

These comparators have push-pull output stages that operate

from the V_DRIVEsupply. This feature allows operation with a

minimum amount of power consumption.

Rev. 0 | Page 15 of 32

AD7262

The two diodes provide ESD protection. Care must be taken to

ensure that the analog input signals never exceed the supply rails

by more than 300 mV. Exceeding 300 mV causes these diodes to

become forward-biased and to start conducting current into the

substrate. These diodes can conduct up to 10 mA without

causing irreversible damage to the part. The C1 capacitors in

Figure 24 are typically 5 pF and can primarily be attributed to

pin capacitance.

When a full-scale step input is applied to either differential input

on the AD7262/AD7262-5 while the other analog input is held

at a constant voltage, 3 μs of settling time is typically required

prior to capturing a stable digital output code.

Transfer Function

The AD7262/AD7262-5 output is twos complement, and the

ideal transfer characteristic is shown in Figure 25. The designed

code transitions occur at successive integer LSB values (that is,

1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog

input range selected. The LSB size for the AD7262/AD7262-5 is

shown in the following equation:

V

DD

V

+

IN

V

+

AMP

OUT

C1

⎛

⎜

⎞

V_REF

2×Gain

V_REF

2×Gain

⎛

⎜

⎞

⎟

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎜

⎝

⎟

V

+

− V

−

⎜

⎟

CM

⎜

⎠ ⎟

⎠

⎝

⎠

⎝

2×

⎟

4096

⎜

⎝

⎟

⎠

V

DD

V

–

AMP

OUT

V

–

IN

C1

011...111

011...110

Figure 24. Analog Input Structure

The AD7262/AD7262-5 can accept differential analog inputs from

V_REF

2×Gain

V_REF

2×Gain

000...001

000...000

111...111

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

V_CM

−

to V_CM+

Table 5 details the analog input range for the AD7262/AD7262-5

for the various PGA gain settings. Here, V_REF= 2.5 V and V_CM

2.5 V (AV_CC/2, with AV_CC= 5 V).

=

100...010

100...001

100...000

Table 5. Analog Input Range for Various PGA Gain Settings

0V

– (FSR/2)) + 1LSB

(V

+ (FSR/2)) – 1LSB

CM

PGA Gain Setting

Analog Input Range for V_IN+ and V_IN−

0.75 V to 3.25 V¹

ANALOG INPUT

1

NOTES

2

3

ꢀ

6

1.875 V to 3.125 V

2.083 V to 2.916 V

2.187 V to 2.813 V

2.292 V to 2.708 V

2.3ꢀꢀ V to 2.656 V

2.396 V to 2.60ꢀ V

2.ꢀ22 V to 2.578 V

2.ꢀꢀ8 V to 2.552 V

2.ꢀ61 V to 2.539 V

2.ꢀ7ꢀ V to 2.526 V

2.ꢀ80 V to 2.520 V

2.ꢀ87 V to 2.513 V

2.ꢀ90 V to 2.510 V

1. FULL-SCALE RANGE (FSR) = V + – V –.

IN IN

Figure 25. Twos Complement Transfer Function

V_DRIVE

The AD7262/AD7262-5 have a V_DRIVEfeature to control the

voltage at which the serial interface operates. V_DRIVEallows the

ADC and the comparators to easily interface to both 3 V and

5 V processors. For example, when the AD7262/AD7262-5 are

operated with AV_CC= 5 V, the V_DRIVEpin can be powered from

a 3 V supply, allowing a large analog input range with low voltage

digital processors.

8

12

16

2ꢀ

32

ꢀ8

6ꢀ

96

128

¹For V_CM= 2 V. If V_CM= AV_CC/2, the analog input range for V_IN+ and V_IN− is 1.6 V

to 3.ꢀ V.

Rev. 0 | Page 16 of 32

AD7262

REFERENCE

TYPICAL CONNECTION DIAGRAMS

The AD7262/AD7262-5 can operate with either the internal

2.5 V on-chip reference or an externally applied reference. The

logic state of the REFSEL pin determines whether the internal

reference is used. The internal reference is selected for both ADCs

when the REFSEL pin is tied to logic high. If the REFSEL pin is

tied to AGND, an external reference can be supplied through

the V_REFA and/or V_REFB pins. On power-up, the REFSEL pin

must be tied to either a low or high logic state for the part to

operate. Suitable reference sources for the AD7262/AD7262-5

include AD780, AD1582, ADR431, REF193, and ADR391.

Figure 26 and Figure 27 are typical connection diagrams for the

AD7262/AD7262-5. In these configurations, the AGND pin is

connected to the analog ground plane of the system, and the

DGND pin is connected to the digital ground plane of the system.

The analog inputs on the AD7262/AD7262-5 are true differen-

tial and have an input impedance in excess of 1 GΩ; thus, no

driving op amps are required. The AD7262/AD7262-5 can operate

with either an internal or an external reference. In Figure 26, the

AD7262/AD7262-5 are configured to operate in control register

mode; thus, G0 to G3, PD1, and PD2 can be connected to ground

(low logic state). Figure 27 has the gain pins configured for a gain

of 2 setup; thus, the device is in pin-driven mode. Both circuit

configurations illustrate the use of the internal 2.5 V reference

The internal reference circuitry consists of a 2.5 V band gap

reference and a reference buffer. When the AD7262/AD7262-5

are operated in internal reference mode, the 2.5 V internal

reference is available at the V_REFA and V_REFB pins, which should

be decoupled to AGND using a 1 μF capacitor. It is recommended

that the internal reference be buffered before applying it elsewhere

in the system. The internal reference is capable of sourcing up

to 90 μA of current when the converter is static. If the internal

reference operation is required for the ADC conversion, the

REFSEL pin must be tied to logic high on power-up. The refer-

ence buffer requires 240 ꢀs to power up and charge the 1 μF

decoupling capacitor during the power-up time.

The C_A_C_BV_CCand the C_C_C_DV_CCpins can be connected to either

a 3 V or a 5 V supply voltage. The AV_CCpin must be connected

to a 5 V supply. All supplies should be decoupled with a 100 nF

capacitor at the device pin, and some supply sources may require a

10 μF capacitor where the source is supplied to the circuit board.

The V_DRIVEpin is connected to the supply voltage of the micro-

processor. The voltage applied to the V_DRIVEinput controls the

voltage of the serial interface. V_DRIVEcan be set to 3 V or 5 V.

Rev. 0 | Page 17 of 32

AD7262

+5V

ANALOG

SUPPLY

1

100nF

10µF

1

10µF

100nF

COMPARATOR

SUPPLY 3V TO 5V

2

100nF

17 44

5

6

8

19 42 28

2

7

11 20 41 12

1

33

3.125V

2.500V

1.875V

27

3V OR 5V

SUPPLY

3

4

V

DRIVE

V

–

+

A

V

– AND V +

A

CONNECT

DIRECTLY

1

10µF

A

100nF

40

39

38

37

GAIN 2

G0

G1

G2

G3

TO SENSOR

OUTPUTS

3.125V

2.500V

1.875V

V

A

SERIAL

INTERFACE

43

V

A

34

35

REF

SCLK

CS

1µF

THIS REFERENCE SIGNAL

MUST BE BUFFERED

BEFORE IT CAN BE

USED ELSEWHERE IN

THE CIRCUIT

AD7262

MICROPROCESSOR/

MICROCONTROLLER

32

31

D

A

B

OUT

18

V

B

D

1µF

24

36

V

REFSEL

CAL

DRIVE

3.125V

2.500V

9

V

+

B

V

– AND V +

B

23

B

PD0/D

IN

1.875V

CONNECT

DIRECTLY

TO SENSOR

OUTPUTS

GAIN 2

22

21

PD1

PD2

3.125V

2.500V

1.875V

10

–

B

13 14 15 16

45 46 47 48

LOW POWER

25 26 29 30

FAST PROPAGATION DELAY

COMPARATOR INPUTS

1

2

THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED IN ALL SYSTEMS.

THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED.

Figure 26. Typical Connection Diagram for the AD7262/AD7262-5 in Control Register Mode (All Gain Pins Tied to Ground) Configured for a PGA Gain of 2

Rev. 0 | Page 18 of 32

AD7262

+5V

ANALOG

SUPPLY

1

100nF

10µF

1

10µF

100nF

COMPARATOR

SUPPLY 3V TO 5V

2

100nF

17 44

5

6

8

19 42 28

2

7

11 20 41 12

1

33

3.125V

2.500V

1.875V

27

3V OR 5V

SUPPLY

3

4

V

DRIVE

V

–

+

A

V

– AND V +

A

CONNECT

DIRECTLY

1

10µF

A

100nF

40

39

38

37

GAIN 2

G0

G1

G2

G3

V

DRIVE

TO SENSOR

OUTPUTS

3.125V

2.500V

1.875V

GAIN 2

SETUP

A

SERIAL

INTERFACE

43

A

34

35

REF

SCLK

CS

1µF

THIS REFERENCE SIGNAL

MUST BE BUFFERED

BEFORE IT CAN BE

USED ELSEWHERE IN

THE CIRCUIT

AD7262

MICROPROCESSOR/

MICROCONTROLLER

32

31

D

A

B

OUT

18

V

B

D

1µF

24

36

V

REFSEL

CAL

DRIVE

3.125V

2.500V

9

V

+

B

V

– AND V +

B

23

22

B

V

PD0/D

IN

DRIVE

CONNECT

DIRECTLY

TO SENSOR

OUTPUTS

1.875V

GAIN 2

BOTH

COMPARATORS

AND ADCs

PD1

PD2

3.125V

2.500V

1.875V

10

POWERED ON

21

–

B

V

DRIVE

13 14 15 16

45 46 47 48

LOW POWER

25 26 29 30

FAST PROPAGATION DELAY

COMPARATOR INPUTS

1

2

THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED IN ALL SYSTEMS.

THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED.

Figure 27. Typical Connection Diagram for the AD7262/AD7262-5 in Pin-Driven Mode with Gain of 2 and Both ADCs and Comparators Fully Powered On

Rev. 0 | Page 19 of 32

AD7262

Comparator Application Details

APPLICATION DETAILS

The comparators on the AD7262/AD7262-5 have been

designed with no internal hysteresis, allowing users the

flexibility to add external hysteretic if required for systems

operating in noisy environments. If the comparators on the

AD7262/AD7262-5 are used with external hysteresis, some

external resistors and capacitors are required, as shown in

Figure 28. The value of R_Fand R_S, the external resistors, can be

determined using the following equation, depending on the

amount of hysteresis required in the application:

The AD7262/AD7262-5 have been specifically designed to meet

the requirements of any motor control shaft position feedback

loop. The devices can interface directly to multiple sensor types,

including optical encoders, magneto resistive sensors, and Hall

effect sensors. Flexible analog inputs that incorporate program-

mable gain ensure that identical board design can be used for a

variety of sensors, which results in reduced design cycles and costs.

The two simultaneous sampling ADCs are used to sample the

sine and cosine outputs from the sensor. No external buffering

is required between the sensor/transducer and the analog inputs

of the AD7262/AD7262-5. The on-chip comparators can be

used to monitor the pole sensors, which can be Hall effect sensors

or the inner tracks from an optical encoder.

R_S

R_S+ R_F

V_HYS

=

×C_x_ C_xV_CC

where C_x_C_xV_CC= C_A_C_BV_CCor C_C_C_DV_CC.

The amount of hysteresis chosen must be sufficient to eliminate

the effects of analog noise at the comparator inputs, which may

affect the stability of the comparator outputs. The level of

hysteresis required in any system depends on the noise in the

system; thus, the values of R_Fand R_Sneed to be carefully selected

to eliminate any noise effects. To increase the level of hysteresis in

the system, increase the value of R_Sor R_F. For example, R_F= 10 MΩ,

R_S= 1 kΩ give 330 μV of hysteresis with a C_x_C_xV_CCof 3.3 V; if

hysteresis is increased to 1 mV, R_S= 3.1 kΩ. In certain applications,

a load capacitor (100 pF) may be required on the comparator

outputs to suppress high frequency transient glitches.

Figure 29 shows how the AD7262/AD7262-5 can be used in a

typical application. An optical encoder is shown in Figure 29,

but other sensor types could as easily be used. Figure 29 indicates

a typical application configuration only, and there are several

other configurations that render equally effective results.

R

F

R

C –

S

x

C

x

SENSOR

S

C +

OUT

x

Figure 28. Recommended Comparator Connection Diagram

Rev. 0 | Page 20 of 32

AD7262

COMP

V

A

AV

REF

CC

REF

AD7262

BUF

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

V

+

–

A

OUTPUT

DRIVERS

D

A

PGA

T/H

OUT

A

SCLK

CAL

CS

REFSEL

G0

CONTROL

LOGIC

G1

G2

G3

B

V

DRIVE

V

+

B

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

OUTPUT

DRIVERS

–

D

B

T/H

PGA

B

OUT

PD0/D

PD1

PD2

IN

BUF

V

B

REF

C

_C V

B CC

A

H.E.

Z

C

+

A

OUTPUT

C

A

OUT

DRIVERS

–

A

COMP

+

U

B

OUTPUT

DRIVERS

B

OUT

–

B

COMP

C

_C _GND

A

B

C

_C V

D CC

C

+

V

C

OUTPUT

DRIVERS

C

D

OUT

C

–

C

COMP

+

W

D

OUTPUT

DRIVERS

OUT

–

D

COMP

_C _GND

C

D

AGND

DGND

Figure 29. Typical System Connection Diagram with Optical Encoder

Rev. 0 | Page 21 of 32

AD7262

MODES OF OPERATION

The AD7262/AD7262-5 allow the user to choose between two

modes of operation, pin-driven mode and control register mode.

POWER-DOWN MODES

The AD7262/AD7262-5 offer the user a number of power-down

options to enable individual device components to be powered

down independently. These options can be chosen to optimize

the power dissipation for different application requirements.

The power-down modes can be selected by either programming

the device via the control register or by driving the PD pins to

the appropriate logic levels. By setting the PD pins to a logic low

level when in pin-driven mode, all four comparators and both

ADCs can be powered down. The PD2 and PD0 pins must be

set to logic high and the PD1 pin set to logic low to power up all

circuitry on the AD7262/AD7262-5. The PD pin configurations

for the various power-down options are outlined in Table 7.

PIN-DRIVEN MODE

In pin-driven mode, the user can select the gain of the PGA, the

power-down mode, internal or external reference, and initiate

a calibration of the offset for both ADC A and ADC B. These

functions are implemented by setting the logic levels on the gain

pins (G3 to G0), the power-down pins (PD2 to PD0), the REFSEL

pin, and the CAL pin, respectively.

The logic state of Pin G3 to Pin G0 determines which mode of

operation is selected. Pin-driven mode is selected if at least one

of the gain pins is set to a logic high state. Alternatively, if all

four gain pins are connected to a logic low, the control register

mode of operation is selected.

Table 7. Power-Down Modes

Comparator A, Comparator C,

ADC A,

ADC B

GAIN SELECTION

PD2 PD1 PD0 Comparator B

Comparator D

The on-board PGA allows the user to select from 14 program-

mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32,

×48, ×64, ×96, and ×128. The PGA accepts fully differential

analog signals and provides three key functions, which include

selecting gains for small amplitude input signals, driving the

ADCs switched capacitive load, and buffering the source from

the switching effects of the SAR ADCs. The AD7262/AD7262-5

offer the user great flexibility in user interface, providing gain

selection via the control register or by driving the gain pins to

the desired logic state. The AD7262/AD7262-5 have four gain

pins, G3, G2, G1 and G0, as shown in Figure 3. Each gain setting

is selected by setting up the appropriate logic state on each of

the four gain pins, as outlined in Table 6. If all four gain pins are

connected to a logic low level, the part is put in control register

mode and the gain settings are selected via the control register.

0

1

1¹

0

1

0

1¹

0

1

0

1

0

1

1¹

Off

On

Off

On

Off

On

Off

On

Off

On

Off

¹PD2 = PD1 = PD0 = 1 resets the AD7262/AD7262-5 when in pin-driven mode

only.

The AV_CCand V_DRIVEsupplies must continue to be supplied to

the AD7262/AD7262-5 when the comparators are powered up

but the ADCs are powered-down. External diodes can be used

from the C_A_C_BV_CCand/or C_C_C_DV_CCto both the AV_CCand the

V_DRIVEsupplies to ensure they retain a supply at all instances.

The AD7262/AD7262-5 can be reset in pin-driven mode only

by setting the PDx pins to a logic high state. When the device is

reset, all the registers are cleared and the four comparators and

the two ADCs are left powered down.

Table 6. Gain Selection

G3

G2

G1

G0

Gain

0

Software control

via control register

In normal mode of operation with the ADCs and comparators

powered on, the C_A_C_BV_CC/C_C_C_DV_CCsupply and the AV_CC

supply can be at different voltage levels, as indicated in Table 1.

When the comparators on the AD7262/AD7262-5 are in power-

down mode, and the C_A_C_BV_CC/C_C_C_DV_CCsupplies are at a

potential 0.3 V greater than or less than the AV_CCsupply, the

supplies consume more current than would be the case if both

sets of supplies were at the same potential. This configuration

does not damage the AD7262/AD7262-5 but results in additional

current flowing in any or all of the AD7262/AD7262-5 supply

pins. This is due to ESD protection diodes within the device. In

applications where power consumption in power-down mode is

critical, it is recommended that the C_A_C_BV_CC/C_C_C_DV_CCsupply

and the AV_CCsupply be held at the same potential.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

ꢀ

6

8

12

16

2ꢀ

32

ꢀ8

6ꢀ

96

128

Rev. 0 | Page 22 of 32

AD7262

Power-Up Conditions

These functions can also be implemented by setting the logic

levels on the gain pins, the power-down pins, and the CAL pin,

respectively. The control register can also be used to read the

offset and gain registers.

On power-up, the status of the gain pins determine which mode

of operation is selected, as outlined in the Gain Selection section.

All registers are set to 0 by default.

Data is loaded from the PD0/D_INpin of the AD7262/AD7262-5

If the AD7262/AD7262-5 are powered up in pin-driven mode,

the gain pins and the PDx pins should be configured to the

appropriate logic states and a calibration initiated if required.

CS

on the falling edge of SCLK when

is in a logic low state. The

control register is selected by first writing the appropriate four

WR bits, as outlined in Table 10. The 12 data bits must then be

clocked into the control register of the device. Thus, on the 16^th

falling SCLK edge, the LSB is clocked into the device. One more

SCLK cycle is then required to write to the internal device

registers. In total, 17 SCLK cycles are required to successfully

write to the AD7262/AD7262-5. The data is transferred on the

PD0/D_INline while the conversion result is being processed.

The data transferred on the D_INline corresponds to the AD7262/

AD7262-5 configuration for the next conversion.

Alternatively, if the AD7262/AD7262-5 are powered up in

control register mode, the comparators and ADCs are powered

down and the default gain is 1. Thus, powering up in control

register mode requires a write to the device to power up the

comparators and the ADCs.

It takes 15 μs to power up the AD7262/AD7262-5 when using

an external reference. When the internal reference is used, 240 μs

are required to power up the AD7262/AD7262-5 with a 1 μF

decoupling capacitor.

Only the information provided on the 12 falling clock edges

CONTROL REGISTER

CS

after the

falling edge and the initial four write address bits is

loaded to the control register. The PD0/D_INpin should have a

logic low state for the four bits RD3 to RD0 when using the

control register to select the power-down modes or gain setting

or when initializing a calibration. The RD bits should also be set

The control register on the AD7262/AD7262-5 is a 12-bit read

and write register, which is used to control the device when not

in pin-driven mode. The PD0/D_INpin serves as the serial

D_INpin for the AD7262/AD7262-5 when the gain pins are set to

0 (that is, the part is not in pin-driven mode). The control

register can be used to select the gain of the PGAs, the power-

down modes, and the calibration of the offset for both ADC A

and ADC B. When operating in the control register mode, PD1

and PD2 should be connected to a low logic state.

to a logic low level to access the ADC results from both D_OUT

A

and D_OUTB.

The power-up status of all bits is 0 and the MSB denotes the first

bit in the data stream. The bit functions are outlined in Table 8

and Table 9.

Table 8. Control Register Bits

MSB

LSB

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RD3

RD2

RD1

RD0

CAL

PD2

PD1

PD0

G3

G2

G1

G0

Table 9. Control Register Bit Function Description

Bits

11 to 8

7

Mnemonic

RD3 to RD0

CAL

Description

Register address bits. These bits select which register the subsequent read is from. See Table 11.

Setting this bit high initiates an internal offset calibration. Once the calibration is completed, this pin can be reset low,

and the internal offset, which is stored in the on-chip offset registers, is automatically removed from the ADC results.

6 to ꢀ

3 to 0

PD2 toPD0

G3 to G0

Power-down bits. These bits select which power-down mode is programmed. See Table 7.

Gain selection bits. These bits select which gain setting is used on the front-end PGA. See Table 6.

Table 10. Write Address Bits

WR3

WR2

WR1

WR0

Read Register Addressed

0

1

Control register

CS

t₈

t₂

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

30

31

SCLK

t_QUIET

THREE-STATE

DB11 DB10

DB0

D

A

OUT

THREE-

STATE

t₁₃

t₁₄

THREE-STATE

PD0/D

WR3 WR2 WR1 WR0 RD3

RD2

RD1

RD0

CAL PD2

PD1

PD0

G3

G2

G1

G0

IN

Figure 30. Timing Diagram for a Write Operation to the Control Register

Rev. 0 | Page 23 of 32

AD7262

Table 11. Read and Write Register Addresses

ON-CHIP REGISTERS

RD3

RD2

RD1

RD0

Comment

The AD7262/AD7262-5 contain a control register, two offset

registers for storing the offsets for each ADC, and two external

gain registers for storing the gain error. The control register and

the offset and gain registers are read and write registers. On

power-up, all registers in the AD7262/AD7262-5 are set to 0.

0

1

0

1

0

1

0

1

0

1

ADC result (default)

Control register

Offset ADC A internal

Offset ADC B internal

Gain ADC A eꢁternal

Gain ADC B eꢁternal

Addressing the On-Chip Registers

Writing to a Register

Reading from a Register

Data is loaded from the PD0/D_INpin of the AD7262/AD7262-5

The internal offset of the device, which has been measured by

the AD7262/AD7262-5 and stored in the on-chip registers

during the calibration, can be read back by the user. The

content of the external gain registers can also be read. To read

the content of any register, the user must first write to the

control register by writing 0001 to the WR3 to WR0 bits via the

PD0/D_INpin, as outlined in Table 10. The next four bits in the

control register are the RD bits, which are used to select the

desired register from which to read. The appropriate 4-bit address

for each of the offset and gain registers is outlined in Table 11.

The remaining eight SCLK cycles bits are used to set the

remaining bits in the control register to the desired state for the

next ADC conversion.

The 19^thSCLK falling edge clocks out the first data bit of the

digital code corresponding to the value stored in the selected

internal device register on the D_OUTA pin. D_OUTB outputs the

conversion result from ADC B. Once the selected register has

been read, the control register must be reset to output the ADC

results for future conversions. This is achieved by writing 0001

to the WR3 to WR0 bits, followed by 0000 to the RD bits. The

remaining eight bits in the control register should then be set to

the required configuration for the next ADC conversion.

CS

on the falling edge of SCLK when

is in a logic low state. Four

address bits and 12 data bits must be clocked into the device.

Thus, on the 16^thfalling SCLK edge, the LSB is clocked into the

AD7262/AD7262-5. One more SCLK cycle is then required to

write to the internal device registers. In total, 17 SCLK cycles

are required to successfully write to the AD7262/AD7262-5.

The control and offset registers are 12-bits registers; the gain

registers are 7-bit registers.

When writing to a register, the user must first write the address

bits corresponding to the selected register. Table 11 shows the

decoding of the address bits. The four RD bits are written MSB

first, that is, RD3 followed by RD2, RD1, and RD0. The

AD7262/AD7262-5 decodes these bits to determine which

register is being addressed. The subsequent 12 bits of data are

written to the addressed register.

When writing to the external gain registers, the seven bits of

data immediately after the four address bits are written to the

register. However, 17 SCLK cycles are still required, and the

PD0/D_INpin of the AD7262/AD7262-5 should be tied low for

the five additional clock cycles.

CS

t₈

t₂

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

30

31

SCLK

t_QUIET

THREE-STATE

DB11_ADB10_A

DB0_A

D

A

OUT

THREE-

STATE

t₁₃

t₁₄

THREE-STATE

RD3 RD2 RD1

RD0 MSB DB10 DB9

DB8

DB7 DB6

DB5

DB4 DB3 DB2

DB1

DB0

PD0/D

IN

Figure 31. Timing Diagram for Writing to a Register

CS

t₈

t₂

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

30

31

SCLK

t_QUIET

THREE-STATE

DB11_ADB10_A

DB0_A

D

A

OUT

t₁₃

t₁₄

THREE-

STATE

THREE-STATE

0

1

RD3 RD2

RD1

RD0

0

PD0/D

IN

Figure 32. Timing Diagram for a Read Operation with PD0/D_INas an Input

Rev. 0 | Page 2ꢀ of 32

AD7262

SERIAL INTERFACE

Figure 33 and Figure 34 show the detailed timing diagrams for

the serial interfacing of the AD7262/AD7262-5. The serial clock

provides the conversion clock and controls the transfer of

information from the AD7262/AD7262-5 after the conversion.

The AD7262/AD7262-5 has two output pins corresponding to

each ADC. Data can be read from the AD7262/AD7262-5 using

both D_OUTA and D_OUTB. Alternatively, a single output pin of the

user’s choice can be used. The SCLK input signal provides the

clock source for the serial interface.

reading on the 21^stSCLK rising edge. The remainder of the 12-bit

result follows, with the final bit in the data transfer being valid

on the 31^strising edge. The LSB is provided on the 30^thfalling

clock edge.

An alternative to reading on the rising SCLK edge is to use a

slower SCLK frequency. If a slower SCLK frequency is used, for

example 32 MHz with the AD7262, this will enable reading on

the subsequent falling SCLK edge after the data has been

clocked out, as illustrated in Figure 35. A throughput rate of

1 MSPS can still be achieved for the AD7262 when a 32 MHz

SCLK frequency is used. The remaining data is then clocked out

by subsequent SCLK falling edges. When using a 32 MHz or

less SCLK frequency with the AD7262 or when using the

AD7262-5, the 20^thfalling clock edge on the serial clock has the

MSB provided for reading and also clocks out the second data bit.

The remainder of the 12-bit result follows, with the final bit in

the data transfer being valid on the 31^stfalling edge. The LSB is

provided on the 30^thfalling clock edge.

CS

The falling edge of

puts the track-and-hold into hold mode,

at which point the analog input is sampled. The conversion is

also initiated at this point and requires a minimum of 19 SCLKs

to complete. The D_OUTx lines remain in three-state while the

conversion is taking place. On the 19^thSCLK falling edge, the

AD7262/AD7262-5 return to track mode and the D_OUTA and

D_OUTB lines are enabled. The data stream consists of 12 bits of

data, MSB first.

The MSB of the conversion result is clocked out on the 19^th

SCLK falling edge to be read by the microcontroller or DSP on

either the subsequent SCLK falling edge (20^thfalling edge) or

the 20^thSCLK rising edge. The choice of whether to read on the

rising or falling SCLK edge depends on the SCLK frequency

being used. When the maximum SCLK frequency of 40 MHz is

used with a V_DRIVEvoltage of 5 V, the maximum specified access

time (t₄) is 23 ns, resulting in 2 ns of setup time, which may not

be sufficient for most DSPs or microcontrollers. Under these

conditions, it is recommended to use the rising SCLK edge to

read the data. In this case, the MSB of the conversion result is

clocked out on the 19^thSCLK falling edge to be read on the 20^th

SCLK rising edge, as shown in Figure 33. The remaining data is

then clocked out by subsequent SCLK falling edges. When using

a 40 MHz SCLK frequency, the 20^thfalling clock edge on the

serial clock clocks out the second data bit, which is provided for

CS

On the rising edge of , D_OUTA and D_OUTB go back into three-

CS

state. If

is not brought high after 31 SCLKs but is instead

held low for an additional 12 SCLK cycles, the data from

ADC B is output on D_OUTA after the ADC A result. Likewise,

the data from ADC A is output on D_OUTB after the ADC B

result. This is illustrated in Figure 34, which shows the D_OUT

A

example. In this case, the D_OUTline in use goes back into three-

th

CS

state on the 45 SCLK falling edge or the rising edge of

whichever occurs first.

,

CS

If the falling edge of SCLK coincides with the falling edge of

the falling edge of SCLK is not acknowledged by the AD7262

and the next falling edge of SCLK is the first one registered after

CS

,

the falling edge of

.

Rev. 0 | Page 25 of 32

AD7262

FIRST DATA BIT CLOCKED OUT

ON THE 19 FALLING EDGE

FIRST DATA BIT READ

ON 20 RISING EDGE

TH

CS

t₈

t₂

1

2

3

4

5

18

19

20

21

22

29

30

31

SCLK

t₅

t₄

DB11

DB10

DB9

DB1

DB0

D

A

B

A

B

A

B

A

B

A

B

A

B

OUT

THREE-STATE

THREE-

STATE

OUT

THREE-

STATE

Figure 33. Serial Interface Timing Diagram When Reading Data on the 20^thRising SCLK Edge with a 40 MHz SCLK

CS

1

2

18

19

20

21

29

30

31

43

44

45

SCLK

t₁₀

D

A

DB13

DB12

DB1

DB0

DB13

DB12

DB1

DB0

B

OUT

A

B

THREE-

STATE

THREE-STATE

Figure 34. Reading Data from Both ADCs on One D_OUTLine with 45 SCLKs

FIRST DATA BIT CLOCKED

OUT ON THIS EDGE

FIRST DATA BIT READ

ON THIS EDGE

CS

t₈

t₂

t₆

3

4

5

1

2

SCLK

18

19

20

t₇

21

29

30

31

t₉

t₅

t₃

t_QUIET

t₄

DB11

DB10

DB9

DB1

DB0

D

A

B

A

B

A

B

A

B

A

B

A

B

OUT

THREE-STATE

THREE-

STATE

DB10

DB9

DB0

D

OUT

THREE-

STATE

Figure 35. Serial Interface Timing Diagram When Reading Data on the Falling SCLK Edge with a Slow SCLK Frequency

Rev. 0 | Page 26 of 32

AD7262

CALIBRATION

The AD7262/AD7262-5 registers store the offset value that can

be accessed easily by the user (see the Reading from a Register

section). When the device is calibrating, the differential analog

inputs for each respective ADC are shorted together internally

and a conversion is performed. A digital code representing the

offset is stored internally in the offset registers, and subsequent

conversion results have this measured offset removed.

INTERNAL OFFSET CALIBRATION

The AD7262/AD7262-5 allow the user to calibrate the device

offset using the CAL pin. This is achieved by setting the CAL

pin to a high logic level, which initiates a calibration on the next

CS

falling edge. The calibration requires one full conversion

CS

cycle, which contains a

falling edge followed by 19 SCLKs to

complete. The CAL pin can remain high for more than one

conversion if desired, and the AD7262/AD7262-5 continue to

calibrate.

When the AD7262/AD7262-5 are calibrated, the calibration

results stored in the internal device registers are only relevant

for the particular PGA gain selected at the time of calibration. If

the PGA gain is changed, the AD7262/AD7262-5 must be

recalibrated. If the device is not recalibrated when the PGA gain

is changed, the offset for the previous gain setting continues to

be removed from the digital output code, which may lead to

inaccuracies.

CS

The CAL pin should only be driven high when the pin is high

CS

or after 19 SCLK cycles have elapsed when

between conversions). The CAL pin must be driven high t₁₂ns

CS CS

is low (that is,

before

goes low. If the

pin goes low before the t₁₂has

elapsed, the calibration result is inaccurate for the current

conversion, but, provided that the CAL pin remains high, the

subsequent calibration conversion is correct. If the CAL pin is

set to a logic high state during a conversion, that conversion result

is corrupted.

The offset range, which can be calibrated for, is 128 least

significant bits at a gain of 1. The maximum offset voltage,

which can be calibrated for, is reduced as the gain of the PGA

is increased.

Provided that the CAL pin has been held high for a minimum

of one conversion, and once t₁₂and t₁₁have been adhered to, the

calibration is complete after the 19^thSCLK cycle, and the CAL

Table 12 details the maximum offset voltage, which can be

removed by the AD7262/AD7262-5 without compromising the

available digital output code range. The least significant bit size is

AV_CC/2^BITs, which is 5/4096 or 1.22 mV for the AD7262/

AD7262-5. The maximum removable offset voltage is given by

CS

pin can be driven to a logic low state. The next

falling edge

after the CAL pin has been driven to a low logic state initiates

a conversion of the differential analog input signal for both

ADC A and ADC B.

1.22 mV

±128 LSB ×

Gain

Alternatively, one can use the control register to initiate an

offset calibration. This is done by setting the CAL bit in the

control register to 1. The calibration is then initiated on the next

Table 12. Offset Range

CS

falling edge, but the current conversion is corrupted. The

Gain

Maximum Removable Offset Voltage

ADCs on the AD7262/AD7262-5 must remain fully powered

up to complete the internal calibration.

1

2

3

32

156.16 mV

78.08 mV

52.053 mV

ꢀ.88 mV¹

¹This is the maꢁimum removable offset for PGA gain ≥ 32.

t₁₁

t₁₂

CAL

t₈

CS

t₆

t₂

1

2

3

19

20

21

30

31

1

2

3

19

20

21

SCLK

t₇

Figure 36. Calibration Timing Diagram

Rev. 0 | Page 27 of 32

AD7262

ADJUSTING THE OFFSET CALIBRATION REGISTERS

SYSTEM GAIN CALIBRATION

The internal offset calibration register can be adjusted manually

to compensate for any signal path offset from the sensors to the

ADC. Here, no internal calibration is required, and the CAL pin

can remain at a low logic state. By changing the contents of the

offset register, different amounts of offset on the analog input

signal can be compensated for. To determine the digital code to

be written to the offset register

The AD7262/AD7262-5 also allow the user to write to an

external gain register, thus enabling the removal of any overall

system gain error. Both ADC A and ADC B have independent

external gain registers, allowing the user to calibrate

independently the gain on both ADC A and ADC B signal

paths. The gain calibration feature can be used to implement

accurate gain matching between ADC A and ADC B.

1. Configure the sensor to its offset state.

2. Perform a number of conversions using the AD7262/

AD7262-5.

The system calibration function is used by setting the sensors to

which the AD7262/AD7262-5 are connected to a 0 gain state.

The AD7262/AD7262-5 convert this analog input to a digital

output code, which corresponds to the system gain and is avail-

able on the D_OUTx pins. This digital output code can then be stored

in the appropriate external register. For details on how to write to

a register, see the Writing to a Register section and Table 11.

3. Take the mean digital output code from both D_OUT

A

and D_OUTB. This is a 12-bit result and the offset register

is 12 bits; thus, the result can be stored directly in the

offset register.

4. Write the digital code to the offset registers to calibrate the

AD7262/AD7262-5.

The gain calibration register contains seven bits of data. By

changing the contents of the gain register, different amounts of

gain on the analog input signal can be compensated for. The

MSB is a sign bit, while the remaining six bits store the multiplica-

tion factor, which is used to adjust the analog input range. The

gain register value is effectively multiplied by the analog input

to scale the conversion result over the full range. Increasing the

gain register multiplication factor compensates for a larger

analog input range, and decreasing the gain register multiplier

compensates for a smaller analog input range. Each bit in the

gain calibration register has a resolution of 2.4 × 10⁻⁴V (1/4096).

A maximum of 1.538% of the analog range can be calibrated for.

The multiplier factor stored in the gain register can be decoded

as outlined in Table 13.

If a +10 mV offset is present in the analog input signal and the

gain of the PGA is 2, the code that needs to be written to the

offset register to compensate for the offset is

+10 mV

=16.39 = 0000 0001 0000

(1.22 mV /2

If a − 10 mV offset is present in the analog input signal and the

gain of the PGA is 2, the code that needs to be written to the

offset register to compensate for the offset is

−10 mV

(305 μV/2)

= −16.39 = 1000 0001 0000

The gain registers can be cleared by writing all 0s to each register,

as described in the Writing to a Register section. For accurate

gain calibration, both the positive and negative full-scale digital

output codes should be measured prior to determining the

multiplication factor that is written to the gain register.

Table 13. Decoding of Multiplication Factors for Gain Calibration

Digital Gain

Error

Gain Register

Code

Multiplier

Equation

Multiplier

Value

Analog Input

Comments

V

LSB

0 LSB

(Sign bit + 6 bits)

0 000000

(1 ꢁ/ꢀ096)

1 − 0/ꢀ096

V_INmaꢁ

1

Sign bit = 0, which implies negative sign

in multiplier equation

V_INmaꢁ – 2ꢀꢀ ꢂV

V_INmaꢁ − (63 × 2ꢀꢀ ꢂV)

V_INmaꢁ

−2 LSB

0 000001

0 111111

1 000000

1 000001

1 111111

1 − 1/ꢀ096

1 − 63/ꢀ096

1 + 0/ꢀ096

1 + 1/ꢀ096

1 + 63/ꢀ096

0.999755859

0.98ꢀ6191ꢀ

1

Sign bit = 0, which implies negative sign

in multiplier equation

Sign bit = 0, which implies negative sign

in multiplier equation

Sign bit = 1, which implies plus sign in

multiplier equation

Sign bit = 1, which implies plus sign in

multiplier equation

−126 LSB

0 LSB

V_INmaꢁ + 2ꢀꢀ ꢂV

V_INmaꢁ + (63 × 2ꢀꢀ ꢂV)

+2 LSB

1.0002ꢀꢀ1ꢀ1

1.015380859

+126 LSB

Sign bit = 1, which implies plus sign in

multiplier equation

Rev. 0 | Page 28 of 32

AD7262

MICROPROCESSOR INTERFACING

The serial interface on the AD7262/AD7262-5 allows the parts

to be directly connected to a range of different microprocessors.

This section explains how to interface the AD7262/AD7262-5

with the Analog Devices, Inc., Blackfin® DSP, the ADSP-BF537.

Table 14. The SPORT0 Receive Configuration 1 Register

(SPORT0_RCR1)

Setting

Description

RCKFE = 1

LRFS = 1

RFSR = 1

Sample data with falling edge of RSCLK

Active low frame signal

Frame every word

AD7262/AD7262-5 TO ADSP-BF53x

The ADSP-BF53x family of DSPs interface directly to the

AD7262/AD7262-5 without any glue logic required. The

V_DRIVEpin of the AD7262/AD7262-5 takes the same supply

voltage as that of the ADSP-BF53x. This allows the ADC to

operate at a higher supply voltage than its serial interface and,

therefore, the ADSP-BF53x, if necessary. The availability of

secondary receive registers on the serial ports of the Blackfin

DSPs means only one serial port is necessary to read from both

D_OUTpins simultaneously. Figure 37 shows both D_OUTA and

D_OUTB of the AD7262/AD7262-5 connected to Serial Port 0 of

the ADSP-BF53x. The SPORT0 Receive Configuration 1

register and SPORT0 Receive Configuration 2 register should

be set up as outlined in Table 14 and Table 15.

IRFS = 1

Internal receive frame sync (RFS) used

Receive MSB first

Zero fill

Internal receive clock

Receive enabled

31-bit data-word

RLSBIT = 0

RDTYPE = 00

IRCLK = 1

RSPEN = 1

SLEN = 11110

TFSR = RFSR = 1

Table 15. The SPORT0 Receive Configuration 2 Register

(SPORT0_RCR2)

Setting

Description

RXSE = 1

Secondary side enabled

A Blackfin driver for the AD7262/AD7262-5 is available to

download at www.analog.com.

AD7262¹

ADSP-BF53x¹

SPORT0

SERIAL

DEVICE A

(PRIMARY)

D

A

DR0PRI

RCLK0

RFS0

OUT

SCLK

CS

D

B

DR0SEC

OUT

SERIAL

DEVICE B

(SECONDARY)

V

DRIVE

V

DD

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 37. Interfacing the AD7262 to the ADSP-BF53x

Rev. 0 | Page 29 of 32

AD7262

APPLICATION HINTS

with a double-sided board. In this technique, the component

side of the board is dedicated to ground planes, while signals are

placed on the solder side.

GROUNDING AND LAYOUT

The analog and digital supplies to the AD7262/AD7262-5 are

independent and separately pinned out to minimize coupling

between the analog and digital sections of the device. The

printed circuit board (PCB) that houses the AD7262/AD7262-5

should be designed so that the analog and digital sections are

separated and confined to certain areas of the board. This

design facilitates the use of ground planes that can be easily

separated.

Good decoupling is also important. All analog supplies should

be decoupled with 10 μF tantalum capacitors in parallel with

100 nF capacitors to GND. To achieve the best results from these

decoupling components, they must be placed as close as possible

to the device, ideally right up against the device. The 0.1 μF

capacitors should have low effective series resistance (ESR) and

effective series inductance (ESI), such as the common ceramic

types or surface-mount types. These low ESR and ESI capacitors

provide a low impedance path to ground at high frequencies to

handle transient currents due to internal logic switching.

To provide optimum shielding for ground planes, a minimum

etch technique is generally best. All five AGND pins of the

AD7262/AD7262-5 should be sunk in the AGND plane. Digital

and analog ground planes should be joined in only one place. If

the AD7262/AD7262-5 are in a system where multiple devices

require an AGND to DGND connection, the connection should

still be made at one point only, a star ground point, that should

be established as close as possible to the ground pins on the

AD7262/AD7262-5.

PCB DESIGN GUIDELINES FOR LFCSP

The land on the chip scale packages (CP-48-1) are rectangular.

The PCB pad for these should be 0.1 mm longer than the

package land length and 0.05 mm wider than the package land

width, thereby having a portion of the pad exposed. To ensure

that the solder joint size is maximized, the land should be

centered on the pad.

Avoid running digital lines under the device because this

couples noise onto the die. However, the analog ground plane

should be allowed to run under the AD7262/AD7262-5 to

avoid noise coupling. The power supply lines to the AD7262/

AD7262-5 should use as large a trace as possible to provide low

impedance paths and reduce the effects of glitches on the power

supply line.

The bottom of the chip scale package has a thermal pad. The

thermal pad on the PCB should be at least as large as the

exposed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the

pad pattern to ensure that shorting is avoided.

To avoid radiating noise to other sections of the board, fast

switching signals, such as clocks, should be shielded with digital

ground, and clock signals should never run near the analog

inputs. Avoid crossover of digital and analog signals. To reduce

the effects of feedthrough within the board, traces on opposite

sides of the board should run at right angles to each other. A

microstrip technique is the best method but is not always possible

To improve thermal performance of the package, use thermal

vias on the PCB, incorporating them into the thermal pad at

1.2 mm pitch grid. The via diameter should be between 0.3 mm

and 0.33 mm, and the via barrel should be plated with 1 oz.

copper to plug the via. The user should connect the PCB thermal

pad to AGND.

Rev. 0 | Page 30 of 32

AD7262

OUTLINE DIMENSIONS

0.30

0.23

0.18

7.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

37

36

48

1

PIN 1

INDICATOR

EXPOSED

5.25

5.10 SQ

4.95

TOP

VIEW

6.75

BSC SQ

PAD

(BOTTOM VIEW)

0.50

0.40

0.30

25

24

12

13

0.25 MIN

5.50

REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

THE EXPOSED METAL PADDLE ON THE

BOTTOM OF THE LFCSP PACKAGE

MUST BE SOLDERED TO PCB GROUND

FOR PROPER HEAT DISSIPATION AND

ALSO FOR NOISE AND MECHANICAL

STRENGTH BENEFITS.

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.50 BSC

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Figure 38. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad

(CP-48-1)

Dimensions shown in millimeters

9.20

9.00 SQ

8.80

0.75

0.60

0.45

1.60

MAX

37

48

36

1

PIN 1

7.20

TOP VIEW

(PINS DOWN)

7.00 SQ

6.80

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

25

12

0.15

0.05

13

24

SEATING

0.08

0.27

0.22

0.17

PLANE

VIEW A

0.50

BSC

LEAD PITCH

COPLANARITY

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

Figure 39. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−ꢀ0°C to +105°C

Package Description

Package Option

AD7262BCPZ¹

ꢀ8-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

ꢀ8-Lead Low Profile Quad Flat Package [LQFP]

Evaluation Board

CP-ꢀ8-1

ST-ꢀ8

AD7262BCPZ-RL7¹

AD7262BCPZ-5¹

AD7262BCPZ-5-RL7¹

AD7262BSTZ¹

AD7262BSTZ-RL7¹

AD7262BSTZ-5¹

AD7262BSTZ-5-RL7¹

EVAL-AD7262EDZ¹

EVAL-CED1Z¹

Development Board

¹Z = RoHS Compliant Part.

Rev. 0 | Page 31 of 32

AD7262

NOTES

registered trademarks are the property of their respective owners.

D07606-0-7/08(0)

Rev. 0 | Page 32 of 32


型号：	AD7262BSTZ-5
厂家：	ADI
描述：	1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators 1 MSPS ， 12位，同步采样SAR ADC， PGA及4个比较转换器模数转换器
文件：	总32页 (文件大小：785K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7262BSTZ-5 [ADI]

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AD7262BSTZ-5-RL7

AD7262BSTZ-RL7

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AD7264BCPZ

AD7264BCPZ

AD7264BCPZ-5

AD7264BCPZ-5

AD7264BCPZ-5-RL7

AD7264BCPZ-RL7

AD7264BCPZ-RL7