AD7277BUJZ-500RL7 [ADI]
3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT; 3 MSPS ， 12位/ 10位/ 8位ADC，采用6引脚TSOT
| 型号： | AD7277BUJZ-500RL7 |
| 厂家： | 
ADI |
| 描述： | 3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT |
| 文件： | 总28页 (文件大小：501K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 MSPS, 12-/10-/8-Bit
ADCs in 6-Lead TSOT
AD7276/AD7277/AD7278
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
DD
Throughput rate: 3 MSPS
Specified for VDD of 2.35 V to 3.6 V
Power consumption
12.6 mW at 3 MSPS with 3 V supplies
Wide input bandwidth
70 dB SNR at 1 MHz input frequency
Flexible power/serial clock speed management
No pipeline delays
12-/10-/8-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
T/H
IN
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Temperature range: −40°C to +125°C
Power-down mode: 0.1 μA typical
6-lead TSOT package
SCLK
SDATA
CS
AD7276/
AD7277/
AD7278
CONTROL
LOGIC
8-lead MSOP package
AD7476 and AD7476A pin-compatible
GND
Figure 1.
GENERAL DESCRIPTION
Table 1.
Part Number
The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed,
low power, successive approximation analog-to-digital converters
(ADCs), respectively. The parts operate from a single 2.35 V
to 3.6 V power supply and feature throughput rates of up to
3 MSPS. The parts contain a low noise, wide bandwidth track-
and-hold amplifier that can handle input frequencies in excess
of 55 MHz.
Resolution
Package
AD7276
AD7277
AD7278
AD72741
AD72731
12
10
8
12
10
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
6-Lead TSOT
6-Lead TSOT
6-Lead TSOT
8-Lead TSOT
8-Lead TSOT
The conversion process and data acquisition are controlled
1 Part contains external reference pin.
using
and the serial clock, allowing the devices to interface
CS
PRODUCT HIGHLIGHTS
with microprocessors or DSPs. The input signal is sampled on
the falling edge of , and the conversion is also initiated at this
CS
point. There are no pipeline delays associated with the part.
1. 3 MSPS ADCs in a 6-lead TSOT package.
2. AD7476/AD7477/AD7478 and AD7476A/AD7477A/
AD7478A pin-compatible.
3. High throughput with low power consumption.
4. Flexible power/serial clock speed management. This allows
maximum power efficiency at low throughput rates.
5. Reference derived from the power supply.
6. No pipeline delay. The parts feature a standard successive
approximation ADC with accurate control of the sampling
The AD7276/AD7277/AD7278 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC; therefore,
the analog input range for the part is 0 to VDD. The conversion
rate is determined by the SCLK.
instant via a
input and once-off conversion control.
CS
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005–2011 Analog Devices, Inc. All rights reserved.
AD7276/AD7277/AD7278
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 16
Circuit Information.................................................................... 16
Converter Operation.................................................................. 16
ADC Transfer Function............................................................. 16
Typical Connection Diagram ................................................... 16
Modes of Operation................................................................... 18
Power vs. Throughput Rate....................................................... 21
Serial Interface ................................................................................ 22
AD7278 in a 10 SCLK Cycle Serial Interface.......................... 24
Microprocessor Interfacing....................................................... 24
Application Hints ........................................................................... 25
Grounding and Layout .............................................................. 25
Evaluating Performance.............................................................. 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7276 Specifications................................................................. 3
AD7277 Specifications................................................................. 5
AD7278 Specifications................................................................. 7
Timing Specifications—AD7276/AD7277/AD7278 ............... 8
Timing Examples........................................................................ 10
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 15
REVISION HISTORY
5/11—Rev. B to Rev. C
Changes to Figure 21...................................................................... 16
Changes to Ordering Guide .......................................................... 27
Changes to Endnote 5 .................................................................... 27
11/09—Rev. A to Rev. B
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 5
Changes to Table 4............................................................................ 7
Changes to Ordering Guide .......................................................... 27
10/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Table 2............................................................................ 3
Changes to Table 5............................................................................ 8
Changes to the Partial Power-Down Mode Section .................. 18
Changes to the Power vs. Throughput Rate Section.................. 21
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 26
7/05—Revision 0: Initial Version
Rev. C | Page 2 of 28
AD7276/AD7277/AD7278
SPECIFICATIONS
AD7276 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, B Grade and A Grade: fSCLK = 48 MHz, fSAMPLE = 3 MSPS, Y Grade:1 fSCLK = 16 MHz, fSAMPLE = 1 MSPS, TA = TMIN to
TMAX, unless otherwise noted.
Table 2.
Parameter
A Grade2, 3
B, Y Grade2,3
Unit
Test Conditions/Comments
fIN = 1 MHz sine wave, B Grade
fIN = 100 kHz sine wave, Y Grade
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)4
Signal-to-Noise Ratio (SNR)
68
69
70
−73
−78
−80
68
69
70
−73
−78
−80
dB min
dB min
dB typ
dB max
dB typ
dB typ
Total Harmonic Distortion (THD)4
Peak Harmonic or Spurious Noise (SFDR)4
Intermodulation Distortion (IMD)4
Second-Order Terms
Third-Order Terms
Aperture Delay
−82
−82
5
−82
−82
5
dB typ
dB typ
ns typ
fa = 1 MHz, fb = 0.97 MHz
fa = 1 MHz, fb = 0.97 MHz
Aperture Jitter
Full Power Bandwidth
18
55
8
18
55
8
ps typ
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
DC ACCURACY
Resolution
12
12
Bits
Integral Nonlinearity4
Differential Nonlinearity4
Offset Error4
1.5
+1/−0.99
4
3.5
5
1
LSB max
LSB max
LSB max
LSB max
LSB max
+1/−0.99
3
3.5
3.5
Guaranteed no missed codes to 12 bits
Gain Error4
Total Unadjusted Error4 (TUE)
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
0 to VDD
0 to VDD
V
1
5.5
42
10
1
5.5
42
10
μA max
μA max
pF typ
pF typ
−40°C to +85°C
85°C to 125°C
When in track
When in hold
Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
1.7
2
0.7
0.8
1
1.7
2
0.7
0.8
1
V min
V min
V max
V max
μA max
pF typ
2.35 V ≤ VDD ≤ 2.7 V
2.7 V < VDD ≤ 3.6 V
2.35 V ≤ VDD ≤ 2.7 V
2.7 V < VDD ≤ 3.6 V
Input Low Voltage, VINL
Input Current, IIN
Typically 10 nA, VIN = 0 V or VDD
5
Input Capacitance, CIN
2
2
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
VDD − 0.2
0.2
2.5
VDD − 0.2
0.2
2.5
V min
ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V
ISINK = 200 μA
V max
μA max
pF typ
4.5
4.5
Straight (natural) binary
Rev. C | Page 3 of 28
AD7276/AD7277/AD7278
Parameter
A Grade2, 3
B, Y Grade2,3
Unit
Test Conditions/Comments
CONVERSION RATE
Conversion Time
291
875
60
291
875
60
ns max
ns max
ns min
MSPS max
14 SCLK cycles with SCLK at 48 MHz, B Grade
14 SCLK cycles with SCLK at 16 MHz, Y Grade
Track-and-Hold Acquisition Time4
Throughput Rate
POWER REQUIREMENTS
VDD
3
3
See the Serial Interface section
2.35/3.6
2.35/3.6
V min/max
IDD
Digital I/Ps 0 V or VDD
Normal Mode (Static)
Normal Mode (Operational)
1
1
mA typ
mA max
mA max
mA typ
mA typ
μA typ
VDD = 3.6 V, SCLK on or off
5.5
2.5
4.2
1.6
34
2
5.5
2.5
4.2
1.6
34
2
VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS, B Grade
VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS, Y Grade
VDD = 3 V, fSAMPLE = 3 MSPS, B Grade
VDD = 3 V, fSAMPLE = 1 MSPS, Y Grade
Partial Power-Down Mode (Static)
Full Power-Down Mode (Static)
μA max
μA max
−40°C to +85°C, typically 0.1 μA
85°C to 125°C
10
10
Power Dissipation6
Normal Mode (Operational)
19.8
9
12.6
4.8
102
7.2
19.8
9
12.6
4.8
102
7.2
mW max
mW max
mW typ
mW typ
μW typ
VDD = 3.6 V, fSAMPLE = 3 MSPS, B Grade
VDD = 3.6 V, fSAMPLE = 1 MSPS, Y Grade
VDD = 3 V, fSAMPLE = 3 MSPS, B Grade
VDD = 3 V, fSAMPLE = 1 MSPS, Y Grade
VDD = 3 V
Partial Power-Down
Full Power-Down
μW max
VDD = 3.6 V, −40°C to +85°C
1 Y Grade specifications are guaranteed by characterization.
2 Temperature range from −40°C to +125°C.
3 Typical specifications are tested with VDD = 3 V and at 25°C.
4 See the Terminology section.
5 Guaranteed by characterization.
6 See the Power vs. Throughput Rate section.
Rev. C | Page 4 of 28
AD7276/AD7277/AD7278
AD7277 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
A Grade1, 2 B Grade1, 2
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)3
Total Harmonic Distortion (THD)3
fIN = 1 MHz sine wave
60.5
−70
−76
−80
60.5
−1
−76
−80
dB min
dB max
dB typ
dB typ
Peak Harmonic or Spurious Noise (SFDR)3
Intermodulation Distortion (IMD)3
Second-Order Terms
Third-Order Terms
Aperture Delay
−82
−82
5
−82
−82
5
dB typ
dB typ
ns typ
fa = 1 MHz, fb = 0.97 MHz
fa = 1 MHz, fb = 0.97 MHz
Aperture Jitter
18
18
ps typ
Full Power Bandwidth
74
10
74
10
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
DC ACCURACY
Resolution
10
0.5
0.5
1.5
2
10
0.5
0.5
1
1.5
2.5
Bits
Integral Nonlinearity3
Differential Nonlinearity3
Offset Error3
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 10 bits
Gain Error3
Total Unadjusted Error (TUE)3
2.5
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
0 to VDD
0 to VDD
V
1
5.5
42
10
1
5.5
42
10
μA max
μA max
pF typ
pF typ
−40°C to +85°C
85°C to 125°C
When in track
When in hold
Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
1.7
2
0.7
0.8
1
1.7
2
0.7
0.8
1
V min
V min
V max
V max
μA max
pF typ
2.35 V ≤ VDD ≤ 2.7 V
2.7 V < VDD ≤ 3.6 V
2.35 V ≤ VDD ≤ 2.7 V
2.7 V < VDD ≤ 3.6 V
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
Typically 10 nA, VIN = 0 V or VDD
4
2
2
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
VDD − 0.2
0.2
2.5
VDD − 0.2
0.2
2.5
V min
ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V
ISINK = 200 μA
V max
μA max
pF typ
4.5
4.5
Straight (natural) binary
CONVERSION RATE
Conversion Time
250
60
3.45
250
60
3.45
ns max
ns min
MSPS max
12 SCLK cycles with SCLK at 48 MHz
SCLK at 48 MHz
Track-and-Hold Acquisition Time3
Throughput Rate
Rev. C | Page 5 of 28
AD7276/AD7277/AD7278
Parameter
A Grade1, 2 B Grade1, 2
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.35/3.6
2.35/3.6
V min/max
IDD
Digital I/Ps 0 V or VDD
Normal Mode (Static)
Normal Mode (Operational)
0.6
5.5
3.5
34
2
0.6
5.5
3.5
34
2
mA typ
mA max
mA typ
μA typ
μA max
μA max
VDD = 3.6 V, SCLK on or off
VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS
VDD = 3 V
Partial Power-Down Mode (Static)
Full Power-Down Mode (Static)
−40°C to +85°C, typically 0.1 μA
85°C to 125°C
10
10
Power Dissipation5
Normal Mode (Operational)
19.8
10.5
102
7.2
19.8
10.5
102
7.2
mW max
mW typ
μW typ
VDD = 3.6 V, fSAMPLE = 3 MSPS
VDD = 3 V
VDD = 3 V
Partial Power-Down
Full Power-Down
μW max
VDD = 3.6 V, −40°C to +85°C
1 Temperature range from −40°C to +125°C.
2 Typical specifications are tested with VDD = 3 V and at 25°C.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
Rev. C | Page 6 of 28
AD7276/AD7277/AD7278
AD7278 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
A Grade1, 2
B Grade1, 2
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)3
Total Harmonic Distortion (THD)3
fIN = 1 MHz sine wave
49
49
dB min
dB max
dB typ
dB typ
−66
−73
−69
−67
−73
−69
Peak Harmonic or Spurious Noise (SFDR)3
Intermodulation Distortion (IMD)3
Second-Order Terms
Third-Order Terms
−76
−76
5
−76
−76
5
dB typ
dB typ
ns typ
fa = 1 MHz, fb = 0.97 MHz
fa = 1 MHz, fb = 0.97 MHz
Aperture Delay
Aperture Jitter
18
18
ps typ
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY
74
10
74
10
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
Resolution
8
8
Bits
Integral Nonlinearity3
Differential Nonlinearity3
Offset Error3
0.2
0.3
0.9
1.2
1.5
0.2
0.3
0.5
1
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 8 bits
Gain Error3
Total Unadjusted Error (TUE)3
1.5
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
0 to VDD
0 to VDD
V
1
5.5
42
10
1
5.5
42
10
μA max
μA max
pF typ
pF typ
−40°C to +85°C
85°C to 125°C
When in track
When in hold
Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
1.7
2
0.7
0.8
1
1.7
2
0.7
0.8
1
V min
V min
V max
V max
μA max
pF typ
2.35 V ≤ VDD ≤ 2.7 V
2.7 V < VDD ≤ 3.6 V
2.35 V ≤ VDD ≤ 2.7 V
2.7 V < VDD ≤ 3.6 V
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
4
2
2
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
VDD − 0.2
0.2
2.5
VDD − 0.2
0.2
2.5
V min
ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V
ISINK = 200 μA
V max
μA max
pF typ
4.5
4.5
Straight (natural) binary
CONVERSION RATE
Conversion Time
208
60
4
208
60
4
ns max
ns min
MSPS max
10 SCLK cycles with SCLK at 48 MHz
SCLK at 48 MHz
Track-and-Hold Acquisition Time3
Throughput Rate
Rev. C | Page 7 of 28
AD7276/AD7277/AD7278
Parameter
A Grade1, 2
B Grade1, 2
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.35/3.6
2.35/3.6
V min/max
IDD
Digital I/Ps = 0 V or VDD
VDD = 3.6 V, SCLK on or off
VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS
VDD = 3 V
Normal Mode (Static)
Normal Mode (Operational)
0.5
5.5
3.5
34
2
0.5
5.5
3.5
34
2
mA typ
mA max
mA typ
μA typ
μA max
μA max
Partial Power-Down Mode (Static)
Full Power-Down Mode (Static)
−40°C to +85°C, typically 0.1 μA
+85°C to +125°C
10
10
Power Dissipation5
Normal Mode (Operational)
19.8
10.5
102
7.2
19.8
10.5
102
7.2
mW max
mW typ
μW typ
VDD = 3.6 V, fSAMPLE = 3 MSPS
VDD = 3 V
VDD = 3 V
Partial Power-Down
Full Power-Down
μW max
VDD = 3.6 V, −40°C to +85°C
1 Temperature range from −40°C to +125°C.
2 Typical specifications are tested with VDD = 3 V and at 25°C.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS—AD7276/AD7277/AD7278
VDD = 2.35 V to 3.6 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter2 Limit at TMIN, TMAX
Unit
Description
kHz min4
MHz max
MHz max
3
fSCLK
500
48
16
B grade
Y grade
AD7276
AD7277
AD7278
tCONVERT
14 × tSCLK
12 × tSCLK
10 × tSCLK
4
tQUIET
ns min
Minimum quiet time required between the bus relinquish and the
start of the next conversion
t1
t2
3
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
μs max
Minimum CS pulse width
6
CS to SCLK setup time
5
t3
4
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA three-state
SCLK falling edge to SDATA three-state
CS rising edge to SDATA three-state
Power-up time from full power-down
5
t4
15
0.4 tSCLK
0.4 tSCLK
5
14
5
4.2
1
t5
t6
t7
5
t8
t9
6
TPOWER-UP
1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
2 Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
3 Mark/space ratio for the SCLK input is 40/60 to 60/40.
4 Minimum fSCLK at which specifications are guaranteed.
5 The time required for the output to cross the VIH or VIL voltage.
6 See the Power-Up Times section.
Rev. C | Page 8 of 28
AD7276/AD7277/AD7278
t4
t8
SCLK
SCLK
V
V
IH
IL
1.4V
SDATA
SDATA
Figure 2. Access Time After SCLK Falling Edge
Figure 4. SCLK Falling Edge SDATA Three-State
t7
SCLK
V
IH
SDATA
V
IL
Figure 3. Hold Time After SCLK Falling Edge
Rev. C | Page 9 of 28
AD7276/AD7277/AD7278
This satisfies the requirement of 60 ns for tACQ. Figure 6 also
shows that tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where
t8 = 14 ns max. This allows a value of 43 ns for tQUIET, satisfying
the minimum requirement of 4 ns.
TIMING EXAMPLES
For the AD7276, if
is brought high during the 14th SCLK rising
CS
edge after the two leading zeros and 12 bits of the conversion
have been provided, the part can achieve the fastest throughput
rate, 3 MSPS. If
is brought high during the 16th SCLK rising
Timing Example 2
CS
edge after the two leading zeros and 12 bits of the conversion
and two trailing zeros have been provided, a throughput rate of
2.97 MSPS is achievable. This is illustrated in the following two
timing examples.
The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time of
t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns minimum and
t
t
ACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + t8 +
QUIET, where t8 = 14 ns max. This satisfies the minimum
Timing Example 1
requirement of 4 ns for tQUIET.
In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz and the
throughput is 3 MSPS. This produces a cycle time of t2 +
12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns minimum and
tACQ = 67 ns.
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
5
13
14
t5
15
t8
16
t7
t3
ZERO
tQUIET
THREE-STATE
t4
Z
DB11
DB10
DB9
DB1
DB0
ZERO
ZERO
SDATA
THREE-
STATE
2 LEADING
ZEROS
2 TRAILING
ZEROS
1/THROUGHPUT
Figure 5. AD7276 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
B
t6
SCLK
1
2
3
4
5
13
t5
14
t9
t7
t3
tQUIET
t4
DB9
Z
ZERO
DB11
DB10
DB1
DB0
SDATA
THREE-STATE
THREE-
STATE
2 LEADING
ZEROS
1/THROUGHPUT
Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle
t1
CS
tCONVERT
t2
B
SCLK
1
2
3
4
5
12
13
14
15
t8
16
tQUIET
12.5(1/f
)
tACQUISITION
SCLK
1/THROUGHPUT
Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle
Rev. C | Page 10 of 28
AD7276/AD7277/AD7278
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameters
Ratings
VDD to GND
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
10 mA
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial (B grade)
Storage Temperature Range
Junction Temperature
6-Lead TSOT Package
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
8-Lead MSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature Soldering
Reflow (10 sec to 30 sec)
Lead Temperature Soldering
Reflow (10 sec to 30 sec)
ESD
230°C/W
92°C/W
205.9°C/W
43.74°C/W
255°C
260°C
1.5 kV
1 Transient currents of up to 100 mA cause SCR latch-up.
Rev. C | Page 11 of 28
AD7276/AD7277/AD7278
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
6
5
V
IN
DD
V
1
2
3
6
5
4
CS
AD7276/
AD7277/
DD
AD7276/
AD7277/
SDATA
CS
GND
SCLK
NC
GND
SDATA
SCLK
AD7278
AD7278
TOP VIEW
(Not to Scale)
TOP VIEW
NC
(Not to Scale)
V
IN
NC = NO CONNECT
Figure 8. 6-Lead TSOT Pin Configuration
Figure 9. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
8-Lead MSOP
Mnemonic
VDD
Description
6-Lead TSOT
1
2
1
7
Power Supply Input. The VDD range for the AD7276/AD7277/AD7278 is 2.35 V to 3.6 V.
GND
Analog Ground. Ground reference point for all circuitry on the
AD7276/AD7277/AD7278. All analog input signals should be referred to this GND
voltage.
3
4
8
6
VIN
SCLK
Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the
part. This clock input is also used as the clock source for the conversion process of the
AD7276/AD7277/AD7278.
5
6
2
SDATA
Data Out. Logic output. The conversion result from the AD7276/AD7277/AD7278 is
provided on this output as a serial data stream. The bits are clocked out on the falling
edge of the SCLK input. The data stream from the AD7276 consists of two leading
zeros followed by 12 bits of conversion data and two trailing zeros, provided MSB first.
The data stream from the AD7277 consists of two leading zeros followed by 10 bits of
conversion data and four trailing zeros, provided MSB first. The data stream from the
AD7278 consists of two leading zeros followed by 8 bits of conversion data and six
trailing zeros, provided MSB first.
3
CS
Chip Select. Active low logic input. This input provides the dual function of initiating
conversion on the AD7276/AD7277/AD7278 and framing the serial data transfer.
4, 5
NC
No Connect.
Rev. C | Page 12 of 28
AD7276/AD7277/AD7278
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
73.0
72.5
72.0
71.5
71.0
70.5
70.0
69.5
69.0
16,384 POINT FFT
F
F
= 3MSPS
–20
–40
SAMPLE
= 1MHz
V
= 3.6V
DD
IN
SINAD = 71.2dB
THD = –80.9dB
SFDR = –82.4dB
V
= 3V
DD
V
= 3V
DD
–60
V
= 2.35V
DD
–80
–100
–120
100
1000
1500
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500
FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 13. AD7276 SNR vs. Analog Input Frequency at 3 MSPS
for Various Supply Voltages, SCLK Frequency = 48 MHz
Figure 10. AD7276 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz
–10
30,000
16,384 POINT FFT
30,000
F
F
= 3MSPS
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
CODES
SAMPLE
= 1MHz
IN
25,000
20,000
15,000
10,000
5,000
0
SINAD = 61.6dB
THD = –80.2dB
SFDR = –83.4dB
V
= 3V
DD
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500
FREQUENCY (kHz)
2046
2047
2048
2049
2050
CODE
Figure 11. AD7277 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz
Figure 14. Histogram of Codes for 30,000 Samples
72.5
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
V
= 3.6V
DD
72.0
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
67.5
V
= 2.35V
DD
V
= 2.35V
DD
V
= 3V
DD
V
= 3V
DD
V
= 3.6V
DD
100
1000
1500
100
1000
1500
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 12. AD7276 SINAD vs. Analog Input Frequency at 3 MSPS
for Various Supply Voltages, SCLK Frequency = 48 MHz
Figure 15. THD vs. Analog Input Frequency at 3 MSPS
for Various Supply Voltages, SCLK Frequency = 48 MHz
Rev. C | Page 13 of 28
AD7276/AD7277/AD7278
–50
1.0
0.8
V
= 3V
DD
–55
0.6
R
= 100Ω
–60
–65
–70
–75
–80
–85
–90
IN
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
R
= 10Ω
IN
R
= 0Ω
IN
100
1000
1500
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
INPUT FREQUENCY (kHz)
Figure 16. THD vs. Analog Input Frequency at 3 MSPS for Various Source
Impedances, SCLK Frequency = 48 MHz, Supply Voltage = 3 V
Figure 18. AD7276 DNL Performance
1.0
V
= 3V
DD
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
Figure 17. AD7276 INL Performance
Rev. C | Page 14 of 28
AD7276/AD7277/AD7278
TERMINOLOGY
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. It is
defined as:
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7276/
AD7277/AD7278, the endpoints of the transfer function are
zero scale at 0.5 LSB below the first code transition and full
scale at 0.5 LSB above the last code transition.
V22
+
V32
+
V42
+ +
V52 V62
THD dB = 20 log
( )
V
1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
through sixth harmonics.
Offset Error
Peak Harmonic or Spurious Noise
The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2, excluding dc) to the rms value
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum; however, for
ADCs with harmonics buried in the noise floor, it is determined
by a noise peak.
Gain Error
The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal after adjusting for the offset error,
that is, VREF − 1.5 LSB.
Total Unadjusted Error
A comprehensive specification that includes gain, linearity, and
offset errors.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb, where
m and n = 0, 1, 2, 3, …. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second-order terms include (fa + fb) and (fa − fb), and the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
Track-and-Hold Acquisition Time
The time required after the conversion for the output of the
track-and-hold amplifier to reach its final value within 0.5 LSB.
See the Serial Interface section for more details.
Signal-to-Noise + Distortion Ratio (SINAD)
The measured ratio of signal to noise plus distortion at the
output of the ADC. The signal is the rms amplitude of the
fundamental, and noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), including
harmonics but excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process: the
more levels, the smaller the quantization noise. For an ideal
N-bit converter, the SINAD is defined as
The AD7276/AD7277/AD7278 are tested using the CCIF
standard in which two input frequencies are used (see fa and fb
in the specifications). In this case, the second-order terms are
usually distanced in frequency from the original sine waves, and
the third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The intermodulation distortion is
calculated in a similar manner to the THD specification, that is,
the ratio of the rms sum of the individual distortion products to
the rms amplitude of the sum of the fundamentals expressed in
decibels.
SINAD = 6.02 N + 1.76 dB
According to this equation, the SINAD is 74 dB for a 12-bit
converter and 62 dB for a 10-bit converter. However, various
error sources in the ADC, including integral and differential
nonlinearities and internal ac noise sources, cause the measured
SINAD to be less than its theoretical value.
Aperture Delay
The measured interval between the leading edge of the sampling
clock and the point at which the ADC takes the sample.
Aperture Jitter
The sample-to-sample variation when the sample is taken.
Rev. C | Page 15 of 28
AD7276/AD7277/AD7278
THEORY OF OPERATION
CIRCUIT INFORMATION
CHARGE
REDISTRIBUTION
DAC
The AD7276/AD7277/AD7278 are fast, micropower, 12-/10-/
8-bit, single-supply ADCs, respectively. The parts can be operated
from a 2.35 V to 3.6 V supply. When operated from a supply
voltage within this range, the AD7276/AD7277/AD7278 are
capable of throughput rates of 3 MSPS when provided with a
48 MHz clock.
SAMPLING
CAPACITOR
A
V
IN
CONTROL
LOGIC
SW1
SW2
ACQUISITION
PHASE
B
COMPARATOR
V
/2
DD
AGND
The AD7276/AD7277/AD7278 provide the user with an on-
chip track-and-hold ADC and a serial interface housed in a tiny
6-lead TSOT or an 8-lead MSOP package, which offers the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part and provides
the clock source for the successive approximation ADC. The
analog input range is 0 V to VDD. An external reference is not
required for the ADC, and there is no reference on-chip. The
reference for the AD7276/AD7277/AD7278 is derived from the
power supply, resulting in the widest dynamic input range.
Figure 20. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7276/AD7277/AD7278 is straight
binary. The designed code transitions occur midway between
successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The
LSB size is VDD/4,096 for the AD7276, VDD/1,024 for the AD7277,
and VDD/256 for the AD7278. The ideal transfer characteristic
for the AD7276/AD7277/AD7278 is shown in Figure 21.
The AD7276/AD7277/AD7278 also feature a power-down
option to save power between conversions. The power-down
feature is implemented across the standard serial interface as
described in the Modes of Operation section.
111...111
111...110
111...000
011...111
CONVERTER OPERATION
1LSB = V
1LSB = V
1LSB = V
/4096 (AD7276)
/1024 (AD7277)
/256 (AD7278)
REF
REF
REF
The AD7276/AD7277/AD7278 are successive approximation
ADCs that are based on a charge redistribution DAC. Figure 19
and Figure 20 show simplified schematics of the ADC. Figure 19
shows the ADC during its acquisition phase, where SW2 is closed,
SW1 is in Position A, the comparator is held in a balanced con-
dition, and the sampling capacitor acquires the signal on VIN.
000...010
000...001
000...000
0.5LSB
+V – 1.5LSB
DD
0V
ANALOG INPUT
Figure 21. AD7276/AD7277/AD7278 Transfer Characteristics
TYPICAL CONNECTION DIAGRAM
Figure 22 shows a typical connection diagram for the AD7276/
AD7277/AD7278. VREF is taken internally from VDD; therefore,
VDD should be decoupled. This provides an analog input range
of 0 V to VDD. The conversion result is output in a 16-bit word
with two leading zeros followed by the 12-bit, 10-bit, or 8-bit
result. The 12-bit result from the AD7276 is followed by two
trailing zeros; the 10-bit and 8-bit results from the AD7277 and
AD7278 are followed by four and six trailing zeros, respectively.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
A
V
IN
CONTROL
LOGIC
SW1
SW2
ACQUISITION
PHASE
B
COMPARATOR
V
/2
DD
AGND
Figure 19. ADC Acquisition Phase
Alternatively, because the supply current required by the AD7276/
AD7277/AD7278 is so low, a precision reference can be used as the
supply source for the AD7276/AD7277/AD7278. A REF19x voltage
reference (REF193 for 3 V) can be used to supply the required
voltage to the ADC (see Figure 22). This configuration is especially
useful if the power supply is noisy or the system’s supply voltage is a
value other than 3 V (for example, 5 V or 15 V). The REF19x
outputs a steady voltage to the AD7276/AD7277/AD7278. If the
low dropout REF193 is used, it must supply a current of typically
1 mA to the AD7276/AD7277/AD7278. When the ADC is
converting at a rate of 3 MSPS, the REF193 must supply a maxi-
mum of 5 mA to the AD7276/AD7277/AD7278.
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced
(see Figure 20). The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
Rev. C | Page 16 of 28
AD7276/AD7277/AD7278
The load regulation of the REF193 is typically 10 ppm/mA
Large source impedances significantly affect the ac performance
of these ADCs and can necessitate the use of an input buffer
amplifier. The AD8021 op amp is compatible with these devices;
however, the choice of the op amp is a function of the particular
application.
(REF193, VS = 5 V), which results in an error of 50 ppm (150 μV)
for the 5 mA drawn from it. When VDD = 3 V from the REF193, it
corresponds to an error of 0.204 LSB, 0.051 LSB, and 0.0128 LSB
for the AD7276, AD7277, and AD7278, respectively. For applica-
tions where power consumption is of concern, use the power-down
mode of the ADC and the sleep mode of the REF19x reference to
improve power performance. See the Modes of Operation section.
V
DD
D1
C2
R1
V
IN
3V
5V
C1
4pF
REF193
SUPPLY
D2
1µF
TANT
CONVERSION PHASE—SWITCH OPEN
TRACK PHASE—SWITCH CLOSED
0.1µF
10µF
0.1µF
680nF
V
V
DD
Figure 23. Equivalent Analog Input Circuit
0V TO V
INPUT
DD
IN
SCLK
SDATA
CS
AD7276/
AD7277/
AD7278
When no amplifier is used to drive the analog input, the source
impedance should be limited to a low value. The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD increases as the source impedance increases and per-
formance degrades. Figure 16 shows a graph of the THD vs. the
analog input frequency for different source impedances when
using a supply voltage of 3 V and sampling at a rate of 3 MSPS.
DSP/
µC/µP
GND
SERIAL
INTERFACE
Figure 22. REF193 as Power Supply to the AD7276/AD7277/AD7278
Table 8 provides typical performance data with various
references used as a VDD source with the same setup conditions.
Digital Inputs
The digital inputs applied to the AD7276/AD7277/AD7278 are
not limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied to the AD7276/AD7277/
AD7278 can be 6 V and are not restricted by the VDD + 0.3 V
limit of the analog inputs. For example, if the AD7276/AD7277/
AD7278 are operated with a VDD of 3 V, then 5 V logic levels can
be used on the digital inputs. However, it is important to note
that the data output on SDATA still has 3 V logic levels when
Table 8. AD7276 Performance (Various Voltage References IC)
Reference Tied to VDD
SNR Performance, 1 MHz Input
AD780 @ 3 V
AD780 @ 2.5 V
REF193
71.3 dB
70.1 dB
70.9 dB
Analog Input
Figure 23 shows an equivalent circuit of the analog input structure
of the AD7276/AD7277/AD7278. The two diodes, D1 and D2,
provide ESD protection for the analog inputs. Care must be taken
to ensure that the analog input signal never exceeds the supply
rails by more than 300 mV. Signals exceeding this value cause
these diodes to become forward biased and to start conducting
current into the substrate. These diodes can conduct a maximum
current of 10 mA without causing irreversible damage to the
part. Capacitor C1 in Figure 23 is typically about 4 pF and can
primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of a switch.
This resistor is typically about 75 Ω. Capacitor C2 is the ADC
sampling capacitor and has a capacitance of 4 pF typically when
in hold mode and 32 pF typically when in track mode. For ac
applications, removing high frequency components from the
analog input signal is recommended by using a band-pass filter
on the relevant analog input pin. In applications where the
harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source.
VDD = 3 V. Another advantage of SCLK and not being restricted
CS
by the VDD + 0.3 V limit is that power supply sequencing issues are
avoided. For example, unlike with the analog inputs, with the
digital inputs, if
or SCLK is applied before V , there is no
CS
DD
risk of latch-up.
Rev. C | Page 17 of 28
AD7276/AD7277/AD7278
can idle high until the next conversion or low until returns
CS
CS
MODES OF OPERATION
high before the next conversion (effectively idling
low).
CS
The mode of operation of the AD7276/AD7277/AD7278 is
selected by controlling the logic state of the
conversion. There are three possible modes of operation: normal
mode, partial power-down mode, and full power-down mode.
signal during a
CS
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
tQUIET, has elapsed by bringing
low again.
CS
The point at which
been initiated determines which power-down mode, if any, the
device enters. Similarly, if the device is already in power-down
is pulled high after the conversion has
CS
Partial Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required. An example of this is when either
the ADC is powered down between each conversion or a series
of conversions is performed at a high throughput rate and then
the ADC is powered down for a relatively long duration between
these bursts of several conversions. When the AD7276/AD7277/
AD7278 are in partial power-down mode, all analog circuitry is
powered down except the bias-generation circuit.
mode,
can control whether the device returns to normal
CS
operation or remains in power-down mode. These modes of
operation are designed to provide flexible power management
options, which can be chosen to optimize the power dissipation/
throughput rate ratio for different application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance
because the device remains fully powered at all times, eliminating
worry about power-up times. Figure 24 shows the general diagram
of AD7276/AD7277/AD7278 operation in this mode.
To enter partial power-down mode, interrupt the conversion
process by bringing
high between the second and 10th falling
CS
edges of SCLK, as shown in Figure 25.
Once is brought high in this window of SCLKs, the part
CS
enters partial power-down mode, the conversion that was
initiated by the falling edge of is terminated, and SDATA
The conversion is initiated on the falling edge of as described
CS
in the Serial Interface section. To ensure that the part remains
CS
is brought high before the
fully powered up at all times,
must remain low until at least
CS
goes back into three-state. If
CS
10 SCLK falling edges elapse after the falling edge of . If
is
CS CS
second SCLK falling edge, the part remains in normal mode and
does not power down. This prevents accidental power-down due
brought high after the 10th SCLK falling edge but before the 16th
SCLK falling edge, the part remains powered up, but the con-
version is terminated and SDATA goes back into three-state.
to glitches on the
line.
CS
For the AD7276, a minimum of 14 serial clock cycles are required
to complete the conversion and access the complete conversion
result. For the AD7277 and AD7278, a minimum of 12 and
10 serial clock cycles are required to complete the conversion
and to access the complete conversion result, respectively.
AD7276/
AD7677/AD7278
CS
1
10
12
14
16
SCLK
SDATA
VALID DATA
Figure 24. Normal Mode Operation
CS
1
2
10
16
SCLK
THREE-STATE
SDATA
Figure 25. Entering Partial Power-Down Mode
Rev. C | Page 18 of 28
AD7276/AD7277/AD7278
To exit this mode of operation and power up the AD7276/
AD7277/AD7278, users should perform a dummy conversion.
Power-Up Times
The AD7276/AD7277/AD7278 have two power-down modes,
partial power-down and full power-down, which are described
in detail in the Modes of Operation section. This section deals
with the power-up time required when coming out of either of
these modes.
On the falling edge of , the device begins to power up and
CS
continues to power up as long as
is held low until after the
CS
falling edge of the 10th SCLK. The device is fully powered up
once 16 SCLKs elapse; valid data results from the next conversion,
th
CS
as shown in Figure 26. If
is brought high before the 10 falling
To power up from partial power-down mode, one cycle is
required. Therefore, with an SCLK frequency of up to 48 MHz,
one dummy cycle is sufficient to allow the device to power up
from partial power-down mode. Once the dummy cycle is
complete, the ADC is fully powered up and the input signal is
acquired properly. The quiet time, tQUIET, must still be allowed
from the point where the bus goes back into three-state after the
edge of SCLK, the AD7276/AD7277/AD7278 go into full power-
down mode. Therefore, although the device can begin to power
CS
up on the falling edge of , it powers down on the rising edge
th
CS
of
as long as this occurs before the 10 SCLK falling edge.
If the AD7276/AD7277/AD7278 are already in partial power-
down mode and
is brought high before the 10th falling edge
CS
dummy conversion to the next falling edge of
.
CS
To power up from full power-down, approximately 1 ꢀs should
be allowed from the falling edge of , shown in Figure 28 as
of SCLK, the device enters full power-down mode. For more
information on the power-up times associated with partial
power-down mode in various configurations, see the Power-Up
Times section.
CS
tPOWER UP
.
Full Power-Down Mode
Note that during power-up from partial power-down mode, the
track-and-hold, which is in hold mode while the part is
powered down, returns to track mode after the first SCLK edge,
following the falling edge of CS. This is shown as Point A in
Figure 26.
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required because power-up from a full power-down takes
substantially longer than that from a partial power-down. This
mode is suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by a
long period of inactivity and thus, power down.
When power supplies are first applied to the AD7276/AD7277/
AD7278, the ADC can power up in either of the power-down
modes or in normal mode. Because of this, it is best to allow a
dummy cycle to elapse to ensure that the part is fully powered
up before attempting a valid conversion. Likewise, if the part is
to be kept in partial power-down mode immediately after the
supplies are applied, then two dummy cycles must be initiated.
When the AD7276/AD7277/AD7278 are in full power-down
mode, all analog circuitry is powered down. To enter full power-
down mode, put the device into partial power-down mode by
bringing
high between the second and 10th falling edges of
CS
SCLK. In the next conversion cycle, interrupt the conversion
process in the same way as shown in Figure 27 by bringing
The first dummy cycle must hold
low until after the 10th
CS
CS
is brought high
SCLK falling edge; in the second cycle,
must be brought high
CS
high before the 10th SCLK falling edge. Once
between the second and 10th SCLK falling edges (see Figure 25).
CS
in this window of SCLKs, the part powers down completely.
Note that it is not necessary to complete the 16 SCLKs once
Alternatively, if the part is to be placed into full power-down
mode when the supplies are applied, three dummy cycles must
is
CS
brought high to enter either of the power-down modes. Glitch
be initiated. The first dummy cycle must hold
low until after
CS
the 10th SCLK falling edge; the second and third dummy cycles
place the part into full power-down mode (see Figure 27). See
the Modes of Operation section.
protection is not available when entering full power-down mode.
To exit full power-down mode and to power up the AD7276/
AD7277/AD7278, users should perform a dummy conversion,
similar to when powering up from partial power-down mode.
On the falling edge of , the device begins to power up and
CS
continues to power up as long as
is held low until after the
CS
falling edge of the 10th SCLK. The required power-up time must
elapse before a conversion can be initiated, as shown in Figure 28.
See the Power-Up Times section for the power-up times
associated with the AD7276/AD7277/AD7278.
Rev. C | Page 19 of 28
AD7276/AD7277/AD7278
THE PART IS FULLY
POWERED UP, SEE THE POWER-
UP TIMES SECTION
THE PART BEGINS
TO POWER UP
CS
1
10
16
1
16
SCLK
A
SDATA
INVALID DATA
VALID DATA
Figure 26. Exiting Partial Power-Down Mode
THE PART ENTERS
PARTIAL POWER-DOWN
THE PART BEGINS
TO POWER UP
THE PART ENTERS
FULL POWER-DOWN
CS
1
2
10
16
1
10
16
SCLK
THREE-STATE
THREE-STATE
INVALID DATA
VALID DATA
SDATA
Figure 27. Entering Full Power-Down Mode
THE PART BEGINS
TO POWER UP
THE PART IS
FULLY POWERED UP
tPOWER UP
CS
1
10
16
1
16
SCLK
SDATA
INVALID DATA
VALID DATA
Figure 28. Exiting Full Power-Down Mode
Rev. C | Page 20 of 28
AD7276/AD7277/AD7278
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
POWER VS. THROUGHPUT RATE
50MHz SCLK
Figure 29 shows the power consumption of the device in
normal mode, in which the part is never powered down. By
using the power-down mode of the AD7276/AD7277/AD7278
when not performing a conversion, the average power consump-
tion of the ADC decreases as the throughput rate decreases.
Figure 30 shows that as the throughput rate is reduced, the
device remains in its power-down state longer, and the average
power consumption over time drops accordingly. For example,
if the AD7276/AD7277/AD7278 are operated in continuous
sampling mode with a throughput rate of 200 kSPS and an SCLK
of 48 MHz (VDD = 3 V) and the devices are placed into power-
down mode between conversions, then the power consumption
is calculated as follows. The power dissipation during normal
operation is 12.6 mW (VDD = 3 V). If the power-up time is one
dummy cycle, that is, 333 ns, and the remaining conversion
time is 290 ns, then the AD7276/AD7277/AD7278 can be said
to dissipate 12.6 mW for 623 ns during each conversion cycle. If
the throughput rate is 200 kSPS, then the cycle time is 5 μs and
the average power dissipated during each cycle is 623/5,000 ×
12.6 mW = 1.56 mW. Figure 29 shows the power vs. throughput
rate when using the partial power-down mode between conver-
sions at 3 V. The power-down mode is intended for use with
throughput rates of less than 600 kSPS, because at higher
sampling rates, there is no power saving achieved by using the
power-down mode.
VARIABLE
SCLK
0
200 400 600 800 1000 1200 1400 1600 1800 2000
THROUGHPUT (kSPS)
Figure 29. Power vs. Throughput Normal Mode
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 3V
DD
0
200
400
600
800
1000
THROUGHPUT (kSPS)
Figure 30. Power vs. Throughput Partial Power-Down Mode
Rev. C | Page 21 of 28
AD7276/AD7277/AD7278
SERIAL INTERFACE
Figure 31 through Figure 34 show the detailed timing diagrams
for serial interfacing to the AD7276, AD7277, and AD7278. The
serial clock provides the conversion clock and controls the transfer
of information from the AD7276/AD7277/AD7278 during
conversion.
If 16 SCLKs are considered in the cycle, then the AD7278 clocks
out six trailing zeros for the last six bits and SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 34.
If the user considers a 14 SCLK cycle serial interface for the
AD7276/AD7277/AD7278, then
must be brought high after
CS
the 14th SCLK falling edge. Then the last two trailing zeros are
ignored, and SDATA goes back into three-state. In this case, the
3 MSPS throughput can be achieved by using a 48 MHz clock
frequency.
The
signal initiates the data transfer and conversion process.
CS
The falling edge of
and takes the bus out of three-state. The analog input is sampled
and the conversion is initiated at this point.
puts the track-and-hold into hold mode
CS
going low clocks out the first leading zero to be read by the
CS
For the AD7276, the conversion requires completing 14 SCLK
cycles. Once 13 SCLK falling edges have elapsed, the track-and-
hold goes back into track mode on the next SCLK rising edge,
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Therefore, the first falling clock edge on the serial
clock provides the first leading zero and clocks out the second
leading zero. The final bit in the data transfer is valid on the 16th
falling edge, because it is clocked out on the previous (15th)
falling edge.
as shown in Figure 31 at Point B. If the rising edge of
occurs
CS
before 14 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the last two bits are zeros and SDATA
returns to three-state on the 16th SCLK falling edge, as shown in
Figure 32.
In applications with a slower SCLK, it is possible to read data on
each SCLK rising edge. In such cases, the first falling edge of SCLK
clocks out the second leading zero and can be read on the first
rising edge. However, the first leading zero clocked out when
goes low is missed if read within the first falling edge. The
15th falling edge of SCLK clocks out the last bit and can be read
on the 15th rising SCLK edge.
For the AD7277, the conversion requires completing 12 SCLK
cycles. Once 11 SCLK falling edges elapse, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
CS
shown in Figure 33 at Point B. If the rising edge of
occurs
CS
before 12 SCLKs elapse, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are considered
in the cycle, the AD7277 clocks out four trailing zeros for the
last four bits and SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 33.
If
goes low just after one SCLK falling edge elapses, then
CS
CS
clocks out the first leading zero and can be read on the SCLK
rising edge. The next SCLK falling edge clocks out the second
leading zero and can be read on the following rising edge.
For the AD7278, the conversion requires completing 10 SCLK
cycles. Once 9 SCLK falling edges elapse, the track-and-hold
goes back into track mode on the next rising edge. If the rising
edge of
occurs before 10 SCLKs elapse, the part enters power-
CS
down mode.
t1
CS
tCONVERT
t6
t2
B
SCLK
1
2
3
4
5
13
t5
14
t9
t7
t3
tQUIET
t4
DB9
Z
ZERO
DB11
DB10
DB1
DB0
SDATA
THREE-STATE
THREE-
STATE
2 LEADING
ZEROS
1/THROUGHPUT
Figure 31. AD7276 Serial Interface Timing Diagram 14 SCLK Cycle
Rev. C | Page 22 of 28
AD7276/AD7277/AD7278
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
5
13
14
t5
15
16
SCLK
t8
t7
t3
ZERO
t4
tQUIET
SDATA
Z
DB11
DB10
DB9
DB1
DB0
ZERO
ZERO
THREE-
STATE
THREE-STATE
2 LEADING
ZEROS
2 TRAILING
ZEROS
1/THROUGHPUT
Figure 32. AD7276 Serial Interface Timing Diagram 16 SCLK Cycle
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
10
11
12
13
14
15
16
SCLK
t5
t8
t7
t3
t4
DB9
tQUIET
SDATA
Z
ZERO
DB8
DB1
DB0
ZERO
ZERO
ZERO
ZERO
THREE-
STATE
THREE-STATE
2 LEADING
ZEROS
4 TRAILING ZEROS
1/THROUGHPUT
Figure 33. AD7277 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
8
9
10
11
14
15
16
SCLK
t5
t8
t7
t4
DB7
t3
tQUIET
SDATA
Z
ZERO
DB6
DB1
DB0
ZERO
ZERO
6 TRAILING ZEROS
ZERO
THREE-
STATE
THREE-STATE
2 LEADING
ZEROS
1/THROUGHPUT
Figure 34. AD7278 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
5
9
10
SCLK
t8
tQUIET
tACQ
8.5 (1/f
)
SCLK
SDATA
Z
ZERO
DB7
DB6
DB5
DB1
DB0
THREE-
STATE
THREE-STATE
2 LEADING ZEROS
1/THROUGHPUT
Figure 35. AD7278 in a 10 SCLK Cycle Serial Interface
Rev. C | Page 23 of 28
AD7276/AD7277/AD7278
AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE
Table 9. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
For the AD7278, if
is brought high during the 10th rising
CS
Setting
Description
edge after the two leading zeros and eight bits of the conversion
are provided, then the part can achieve a 4 MSPS throughput
rate. For the AD7278, the track-and-hold goes back into track
mode on the ninth rising edge. In this case, a fSCLK = 48 MHz and
throughput of 4 MSPS result in a cycle time of t2 + 8.5(1/fSCLK) +
tACQ = 250 ns, where t2 = 6 ns minimum and tACQ = 67 ns. This
satisfies the requirement of 60 ns for tACQ. Figure 35 shows that
tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where t8 = 14 ns max.
This allows a value of 43 ns for tQUIET, satisfying the minimum
requirement of 4 ns.
RCKFE = 1
LRFS = 1
RFSR = 1
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
IRFS = 1
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
Receive MSB first
Zero fill
Internal receive clock
Receive enabled
16-bit data-word (or can be set to 1101 for
14-bit data-word)
MICROPROCESSOR INTERFACING
TFSR = RFSR = 1
AD7276/AD7277/AD7278-to-ADSP-BF53x
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
The ADSP-BF53x family of DSPs interfaces directly to the
AD7276/AD7277/AD7278 without requiring glue logic. The
SPORT0 Receive Configuration 1 Register should be set up as
outlined in Table 9.
AD7276/
AD7277/
AD7278*
ADSP-BF53x*
SPORT0
RCLK0
SCLK
DOUT
CS
DR0PRI
RFS0
DT0
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. Interfacing with ADSP-BF53x
Rev. C | Page 24 of 28
AD7276/AD7277/AD7278
APPLICATION HINTS
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF ceramic capacitors in parallel with
0.1 μF capacitors to GND. To achieve the best results from these
decoupling components, they must be placed as close as possible
to the device, ideally right up against the device. The 0.1 μF
capacitors should have low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of common
ceramic or surface-mount types of capacitors. Capacitors with
low ESR and low ESI provide a low impedance path to ground
at high frequencies, which allow them to handle transient
currents due to internal logic switching.
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7276/AD7277/
AD7278 should be designed so that the analog and digital
sections are separated and confined to certain areas of the
board. This design facilitates using ground planes that can easily
be separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All AGND pins of the AD7276/
AD7277/AD7278 should be sunk into the AGND plane. Digital
and analog ground planes should be joined in one place only. If
the AD7276/AD7277/AD7278 are in a system where multiple
devices require an AGND-to-DGND connection, the connection
should still be made at only one point, a star ground point
established as close as possible to the ground pin on the
AD7276/AD7277/AD7278.
EVALUATING PERFORMANCE
The recommended layout for the AD7276/AD7277/AD7278 is
outlined in the evaluation board documentation. The evaluation
board package includes a fully assembled and tested evaluation
board, documentation, and software for controlling the board
from the PC via the evaluation board controller. To demonstrate/
evaluate the ac and dc performance of the AD7276/AD7277,
the evaluation board controller can be used in conjunction with
the AD7276/AD7277 evaluation board, as well as with many
other Analog Devices evaluation boards ending in the CB
designator,
Avoid running digital lines under the device because this
couples noise onto the die. However, the analog ground plane
should be allowed to run under the AD7276/AD7277/AD7278
to avoid noise coupling. The power supply lines to the AD7276/
AD7277/AD7278 should use as large a trace as possible to provide
low impedance paths and reduce the effects of glitches on the
power supply line.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7276/
AD7277. The software and documentation are on a CD shipped
with the evaluation board.
To avoid radiating noise to other sections of the board,
components with fast-switching signals, such as clocks, should
be shielded with digital ground, and they should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. To reduce the effects of feedthrough within the board,
traces on opposite sides of the board should run at right angles
to each other. A microstrip technique is by far the best method,
but it is not always possible to use this approach with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, and signals are placed on the
solder side.
Rev. C | Page 25 of 28
AD7276/AD7277/AD7278
OUTLINE DIMENSIONS
2.90 BSC
6
1
5
2
4
3
2.80 BSC
1.60 BSC
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
*
0.90
0.87
0.84
0.20
0.08
*
1.00 MAX
8°
4°
0°
0.10 MAX
SEATING
PLANE
0.60
0.45
0.30
0.50
0.30
*
COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 37. 6-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-6)
Dimensions shown in millimeters
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 38. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. C | Page 26 of 28
AD7276/AD7277/AD7278
ORDERING GUIDE
Temperature
Notes Range
Linearity
Package
Option
Model1
Error (LSB)2 Package Description
Branding
C1W
C30
C30
C30
AD7276BRM
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
1 max
1 max
1 max
1 max
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
RM-8
RM-8
RM-8
AD7276BRMZ
AD7276BRMZ-REEL
AD7276BUJZ-REEL7
AD7276BUJZ-500RL7
AD7276YUJZ-500RL7
AD7276YUJZ-REEL7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
1 max
1 max
1 max
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
C30
3
3
C4W
C4W
AD7276ARMZ
AD7276ARMZ-REEL
AD7276AUJZ- 500RL7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
1.5 max
1.5 max
1.5 max
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
RM-8
RM-8
C6S
C6S
C6S
AD7276AUJZ-REEL7
−40°C to +125°C
1.5 max
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
C6S
AD7277BRMZ
AD7277BRMZ-REEL
AD7277BUJZ-500RL7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
0.5 max
0.5 max
0.5 max
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
RM-8
RM-8
C31
C31
C31
AD7277BUJZ-REEL7
−40°C to +125°C
0.5 max
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
C31
AD7277ARMZ
AD7277ARMZ-RL
AD7277AUJZ-500RL7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
0.5 max
0.5 max
0.5 max
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
RM-8
RM-8
C6T
C6T
C6T
AD7277AUJZ-RL7
−40°C to +125°C
0.5 max
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
C6T
AD7278BRMZ
AD7278BRMZ-REEL
AD7278BUJZ-500RL7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
0.3 max
0.3 max
0.3 max
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
RM-8
RM-8
C32
C32
C32
AD7278BUJZ-REEL7
−40°C to +125°C
0.3 max
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
C32
AD7278ARMZ
AD7278ARMZ-RL
AD7278AUJZ-500RL7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
0.3 max
0.3 max
0.3 max
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
RM-8
RM-8
C6U
C6U
C6U
AD7278AUJZ-RL7
−40°C to +125°C
0.3 max
6-Lead Thin Small Outline Transistor Package UJ-6
(TSOT)
C6U
4
5
EVAL-AD7276CBZ
EVAL-CONTROL BRD2
Evaluation Board
Control Board
1 Z = RoHS Compliant Part.
2 Linearity error refers to integral nonlinearity.
3 Y Grade part, fSAMPLE = 1 MSPS.
4 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.
5 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards that end in a CB designator. To order a complete
evaluation kit, the particular ADC evaluation board (such as EVAL-AD7276CBZ), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant
evaluation board user guide for more information.
Rev. C | Page 27 of 28
AD7276/AD7277/AD7278
NOTES
©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04903-0-5/11(C)
Rev. C | Page 28 of 28
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