AD7298-1_17 [ADI]
8-Channel, 1 MSPS, 10-Bit SAR ADC;
| 型号： | AD7298-1_17 |
| 厂家： | 
ADI |
| 描述： | 8-Channel, 1 MSPS, 10-Bit SAR ADC |
| 文件： | 总25页 (文件大小：764K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel, 1 MSPS, 10-Bit SAR ADC
AD7298-1
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
DD
GND
10-bit SAR ADC
8 single-ended inputs
V
REF
Channel sequencer functionality
Fast throughput of 1 MSPS
Analog input range: 0 V to 2.5 V
Temperature range: −40°C to +125°C
Specified for VDD of 2.8 V to 3.6 V
Logic voltage VDRIVE = 1.65 V to 3.6 V
Power-down current: <10 µA
Internal 2.5 V reference
REF
BUF
10-BIT
V
IN0
IN7
SUCCESSIVE
APPROXIMATION
ADC
T/H
INPUT
MUX
AD7298-1
V
SEQUENCER
Internal power-on reset
High speed serial interface SPI
20-lead LFCSP
SCLK
DOUT
DIN
CONTROL
LOGIC
CS
V
DRIVE
PD/RST
Figure 1.
GENERAL DESCRIPTION
The AD7298-1 is a 10-bit, high speed, low power, 8-channel,
successive approximation ADC. The part operates from a single
3.3 V power supply and features throughput rates up to 1 MSPS.
The device contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 30 MHz.
PRODUCT HIGHLIGHTS
1. Ideally Suited to Monitoring System Variables in a Variety
of Systems. This includes telecommunications, and process
and industrial control.
2. High Throughput Rate of 1 MSPS with Low Power
Consumption.
3. Eight Single-Ended Inputs with a Channel Sequencer. A
consecutive sequence of channels can be selected on which
the ADC cycles and converts.
The AD7298-1 offers a programmable sequencer, which enables
the selection of a preprogrammable sequence of channels for
conversion. The device has an on-chip, 2.5 V reference that can
be disabled to allow the use of an external reference.
The device offers a 4-wire serial interface compatible with SPI and
DSP interface standards.
The AD7298-1 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. The part also
offers flexible power/throughput rate management options. The
part is offered in a 20-lead LFCSP package.
Rev. A
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.
AD7298-1* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• AD7298-1 Material Declaration
• PCN-PDN Information
DOCUMENTATION
• Quality And Reliability
Application Notes
• Symbols and Footprints
• AN-742: Frequency Domain Response of Switched-
Capacitor ADCs
DISCUSSIONS
View all AD7298-1 EngineerZone Discussions.
• AN-931: Understanding PulSAR ADC Support Circuitry
Data Sheet
• AD7298-1: 8-Channel, 1 MSPS, 10-Bit SAR ADC Data Sheet
Technical Books
SAMPLE AND BUY
Visit the product page to see pricing options.
• The Data Conversion Handbook, 2005
TECHNICAL SUPPORT
REFERENCE MATERIALS
Technical Articles
Submit a technical question or find your regional support
number.
• MS-1779: Nine Often Overlooked ADC Specifications
• MS-2210: Designing Power Supplies for High Speed ADC
Tutorials
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
• Integrated SAR ADC Family in 4mm x 4mm Package
• MT-002: What the Nyquist Criterion Means to Your
Sampled Data System Design
• MT-031: Grounding Data Converters and Solving the
Mystery of "AGND" and "DGND"
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AD7298-1
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Input ............................................................................... 13
VDRIVE ............................................................................................ 14
The Internal or External Reference.......................................... 14
Control Register.............................................................................. 15
Modes of Operation ....................................................................... 16
Traditional Multichannel Mode of Operation........................ 16
Repeat Operation ....................................................................... 17
Power-Down Modes .................................................................. 18
Powering Up the AD7298-1...................................................... 19
Reset............................................................................................. 19
Serial Interface ................................................................................ 20
Layout and Configuration............................................................. 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Description .............................. 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Circuit Information........................................................................ 13
Converter Operation.................................................................. 13
REVISION HISTORY
1/11—Rev. 0 to Rev. A
Removed Input Impedance Parameter.......................................... 3
Added Input Capacitance Parameter of 8 pF................................ 3
Changes to Figure 10...................................................................... 10
Changed C1 Value to 8 pF in Analog Input Section.................. 13
Changes to Figure 22...................................................................... 14
10/10—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD7298-1
SPECIFICATIONS
VDD = 2.8 V to 3.6 V, VDRIVE = 1.65 V to 3.6 V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, VREF = 2.5 V internal, TA = −40°C to +125°C, unless
otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)1
fIN = 50 kHz sine wave
61
61.5
61.5
−82
−83
dB
dB
dB
dB
Signal-to-Noise-(and-Distortion) Ratio (SINAD)2 61
Total Harmonic Distortion (THD)2
Spurious-Free Dynamic Range (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
−75
−76
fA = 40.1 kHz, fB = 41.5 kHz
fIN = 50 kHz, fNOISE = 60 kHz
−86
−86
−90
dB
dB
dB
Third-Order Terms
Channel-to-Channel Isolation
SAMPLE AND HOLD
Aperture Delay3
12
ns
ps
MHz
MHz
Aperture Jitter3
40
30
10
Full Power Bandwidth
At 3 dB
At 0.1 dB
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)2
Offset Error2
0.25
0.3
0.5
0.5
0.5
1.125
LSB
LSB
LSB
Guaranteed no missed codes to 10 bits
Offset Error Matching2
Offset Temperature Drift
Gain Error2
Gain Error Matching2
Gain Temperature Drift
ANALOG INPUT
0.625
1.125
LSB
ppm/°C
LSB
LSB
ppm/°C
4
0.25
0.16
0.5
1
0.625
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0
VREF
1
V
0.01
32
8
μA
pF
pF
When in track mode
When in hold mode
REFERENCE INPUT/OUTPUT
Reference Output Voltage4
Long-Term Stability
Output Voltage Hysteresis
Reference Input Voltage Range
DC Leakage Current
VREF Output Impedance
VREF Temperature Coefficient
VREF Noise
2.4925
1
2.5
150
50
2.5075
V
0.3ꢀ maꢁimum at 25°C
For 1000 hours
ppm
ppm
V
μA
Ω
2.5
1
0.01
Eꢁternal reference applied to the VREF pin
Bandwidth = 10 MHz
1
12
60
35
ppm/°C
μV rms
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
V
V
μA
pF
0.3 × VDRIVE
1
0.01
VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
3
Rev. A | Page 3 of 24
AD7298-1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, VOH
VDRIVE − 0.3
VDRIVE − 0.2
V
V
VDRIVE < 1.8
VDRIVE ≥ 1.8
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance3
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2, 3
0.4
1
V
μA
pF
0.01
8
1
t2 + (16 × tSCLK
100
1
)
μs
ns
MSPS
For VIN0 to VIN7 with one cycle latency
Full-scale step input
fSCLK = 20 MHz; for analog voltage
conversions, one cycle latency
Throughput Rate
POWER REQUIREMENTS
VDD
Digital inputs = 0 V or VDRIVE
VDD = 3.6 V, VDRIVE = 3.6 V
2.8
1.65
3
3
3.6
3.6
V
V
VDRIVE
5
ITOTAL
Normal Mode (Operational)
Normal Mode (Static)
Partial Power-Down Mode
Full Power-Down Mode
5.8
4.1
2.7
1
6.4
4.6
3.3
1.6
10
mA
mA
mA
μA
TA = −40°C to +25°C
TA = −40°C to +125°C
μA
Power Dissipation6
Normal Mode (Operational)
17.4
19.2
23
16.6
11.9
5.8
mW
mW
mW
mW
μW
VDD = 3 V, VDRIVE = 3 V
Normal Mode (Static)
Partial Power-Down Mode
Full Power-Down Mode
14.8
9.8
3.6
TA = −40°C to +25°C
TA = −40°C to +125°C
36
μW
1 All specifications eꢁpressed in decibels are referred to full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
2 See the Terminology section.
3 Sample tested during initial release to ensure compliance.
4 Refers to the VREF pin specified for 25°C.
5 ITOTAL is the total current flowing in VDD and VDRIVE
.
6 Power dissipation is specified with VDD = VDRIVE = 3.6 V, unless otherwise noted.
Rev. A | Page 4 of 24
AD7298-1
TIMING SPECIFICATIONS
VDD = 2.8 V to 3.6 V, VDRIVE = 1.65 V to 3.6 V, VREF = 2.5 V internal, TA = −40°C to +125°C, unless otherwise noted. Sample tested during
initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level
of 1.6 V.
Table 2.
Parameter
tCONVERT
Limit at TMIN, TMAX
Unit
µs max
ns typ
kHz min
MHz max
ns min
Test Conditions/Comments
Conversion time
Each ADC channel VIN0 to VIN7, fSCLK = 20 MHz
Frequency of external serial clock
Frequency of external serial clock
t2 + (16 × tSCLK
)
820
50
20
6
1
fSCLK
tQUIET
Minimum quiet time required between the end of the serial read and the start of
the next voltage conversion in repeat and nonrepeat mode.
t2
10
15
ns min
ns max
CS to SCLK setup time
1
t3
Delay from CS (falling edge) until DOUT three-state disabled
Data access time after SCLK falling edge
VDRIVE = 1.65 V to 3 V
VDRIVE = 3 V to 3.6 V
SCLK low pulse width
1
t4
35
28
0.4 × tSCLK
0.4 × tSCLK
14
16/34
5
4
ns max
ns max
ns min
ns min
ns min
ns min/ns max
ns min
ns min
ns max
ms max
t5
t6
t7
t8
t9
SCLK high pulse width
SCLK to DOUT valid hold time
1
1
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Delay from CS rising edge to DOUT high impedance
Internal reference power-up time from full power-down
t10
t11
1
30
6
tPOWER-UP
1 Measured with a load capacitance on DOUT of 15 pF.
Rev. A | Page 5 of 24
AD7298-1
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Table 4. Thermal Resistance
Package Type
Rating
θJA
θJC
Unit
VDD to GND, GND1
VDRIVE to GND, GND1
Analog Input Voltage to GND1
Digital Input Voltage to GND
Digital Output Voltage to GND
VREF to GND1
−0.3 V to +5 V
−0.3 V to + 5 V
−0.3 V to +3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to +3 V
−0.3 V to +0.3 V
10 mA
20-Lead LFCSP
52
6.5
°C/W
ESD CAUTION
AGND to GND
Input Current to Any Pin Except Supplies
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Pb-free Temperature, Soldering
Reflow
−40°C to +125°C
−65°C to +150°C
150°C
260(0)°C
3.5 kV
ESD
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 6 of 24
AD7298-1
PIN CONFIGURATION AND FUNCTION DESCRIPTION
15 SCLK
14 DOUT
V
V
V
V
V
1
2
3
4
5
IN3
IN4
IN5
IN6
IN7
AD7298-1
13 DIN
TOP VIEW
(Not to Scale)
NC
12
11 CS
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED METAL PADDLE ON THE BOTTOM
OF THE LFCSP PACKAGE SHOULD BE SOLDERED
TO PCB GROUND FOR PROPER FUNCTIONALITY
AND HEAT DISSIPATION.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1 to 5,
18 to 20
VIN3, VIN4
VIN5, VIN6
Analog Inputs. The AD7298-1 has eight single-ended analog inputs that are multiplexed into the on-chip track-
and-hold. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels should be
connected to GND1 to avoid noise pickup.
,
,
V
V
IN7, VIN0
IN1, VIN2
6
7
GND1
Ground. Ground reference point for the internal reference circuitry on the AD7298-1. The external reference
signals and all analog input signals should be referred to the GND1 voltage. The GND1 pin should be connected
to the ground plane of a system. All ground pins should ideally be at the same potential and must not be more
than 0.3 V apart, even on a transient basis. The VREF pin should be decoupled to this ground pin via a 10 µF
decoupling capacitor.
Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin.
Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the
rest of a system. Decoupling capacitors should be connected to this pin to decouple the reference buffer. For
best performance, it is recommended to use a 10 µF decoupling capacitor on this pin to GND1. The internal
reference can be disabled and an external reference supplied to this pin, if required. The input voltage range for
the external reference is 2.0 V to 2.5 V.
VREF
8
9
DCAP
Decoupling Capacitor Pins. Decoupling capacitors (1 µF recommended) are connected to this pin to decouple
the internal LDO.
Ground. Ground reference point for all analog and digital circuitry on the AD7298-1. The GND pin should be
connected to the ground plane of the system. All ground pins should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis. Both the DCAP and VDD pins should be decoupled to this
GND pin.
GND
10
11
VDD
CS
Supply Voltage, 2.8 V to 3.6 V. This supply should be decoupled to GND with 10 µF and 100 nF decoupling capacitors.
Chip Select, Active Low Logic Input. This pin is edge triggered on the falling edge of this input, the track-and-
hold goes into hold mode, and a conversion is initiated. This input also frames the serial data transfer. When CS is
low, the output bus is enabled and the conversion result becomes available on the DOUT output.
12
13
NC
DIN
No Connect.
Data In, Logic Input. Data to be written to the AD7298-1 control register is provided on this input and is clocked
into the register on the falling edge of SCLK.
14
DOUT
Serial Data Output. The conversion result from the AD7298-1 is provided on this output as a serial data stream.
The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7298-1 consists of
four address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of
conversion data (MSB first).
15
SCLK
Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7298-1.
Rev. A | Page 7 of 24
AD7298-1
Pin No.
Mnemonic Description
16
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the interface
operates. This pin should be decoupled to ground. The voltage range on this pin is 1.65 V to 3.6 V and may be less
than the voltage at VDD but should never exceed it by more than 0.3 V.
17
PD/RST
Power-Down Pin. This pin places the part into full power-down mode and enables power conservation when operation
is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a maximum
of 100 ns. If the maximum time is exceeded, the part enters power-down mode. When placing the AD7298-1 into full
power-down mode, the analog inputs must return to 0 V.
EPAD
The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB ground for proper
functionality and heat dissipation.
Rev. A | Page 8 of 24
AD7298-1
TYPICAL PERFORMANCE CHARACTERISTICS
0
0.50
0.40
0.30
0.20
0.10
0
V
f
= V
= 3V
= 1.17647MHz
DD
DRIVE
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
SAMPLE
f
f
= 50kHz
IN
= 20MHz
SCLK
SNR = 61.83dB
THD = –80.23dB
INL (Positive)
INL (Negative)
–0.10
–0.20
–0.30
–0.40
–0.50
0
100
200
300
400
500
600
1.0
1.2
1.4
1.6
1.8
(V)
2.0
2.2
2.4
2.6
FREQUENCY (MHz)
V
REF
Figure 3. Typical FFT
Figure 6. INL vs. VREF
1.0
0.8
0.6
0.4
0.2
0
0.50
0.40
0.30
0.20
0.10
0
V
V
= 3V
= 3V
DD
DRIVE
INL (Positive)
0.2
0.4
–0.6
–0.8
–1.0
–0.10
–0.20
–0.30
–0.40
–0.50
INL (Negative)
1
101 201 301 401 501 601 701 801 901 1001
CODE
1.0
1.2
1.4
1.6
1.8
(V)
2.0
2.2
2.4
2.6
V
REF
Figure 4. Typical ADC INL
Figure 7. DNL vs. VREF
1.0
0.8
11
10
9
V
= 3V
= 3V
DD
DRIVE
V
0.6
0.4
8
0.2
7
0
6
0.2
5
–0.4
–0.6
–0.8
–1.0
4
3
V
= 3V
DD
V
= 3V
DRIVE
2
1
101 201 301 401 501 601 701 801 901 1001
CODE
0
0.5
1.0
1.5
2.0
2.5
EXTERNAL VOLTAGE REFERENCE (V)
Figure 5. Typical ADC DNL
Figure 8. Effective Number of Bits vs. VREF
Rev. A | Page 9 of 24
AD7298-1
62.0
61.5
61.0
60.5
60.0
59.5
59.0
58.5
58.0
3.0
V
V
= 3V
= 3V
V
= V = 3V
DRIVE
DD
DRIVE
DD
2.5
2.0
1.5
1.0
R
R
R
R
R
R
= 0Ω
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
= 10Ω
= 33Ω
= 47Ω
= 100Ω
= 200Ω
10
100
INPUT FREQUENCY (kHz)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
CURRENT LOAD (mA)
Figure 12. SINAD vs. Analog Input Frequency for Various Source Impedances
Figure 9. VREF vs. Reference Output Current Drive
62.00
–90
–92
V
V
= 3V
= 3V
DD
DRIVE
V
V
= 3V
= 3V
DD
DRIVE
61.75
61.50
61.25
61.00
60.75
60.50
–94
–96
–98
–100
–102
–104
–106
–108
–110
1.0
1.5
2.0
2.5
1k
10k
100k
1M
10M
100M
EXTERNAL REFERENCE VOLTAGE (V)
RIPPLE FREQUENCY (Hz)
Figure 13. SINAD vs. Reference Voltage
Figure 10. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
–80
110
105
100
95
V
V
= 3V
DD
= 3V
DRIVE
–81
–82
–83
–84
–85
–86
–87
–88
–89
–90
90
85
80
75
70
1.0
1.5
2.0
2.5
0
50 100 150 200 250 300 350 400 450 500 550
fNOISE (kHz)
EXTERNAL REFERENCE VOLTAGE (V)
Figure 14. THD vs. Reference Voltage
Figure 11. Channel-to-Channel Isolation, fIN = 50 kHz
Rev. A | Page 10 of 24
AD7298-1
–60
–65
–70
–75
–80
–85
–90
19
18
17
16
15
14
13
12
11
10
R
R
R
R
R
R
= 0Ω
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
V
= V = 3V
DRIVE
DD
= 10Ω
= 33Ω
= 47Ω
= 100Ω
= 200Ω
V
V
= 3V
= 3V
DD
DRIVE
10
100
INPUT FREQUENCY (kHz)
0
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT (kSPS)
Figure 15. THD vs. Analog Input Frequency for Various Source Impedances
Figure 17. Power vs. Throughput in Normal Mode with VDD = 3 V
6
4.0
V = 3V
DRIVE
V
= V = 3V
DRIVE
–40°C
0°C
+85°C
DD
+105°C
+125°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
+25°C
5
4
3
2
1
0
V
CURRENT
DD
V
CURRENT
600
DRIVE
0
200
400
800
1000
1200
2.8
2.9
3.0
3.1
3.2
(V)
3.3
3.4
3.5
3.6
THROUGHPUT (kSPS)
V
DD
Figure 16. Average Supply Current vs. Throughput Rate
Figure 18. Full Shutdown Current vs. Supply Voltage for Various
Temperatures
Rev. A | Page 11 of 24
AD7298-1
TERMINOLOGY
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Signal-to-Noise-and-Distortion Ratio (SINAD)
The measured ratio of signal-to-noise and distortion at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-noise-and-distortion ratio for an ideal N-
bit converter with a sine wave input is given by
Offset Error
The deviation of the first code transition (00…000) to
(00…001) from the ideal—that is, GND1 + 1 LSB.
Offset Error Matching
The difference in offset error between any two channels.
Gain Error
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
The deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, VREF − 1 LSB) after the offset
error has been adjusted out.
Thus, the SINAD is 61.96 dB for an ideal 10-bit converter.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7298-1, it is defined as
Gain Error Matching
The difference in gain error between any two channels.
Track-and-Hold Acquisition Time
2
V22 +V32 +V42 +V52 +V6
THD(dB) = 20log
The track-and-hold amplifier returns to track mode at the end
of the conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within 1 LSB, after the end of the conversion.
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through sixth harmonics.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, fS. The frequency
of the input varies from 5 kHz to 25 MHz.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Typically, the value of this specification
is determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
PSRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints are
zero scale, a point 1 LSB below the first code transition, and full
scale, a point 1 LSB above the last code transition.
Rev. A | Page 12 of 24
AD7298-1
CIRCUIT INFORMATION
The AD7298-1 is a high speed, 8-channel, 10-bit ADC. The part
can be operated from a 2.8 V to 3.6 V supply and is capable of
throughput rates of 1 MSPS per analog input channel.
CAPACITIVE
DAC
A
V
IN
CONTROL
LOGIC
SW1
The AD7298-1 provides the user with an on-chip, track-and-hold
ADC and a serial interface housed in a 20-lead LFCSP. The
AD7298-1 has eight, single-ended input channels with channel
repeat functionality, which allows the user to select a channel
sequence through which the ADC can cycle with each consecutive
B
SW2
COMPARATOR
GND1
Figure 20. ADC Conversion Phase
ANALOG INPUT
falling edge. The serial clock input accesses data from the
CS
Figure 21 shows an equivalent circuit of the analog input structure
of the AD7298-1. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the internally generated
LDO voltage of 2.5 V (DCAP) by more than 300 mV. This causes
the diodes to become forward-biased and to start conducting
current into the substrate. The maximum current these diodes
can conduct without causing irreversible damage to the part is
10 mA. Capacitor C1, in Figure 21, is typically about 8 pF and
can primarily be attributed to pin capacitance. The R1 resistor is
a lumped component made up of the on resistance of a switch
(track-and-hold switch) and includes the on resistance of the
input multiplexer. The total resistance is typically about 155 Ω.
The capacitor, C2, is the ADC sampling capacitor and has a
capacitance of 34 pF typically.
part, controls the transfer of data written to the ADC, and
provides the clock source for the successive approximation
ADC. The analog input range for the AD7928-1 is 0 V to VREF
The AD7298-1 operates with one cycle latency, which means
that the conversion result is available in the serial transfer
following the cycle in which the conversion is performed.
.
The AD7298-1 provides flexible power management options to
allow the user to achieve the best power performance for a given
throughput rate. These options are selected by programming
the partial power-down bit, PPD, in the control register and
using the
/
pin.
PD RST
CONVERTER OPERATION
The AD7298-1 is a 10-bit successive approximation ADC based
around a capacitive DAC. Figure 19 and Figure 20 show simplified
schematics of the ADC. The ADC is comprised of control logic,
SAR, and a capacitive DAC that are used to add and subtract
fixed amounts of charge from the sampling capacitor to bring
the comparator back into a balanced condition. Figure 19 shows
the ADC during its acquisition phase. SW2 is closed and SW1 is
in Position A. The comparator is held in a balanced condition
and the sampling capacitor acquires the signal on the selected
VIN channel.
D
(2.5V)
CAP
C2
pF
D1
D2
R1
V
IN
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
C1
pF
Figure 21. Equivalent Analog Input Circuit
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-pass
filter on the relevant analog input pin. In applications where
harmonic distortion and signal-to-noise ratios are critical, the
analog input should be driven from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC. This may necessitate the use of an input buffer amplifier.
The choice of the op amp is a function of the particular application
performance criteria.
CAPACITIVE
DAC
A
V
IN
CONTROL
LOGIC
SW1
B
SW2
COMPARATOR
GND1
Figure 19. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 20), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the capacitive DAC are used to
add and subtract fixed amounts of charge to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. Figure 22 shows the transfer
function of the ADC.
Rev. A | Page 13 of 24
AD7298-1
ADC Transfer Function
This enables the AD7298-1 to operate with a larger dynamic
range with a VDD of 3.3 V while still being able to interface to
1.8 V processors. Take care to ensure VDRIVE does not exceed
The output coding of the AD7298-1 is straight binary for the
analog input channel conversion results. The designed code
transitions occur at successive LSB values (that is, 1 LSB, 2 LSBs,
and so forth). The LSB size is VREF/1024 for the AD7298-1. The
ideal transfer characteristic for the AD7298-1 for straight binary
coding is shown in Figure 22.
V
DD by more than 0.3 V (see the Absolute Maximum Ratings
section).
THE INTERNAL OR EXTERNAL REFERENCE
The AD7298-1 can operate with either the internal 2.5 V on-chip
reference or an externally applied reference. The EXT_REF bit
in the control register is used to determine whether the internal
reference is used. If the EXT_REF bit is selected in the control
register, an external reference can be supplied through the VREF
pin. At power-up, the internal reference is enabled. Suitable
external reference sources for the AD7298-1 include AD780,
AD1582, ADR431, REF193, and ADR391.
111...111
111...110
111...000
011...111
1LSB = V
REF
/1024
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When the AD7298-1 is operated
in internal reference mode, the 2.5 V internal reference is
available at the VREF pin, which should be decoupled to GND1
using a 10 µF capacitor. It is recommended that the internal
reference be buffered before applying it elsewhere in the system.
000...010
000...001
000...000
0V
1LSB
+V
REF
– 1LSB
ANALOG INPUT
NOTES
1. V
IS 2.5V.
REF
The internal reference is capable of sourcing up to 2 mA of current
when the converter is static. The reference buffer requires 5.5 ms to
power up and charge the 10 µF decoupling capacitor during the
power-up time.
Figure 22. Straight Binary Transfer Characteristic
VDRIVE
The AD7298-1 also provides the VDRIVE feature. VDRIVE controls
the voltage at which the serial interface operates. VDRIVE allows
the ADC to easily interface to both 1.8 V and 3 V processors.
For example, if the AD7298-1 were operated with a VDD of
3.3 V, the VDRIVE pin could be powered from a 1.8 V supply.
Rev. A | Page 14 of 24
AD7298-1
CONTROL REGISTER
The control register of the AD7298-1 is a 16-bit, write-only
register. Data is loaded from the DIN pin of the AD7298-1 on
the falling edge of SCLK. The data is transferred on the DIN
line at the same time that the conversion result is read from the
part. The data transferred on the DIN line corresponds to the
AD7298-1 configuration for the next conversion. This requires
16 serial clocks for every data transfer. Only the information
provided on the first 16 falling clock edges (after the falling
edge of ) is loaded to the control register. MSB denotes the
CS
first bit in the data stream. The bit functions are outlined in
Table 6 and Table 7. At power-up, the default content of the
control register is all zeros.
Table 6. Control Register Bit Functions
MSB
LSB
D15
D14
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WRITE REPEAT
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0
DONTC DONTC EXT_REF
DONTC
PPD
Table 7. Control Register Bit Function Description
Bit
Mnemonic Description
D15
WRITE
The value written to this bit determines whether the subsequent 15 bits are loaded to the control register. If this
bit is a 1, the following 15 bits are written to the control register. If this bit is a 0, then the remaining 15 bits are not
loaded to the control register, and it remains unchanged.
D14
REPEAT
This bit enables the repeated conversion of the selected sequence of channels.
D13 to
D6
CH0 to
CH7
These eight channel selection bits are loaded at the end of the current conversion and select which analog input
channel is to be converted in the next serial transfer, or they can select the sequence of channels for conversion in
the subsequent serial transfers. Each CHx bit corresponds to an analog input channel. A channel or sequence of
channels is selected for conversion by writing a 1 to the appropriate CHx bit/bits. Channel address bits
corresponding to the conversion result are output on DOUT prior to the 10 bits of data. The next channel to be
converted is selected by the mux on the 14th SCLK falling edge.
D5
D4, D3,
D1
0
Zero should be written to this bit.
Don’t care.
DONTC
D2
EXT_REF
PPD
Writing Logic 1 to this bit, enables the use of an external reference. The input voltage range for the external
reference is 1 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance is affected.
This partial power-down mode is selected by writing a 1 to this bit in the control register. In this mode, some of
the internal analog circuitry is powered down. The AD7298-1 retains the information in the control register while
in partial power-down mode. The part remains in this mode until a 0 is written to this bit.
D0
Table 8. Channel Address Bits
ADD3
ADD2
ADD1
ADD0
Analog Input Channel
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
Rev. A | Page 15 of 24
AD7298-1
MODES OF OPERATION
The AD7298-1 offers different modes of operation that are
designed to provide additional flexibility for the user. These
options can be chosen by programming the content of the
control register to select the desired mode.
subsequent (second)
falling edge; and the third falling edge
CS
CS
will have the result (VIN2) available for reading. The AD7298-1
operates with one cycle latency, therefore the conversion result
corresponding to each conversion is available one serial read
cycle after the cycle in which the conversion was initiated.
TRADITIONAL MULTICHANNEL MODE OF
OPERATION
As the device operates with one cycle latency, the control
register configuration sets up the configuration for the next
The AD7298-1 can operate as a traditional multichannel ADC,
where each serial transfer selects the next channel for conversion.
One must write to the control register to configure and select
the desired input channel prior to initiating any conversions. In
conversion, which is initiated on the next
falling edge, but
CS
the first bit of the corresponding result is not clocked out until
the subsequent falling edge, as shown in Figure 23.
CS
the traditional mode of operation, the
signal is used to frame
CS
If more than one channel is selected in the control register, the
AD7298-1 converts all selected channels sequentially in ascending
the first write to the converter on the DIN pin. In this mode of
operation, the REPEAT bit in the control register is set to a low
logic level (0), therefore the REPEAT function is not in use. The
data, which appears on the DOUT pin during the initial write to
order on successive
falling edges. Once all the selected channels
CS
in the control register are converted, the AD7298-1 ceases converting
until the user rewrites to the control register to select the next
channel for conversion. This operation is shown in Figure 24.
DOUT returns all 1s if the sequence of conversions is completed or
if no channel is selected.
the control register, is invalid. The first
falling edge initiates a
CS
write to the control register to configure the device; a conversion is
then initiated for the selected analog input channel (VIN0) on the
CS
1
10
16
1
16
1
16
1
16
SCLK
DOUT
CONVERSION RESULT
FOR CHANNEL 4
CONVERSION RESULT
FOR CHANNEL 1
INVALID DATA
INVALID DATA
DATA WRITTEN TO CONTROL
REGISTER CHANNEL 1 SELECTED
DATA WRITTEN TO CONTROL
REGISTER CHANNEL 4 SELECTED
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
DIN
Figure 23. Configuring a Conversion and Read with the AD7298-1, One Channel Selected for Conversion
CS
1
10
16
1
16
1
16
SCLK
DOUT
CONVERSION RESULT
FOR CHANNEL 1
INVALID DATA
INVALID DATA
DATA WRITTEN TO CONTROL
REGISTER CH 1 AND 2 SELECTED
NO WRITE TO THE
CONTROL REGISTER
DATA WRITTEN TO CONTROL
REGISTER CHANNEL 5 SELECTED
DIN
CS
1
16
1
16
SCLK
DOUT
CONVERSION RESULT
FOR CHANNEL 2
CONVERSION RESULT
FOR CHANNEL 5
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
DIN
Figure 24. Configuring a Conversion and Read with the AD7298-1, Numerous Channels Selected for Conversion
Rev. A | Page 16 of 24
AD7298-1
CS
1
10
16
1
16
1
16
SCLK
DOUT
CONVERSION RESULT
FOR CHANNEL 0
INVALID DATA
INVALID DATA
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
DIN
DATA WRITTEN TO CONTROL
REGISTER CH0, CH1, AND CH2
SELECTED: REPEAT = 1
CS
1
16
1
16
1
16
SCLK
DOUT
CONVERSION RESULT
FOR CHANNEL 2
CONVERSION RESULT
FOR CHANNEL 0
CONVERSION RESULT
FOR CHANNEL 1
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
DIN
Figure 25. Configuring a Conversion and Read in Repeat Mode
REPEAT OPERATION
The REPEAT bit in the control register allows the user to select
a sequence of channels on which the AD7298-1 continuously
converts. When the REPEAT bit is set in the control register, the
AD7298-1 continuously cycles through the selected channels in
ascending order, beginning with the lowest channel and converting
all channels selected in the control register. On completion of
the sequence, the AD7298-1 returns to the first selected channel
in the control register and recommences the sequence.
To select a sequence of channels, the associated channel bit
must be set to a logic high state (1) for each analog input whose
conversion is required. For example, if the REPEAT bit = 1, then
CH0, CH1, and CH2 = 1. The VIN0 analog input is converted on
the first
falling edge following the write to the control register,
CS
the VIN1 channel is converted on the subsequent
falling edge,
CS
and the VIN0 conversion result is available for reading. The third
falling edge following the write operation initiates a conversion
CS
The conversion sequence of the selected channels in the repeat
mode of operation continues until the control register of the
AD7298-1 is reprogrammed. It is not necessary to write to the
control register once a repeat operation is initiated unless a change
in the AD7298-1 configuration is required. The WRITE bit
must be set to zero, or the DIN line tied low to ensure that the
control register is not accidentally overwritten or the automatic
conversion sequence interrupted.
on VIN2 and has the VIN1 result available for reading. The AD7298-1
operates with one cycle latency, therefore the conversion result
corresponding to each conversion is available one serial read
cycle after the cycle in which the conversion is initiated.
This mode of operation simplifies the operation of the device by
allowing consecutive channels to be converted without having
to reprogram the control register or write to the part on each
serial transfer. Figure 25 illustrates how to set up the AD7298-1
to continuously convert on a particular sequence of channels.
To exit the repeat mode of operation and revert to the traditional
mode of operation of a multichannel ADC, ensure that the
REPEAT bit = 0 on the next serial write.
A write to the control register during the repeat mode of operation
resets the cycle even if the selected channels are unchanged.
Thus, the next conversion by the AD7298-1 after a write
operation will be the first selected channel in the sequence.
Rev. A | Page 17 of 24
AD7298-1
Partial Power-Down Mode
POWER-DOWN MODES
In this mode, part of the internal circuitry on the AD7298-1
is powered down. The AD7298-1 enters partial power-down
The AD7298-1 has a number of power conservation modes of
operation that are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for different application
requirements. The power-down modes of operation of the
AD7298-1 are controlled by the power-down (PPD) bit in the
on the
rising edge once the current serial write operation
CS
containing 16 SCLK clock cycles is completed. To enter partial
power-down, the PPD bit in the control register should be set to
1 on the last required read transfer from the AD7298-1. Once in
partial power-down mode, the AD7298-1 transmits all 1s on the
PD RST
control register and the
/
pin on the device. When power
DOUT pin if
is toggled low.
CS
supplies are first applied to the AD7298-1, care should be taken
to ensure that the part is placed in the required mode of operation.
The AD7298-1 remains in partial power-down until the power-
down bit, PPD, in the control register is changed to Logic Level 0.
Normal Mode
The AD7298-1 begins powering up on the rising edge of
CS
Normal mode is intended for the fastest throughput rate
performance because the user does not have to be concerned
about any power-up times since the AD7298-1 remains fully
powered on at all times. Figure 26 shows the general diagram
of the normal mode operation of the AD7298-1. The conversion
following the write to the control register disabling the power-
down bit. Once tQUIET has elapsed, a full 16 SCLK writes to the
control register must be completed to update its content with
the desired channel configuration for the subsequent conversion.
A valid conversion is then initiated on the next
falling edge.
CS
is initiated on the falling edge of
and the track-and-hold enters
CS
hold mode. On the 14th SCLK falling edge, the track-and-hold
returns to track mode and starts acquiring the analog input, as
described in the Serial Interface section. The data presented to
the AD7298-1 on the DIN line during the first 16 clock cycles of
the data transfer are loaded into the control register (provided the
WRITE bit is 1). The part remains fully powered up in normal
mode at the end of the conversion as long as the PPD bit is set
to 0 in the write transfer during that conversion.
Because the AD7298-1 has one cycle latency, the first conversion
result after exiting partial power-down mode is available in the
fourth serial transfer, as shown in Figure 27. The first cycle updates
the PPD bit, the second cycle updates the configuration and
Channel ID bits, the third completes the conversion, and the
fourth accesses the DOUT valid result. The use of this mode
enables a reduction in the overall power consumption of the device.
Full Power-Down Mode
To ensure continued operation in normal mode, the PPD bit
should be loaded with 0 on every data write operation. Sixteen
serial clock cycles are required to complete the conversion and
access the conversion result. For specified performance, the
throughput rate should not exceed 1 MSPS. When a conversion
In this mode, all internal circuitry on the AD7298-1 is powered
down, and no information is retained in the control register or any
other internal register.
The AD7298-1 is placed into full power-down mode by bringing
PD RST
the logic level on the
When placing the AD7298-1 in full power-down mode, the ADC
PD RST
pin is asynchronous to the
/
pin low for greater than 100 ns.
is complete and the
has returned high, a minimum of the quiet
CS
time, tQUIET, must elapse before bringing
low again to initiate
CS
inputs must return to 0 V. The
/
another conversion and access the previous conversion result.
clock; therefore, it can be triggered at any time. The part can be
CS
PD RST
pin
powered up for normal operation by bringing the
logic level back to a high logic state.
/
1
16
SCLK
DOUT
4 CHANNEL ADDRESS BITS
+ CONVERSION RESULT
The full power-down feature can be used to reduce the average
power consumed by the AD7298-1 when operating at lower
throughput rates. The user should ensure that tPOWER-UP has
elapsed prior to programming the control register and initiating
a valid conversion.
DATA WRITTEN TO CONTROL
REGISTER IF REQUIRED
DIN
Figure 26. Normal Mode Operation
THE PART IS FULLY
PART IS IN
PARTIAL
POWER DOWN
PART BEGINS TO
POWER UP ON CS
RISING EDGE.
POWERED UP ONCE THE
WRITE TO THE CONTROL
REGISTER IS COMPLETED.
tQUIET
tQUIET
CS
1
10
16
1
16
1
16
SCLK
DOUT
INVALID DATA
INVALID DATA
WRITE TO CONTROL
REGISTER, PPD = 0.
WRITE TO THE CONTROL
REGISTER, SELECT CH1, PPD = 0
NO WRITE TO
CONTROL REGISTER
DIN
CONTROL REGISTER CONFIGURED
TO POWER UP DEVICE.
SELECT ANALOG INPUT CHANNELS
FOR CONVERSION. THE NEXT CYCLE
WILL CONVERT THE FIRST CHANNEL
AD7298 CONVERTING CHANNEL 1
NEXT CYCLE HAS CHANNEL 1
RESULT AVAILABLE FOR READING.
PROGRAMMED IN THIS WRITE OPERATION.
Figure 27. Partial Power-Down Mode of Operation
Rev. A | Page 18 of 24
AD7298-1
POWERING UP THE AD7298-1
RESET
The AD7298-1 contains a power-on reset circuit that sets the
control register to its default setting of all zeros; therefore, the
internal reference is enabled and the device is configured for the
normal mode of operation. At power-up, the internal reference is
by default enabled, which takes up to 6 ms (maximum) to power up.
The AD7298-1 includes a reset feature that can be used to reset
the device and the contents of all internal registers, including
the control register, to their default state.
PD RST
pin should be brought
To activate the reset operation, the
low for no longer than 100 ns. It is asynchronous with the clock;
PD RST
/
If an external reference is being used, the user does not need to
wait for the internal reference to power up fully. The AD7298-1
digital interface is fully functional after 500 µs from the initial
power-up. Therefore, the user can write to the control register
after 500 µs to switch to external reference mode. The AD7298-1 is
then immediately ready to convert once the external reference is
available on the VREF pin.
therefore, it can be triggered at any time. If the
held low for greater than 100 ns, the part enters full power-down
PD RST
/
pin is
mode. It is imperative that the
/
pin be held at a stable
logic level at all times to ensure normal operation.
When supplies are first applied to the AD7298-1, the user must
wait the specified 500 µs before programming the control register
to select the desired channels for conversion.
Rev. A | Page 19 of 24
AD7298-1
SERIAL INTERFACE
Figure 28 shows the detailed timing diagram for the serial interface
to the AD7298-1. The serial clock provides the conversion clock
and controls the transfer of information to and from the AD7298-1
during each conversion.
When
goes low, it provides the first address bit to be read in
CS
by the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges, beginning with a second
address bit. Thus, the first falling clock edge on the serial clock
has the first address bit provided for reading and also clocks out
the second address bit. The three remaining address bits and 12
data bits are clocked out by subsequent SCLK falling edges. The
final bit in the data transfer is valid for reading on the 16th falling
edge having been clocked out on the previous (15th) falling edge.
The
signal initiates the data transfer and conversion process.
CS
The falling edge of
puts the track-and-hold into hold mode
CS
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires 16 SCLK cycles to complete. The track-and-hold
goes back into track mode on the 14th SCLK falling edge as shown
in Figure 28 at Point B. On the 16th SCLK falling edge or on the
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge depending on the SCLK frequency.
The first rising edge of SCLK after the
falling edge would
CS
rising edge of , the DOUT line goes back into three-state.
CS
have the first address bit provided, and the 15th rising SCLK
edge would have last data bit provided.
If the rising edge of
occurs before 16 SCLKs have elapsed,
CS
the conversion is terminated, the DOUT line goes back into
three-state, and the control register is not updated; otherwise,
DOUT returns to three-state on the 16th SCLK falling edge.
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7298-1.
Writing information to the control register takes place on the
first 16 falling edges of SCLK in a data transfer, assuming the
MSB (that is, the WRITE bit) has been set to 1. The 16-bit word
read from the AD7298-1 always contains four channel address
bits that the conversion result corresponds to, followed by the
12-bit conversion result.
For the AD7298-1, four channel address bits (ADD3 to ADD0)
that identify which channel the conversion result corresponds
to, precede the 10 bits of data (see Table 8).
tQUIET
CS
tACQUISITION
t2
t6
B
1
2
3
4
5
13
14
15
t5
16
SCLK
t4
t7
t8
t3
THREE-
STATE
DON’T
CARE
DON’T
CARE
DOUT
DIN
ADD3
ADD2
t9
ADD1
ADD0
DB9
DB8
DB0
THREE-
STATE
t10
DONTC
WRITE
REPEAT
CH0
CH1
CH2
CH3
EXT_REF
PPD
Figure 28. Serial Interface Timing Diagram
Rev. A | Page 20 of 24
AD7298-1
LAYOUT AND CONFIGURATION
For optimum performance, carefully consider the power supply
and ground return layout on any PCB where the AD7298-1 is
used. The PCB containing the AD7298-1 should have separate
analog and digital sections, each having its own area of the board.
The AD7298-1 should be located in the analog section on any PCB.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Shield clocks and other components with fast switching
digital signals from other parts of the board by a digital ground.
Avoid crossover of digital and analog signals, if possible. When
traces cross on opposite sides of the board, ensure that they run
at right angles to each other to reduce feedthrough effects on
the board.
Decouple the power supply to the AD7298-1 to ground with
10 µF and 0.1 µF capacitors. Place the capacitors as physically
close as possible to the device, with the 0.1 µF capacitor ideally
right up against the device. It is important that the 0.1 µF
capacitor has low effective series resistance (ESR) and low
effective series inductance (ESL); common ceramic types of
capacitors are suitable. The 0.1 µF capacitors provide a low
impedance path to ground for high frequencies caused by
transient currents due to internal logic switching. The 10 µF
capacitors are the tantalum bead type.
The best board layout technique is the microstrip technique where
the component side of the board is dedicated to the ground
plane only, and the signal traces are placed on the solder side;
however, this is not always possible with a 2-layer board.
Rev. A | Page 21 of 24
AD7298-1
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.75
2.60 SQ
2.35
11
5
6
BOTTOM VIEW
10
0.50
0.40
0.30
0.25 MIN
TOP VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 29. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very, Very Thin Quad
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-20-8
CP-20-8
AD7298-1BCPZ
AD7298-1BCPZ-RL
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
1 Z = RoHS Compliant Part.
Rev. A | Page 22 of 24
AD7298-1
NOTES
Rev. A | Page 23 of 24
AD7298-1
NOTES
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09321-0-1/11(A)
Rev. A | Page 24 of 24
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