AD734BNZ [ADI]
10 MHz, Four-Quadrant Multiplier/Divider; 10兆赫，四象限乘法器/除法器
| 型号： | AD734BNZ |
| 厂家： | 
ADI |
| 描述： | 10 MHz, Four-Quadrant Multiplier/Divider |
| 文件： | 总20页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10 MHz, Four-Quadrant
Multiplier/Divider
AD734
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High accuracy
AD734
0.1% typical error
High speed
X1
X2
X = X – X
1
2
HIGH ACCURACY
TRANSLINEAR CORE
XIF
10 MHz full power bandwidth
450 V/μs slew rate
200 ns settling to 0.1% at full power
Low distortion
−80 dBc from any input
Third-order IMD typically −75 dBc at 10 MHz
Low noise
94 dB SNR, 10 Hz to 20 kHz
70 dB SNR, 10 Hz to 10 MHz
Direct division mode
2 MHz BW at gain of 100
DD
U
XY ÷ U – Z
+
XZ
DENOMINATOR
CONTROL
WIF
W
U
–
U0
U1
A
O
∞
ER
R
U
U2
Y1
Y2
Y = Y – Y
Z = Z – Z
2
Z1
Z2
1
2
1
YIF
ZIF
Figure 1.
APPLICATIONS
High performance replacement for AD534
Multiply, divide, square, square root
Modulators, demodulators
Wideband gain control, rms-to-dc conversion
Voltage-controlled amplifiers, oscillators, and filters
Demodulator with 40 MHz input bandwidth
GENERAL DESCRIPTION
The AD734 is an accurate high speed, four-quadrant analog
multiplier that is pin compatible with the industry-standard
AD534 and provides the transfer function W = XY/U. The
AD734 provides a low impedance voltage output with a full
power (20 V p-p) bandwidth of 10 MHz. Total static error
(scaling, offsets, and nonlinearities combined) is 0.1% of full
scale. Distortion is typically less than −80 dBc and guaranteed.
The low capacitance X, Y, and Z inputs are fully differential.
In most applications, no external components are required to
define the function.
10 MHz to a gain of 20 dB, 2 MHz at a gain of 40 dB, and 200 kHz
at a gain of 60 dB, for a gain-bandwidth product of 200 MHz.
The advanced performance of the AD734 is achieved by a
combination of new circuit techniques, the use of a high speed
complementary bipolar process, and a novel approach to laser
trimming based on ac signals rather than the customary dc
methods. The wide bandwidth (>40 MHz) of the AD734’s input
stages and the 200 MHz gain-bandwidth product of the multiplier
core allow the AD734 to be used as a low distortion demodulator
with input frequencies as high as 40 MHz as long as the desired
output frequency is less than 10 MHz.
The internal scaling (denominator) voltage, U, is 10 V, derived
from a buried-Zener voltage reference. A new feature provides
the option of substituting an external denominator voltage,
allowing the use of the AD734 as a two-quadrant divider with a
1000:1 denominator range and a signal bandwidth that remains
The AD734AQ and AD734BQ are specified for the industrial
temperature range of −40°C to +85°C and come in a 14-lead
CERDIP and a 14-lead PDIP package. The AD734SQ/883B,
available processed to MIL-STD-883B for the military range of
−55°C to +125°C, is available in a 14-lead CERDIP.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
AD734
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Description.................................................................. 10
Available Transfer Functions .................................................... 10
Direct Denominator Control.................................................... 11
Operation as a Multiplier .......................................................... 12
Operation as a Divider............................................................... 14
Division by Direct Denominator Control............................... 14
A Precision AGC Loop.............................................................. 15
Wideband RMS-to-DC Converter Using U Interface........... 16
Low Distortion Mixer................................................................ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
2/11—Rev. D to Rev. E
Changes to Figure 4, Figure 5, and Figure 6.................................. 7
Changes to Figure 22 and Figure 23............................................. 12
Changes to Figure 27 and Figure 28............................................. 14
Changes to Figure 36...................................................................... 17
1/11—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Figure 1 and General Description Section ............... 1
Deleted Product Highlights Section............................................... 1
Change to Endnote 3........................................................................ 4
Changes to Table 2 and Table 3....................................................... 5
Added Pin Configuration and Function Descriptions Section.. 6
Added Figure 3; Renumbered Sequentially .................................. 6
Added Table 4; Renumbered Sequentially .................................... 6
Changes to Functional Description Section ............................... 10
Changes to Figure 36...................................................................... 17
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 19
Rev. E | Page 2 of 20
AD734
SPECIFICATIONS
TA = +25°C, +VS = VP = +15 V, −VS = VN = −15 V, RL ≥ 2 kΩ, unless otherwise noted.
⎧
⎪
⎫
⎪
X1 − X2 Y1 − Y2
−
Generalized transfer function:
W = A
(
Z1 − Z2
)
⎨
⎬
O
U1 −U2
⎪
⎪
⎩
⎭
Table 1.
A
B
S
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
MULTIPLIER PERFORMANCE
Transfer Function
W =
XY/10
W =
XY/10
W =
XY/10
Total Static Error1
Over TMIN to TMAX
vs. Temperature
vs. Either Supply
Peak Nonlinearity
−10 V ≤ X, Y ≤ 10 V
0.1
0.4
1
0.1
0.25
0.6
0.1
0.4
%
1.25
%
TMIN to TMAX
0.004
0.01
0.05
0.003
0.01
0.05
0.004
0.01
0.05
%/°C
%/V
%
VS = 14 V to 16 V
0.05
0.05
0.05
−10 V ≤ X ≤ +10 V,
Y = +10 V
−10 V ≤ Y ≤ +10 V,
X = +10 V
0.025
0.025
0.025
%
THD2
X = 7 V rms, Y =
+10 V, f ≤ 5 kHz
−58
−66
−58
dBc
TMIN to TMAX
−55
−60
−63
−80
−55
−60
dBc
dBc
Y = 7 V rms, X =
+10 V, f ≤ 5 kHz
TMIN to TMAX
−57
−60
−74
−70
−57
–60
dBc
dBc
Feedthrough
X = 7 V rms, Y =
nulled, f ≤ 5 kHz
−85
−85
−85
−85
–85
−85
Y = 7 V rms, X =
nulled, f ≤ 5 kHz
−66
−76
−66
dBc
Noise (RTO)
X = Y = 0 V
Spectral Density
Total Output Noise
100 Hz to 1 MHz
10 Hz to 20 kHz
TMIN to TMAX
1.0
1.0
1.0
μV/√Hz
dBc
−94
−88
−85
−94
−88
−85
−94
−88
−85
dBc
DIVIDER PERFORMANCE
(Y = 10 V)
Transfer Function
W =
W =
W =
XY/U
XY/U
XY/U
Gain Error
Y = 10 V, U = 100 mV
to 10 V
1
1
1
%
X Input Clipping Level
U Input Scaling Error3
Y ≤ 10 V
1.25 × U
1.25 × U
100
1.25 × U
100
V
0.3
0.8
0.15
0.65
0.3
1
%
%
ns
TMIN to TMAX
Output to 1%
U = 1 V to 10 V step,
X = 1 V
100
INPUT INTERFACES
(X, Y, AND Z)
3 dB Bandwidth
Operating Range
40
40
40
MHz
V
Differential or
common mode
12.5
12.5
12.5
X Input Offset Voltage
Y Input Offset Voltage
Z Input Offset Voltage
15
25
10
12
20
50
5
15
25
10
12
20
90
mV
mV
mV
mV
mV
mV
dB
TMIN to TMAX
TMIN to TMAX
15
5
6
10
50
TMIN to TMAX
f ≤ 1 kHz
Z Input PSRR (Either
Supply)
54
50
70
66
56
70
54
50
70
TMIN to TMAX
dB
Rev. E | Page 3 of 20
AD734
A
B
S
Parameter
Conditions
Min
Typ
85
Max
Min
Typ
85
Max
Min
Typ
85
Max
Unit
dB
CMRR
f = 5 kHz
70
70
70
Input Bias Current
(X, Y, Z Inputs)
50
300
400
50
150
300
50
300
500
nA
TMIN to TMAX
Differential
Differential
nA
kΩ
pF
Input Resistance
50
2
50
2
50
2
Input Capacitance
DENOMINATOR INTERFACES
(U0, U1, AND U2)
Operating Range
VN to
VN to
VN to
V
VP − 3
VP − 3
VP − 3
Denominator Range
Interface Resistor
1000:1
28
1000:1
28
1000:1
28
U1 to U2
kΩ
OUTPUT AMPLIFIER (W)
Output Voltage Swing
Open-Loop Voltage Gain
Dynamic Response
TMIN to TMAX
12
12
12
V
X = Y = 0, input to Z
72
72
72
dB
From X or Y input,
CLOAD ≤ 20 pF
3 dB Bandwidth
Slew Rate
W ≤ 7 V rms
8
10
8
10
8
10
MHz
V/μs
450
450
450
Settling Time
+20 V or −20 V
output step
To 1%
125
200
50
125
200
50
125
200
50
ns
To 0.1%
ns
Short-Circuit Current
POWER SUPPLIES, VS
Operating Supply Range
Quiescent Current
TMIN to TMAX
20
80
20
80
20
80
mA
8
6
16.5
12
8
6
16.5
12
8
6
16.5
12
V
TMIN to TMAX
9
9
9
mA
1 Figures given are percent of full scale (for example, 0.01% = 1 mV).
2 dBc refers to decibels relative to the full-scale input (carrier) level of 7 V rms.
3 See Figure 28 for test circuit.
Rev. E | Page 4 of 20
AD734
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage
18 V
Internal Power Dissipation
for TJ max = 175°C
X, Y, and Z Input Voltages
Output Short-Circuit Duration
Storage Temperature Range
Q-14
500 mW
VN to VP
Indefinite
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
−65°C to +150°C
−65°C to +150°C
N-14
Operating Temperature Range
AD734A, AD734B (Industrial)
AD734S (Military)
Lead Temperature Range (Soldering, 60 sec)
Transistor Count
Table 3. Thermal Resistance
Package Type
14-Lead PDIP (N-14)
14-Lead CERDIP (Q-14)
−40°C to +85°C
−55°C to +125°C
+300°C
θJA
Unit
°C/W
°C/W
150
110
81
ESD Rating
500 V
ESD CAUTION
0.093 (2.3622)
W
Z2
Z1
12
10
11
DD
ER
13
9
VP
VN
Y2
14
8
7
0.122
(3.0988)
1
X1
2
6
Y1
X2
3
4
5
U1
U2
U0
Figure 2. Chip Dimensions and Bonding Diagram, Dimensions shown in inches and (mm), (Contact factory for latest dimensions)
Rev. E | Page 5 of 20
AD734
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
X1
X2
U0
U1
U2
Y1
Y2
1
2
3
4
5
6
7
14 VP
13 DD
AD734
12
W
TOP VIEW
(Not to Scale)
11 Z1
10 Z2
9
8
ER
VN
Figure 3. 14-Lead PDIP and 14-Lead CERDIP
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
X1
X2
U0
U1
U2
Y1
Y2
VN
ER
Z2
Z1
W
X Differential Multiplicand Input.
X Differential Multiplicand Input.
Denominator Current Source Enable Interface.
Denominator Interface—see the Functional Description section.
Denominator Interface—see the Functional Description section.
Y Differential Multiplicand Input.
Y Differential Multiplicand Input.
Negative Supply.
9
Reference Voltage.
10
11
12
13
14
Z Differential Summing Input.
Z Differential Summing Input.
Output.
Denominator Disable.
Positive Supply.
DD
VP
Rev. E | Page 6 of 20
AD734
TYPICAL PERFORMANCE CHARACTERISTICS
100
80
60
40
20
0
0.10
0.08
V
R
C
= ±15V
Y INPUT, X = 10V
S
0.06
0.04
= 2kΩ
LOAD
LOAD
= 20pF
0.02
0
X INPUT, Y = 10V
–0.02
–0.04
–0.06
–0.08
–0.10
COMMON-MODE
SIGNAL = 7V RMS
–2V
0
2V
1k
10k
100k
1M
10M
SIGNAL AMPLITUDE
FREQUENCY (Hz)
Figure 7. CMRR vs. Frequency
Figure 4. Differential Gain at 3.58 MHz and RLOAD = 2 kΩ
100
80
60
40
20
0
0.25
0.20
0.15
0.10
0.05
0
V
R
C
= ±15V
S
= 2kΩ
= 20pF
LOAD
LOAD
VN
VP
–0.05
–0.10
–0.15
–0.20
–0.25
–2V
0
2V
1k
10k
100k
1M
10M
SIGNAL AMPLITUDE
FREQUENCY (Hz)
Figure 5. Differential Phase at 3.58 MHz and RLOAD = 2 kΩ
Figure 8. PSRR vs. Frequency
0
0.5
0.4
INPUT SIGNAL = 7V RMS
Y INPUT, X NULLED
V
= ±15V
S
X = 1.4V RMS
Y = 10V
–40
–60
0.3
R
C
= 500Ω
= 20pF
LOAD
LOAD
0.2
0.1
0
X INPUT, Y NULLED
–80
–0.1
–0.2
–0.3
–0.4
–0.5
–100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100k
1M
FREQUENCY (Hz)
10M
Figure 9. Feedthrough vs. Frequency
Figure 6. Gain Flatness, 300 kHz to 10 MHz, RLOAD = 500 Ω
Rev. E | Page 7 of 20
AD734
0
–20
–40
–60
–80
5
4
V
= ±15V
S
TEST INPUT = 1V RMS
U = 2V
OTHER INPUT = 2V DC
X = 1.4V RMS
Y = 10V
R
C
3
= 500Ω
LOAD
LOAD
2
= 20pF, 47pF, 100pF
INCREASING
1
C
LOAD
0
X INPUT
–1
–2
–3
–4
–5
Y INPUT
1k
10k
100k
1M
10M
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Gain vs. Frequency vs. CLOAD
Figure 10. THD vs. Frequency, U = 2 V
0
–20
–40
–60
–80
TEST INPUT = 7V RMS
OTHER INPUT = 10V DC
0
–30
R
≥2kΩ
LOAD
–60
–90
X INPUT
V
= ±15V
–120
–150
–180
–210
S
X = 1.4V RMS
Y = 10V
R
C
Y INPUT
= 500Ω
LOAD
LOAD
= 20pF, 47pF, 100pF
INCREASING
C
LOAD
100k
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 11. THD vs. Frequency, U = 10 V
Figure 14. Phase vs. Frequency vs. CLOAD
0
–20
FREQUENCY = 1MHz
VP = +15V
VN = –15V
R
= 2kΩ
LOAD
–40
INCREASING
C
LOAD
X INPUT. Y = 10V DC
–60
Y INPUT. X = 10V DC
–80
5V
50ns
–100
–10dBm
70.7mV RMS
10dBm
707mV RMS
30dBm
7V RMS
SIGNAL LEVEL
Figure 15. Pulse Response vs. CLOAD
CLOAD = 0 pF, 47 pF, 100 pF, 200 pF
,
Figure 12. THD vs. Signal Level, f = 1 MHz
Rev. E | Page 8 of 20
AD734
20
15
20
15
10
5
INPUT OFFSET VOLTAGE
DRIFT WILL TYPICALLY BE
WITHIN SHADED AREA
10
5
0
0
–5
–5
–10
–15
–10
–15
–20
–55 –35 –15
5
25
45
65
85
105 125
105 125
105 125
8
9
10
11
12
13
14
15
16
17
18
TEMPERATURE (°C)
SUPPLY VOLTAGE (±V )
S
Figure 18. VOS Drift, X Input
Figure 16. Output Swing vs. Supply Voltage
60
40
0
–10
–20
–30
INPUT OFFSET VOLTAGE
DRIFT WILL TYPICALLY BE
WITHIN SHADED AREA
U = 10V
20
U = 5V
0
U = 2V
–20
–40
–60
U = 1V
X
Y
FREQ =
FREQ –1MHz
(FOR EXAMPLE,
– X = 1MHz
FOR ALL CURVES)
1
1
Y
1
1
–55 –35 –15
5
25
45
65
85
10
20 30 40
50
60
70
80
90
100
TEMPERATURE (°C)
Y
FREQUENCY (MHz)
1
Figure 19. VOS Drift, Z Input
Figure 17. Output Amplitude vs. Input Frequency, When Used as
Demodulator
8
6
INPUT OFFSET VOLTAGE
DRIFT WILL TYPICALLY BE
WITHIN SHADED AREA
4
2
0
–2
–4
–6
–55 –35 –15
5
25
45
65
85
TEMPERATURE (°C)
Figure 20. VOS Drift, Y Input
Rev. E | Page 9 of 20
AD734
FUNCTIONAL DESCRIPTION
be replaced by a fixed or variable external voltage ranging from
10 mV to more than 10 V.
The AD734 embodies more than two decades of experience in
the design and manufacture of analog multipliers to provide:
The high gain output op amp nulls the difference between XY/
U and an additional signal, Z, to generate the final output, W.
The actual transfer function can take on several forms, depending
on the connections used. The AD734 can perform all of the
functions supported by the AD534, and new functions using
the direct-division mode provided by the U interface.
•
•
•
A new output amplifier design with more than 20 times the
slew rate of the AD534 (450 V/μs vs. 20 V/μs) for a full
power (20 V p-p) bandwidth of 10 MHz.
Very low distortion, even at full power, through the use of
circuit and trimming techniques that virtually eliminate all
of the spurious nonlinearities found in earlier designs.
Direct control of the denominator, resulting in higher
multiplier accuracy and a gain-bandwidth product at small
denominator values that is typically 200 times greater than
that of the AD534 in divider modes.
Very clean transient response, achieved through the use of
a novel input stage design and wideband output amplifier,
which also ensure that distortion remains low even at high
frequencies.
Superior noise performance by careful choice of device
geometries and operating conditions, which provide a
guaranteed 88 dB of dynamic range in a 20 kHz bandwidth.
Each input pair (X1 and X2, Y1 and Y2, Z1 and Z2) has a
differential input resistance of 50 kΩ; this is formed by actual
resistors (not a small-signal approximation) and is subject to a
tolerance of 20%. The common-mode input resistance is
several megohms and the parasitic capacitance is about 2 pF.
•
•
The bias currents associated with these inputs are nulled by
laser-trimming, such that when one input of a pair is optionally
ac-coupled and the other is grounded, the residual offset voltage
is typically less than 5 mV, which corresponds to a bias current
of only 100 nA. This low bias current ensures that mismatches
in the sources’ resistances at a pair of inputs does not cause an
offset error. These currents remain low over the full temperature
range and supply voltages.
Figure 3 shows the lead configuration of the 14-lead PDIP and
CERDIP packages.
The common-mode range of the X, Y, and Z inputs does not
fully extend to the supply rails. Nevertheless, it is often possible
to operate the AD734 with one terminal of an input pair con-
nected to either the positive or negative supply, unlike previous
multipliers. The common-mode resistance is several megohms.
Figure 1 is a simplified block diagram of the AD734. Operation
is similar to that of the industry-standard AD534, and in many
applications, these parts are pin compatible. The main functional
difference is the provision for direct control of the denominator
voltage, U, explained fully in the Direct Denominator Control
section. Internal signals are in the form of currents, but the
function of the AD734 can be understood using voltages
throughout, as shown in Figure 1.
The full-scale output of 10 V can be delivered to a load resistance
of 1 kΩ (although the specifications apply to the standard multi-
plier load condition of 2 kΩ). The output amplifier is stable,
driving capacitive loads of at least 100 pF, when a slight increase
in bandwidth results from the peaking caused by this capacitance.
The 450 V/μs slew rate of the AD734 output amplifier ensures
that the bandwidth of 10 MHz can be maintained up to the full
output of 20 V p-p. Operation at reduced supply voltages is
possible, down to 8 V, with reduced signal levels.
The AD734 differential X, Y, and Z inputs are handled by
wideband interfaces that have low offset, low bias current, and
low distortion. The AD734 responds to the difference signals
X = X1 − X2, Y = Y1 − Y2, and Z = Z1 − Z2, and rejects common-
mode voltages on these inputs. The X, Y, and Z interfaces provide a
nominal full-scale (FS) voltage of 10 V, but, due to the special
design of the input stages, the linear range of the differential
input can be as large as 17 V. Also, unlike previous designs, the
response on these inputs is not clipped abruptly above 15 V,
but drops to a slope of one half.
AVAILABLE TRANSFER FUNCTIONS
The uncommitted (open-loop) transfer function of the AD734 is
X1 − X2 )Y1 −Y2
)
⎧
⎨
⎩
⎫
W = AO
−
(
Z1 − Z2
)
(1)
⎬
U
⎭
The bipolar input signals X and Y are multiplied in a translinear
core of novel design to generate the product XY/U. The denomina-
tor voltage, U, is internally set to an accurate, temperature-stable
value of 10 V, derived from a buried-Zener reference. An uncali-
brated fraction of the denominator voltage U appears between
the voltage reference pin (ER) and the negative supply pin (VN),
for use in certain applications where a temperature-compensated
voltage reference is desirable. The internal denominator, U, can
be disabled, by connecting the denominator disable Pin 13
(DD) to the positive supply pin (VP); the denominator can then
where AO is the open-loop gain of the output op amp, typically
72 dB. When a negative feedback path is provided, the circuit
forces the quantity inside the brackets essentially to zero,
resulting in the equation
(X1 − X2)(Y1 − Y2) = U (Z1 − Z2)
(2)
This is the most useful generalized transfer function for the
AD734; it expresses a balance between the product XY and the
product UZ. The absence of the output, W, in this equation only
reflects the fact that the input to be connected to the op amp
output is not specified.
Rev. E | Page 10 of 20
AD734
Most of the functions of the AD734 (including division, unlike
the AD534 in this respect) are realized with Z1 connected to W.
Therefore, substituting W in place of Z1 in Equation 2 results in
an output.
DIRECT DENOMINATOR CONTROL
A valuable new feature of the AD734 is the provision to replace
the internal denominator voltage, U, with any value from 10 mV to
10 V. This can be used
(X1 − X2 )(Y1 −Y2 )
•
•
•
To simply alter the multiplier scaling, thus improve accu-
racy and achieve reduced noise levels when operating with
small input signals.
To implement an accurate two-quadrant divider, with a
1000:1 gain range and an asymptotic gain-bandwidth
product of 200 MHz.
W =
+ Z2
(3)
U
The free input, Z2, can be used to sum another signal to the
output; in the absence of a product signal, W simply follows the
voltage at Z2 with the full 10 MHz bandwidth. When not needed
for summation, Z2 should be connected to the ground
associated with the load circuit. The allowable polarities can be
shown in the following shorthand form:
To achieve certain other special functions, such as
AGC or rms.
(±X)(±Y)
(+U)
Figure 21 shows the internal circuitry associated with
denominator control. Note, first, that the denominator is
actually proportional to a current, Iu, having a nominal value of
356 μA for U = 10 V, whereas the primary reference is a voltage,
generated by a buried-Zener circuit and laser-trimmed to have a
very low temperature coefficient. This voltage is nominally 8 V
with a tolerance of 10%.
(±W) =
+ ± Z
(4)
In the recommended direct divider mode, the Y input is set to a
fixed voltage (typically 10 V) and U is varied directly; it can have
any value from 10 mV to 10 V. The magnitude of the ratio X/U
cannot exceed 1.25; for example, the peak X input for U = 1 V is
1.25 V. Above this level, clipping occurs at the positive and
negative extremities of the X input. Alternatively, the AD734
can be operated using the standard (AD534) divider connections
(see Figure 27), when the negative feedback path is established
via the Y2 input. Substituting W for Y2 in Equation 2,
NOMINALLY
356µA for
U = 10V
Iu
VP
14
13
AD734
LINK TO
DISABLE
+
DD
ER
U0
U1
3
4
Qu
Qd
Z2 − Z1
+Y1
Rr
100kΩ
W =U
(5)
TC
(
X1 − X2
)
9
8
Ru
28kΩ
Rd
NOM
22.5kΩ
Qr
In this case, note that the variable X is now the denominator,
U2
5
NOM
8V
and the previous restriction (X/U ≤ 1.25) on the magnitude of
the X input does not apply. However, X must be positive for the
feedback polarity to be correct. Y1 can be used for summing
purposes or connected to the load ground if not needed. The
shorthand form in this case is
VN
NEGATIVE SUPPLY
Figure 21. Denominator Control Circuitry
After temperature-correction (block TC), the reference voltage
is applied to Transistor Qd and trimmed Resistor Rd, which
generate the required reference current. Transistor Qu and
Resistor Ru are not involved in setting up the internal denomina-
tor, and their associated control pins, U0, U1, and U2, are
normally grounded. The reference voltage is also made
available, via the 100 kΩ resistor, Rr, at Pin 9 (ER).
(±Z)
(±W)=(+U)
+(±Y)
(6)
(+X)
In some cases, feedback can be connected to two of the available
inputs. This is true for the square-rooting connections (see
Figure 28), where W is connected to both X1 and Y2. Set X1 =
W and Y2 = W in Equation 2, and anticipating the possibility of
again providing a summing input, set X2 = S and Y1 = S, so that,
in shorthand form,
When the control pin, DD (denominator disable), is connected
to VP, the internal source of Iu is shut off, and the collector
current of Qu must provide the denominator current. The resistor
Ru is laser-trimmed such that the multiplier denominator is
exactly equal to the voltage across it (that is, across Pin U1 and
Pin U2). Note that this trimming only sets up the correct
internal ratio; the absolute value of Ru (nominally 28 kΩ) has a
tolerance of 20%. Also, the alpha of Qu (typically 0.995), which
may be seen as a source of scaling error, is canceled by the alpha of
other transistors in the complete circuit.
(±W) = (+U)(+Z) +(±S)
(7)
This is seen more generally to be the geometric-mean function,
because both U and Z can be variable; operation is restricted to
one quadrant. Feedback can also be taken to the U interface.
Full details of the operation in these modes is provided in the
Wideband RMS-to-DC Converter Using U Interface section.
In the simplest scheme (see Figure 22), an externally provided
control voltage, VG, is applied directly to U0 and U2 and the
resulting voltage across Ru is therefore reduced by one VBE. For
example, when VG = 2 V, the actual value of U is about 1.3 V.
Rev. E | Page 11 of 20
AD734
This error is not important in some closed-loop applications,
such as automatic gain control (AGC), but clearly is not acceptable
where the denominator value must be well-defined. When it is
required to set up an accurate, fixed value of U, the on-chip
reference can be used. The transistor Qr is provided to cancel
the VBE of Qu, and is biased by an external resistor, R2, as shown
in Figure 23. R1 is chosen to set the desired value of U and
consists of a fixed and adjustable resistor.
in Figure 31, where a fixed numerator of 10 V is generated for a
divider application. Y2 is tied to VN, but Y1 is 10 V above this;
therefore, the common-mode voltage at this interface is still 5 V
above VN, which satisfies the internal biasing requirements (see
Table 1).
OPERATION AS A MULTIPLIER
All of the connection schemes used in this section are essentially
identical to those used for the AD534, with which the AD734 is
pin compatible. The only precaution to be noted in this regard
is that in the AD534, Pin 3, Pin 5, Pin 9, and Pin 13 are not
internally connected, and Pin 4 has a slightly different purpose.
In many cases, an AD734 can be directly substituted for an
AD534 with immediate benefits in static accuracy, distortion,
feedthrough, and speed. Where Pin 4 was used in an AD534
application to achieve a reduced denominator voltage, this
function can now be much more precisely implemented with
the AD734 using alternative connections (see the Direct
Denominator Control section).
Iu
VP
DD
ER
+V
14
S
AD734
~60µA
U0
U1
+
3
4
Qu
13
9
Rr
100kΩ
V
NC
G
NC
Ru
28kΩ
U2
Qr
–
5
VN
8
–V
S
Figure 22. Low Accuracy Denominator Control
Iu
Operation from supplies down to 8 V is possible. The supply
current is essentially independent of voltage. As is true of all
high speed circuits, careful power supply decoupling is important
in maintaining stability under all conditions of use. The decoupling
capacitors should always be connected to the load ground,
because the load current circulates in these capacitors at high
frequencies. Note the use of the special symbol (a triangle with
the letter L inside it) to denote the load ground (see Figure 24).
VP
+V
14
S
AD734
U0
DD
3
Qu
13
9
Rr
100kΩ
U1
U2
R2
4
5
ER
VN
Ru
28kΩ
Qr
NC
NOM
8V
R1
8
–V
S
Standard Multiplier Connections
Figure 24 shows the basic connections for multiplication. The X
and Y inputs are shown as optionally having their negative nodes
grounded, but they are fully differential, and in many applications
the grounded inputs can be reversed (to facilitate interfacing
with signals of a particular polarity, while achieving some desired
output polarity) or both can be driven.
Figure 23. Connections for a Fixed Denominator
Table 5 shows useful values of the external components for
setting up nonstandard denominator values.
Table 5. Component Values for Setting Up Nonstandard
Denominator Values
The AD734 has an input resistance of 50 kΩ 20% at the X, Y,
and Z interfaces, which allows ac coupling to be achieved with
moderately good control of the high-pass (HP) corner frequency;
a capacitor of 0.1 μF provides a HP corner frequency of 32 Hz.
When a tighter control of this frequency is needed, or when the
HP corner is above about 100 kHz, an external resistor should
be added across the pair of input nodes.
Denominator
R1 (Fixed)
34.8 kΩ
64.9 kΩ
86.6 kΩ
174 kΩ
R1 (Variable)
R2
5 V
3 V
2 V
1 V
20 kΩ
20 kΩ
50 kΩ
100 kΩ
120 kΩ
220 kΩ
300 kΩ
620 kΩ
The denominator can also be current controlled, by grounding
Pin 3 (U0) and withdrawing a current of Iu from Pin 4 (U1).
The nominal scaling relationship is U = 28 × Iu, where u is
expressed in volts and Iu is expressed in milliamps. Note,
however, that while the linearity of this relationship is very
good, it is subject to a scale tolerance of 20%. Note that the
common-mode range on Pin 3 through Pin 5 actually extends
from 4 V to 36 V below VP; therefore, it is not necessary to
restrict the connection of U0 to ground to use some other
voltage.
+15V
AD734
X
INPUT
1
2
3
4
5
6
X1
X2
U0
U1
U2
Y1
VP 14
DD 13
±10V FS
NC
0.1µF
L
(X – X )(Y – Y )
1
2
1
2
+ Z
W
12
W =
2
10V
LOAD
Z1 11
Z2 10
GROUND
Z
2
OPTIONAL
SUMMING INPUT
±10V FS
NC
Y INPUT
±10V FS
ER
VN
9
8
L
0.1µF
7
Y2
The output ER can also be buffered, rescaled, and used as a
general-purpose reference voltage. It is generated with respect
to the negative supply line, Pin 8 (VN), but this is acceptable
when driving one of the signal interfaces. An example is shown
–15V
Figure 24. Basic Multiplier Circuit
Rev. E | Page 12 of 20
AD734
At least one of the two inputs of any pair must be provided with
a dc path (usually to ground). The careful selection of ground
returns is important in realizing the full accuracy of the AD734.
The Z2 pin is normally connected to the load ground, which can be
remote in some cases. It can also be used as an optional summing
input (see Equation 3 and Equation 4) having a nominal FS
input of 10 V and the full 10 MHz bandwidth.
The smallest FS current is simply 10 V/50 kΩ, or 200 μA,
with a tolerance of about 20%. To guarantee a 1% conversion
tolerance without adjustment, RS must be less than 2.5 kΩ. The
maximum full-scale output current should be limited to about
10 mA (thus, RS = 1 kΩ). This concept can be applied to all
connection modes, with the appropriate choice of terminals.
Squaring and Frequency-Doubling
In applications where high absolute accuracy is essential, the
scaling error caused by the finite resistance of the signal source(s)
may be troublesome; for example, a 50 Ω source resistance at
just one input introduces a gain error of −0.1%; if both the X
and Y inputs are driven from 50 Ω sources, the scaling error in
the product is −0.2%. If the source resistances are known, this
gain error can be completely compensated by including the
appropriate resistance (50 Ω or 100 Ω, respectively, in the
preceding cases) between the output, W (Pin 12), and the Z1
feedback input (Pin 11). If Rx is the total source resistance
associated with the X1 and X2 inputs, and Ry is the total source
resistance associated with the Y1 and Y2 inputs, and neither Rx
nor Ry exceeds 1 kΩ, a resistance of Rx + Ry in series with
Pin Z1 provides the required gain restoration.
Squaring of an input signal, E, is achieved by connecting the X
and Y inputs in parallel; the phasing can be chosen to produce
an output of E2/U or −E2/U as desired. The input can have
either polarity, but the basic output is either always positive or
negative; as for multiplication, the Z2 input can be used to add a
further signal to the output.
When the input is a sine wave, a squarer behaves as a frequency
doubler, because
(Esinwt)2 = E2 (1 − cos2wt)/2
(8)
Equation 8 shows a dc term at the output, which varies strongly
with the amplitude of the input, E. This dc term can be avoided
using the connection shown in Figure 26, where an RC network
is used to generate two signals whose product has no dc term.
The output is
Pin 9 (ER) and Pin 13 (DD) should be left unconnected in this
application. The U inputs (Pin 3, Pin 4, and Pin 5) are shown
connected to ground; they can alternatively be connected to
VN, if desired. In applications where Pin 2 (X2) happens to
be driven with a high amplitude, high frequency signal, the
capacitive coupling to the denominator control circuitry via
an ungrounded Pin 3 can cause high frequency distortion.
However, the AD734 can be operated without modification in
an AD534 socket and these three pins left unconnected with the
preceding caution noted.
⎛
⎞
⎟
⎟
⎠
⎧ E
π ⎫⎧ E
π ⎫
1
10 V
⎛
⎝
⎞
⎛
⎝
⎞
⎜
W = 4
sin wt +
sin wt −
(9)
⎨
⎜
⎟⎬⎨
⎜
⎟⎬
⎜
4
⎠
⎭
4
⎠
2
2
⎩
⎭⎩
⎝
for w = 1/CR1, which is just
W = E2(cos2wt)/(10 V)
(10)
which has no dc component. To restore the output to 10 V
when E = 10 V, a feedback attenuator with an approximate ratio
of 4 is used between W and Z1; this technique can be used
wherever it is desired to achieve a higher overall gain in the
transfer function.
+15V
AD734
0.1µF
1
2
3
4
5
6
X1
X2
U0
U1
U2
Y1
VP 14
X INPUT
±10V FS
L
The values of R3 and R4 include additional compensation for the
effects of the 50 kΩ input resistance of all three interfaces; R2 is
included for a similar reason. These resistor values should not
be altered without careful calculation of the consequences. With
the values shown, the center frequency f0 is 100 kHz for C =
1 nF. The amplitude of the output is only a weak function of
frequency; the output amplitude is 0.5% too low at f = 0.9f0 and
f = 1.1f0. The cross-connection is simply to produce the cosine
output with the sign shown in Equation 10; however, the sign in
this case is rarely important.
DD 13
NC
1
(X – X )(Y – Y )
1
1
2
1
2
I
=
+
W
W
12
R
10V
50kΩ
S
R
Z1 11
Z2 10
S
NC
ER
VN
9
8
Y INPUT
±10V FS
I
W
±10mA MAX FS
0.1µF
7
Y2
±10V MAXIMUM
LOAD VOLTAGE
L
L
–15V
Figure 25. Conversion of Output to a Current
Current Output
It may occasionally be desirable to convert the output voltage to
a current. In correlation applications, for example, multiplication is
followed by integration; if the output is in the form of a current,
a simple grounded capacitor can perform this function. Figure 25
shows how this can be achieved. The op amp forces the voltage
across Z1 and Z2, and thus across the resistor, RS, to be the
product XY/U. Note that the input resistance of the Z interface
is in shunt with RS, which must be calculated accordingly.
Rev. E | Page 13 of 20
AD734
+15V
NC
+15V
NC
R2
1.6kΩ
AD734
0.1µF
AD734
0.1µF
D
1
2
3
4
5
6
X1
X2
U0
U1
U2
Y1
VP 14
DD 13
12
1
2
3
4
5
6
X1
X2
U0
U1
U2
Y1
VP 14
DD 13
12
Z1 11
R1
1.6kΩ
L
L
W = (10V) (Z – Z ) + S
2
1
R3
13kΩ
W
W
–
+
2
Esinωt
E cos2ωt/10V
Z1 11
Z2 10
S
OPTIONAL
SUMMING
INPUT
Z INPUT
+10mV TO
+10V
R4
4.32kΩ
Z2
ER
VN
10
9
L
NC
NC
ER
VN
9
8
±10V FS
0.1µF
C
0.1µF
L
7
Y2
7
Y2
8
L
L
–15V
–15V
Figure 28. Connection for Square Rooting
Figure 26. Frequency Doubler
Connections for Square-Rooting
OPERATION AS A DIVIDER
The AD734 can be used to generate an output proportional to
the square root of an input using the connections shown in
Figure 28. Feedback is now via both the X and Y inputs, and is
always negative because of the reversed polarity between these
two inputs. The Z input must have the polarity shown, but
because it is applied to a differential port, either polarity of
input can be accepted with reversal of Z1 and Z2, if necessary.
The diode, D, which can be any small-signal type (1N4148
being suitable), is included to prevent a latching condition,
which can occur if the input is momentarily of the incorrect
polarity of the input. The output is always negative.
The AD734 supports two methods for performing analog
division. The first is based on the use of a multiplier in a
feedback loop. This is the standard mode recommended for
multipliers having a fixed scaling voltage, such as the AD534,
and is described in this section. The second uses the AD734’s
unique capability for externally varying the scaling (denominator)
voltage directly, and is described in the Division by Direct
Denominator Control section.
Feedback Divider Connections
Figure 27 shows the connections for the standard (AD534)
divider mode. Feedback from the output, W, is now taken to the
Y2 (inverting) input, which, if the X input is positive, establishes a
negative feedback path. Y1 should normally be connected to the
ground associated with the load circuit, but can optionally be
used to sum a further signal to the output. If desired, the
polarity of the Y input connections can be reversed, with W
connected to Y1 and Y2 used as the optional summation input. In
this case, either the polarity of the X input connections must be
reversed or the X input voltage must be negative.
Note that the loading on the output side of the diode is provided
by the 25 kΩ of input resistance at X1 and Y2, and by the user’s
load. In high speed applications, it may be beneficial to include
further loading at the output (to 1 kΩ minimum) to speed up
response time. As in previous applications, a further signal, shown
in Figure 28 as S, can be summed to the output; if this option is
not used, this node should be connected to the load ground.
DIVISION BY DIRECT DENOMINATOR CONTROL
+15V
The AD734 can be used as an analog divider by directly varying
the denominator voltage. In addition to providing much higher
accuracy and bandwidth, this mode also provides greater
flexibility, because all inputs remain available. Figure 29 shows
the connections for the general case of a three-input multiplier
divider, providing the function
AD734
0.1µF
X INPUT
+0.1V TO
+10V
1
2
3
4
5
6
X1
X2
U0
U1
U2
Y1
VP 14
L
DD 13
NC
(Z – Z )
2
1
W = 10
+Y1
W
12
(X – X )
1
2
Z1 11
Z2 10
Z INPUT
±10V FS
(X1 − X2 )(Y1 −Y2 )
Y
1
NC
0.1µF
ER
VN
9
8
W =
+ Z2
(11)
OPTIONAL
SUMMING
INPUT
(U1 −U2 )
7
Y2
L
L
±10V FS
where the X, Y, and Z signals can all be positive or negative,
–15V
but the difference U = U1 − U2 must be positive and in the range
10 mV to 10 V. If a negative denominator voltage must be used,
simply ground the noninverting input of the op amp. As previ-
ously noted, the X input must have a magnitude of less than 1.25U.
Figure 27. Standard (AD534) Divider Connection
The numerator input, which is differential and can have either
polarity, is applied to Pin Z1 and Pin Z2. As with all dividers
based on feedback, the bandwidth is directly proportional to
the denominator, being 10 MHz for X = 10 V and reducing to
100 kHz for X = 100 mV. This reduction in bandwidth, and
the increase in output noise (which is inversely proportional
to the denominator voltage) preclude operation much below a
denominator of 100 mV. Division using direct control of the
denominator (see Figure 29) does not have these shortcomings.
Rev. E | Page 14 of 20
AD734
+15V
The transfer function is
AD734
1
2
3
4
5
6
X1
VP 14
X INPUT
U
⎛
⎜
⎞
⎟
X1 − X2
U1 −U2
(X – X )(Y – Y )
1
2
1
2
X2
U0
U1
U2
Y1
DD 13
0.1µF
+ Z
W =10V
+ Z2
(12)
W =
2
U
– U
⎜
⎝
⎟
⎠
1
2
1
W
12
LOAD
2MΩ
U INPUT
Z1 11
Z2 10
L
GROUND
The ac performance of this circuit remains as shown in Figure 30.
U
2
+15V
Z
2
NC
ER
VN
9
8
AD734
OPTIONAL
SUMMING
INPUT
0.1µF
L
Y INPUT
1
2
3
4
5
6
X1
X2
U0
U1
U2
Y1
VP 14
7
Y2
X INPUT
U
(X – X )10V
1
2
DD 13
0.1µF
±10V FS
+ Z
W =
2
–15V
U
– U
1
2
1
W
12
Figure 29. Three-Variable Multiplier/Divider Using Direct Denominator
Control
LOAD
U INPUT
2MΩ
Z1 11
Z2 10
L
GROUND
U
2
This connection scheme can also be viewed as a variable-gain
Z
2
ER
VN
9
8
OPTIONAL
SUMMING
INPUT
0.1µF
element, whose output, in response to a signal at the X input, is
controllable by both the Y input (for attenuation, using Y less
than U) and the U input (for amplification, using U less than
Y). The ac performance is shown in Figure 30; for these results,
Y was maintained at a constant 10 V. At U = 10 V, the gain is
unity and the circuit bandwidth is a full 10 MHz. At U = 1 V,
the gain is 20 dB and the bandwidth is essentially unaltered. At
U = 100 mV, the gain is 40 dB and the bandwidth is 2 MHz.
Finally, at U = 10 mV, the gain is 60 dB and the bandwidth is
250 kHz, corresponding to a 250 MHz gain-bandwidth product.
70
L
7
Y2
100kΩ
SCALE
AJDUST
±10V FS
200kΩ
–15V
OP AMP = AD712 DUAL
Figure 31. Two-Quadrant Divider with Fixed 10 V Scaling
A PRECISION AGC LOOP
The variable denominator of the AD734 and its high gain
bandwidth product make it an excellent choice for precise
automatic gain control (AGC) applications. Figure 32 shows a
suggested method. The input signal, EIN, which can have a peak
amplitude from 10 mV to 10 V at any frequency from 100 Hz to
10 MHz, is applied to the X input and a fixed positive voltage EC
to the Y input. Op Amp A2 and Capacitor C2 form an integrator
with a current summing node at its inverting input. (The AD712
dual op amp is a suitable choice for this application.) In the absence
of an input, the current in D2 and R2 causes the integrator output
to ramp negative, clamped by Diode D3, which is included to
reduce the time required for the loop to establish a stable,
calibrated, output level after the circuit has received an input
signal. With no input to the denominator (U0 and U2), the gain
of the AD734 is very high (about 70 dB), and thus even a small
input causes a substantial output.
U = 10mV
60
50
U = 100mV
40
30
U = 1
V
20
10
0
U = 10V
10k
100k
FREQUENCY (Hz)
1M
10M
R3
1MΩ
Figure 30. Three-Variable Multiplier/Divider Performance
C1
A1
+15V
1µF
The 2 MΩ resistor is included to improve the accuracy of the
gain for small denominator voltages. At high gains, the X input
offset voltage can cause a significant output offset voltage. To
eliminate this problem, a low-pass feedback path can be used
from W to X2; see Figure 32 for details.
AD734
1
2
3
4
5
6
X1
X2
U0
U1
U2
Y1
VP 14
E
IN
D1
1N914
DD 13
0.1µF
W
12
E
OUT
D3
C2
1µF
C1
1µF
Z1 11
Z2 10
NC
L
A2
1N914
Where a numerator of 10 V is needed, to implement a two-
quadrant divider with fixed scaling, the connections shown in
Figure 31 can be used. The reference voltage output appearing
between Pin 9 (ER) and Pin 8 (VN) is amplified and buffered by
the second op amp, to impose 10 V across the Y1/Y2 input.
Note that Y2 is connected to the negative supply in this application.
This is permissible because the common-mode voltage is still
high enough to meet the internal requirements.
L
ER
VN
9
8
0.1µF
E
C
+1V TO
+10V
D2
1N914
7
Y2
–15V
R2
1MΩ
R1
1MΩ
OP AMP = AD712 DUAL
Figure 32. Precision AGC Loop
Diode D1 and C1 form a peak detector, which rectifies the output
and causes the integrator to ramp positive. When the current in
R1 balances the current in R2, the integrator output holds the
denominator output at a constant value. This occurs when there
Rev. E | Page 15 of 20
AD734
+15V
is sufficient gain to raise the amplitude of EIN to that required to
establish an output amplitude of EC over the range of 1 V to 10 V.
The X input of the AD734, which has finite offset voltage, can be
troublesome at the output at high gains. The output offset is
reduced to that of the X input (1 mV or 2 mV) by the offset
loop comprising R3, C3, and Buffer A1. The low-pass corner
frequency of 0.16 Hz is transformed to a high-pass corner that is
multiplied by the gain (for example, 160 Hz at a gain of 1000).
AD734
0.1µF
L
V
1
2
3
4
5
6
X1
X2
U0
U1
U2
Y1
VP 14
DD 13
12
IN
1/2
AD708
U2b
R1
3.32kΩ
L
W
1/2
AD708
U2a
C1
47µF
C2
1µF
Z1 11
Z2 10
L
L
L
L
ER
VN
9
8
2
V
V
=
O
IN
0.1µF
7
Y2
In applications not requiring operation down to low frequencies,
Amplifier A1 can be eliminated, but the AD734’s input resistance
of 50 kΩ between X1 and X2 reduces the time constant and
increases the input offset. Using a nonpolar 20 mF tantalum
capacitor for C1 results in the same unity-gain high-pass corner; in
this case, the offset gain increases to 20, which is still acceptable.
L
–15V
Figure 34. A Two-Chip, Wideband RMS-to-DC Converter
In this application, the AD734 and an AD708 dual op amp
serve as a two-chip rms-to-dc converter with a 10 MHz
bandwidth. Figure 35 shows the circuit’s performance for
Figure 33 shows the error in the output for sinusoidal inputs at
100 Hz, 100 kHz, and 1 MHz, with EC set to 10 V. The output
error for any frequency between 300 Hz and 300 kHz is similar
to that for 100 kHz. At low signal frequencies and low input
amplitudes, the dynamics of the control loop determine the gain
error and distortion; at high frequencies, the 200 MHz gain-
bandwidth product of the AD734 limits the available gain.
square-, sine-, and triangle-wave inputs. The circuit accepts
signals as high as 10 V p-p with a crest factor of 1 or 1 V p-p
with a crest factor of 10. The circuit’s response is flat to 10 MHz
with an input of 10 V, flat to almost 5 MHz for an input of 1 V,
and to almost 1 MHz for inputs of 100 mV. For accurate
measurements of input levels below 100 mV, the AD734’s
output offset (Z interface) voltage, which contributes a dc error,
must be trimmed out.
The output amplitude tracks EC over the range of 1 V to slightly
more than 10 V.
In the circuit shown in Figure 34, the AD734 squares the input
signal, and its output (VIN2) is averaged by a low-pass filter that
consists of R1 and C1 and has a corner frequency of 1 Hz. Because
of the implicit feedback loop, this value is both the output value,
2
1
100kHz
V
RMS, and the denominator in Equation 13. U2a and U2b, an
AD708 dual dc precision op amp, serve as unity-gain buffers,
supplying both the output voltage and driving the U interface.
0
100
10
1
–1
100Hz
1MHz
–2
0.01
0.1
1
10
100m
10m
INPUT AMPLITUDE (V)
Figure 33. AGC Amplifier Output Error vs. Input Voltage
WIDEBAND RMS-TO-DC CONVERTER USING U
INTERFACE
SQUARE WAVE
SINE WAVE
TRI-WAVE
1m
The AD734 is well-suited to such applications as implicit rms-
to-dc conversion, where the AD734 implements the function
100µ
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
2
avg
[
VIN
VRMS
using its direct divide mode. Figure 34 shows the circuit.
]
Figure 35. RMS-to-DC Converter Performance
VRMS
=
(13)
Rev. E | Page 16 of 20
AD734
The possible two-tone intermodulation products are at 2 ×
LOW DISTORTION MIXER
9.95 MHz − 10.05 MHz 9.00 MHz and 2 × 10.05 − 9.95 MHz
9.00 MHz; of these, only the third-order products at 0.850 MHz
and 1.150 MHz are within the 10 MHz bandwidth of the AD734;
the desired output signals are at 0.950 MHz and 1.050 MHz.
Note that the difference between the desired outputs and third-
order products (see Figure 37) is approximately 78 dB, which
corresponds to a computed third-order intercept point of +46 dBm.
The AD734’s low noise and distortion make it especially suitable
for use as a mixer, modulator, or demodulator. Although the
AD734’s −3 dB bandwidth is typically 10 MHz and is established
by the output amplifier, the bandwidth of its X and Y interfaces
and the multiplier core are typically in excess of 40 MHz. Thus,
provided that the desired output signal is less than 10 MHz, as
is typically the case in demodulation, the AD734 can be used
with both its X and Y input signals as high as 40 MHz. One test
of mixer performance is to linearly combine two closely spaced,
equal-amplitude sinusoidal signals and then mix them with a
third signal to determine the mixer’s two-tone, third-order
intermodulation products.
REF – 10.0dBm
10dB/DIV
MARKER 950 000.0Hz
– 15.8dBm
RANGE – 5.0dBm
+15V
HP3326A
COMBINE
A + B
AD734
0.1µF
1
2
3
4
5
6
X1
X2
U0
U1
U2
Y1
VP 14
DD 13
12
OP177
HP3585A
WITH 10X PROBE
dBm REF TO 50Ω
DATEL
DVC-8500
W
2kΩ
Z1 11
Z2 10
HP3326A
HIGH VOLTAGE
OPTION
ER
VN
9
8
0.1µF
CENTER 990 000.0Hz
RBW 1kHz
SPAN 500 000.0Hz
ST 47.0sec
7
Y2
VBW 30Hz
–15V
Figure 37. AD734 Third-Order Intermodulation Performance for f1 =
9.95 MHz, f2 = 10.05 MHz, and f0 = 9.00 MHz and for Signal Levels of f1 = f2 =
6 dBm and f0 = +24 dBm (All Displayed Signal Levels Are Attenuated 20 dB by
the 10X Probe Used to Measure the Mixer’s Output)
Figure 36. AD734 Mixer Test Circuit
Figure 36 shows a test circuit for measuring the AD734’s
performance in this regard. In this test, two signals, at 10.05 MHz
and 9.95 MHz, are summed and applied to the AD734 X
interface. A second 9 MHz signal is applied to the AD734 Y
interface. The voltage at the U interface is set to 2 V to use the
full dynamic range of the AD734; that is, by connecting the W
and Z1 pins together, grounding the Y2 and X2 pins, and setting
U = 2 V, the overall transfer function is
REF – 10.0dBm
10dB/DIV
MARKER 950 000.0Hz
– 21.8dBm
RANGE – 10.0dBm
X1Y1
2V
(14)
W =
and W can be as high as 20 V p-p when X1 = 2 V p-p and Y1 =
10 V p-p. The 2 V p-p signal level corresponds to 10 dBm into a
50 Ω input termination resistor connected from X1 or Y1 to
ground.
CENTER 990 000.0Hz
RBW 1kHz
SPAN 500 000.0Hz
ST 156sec
VBW 10Hz
If the two X1 inputs are at Frequency f1 and Frequency f2 and the
frequency at the Y1 input is f0, then the two-tone third-order
intermodulation products should appear at Frequency 2f1 – f2
f0 and Frequency 2f2 – f1 f0. Figure 37 and Figure 38 show the
output spectra of the AD734 with f1 = 9.95 MHz, f2 = 10.05 MHz,
and f0 = 9.00 MHz for a signal level of f1 = f2 = 6 dBm and f0 =
+24 dBm in Figure 37 and f1 = f2 = 0 dBm and f0 = +24 dBm in
Figure 38. This performance is without external trimming of
the AD734 X and Y input offset voltages.
Figure 38. AD734 Third-Order Intermodulation Performance for f1 =
9.95 MHz, f2 = 10.05 MHz, and f0 = 9.00 MHz and for Signal Levels of f1 = f2 =
0 dBm and f0 = +24 dBm (All Displayed Signal Levels Are Attenuated 20 dB by
the 10X Probe Used to Measure the Mixer’s Output)
Rev. E | Page 17 of 20
AD734
OUTLINE DIMENSIONS
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
1
8
7
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 39. 14-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-14)
Dimensions shown in inches and (millimeters)
0.098 (2.49) MAX
8
0.005 (0.13) MIN
14
0.310 (7.87)
0.220 (5.59)
1
7
PIN 1
0.100 (2.54) BSC
0.785 (19.94) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15°
0°
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 40. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions shown in inches and (millimeters)
Rev. E | Page 18 of 20
AD734
ORDERING GUIDE
Model1
AD734AN
AD734ANZ
AD734BN
AD734BNZ
AD734AQ
AD734BQ
AD734SQ/883B
AD734SCHIPS
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−55°C to +125°C
Package Description
Package Option
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Ceramic Dual In-Line Package [CERDIP]
14-Lead Ceramic Dual In-Line Package [CERDIP]
14-Lead Ceramic Dual In-Line Package [CERDIP]
Die
N-14
N-14
N-14
N-14
Q-14
Q-14
Q-14
1 Z = RoHS Compliant Part.
Rev. E | Page 19 of 20
AD734
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00827-0-2/11(E)
Rev. E | Page 20 of 20
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