AD73560BB-80_技术文档

Six-InputChannel

AnalogFrontEnd

a

PreliminaryTechnicalData

AD73560

FEATURES

F UNC T IO NAL BLO C K D IAG RAM

AFE PERFORMANCE

Six 16-Bit A/ D Converters

Program m able Input Sam ple Rate

Sim ultaneous Sam pling

76 dB SNR

64 kS/ s Maxim um Sam ple Rate

–83 dB Crosstalk

Low Group Delay (25 m s Typ per ADC Channel)

Program m able Input Gain

Single Supply Operation

On-Chip Reference

POWER-DOWN

CONTROL

MEMORY

DATA ADDRESS

GENERATORS

PROGRAMMABLE

I/O

AND

PROGRAM

SEQUENCER

16K PM

(OPTIONAL 8K)

16K DM

(OPTIONAL 8K)

FULL MEMORY

MODE

DAG

2

DAG

1

FLAGS

EXTERNAL

ADDRESS

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

EXTERNAL

DATA

BUS

PROGRAM MEMORY DATA

DATA MEMORY DATA

BYTE DMA

CONTROLLER

FLASH

Byte Memory

64 kbytes

SERIAL PORTS

ARITHMETIC UNITS

TIMER

ALU

SHIFTER

MAC

SPORT

0

SPORT 1

ADSP-2100 BASE

ARCHITECTURE

DSP PERFORMANCE

SERIAL PORT

19ns Instruction Cycle Tim e @3.3 V, 52 MIPS

Sustained Perform ance

REF

SPO RT

2

Single-Cycle Instruction Execution

Single-Cycle Context Sw itch

ADC1

AD C2

ADC3

ADC4

AD C5

AD C6

3-Bus Architecture Allow s Dual Operand Fetches in

Every Instruction Cycle

ANALO G FRO NT END

SECTION

Multifunction Instructions

Pow er-Dow n Mode Featuring Low CMOS Standby

Pow er Dissipation w ith 400 Cycle Recovery from

Pow er-Dow n Condition

An on-chip reference voltage of 2.5V is included. T he

sampling rate of the device is programmable with four

separate settings offering 64 kHz, 32 kHz, 16 kHz and 8

kHz sampling rates (from a master clock of 16.384 MHz)

while the serial port (SPORT 2) allows easy expansion of

the number of input channels by cascading extra AFE

external to the AD73560.

Low Pow er Dissipation in Idle Mode

FLASH MEMORY

64Kbytes

T he AD73560’s DSP engine combines the ADSP-2100

family base architecture (three computational units, data

address generators and a program sequencer) with two

serial ports, a 16-bit internal DMA port, a byte DMA

port, a programmable timer, Flag I/O, extensive interrupt

capabilities and on-chip program and data memory.

T he AD73560-80 integrates 80K bytes of on-chip memory

configured as 16K words (24-bit) of program RAM and

16 K (16-bit) of data RAM. T he AD73560-40 integrates

40K bytes of on-chip memory configured as 8K words

(24-bit) of program RAM and 8K (16-bit) of data RAM.

Power-down circuitry is also provided to meet the low

power needs of battery operated portable equipment. T he

AD73560 is available in a 119-ball PBGA package.

Writable in pages of 128 bytes

Fast Page Write Cycle of 5m s (typical)

G E NE R AL D E S C R IP T IO N

T he AD73560 is a six-input channel analog front-end

processor for general purpose applications including in-

dustrial power metering or multichannel analog inputs. It

features six 16-bit A/D conversion channels each of which

provide 76 dB signal-to-noise ratio over a DC to 4KHz

signal bandwidth. Each channel also features a program-

mable input gain amplifier (PGA) with gain settings in

eight stages from 0 dB to 38 dB.

T he AD73560 is particularly suitable for industrial power

metering as each channel samples synchronously, ensuring

that there is no (phase) delay between the conversions.

T he AD73560 also features low group delay conversions

on all channels.

REV. PrA

8/99

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(AVDD = +3V ± 10%; DVDD = +3V ± 10%; DGND = AGND = 0 V, f_MCLK= 16.384 MHz,

AD73560–SPECIFICATIONS f_SCLK= 8.192 MHz, f_S= 8 kHz; T = T_MINto T , unless otherwise noted.)

A

MAX

AD 73560A

Typ

P ar am eter

Min

M a x

Units

Test Conditions/Com m ents

RE F E RE N C E

REFCAP

Absolute Voltage, V_REFCAP

REFCAP T C

1.125

1.25

50

1.375

V

ppm/°C

0.1 µF Capacitor Required from REFCAP

to AGND2

REFOUT

T ypical Output Impedance

Absolute Voltage, V_REFOUT

M inimum Load Resistance

Maximum Load Capacitance

130

1.25

⍀

V

k ⍀

pF

1.125

1

1.375

100

U nloaded

ADC SPECIFICAT IONS

Maximum Input Range at VIN^{2, 3}

1.578

–2.85

V p-p

dBm

V p-p

dBm

5VEN = 0, Measured Differentially

Nominal Reference Level at VIN

(0 dBm0)

1.0954

–6.02

Absolute Gain

PGA = 0 dB

PGA = 38 dB

Gain T racking Error

Signal to (Noise + Distortion)

PGA = 0 dB

–0.8

+0.8

dB

1.0 kHz

±0.1

1.0 kHz, +3 dBm0 to –50 dBm0

73

77

62

dB

0 Hz to f_S/2; f_S= 8 kHz

0 Hz to 4 kHz; f_S= 64 kHz

PGA = 38 dB

T otal Harmonic Distortion

PGA = 0 dB

PGA = 38 dB

Intermodulation Distortion

Idle Channel Noise

Crosstalk ADC-to-ADC

–83

–70

–76

–70

–83

–76

dB

PGA = 0 dB

ADC1 Input Signal Level: 1.0 kHz

ADC2 Input at Idle

DC Offset

Power Supply Rejection

–30

+10

–55

+45

mV

dB

PGA = 0 dB

Input Signal Level at AVDD and DVDD

Pins 1.0 kHz, 100 mV p-p Sine Wave

64 kHz Output Sample Rate

32 kHz Output Sample Rate

16 kHz Output Sample Rate

8 kHz Output Sample Rate

D MCLK = 16.384 MH z

Group Delay^{4, 5}

25

50

95

190

25

µs

Input Resistance at VIN^2,

k⍀⁶

4

F REQ U EN C Y RESP O N SE

(ADC)⁷T ypical Output

Frequency (Normalized to f_S)

0

dB

d B

0.03125

0.0625

0.125

0.1875

0.25

0.3125

0.375

0.4375

> 0.5

–0.1

–0.25

–0.6

–1.4

–2.8

–4.5

–7.0

–9.5

< –12.5

d B

–2 –

REV. PrA

AD73560

AD73560A

Typ

P ar am eter

Min

M a x

Units

Test Conditions/Com m ents

LO G IC IN PU T S

V_INH, Input High Voltage

V_DD– 0.8

0

V_DD

0.8

10

V

µA

pF

V_INL, Input Low Voltage

I

_IH, Input Current

C_IN, Input Capacitance

10

LOGIC OUT PUT

V_OH, Output High Voltage

V_OL, Output Low Voltage

T hree-State Leakage Current

V_DD– 0.4

0

–10

V_DD

0.4

+10

V

µA

| IOUT | - 100 µA

POWER SUPPLIES

AVDD1, AVDD2

DVDD

2.7

3.3

V

8

I_DD

See T able I

NOT ES

¹Operating temperature range is as follows: –40°C to +85°C. T herefore, T _MIN= –40°C and T _MAX= +85°C.

²T est conditions: Input PGA set for 0 dB gain (unless otherwise noted).

³At input to sigma-delta modulator of ADC.

⁴Guaranteed bydesign.

⁵Overall group delay will be affected by the sample rate and the external digital filtering.

⁶T he ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 X 10¹¹)/DMCLK.

⁷Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier bypassed

and input gain of 0 dB.

⁸T est Conditions: no load on digital inputs, analog inputs ac coupled to ground.

Specifications subject to change without notice.

Table I. AFE Section Cur r ent Sum m ar y (AVD D = D VD D = +3.3 V)

Total

Analog

Current

D igital Current

Current (Max) SE

MCLK

ON

Conditions

Com m ents

ADCs Only On

REFCAP Only On

REFC AP and

12

0.75

10

0.04

26.5

1.0

1

0

YE S

N O

REF OU T D isabled

REFOU T Only On

All Sections Off

3.3

0.01

0.04

1.2

4.5

1.5

0

N O

YE S

MCLK Active Levels Equal to 0 V

and D VD D

All Sections Off

0.01

0.03

0.1

0

N O

Digital Inputs Static and Equal to

0V or DVDD

T he above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.

REV. PrA

–3 –

(AVDD = DVDD = +3.0V to 3.6V; DGND = AGND = 0 V, f_MCLK= 16.384 MHz,

f_SAMP= 64 kHz; T = T_MINto T , unless otherwise noted)

AD73560–SPECIFICATIONS

A

MAX

P ARAMETER

Test Conditions

Min

Typ

M a x

Unit

D SP SECTIO N

V_IH

V_IL

V_OH

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

I_OH= –0.5 mA

@ V_DD= min

I_OH= –100 µA⁶

@ V_DD= min

I_OL= 2 mA

@ V_DD= max

V_IN= V_DDmax

@ V_DD= max

V_IN= 0 V

2.0

2.2

V

0.8

2.4

V

V_DD–0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

0.4

10

V

µA

I_IL

Lo-Level Input Current³

T hree-State Leakage Current⁷

Supply Current (Idle)⁹

I_OZH

I_OZL

I_DD

@ V_DD= max

V_IN= V_DDmax⁸

@ V_DD= max

V_IN= 0 V⁸

@ V_DD= 3.3

t_CK= 19 ns¹⁰

t_CK= 25 ns¹⁰

t_CK= 30 ns¹⁰

@ V_DD= 3.3

T _AMB= +25°C

t_CK= 19 ns¹⁰

t_CK= 25 ns¹⁰

t_CK= 30 ns¹⁰

@ V_IN= 2.5 V

f_IN= 1.0 MHz

T _AMB= +25°C

@ V_IN= 2.5 V

f_IN= 1.0 MHz

T _AMB= +25°C

10

8

7

mA

I_DD

Supply Current (Dynamic)¹¹

51

41

34

mA

C_I

Input Pin Capacitance^{3, 6, 12}

8

pF

C_O

Output Pin Capacitance^{6, 7, 12, 13}

NOTES

¹Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, T FS0, T FS1, A1–A13, PF0–PF7.

²Input only pins: RESET , BR, DR0, DR1, PWD .

³Input only pins: CLKIN, RESET , BR, DR0, DR1, PWD.

⁴Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT 0, DT 1, CLKOUT , FL2–0, BGH.

⁵Although specified for T T L outputs, all AD73560 outputs are CMOS-compatible and will drive to V_DDand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷T hree-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT 0, DT 1, SCLK0, SCLK1, T FS0, T FS1, RFS0, RFS1, PF0–PF7.

⁸0 V on BR.

⁹Idle refers to AD73560 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V_DDor GND.

10

V

I

= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and

IN

11

DD

type 6, and 20% are idle instructions.

¹²Applies to PBGA package type.

¹³Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

–4 –

REV. PrA

Preliminary Technical Data

AD73560

(AVDD = +3 V ؎ 10%; DVDD = +3 V ؎ 10%; AGND = DGND = 0V;

1

TIMINGCHARACTERISTICS-AFE SECTION

T = T to T , unless otherwise noted)

A

MlN

MAX

Lim it at

P ar am eter

T_A= –40؇C to +85؇C

Units

Description

C lock Signals

See Figure 1

t₁

t₂

t₃

61

24.4

ns min

AMCLK Period

AMCLK Width High

AMCLK Width Low

Serial Port

See Figures 3 and 4

t₄

t₅

t₆

t₇

t₈

t₉

t₁₀

t₁₁

t₁₂

t₁₃

t₁

ns min

ns max

ns min

ns max

SCLK Period (SCLK=AMCLK)

SCLK Width H igh

SCLK Width Low

SDI/SDIFS Setup Before SCLK Low

SDI/SDIFS Hold After SCLK Low

SDOFS Delay from SCLK High

SDOFS Hold After SCLK High

SDO Hold After SCLK High

SDO Delay from SCLK High

SCLK Delay from AMCLK

0.4 x t₁

20

0

10

30

NOT ES

¹For details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition.

Specifications subject to change without notice.

AB SO LUT E M AXIM UM RAT ING S*

(T_A= +25°C unless otherwise noted)

Reflow Soldering

AVD D , D VD D to GN D . . . . . . . . . . . –0.3 V to +4.6 V

AGN D to D GN D . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

D igital I/O Voltage to D GN D. –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND –0.3 V to AVDD + 0.3 V

Operating T emperature Range

Industrial (B Version) . . . . . . . . . . . . . –20°C to +85°C

Storage T emperature Range . . . . . . . . –40°C to +125°C

M aximum Junction T emperature . . . . . . . . . . . . +150°C

PBGA, q_JAT hermal Impedance . . . . . . . . . . . . . . 25°C/W

M aximum T emperature . . . . . . . . . . . . . . . . . . +225°C

T ime at M aximum T emperature . . . . . . . . . . . . 15 sec

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. T his is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods mayaffect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD73560 features proprietary ESD protection circuitry, permanent damage

may occur on devices subjected to high energy electrostatic discharges. T herefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functional-

ity.

WARNING!

ESD SENSITIVE DEVICE

O R D E R ING G U ID E

Tem perature

Range

P ackage

Description

P ackage

Options

Model

AD 73560BB-80

AD 73560BB-40

–20°C to +85°C

119-Ball Plastic Grid Array

B-119

REV. PrA

–5 –

AD73560

1 2 3 4 5 6 7

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

T

M

N

P

R

T

U

1 2 3 4 5 6 7

PBGABallConfigurations

P BG A

Ball

P BG A

Ball

P BG A

Ball

P BG A

Ball

Number

Name

Number

Name

Number

Name

Number

Name

A1

A2

A3

A4

A5

A6

A7

B1

B2

B3

B4

B5

B6

B7

C 1

C 2

C 3

C 4

C 5

C 6

C 7

D 1

D 2

D 3

D 4

D 5

D 6

D 7

E1

E2

IRQE/PF4

DMS

E3

E4

E5

E6

E7

F 1

F 2

F 3

F 4

F 5

F 6

F 7

G 1

G 2

G 3

G 4

G 5

G 6

G 7

H 1

H 2

H 3

H 4

H 5

H 6

H 7

J1

RFS0

J5

J6

J7

D22

D21

D20

ELOUT

ELIN

EINT

D 19

D 18

D 17

D 16

BG

D 3/IACK

D 5/IAL

D 8

D 9

D 12

D 15

EBG

N 7

P1

P2

P3

P4

P 5

P6

P7

R1

R2

R3

R4

R5

R6

R7

T 1

T 2

T 3

T 4

T 5

T 6

D 13

EBR

A3/IAD2

A2/IAD 1

A1/IAD 0

A0

D R 0

SC LK0

D T 1

PWDACK

BGH

PF0[MODE A]

PF1[MODE B]

T FS1

RFS1

D R1

G N D

PWD

VD D (EXT )

PF2[MODE C]

SCLK1

ERESET

RESET

PF3

VD D (IN T )

CLKIN

A11/IAD10

A7/IAD6

A4/IAD3

IRQL0/PF5

PMS

D0/IAD13

DVDD

D G N D

ARESET

SC LK2

M C LK

SD O

SD OFS

SD IFS

SD I

K1

K2

K 3

K4

K5

K6

K7

L1

L2

L3

L4

L5

L6

L7

M 1

M 2

M 3

M 4

M 5

M 6

M 7

N 1

N 2

N 3

N 4

N 5

N 6

WR

XT AL

A12/IAD11

A8/IAD7

A5/IAD 4

IRQL1/PF6

IOMS

SE

REFCAP

REFOU T

VIN N 2

VIN P2

VIN N 1

VIN P1

VIN N 3

VIN P3

VIN N 4

AG N D

AVD D

VIN P6

VIN N 6

VIN P5

VINN5

VIN P4

RD

VD D (EXT )

A13/IAD12

A9/IAD 8

G N D

IRQ2/PF7

CMS

BMS

C LKOU T

G N D

D 2/IAD 15

D 4/IS

D 7/IWR

VD D (EXT ) T 7

D 11

U 1

U 2

U 3

U 4

FL0

FL1

FL2

EMS

EE

EC LK

D 23

D 14

BR

D 1/IAD 14

VD D (IN T ) U 5

D 6/IRD

G N D

D 10

A10/IAD9

A6/IAD 5

D T 0

J2

J3

J4

U 6

U 7

T FS0

REV. PrA

–6 –

Preliminary Technical Data

AD73560

P IN F U NC T IO N D E SC R IP T IO N

Mnem onic

Function

VIN P1

VIN N 1

VIN P2

VIN N 2

VIN P3

VIN N 3

VIN P4

VIN N 4

VIN P5

VIN N 5

VIN P6

VIN N 6

R E F O U T

Analog Input to the Positive T erminal of Input Channel 1.

Analog Input to the Negative T erminal of Input Channel 1.

Analog Input to the Positive T erminal of Input Channel 2.

Analog Input to the Negative T erminal of Input Channel 2.

Analog Input to the Positive T erminal of Input Channel 3.

Analog Input to the Negative T erminal of Input Channel 3.

Analog Input to the Positive T erminal of Input Channel 4.

Analog Input to the Negative T erminal of Input Channel 4.

Analog Input to the Positive T erminal of Input Channel 5.

Analog Input to the Negative T erminal of Input Channel 5.

Analog Input to the Positive T erminal of Input Channel 6.

Analog Input to the Negative T erminal of Input Channel 6.

Buffered Reference Output, which has a nominal value of 1.25 V. T his pin can be overdriven by an

external reference if required.

RE F C AP

A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. T he capacitor should be

fixed to this pin.

AVD D

AG N D

D G N D

D VD D

ARE SE T

Analog Power Supply Connection.

Analog Ground/Substrate Connection.

Digital Ground/Substrate Connection.

D igital Power Supply Connection.

Active Low Reset Signal. T his input resets the entire chip, resetting the control registers and clearing the

digital circuitry.

SC LK 2

Output Serial Clock whose rate determines the serial transfer rate to/from the AFE0. It is used to

clock data or control information to and from the serial port (SPORT 2). T he frequency of SCLK is

equal to the frequency of the master clock (MCLK) divided by an integer number—this integer number

being the product of the external master clock rate divider and the serial clock rate divider.

Master Clock Input. MCLK is driven from an external clock signal.

Serial Data Output of the AD73560. Both data and control information may be output on this pin and are

clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and

when SE is low.

M C L K

SD O

SD OFS

SD IFS

Framing Signal Output for SDO Serial T ransfers. T he frame sync is one bit wide and it is active one SCLK

period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK.

SDOFS is in three-state when SE is low.

Framing Signal Input for SDI Serial T ransfers. T he frame sync is one bit wide and it is valid one SCLK period

before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored

when SE is low.

SD I

SE

Serial Data Input of the AD73560. Both data and control information may be input on this pin and are clocked

on the negative edge of SCLK. SDI is ignored when SE is low.

SPORT Enable. Asynchronous input enable pin for the SPORT . When SE is set low by the DSP, the output

pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to

decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their

original values (before SE was brought low); however, the timing counters and other internal registers are at

their reset values.

RESET

BR

(Input) Processor Reset Input

(Input) Bus Request Input

BG

(Output) Bus Grant Output

BG H

D M S

PM S

IOM S

BM S

C M S

RD

(Output) Bus Grant Hung Output

(Output) Data Memory Select Output

(Output) Program Memory Select Output

(Output) Memory Select Output

(Output) Byte Memory Select Output

(Output) Combined Memory Select Output

(Output) Memory Read Enable Output

WR

(Output) Memory Write Enable Output

IRQ2/

PF7

(Input) Edge- or Level-Sensitive Interrupt

(Input/Output) Request.¹Programmable I/O Pin

REV. PrA

–7 –

AD73560

P IN F U NC T IO N D E SC R IP T IO N

Mnem onic

Function

IRQL0/

PF6

IRQL1/

PF5

IRQE/

PF4

(Input) Level-Sensitive Interrupt Requests¹

(Input/Output) Programmable I/O Pin

(Input) Level-Sensitive Interrupt Requests¹

(Input/Output) Programmable I/O Pin

(Input) Edge-Sensitive Interrupt Requests¹

(Input/Output) Programmable I/O Pin

Mode D/

PF3

Mode C/

PF2

Mode B/

PF1

Mode A/

PF0

(Input) Mode Select Input—Checked Only During RESET

(Input/Output) Programmable I/O Pin During Normal Operation

(Input) Mode Select Input—Checked Only During RESET

(Input/Output) Programmable I/O Pin During Normal Operation

(Input) Mode Select Input—Checked Only During RESET

(Input/Output) Programmable I/O Pin During Normal Operation

(Input) Mode Select Input—Checked Only During RESET

(Input/Output) Programmable I/O Pin During Normal Operation

CLKIN ,

XT AL

C LKOU T

SPORT 0

SPORT 1

IRQ1:0

FI

(Inputs) Clock or Quartz Crystal Input

(Output) Processor Clock Output

(Inputs/Outputs) Serial Port I/O Pins

(Inputs) Edge- or Level-Sensitive Interrupts,

(Input) Flag In²

F O

(Output) Flag Out²

PWD

(Input) Power-Down Control Input

(Output) Power-Down Control Output

PWD ACK

FL0, FL1,

FL2

(Outputs) Output Flags

VDD and

G N D

Power and Ground

EZ-ICEPort

ERESET

EM S

(Inputs/Outputs) For Emulation Use

EE

EC LK

ELOU T

ELIN

EIN T

EBR

EBG

NOT ES

¹Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate inter-

rupt vector address when the pin is asserted, either by external de4vices, or set as a programmable flag.

²SPORT configuration determined by the DSP System Control Register. Software configurable.

REV. PrA

–8 –

Preliminary Technical Data

AD73560

T he two address buses (PMA and DMA) share a single

external address bus, allowing memory to be expanded

off-chip, and the two data buses (PMD and DMD) share

a single external data bus. Byte memory space and I/O

memory space also share the external buses.

An interface to low cost byte-wide memory is provided by

the Byte DMA port (BDMA port). T he BDMA port is bi-

directional and can directly address up to four megabytes

of external RAM or ROM for off-chip storage of program

overlays or data tables.

AR C H IT E C T U R E O VE R VIE W

T he AD73560 instruction set provides flexible data moves

and multifunction (one or two data moves with a

computaion) instructions. Every instructions can be ex-

ecuted in a single processor cycle. T he AD73560 assem-

bly language uses an algebraic syntax for ease of coding

and readability. A comprehensive set of development tools

supports program development.

T he AD73560 can respond to eleven interrupts. T here

can be up to six external interrupts (one edge-sensitive,

two level-sensitive and three configurable) and seven in-

ternal interrupts generated by the timer, the serial ports

(SPORT s), the Byte DMA port and the power-down cir-

cuitry. T here is also a master RESET signal. T he two

serial ports provide a complete synchronous serial inter-

face with optional companding in hardware and a wide

variety of framed or frameless data transmit and receive

modes of operation.

POWER-DOWN

CONTROL

MEMORY

DATA ADDRESS

GENERATORS

PROGRAMMABLE

I/O

AND

PROGRAM

SEQUENCER

16K PM

16K DM

(OPTIONAL 8K)

FULL MEMORY

MODE

DAG

1

DAG

2

FLAGS

EXTERNAL

ADDRESS

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

EXTERNAL

DATA

BUS

PROGRAM MEMORY DATA

DATA MEMORY DATA

BYTE DMA

CONTROLLER

FLASH

Byte Memory

64 kbytes

SERIAL PORTS

ARITHMETIC UNITS

TIMER

ALU

SHIFTER

MAC

SPORT

0

SPORT 1

Each port can generate an internal programmable serial

clock or accept an external serial clock.

ADSP-2100 BASE

ARCHITECTURE

T he AD73560 provides up to 13 general-purpose flag

pins. T he data input and output pins on SPORT 1 can be

alternatively configured as an input flag and an output

flag. In addition, there are eight flags that are program-

mable as inputs or outputs and three flags that are always

outputs.

SERIAL PORT

REF

SPORT

2

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ANALOG FRONT END

SECTION

A programmable interval timer generates periodic inter-

rupts. A 16-bit count register (T COUNT ) is

decremented every n processor cycle, where n is a scaling

value stored in an 8-bit register (T SCALE). When the

value of the count register reaches zero, an interrupt is

generated and the count register is reloaded from a 16-bit

Figure 1. Functional Block Diagram

Figure 1 is an overall block diagram of the AD73560.

T he processor section contains three independent compu-

tational units: the ALU, the multiplier/accumulator

(MAC) and the shifter. T he computational units process

16 bit data directly and have provisions to support

multiprecision computations. T he ALU performs a stan-

dard set of arithmetic and logic operations; division

primitives are also supported. T he MAC performs single-

cycle multiply, multiply/add and multiply/subtract opera-

tions with 40 bits of accumulation. T he shifter performs

logical and arithmetic shifts, normalization,

period register (T PERIOD ).

An alog F r on t E n d

T he analog front end of the AD73560 is configured as a

separate block that is normally connected to either

SPORT 0 or SPORT 1 of the DSP section. As it is not

hardwired to either SPORT the user has total flexibility

in how they wish to allocate system resources to support

the AFE. It is also possible to further expand the number

of analog input channels connected to the SPORT by

cascading single AD73360 devices external to the

AD 73560.

denormalization and derive exponent operations.

T he internal result (R) bus connects the computational

units so that the output of any unit may be the input of any

unit on the next cycle.

T he AFE is configured as six input channels. It comprises

six independent encoder channels each featuring signal

conditioning, programmable gain amplifier, sigma-delta

A/D convertor and decimator sections. Each of these

sections is described in further detail below.All channels

share a common internal reference whose nominal value is

1.25V. Figure 2 shows a block diagram of the AFE sec-

tion of the AD73560. It shows six input channels along

with a common reference. Communication to all channels

is handled by the SPORT 2 block which interfaces to

either SPORT 0 or SPORT 1 of the DSP section.

A powerful program sequencer and two dedicated data

address generators ensure efficient delivery of operands to

these computational units. T he sequencer supports condi-

tional jumps, subroutine calls and returns in a single

cycle. With internal loop counters and loop stacks, the

AD73560 executes looped code with zero overhead; no

explicit jump instructions are required to maintain loops.

T wo data address generators (DAGs) provide addresses

for simultaneous dual operand fetches (from data memory

and program memory). Each DAG maintains and updates

four address pointers. Whenever the pointer is used to

access data (indirect addressing), it is post-modified by

the value of one of four possible modify registers. A

length value may be associated with each pointer to imple-

ment automatic modulo addressing for circular buffers.

REV. PrA

–9 –

AD73560

VINP1

VINN1

ANALOG

⌺-⌬

MODULATOR

SIGNAL

CONDITIONING

0/38dB

PGA

DECIMATOR

SDI

SDIFS

SCLK2

VINP2

VINN2

ANALOG

⌺-⌬

MODULATOR

SIGNAL

CONDITIONING

0/38dB

PGA

VINP3

VINN3

ANALOG

⌺-⌬

MODULATOR

SIGNAL

CONDITIONING

0/38dB

PGA

ARESET

AMCLK

SE

REFERENCE

REFCAP

REFOUT

SERIAL

I/O

PORT

AD73360

VINP4

VINN4

ANALOG

⌺-⌬

MODULATOR

SIGNAL

CONDITIONING

0/38dB

PGA

DECIMATOR

VINP5

VINN5

ANALOG

SIGNAL

CONDITIONING

0/38dB

PGA

-

⌺ ⌬

MODULATOR

SDO

SDOFS

VINP6

VINN6

ANALOG

⌺-⌬

MODULATOR

SIGNAL

CONDITIONING

0/38dB

PGA

Figure 2. Function Block Diagram of Analog Front End

amplifiers in the circuit. T he input signal level to the

sigma-delta modulator should not exceed the maximum

input voltage permitted.

F UNC T IO NAL D SE C RIP T IO N - AF E

T he PGA gain is set by bits IGS0, IGS1 and IGS2 in

control Registers D, E and F.

E n cod er C h a n n el

Each encoder channel consists of a signal conditioner, a

switched capacitor PGA and a sigma-delta analog-to-

digital converter (ADC). An on-board digital filter, which

forms part of the sigma-delta ADC, also performs critical

system-level filtering. Due to the high level of

oversampling, the input antialias requirements are reduced

such that a simple single pole RC stage is sufficient to

give adequate attenuation in the band of interest.

Table II. P GA Settings for the Encoder Channel

IxGS2

IxGS1

IxGS0

Gain (dB)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

6

12

18

20

26

32

38

S ign a l C on d ition er

Each analog channel has an independent signal condition-

ing block. T his allows the analog input to be configured

by the user depending on whether differential or single-

ended mode is used.

P r ogr a m m a ble G a in Am p lifier

A D C

Each encoder section’s analog front end comprises a

switched capacitor PGA that also forms part of the sigma-

delta modulator. T he SC sampling frequency is DMCLK/

8. T he PGA, whose programmable gain settings are

shown in T able II, may be used to increase the signal

level applied to the ADC from low output sources such as

microphones, and can be used to avoid placing external

Each channel has its own ADC consisting of an analog

sigma-delta modulator and a digital antialiasing decima-

tion filter. T he sigma-delta modulator noise-shapes the

signal and produces 1-bit samples at a DMCLK/8 rate.

T his bitstream, representing the analog input signal, is

input to the antialiasing decimation filter. T he decimation

filter reduces the sample rate and increases the resolution.

REV. PrA

–1 0 –

Preliminary Technical Data

AD73560

noise-shaping will push the inherent quantization noise to

an out-of-band position. T he detail of Figure 4c shows

the response of the digital decimation filter (Sinc-cubed

response) with nulls every multiple of D M CLK/256,

which is the decimation filter update rate. T he final detail

in Figure 4d shows the application of a final antialias filter

in the DSP engine. This has the advantage of being imple-

mented according to the user’s requirements and avail-

able MIPS. T he filtering in Figures 4a through 4c is

implemented in the AD73560.

An a log Sigm a - D elta M od u la tor

T he AD73560 input channels employ a sigma-delta conver-

sion technique, which provides a high resolution 16-bit out-

put with system filtering being implemented on-chip.

Sigma-delta converters employ a technique known as

oversampling, where the sampling rate is many times the

highest frequency of interest. In the case of the AD73560,

the initial sampling rate of the sigma-delta modulator is

DMCLK/8. T he main effect of oversampling is that the

quantization noise is spread over a very wide bandwidth,

up to f_S/2 = DMCLK/16 (Figure 3a). T his means that the

noise in the band of interest is much reduced. Another

complementary feature of sigma-delta converters is the use

of a technique called noise-shaping. T his technique has

the effect of pushing the noise from the band of interest to

an out-of-band position (Figure 3b). T he combination of

these techniques, followed by the application of a digital

filter, reduces the noise in band sufficiently to ensure good

dynamic performance from the part (Figure 3c).

F

= DMCLK/8

F

= 4kHz

SINIT

B

a. Analog Antialias Filter Transfer Function

SIGNAL TRANSFER FUNCTION

NOISE TRANSFER FUNCTION

BAND

F

/2

S

OF

DMCLK/16

INTEREST

F

= DMCLK/8

a.

F

= 4kHz

SINIT

B

b. Analog Sigm a-Delta Modulator Transfer Function

NOISE-SHAPING

BAND

OF

F

/2

S

DMCLK/16

INTEREST

b.

F

= DMCLK/256

F

= 4kHz

SINTER

B

c. Digital Decim ator Transfer Function

DIGITAL FILTER

BAND

OF

F

/2

S

DMCLK/16

INTEREST

c.

Figure 3. Sigm a-Delta Noise Reduction

F

= 4kHz

F

= 8kHz

F

= DMCLK/256

SINTER

SFINAL

B

Figure 4 shows the various stages of filtering that are em-

ployed in a typical AD73560 application. In Figure 4a we

see the transfer function of the external analog antialias

filter. Even though it is a single RC pole, its cutoff fre-

quency is sufficiently far away from the initial sampling

frequency (DMCLK/8) that it takes care of any signals

that could be aliased by the sampling frequency. T his also

shows the major difference between the initial

oversampling rate and the bandwidth of interest. In Figure

4b, the signal and noise-shaping responses of the sigma-

delta modulator are shown. T he signal response provides

further rejection of any high frequency signals while the

d. Final Filter LPF (HPF) Transfer Function

Figure 4. DC Frequency Responses

D ecim a tion F ilter

T he digital filter used in the AD73560 carries out two

important functions. Firstly, it removes the out-of-band

quantization noise, which is shaped by the analog modula-

tor and secondly, it decimates the high frequency

bitstream to a lower rate 15-bit word.

REV. PrA

–1 1 –

AD73560

T he antialiasing decimation filter is a sinc-cubed digital

filter that reduces the sampling rate from DMCLK/8 to

DMCLK/256, and increases the resolution from a single

bit to 15 bits. Its Z transform is given as: [(1–Z^–32)/(1–Z^–

¹)]³. T his ensures a minimal group delay of 25 µs.

In both transmit and receive modes, data is transferred at

the serial clock (SCLK2) rate with the MSB being trans-

ferred first. Communication between the AFE section and

DSP section must always be initiated by the ADE section

(AFE is in master mode, DSP is in slave mode). T his

ensures that there is no collision between input data and

output samples.

AD C C od in g

T he ADC coding scheme is in twos complement format (see

Figure 8). T he output words are formed by the decimation

filter, which grows the word length from the single-bit output of

the sigma-delta modulator to a 15-bit word, which is the final

output of the ADC block. In 16-bit Data Mode this value is left

shifted with the LSB being set to 0. For input values equal to or

greater than positive full scale, however, the output word is set

at 0x7FFF, which has the LSB set to 1. In mixed Control/Data

Mode, the resolution is fixed at 15 bits, with the MSB of the

16-bit transfer being used as a flag bit to indicate either control

or data in the frame.

S P O R T 2 O ver view

SPORT 2 is a flexible, full-duplex, synchronous serial port

whose protocol has been designed to allow addition AFE’s

(up to a limit of 7 external devices) to be connected in cas-

cade to the DSP section. It has a very flexible architecture

that can be configured by programming two of the internal

control registers in each AFE block. SPORT 2 has three dis-

tinct modes of operation: Control Mode, Data Mode and

Mixed Control/Data Mode.

NOT E: As each AFE has its own SPORT section, the

register settings in each must be programmed. T he regis-

ters which control SPORT and sample rate operation

(CRA and CRB) must be programmed with the same val-

ues, otherwise incorrect operation may occur.

V

+ (V

؋

0.32875)

V

INN

REF

ANALOG

INPUT

V

REF

In Control Mode (CRA:0 = 0), the device’s internal con-

figuration can be programmed by writing to the eight

internal control registers. In this mode, control informa-

tion can be written to or read from the AFE. In Data

Mode (CRA:0 = 1), any information that is sent to the

AFE is ignored, while the encoder section (ADC) data is

read from the device. In this mode, only ADC data is read

from the device. Mixed mode (CRA:0 = 1 and CRA:1 =

1) allows the user to send control information and receive

either control information or ADC data. T his is achieved

by using the MSB of the 16-bit frame as a flag bit. Mixed

mode reduces the resolution to 15 bits with the MSB be-

ing used to indicate whether the information in the 16-bit

frame is control information or ADC data.

V

INP

V

- (V

؋

REF

0.32875)

REF

10...00

00...00

01...11

ADC CODE DIFFERENTIAL

V

+ (V

؋

0.6575)

REF

V

INN

ANALOG

INPUT

V

INP

V

- (V

؋

0.6575)

REF

SPORT 2 features a single 16-bit serial register that is

used for both input and output data transfers. As the input

and output data must share the same register there are

some precautions that must be observed. T he primary

precaution is that no information must be written to

SPORT 2 without reference to an output sample event,

which is when the serial register will be overwritten with

the latest ADC sample word. Once SPORT 2 starts to

output the latest ADC word, it is safe for the DSP to write

new control words to the AFE. In certain configurations,

data can be written to the device to coincide with the out-

put sample being shifted out of the serial register—see

section on interfacing devices. T he serial clock rate

(CRB:2–3) defines how many 16-bit words can be written

to a device before the next output sample event will hap-

pen.

10...00

00...00

ADC CODE SINGLE-ENDED

01...11

Figure 5. ADC Transfer Function

Volta ge Refer en ce

T he AD73560 reference, REFCAP, is a bandgap refer-

ence that provides a low noise, temperature-compensated

reference to the ADC. A buffered version of the reference

is also made available on the REFOUT pin and can be

used to bias other external analog circuitry. T he reference

has a nominal value of 1.25 V.

T he reference output (REFOUT ) can be enabled for bias-

ing external circuitry by setting the RU bit (CRC:6) of

C RC .

AFE Ser ial P or t (SP O RT2)

T he SPORT 2 block diagram, shown in Figure 9, details

the blocks associated with AFE including the eight control

registers (A–H ), external AMCLK to internal DMCLK

divider and serial clock divider. T he divider rates are

controlled by the setting of Control Register B. T he AFE

features a master clock divider that allows users the flex-

ibility of dividing externally available high frequency DSP

clocks to generate a lower frequency master clock inter-

nally in the AFE which may be more suitable for either

T he AFE section communicate with DSP via the bi-direc-

tional synchronous serial port (SPORT 2) which interfaces to

either SPORT 0 or SPORT 1 of the DSP section.

SPORT 2 is used to transmit and receive digital data and

control information. Additional external AFE’s can be

cascaded to the internal AFE (up to a limit of 7) to

provide additional input channels if required.

REV. PrA

–1 2 –

Preliminary Technical Data

AD73560

sponding to the various bit settings. T he default divider

ratio is divide-by-one.

serial transfer or sampling rate requirements. T he master

clock divider has five divider options (÷1 default condi-

tion, ÷2, ÷3, ÷4, ÷5) that are set by loading the master

clock divider field in Register B with the appropriate code

(see T able VI). Once the internal device master clock

(DMCLK) has been set using the master clock divider,

the sample rate and serial clock settings are derived from

D M C L K .

Table III. D MC LK (Inter nal) Rate D ivider Settings

MCD 2

MCD 1

MCD 0

D MCLK Rate

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AM C L K

AM CLK/2

AM CLK/3

AM CLK/4

AM CLK/5

AM C L K

AM C LK

AMCLK

(EXTERNAL)

DMCLK

(INTERNAL)

MCLK

DIVIDER

SCLK

AM C LK

SCLK2

SE

DIVIDER

SERIAL PORT

(SPORT)

ARESET

Ser ial C lock Rate D ivider

SDIFS

SDI

SDOFS

SDO

SERIAL REGISTER

T he AFE features a programmable serial clock divider that

allows users to match the serial clock (SCLK2) rate of the

data to that of the DSP. T he maximum SCLK2 rate available

is D MCLK and the other available rates are: DMCLK/2,

D MCLK/4 and D MCLK/8. T he slowest rate (D MCLK/8)

is the default SCLK2 rate. T he serial clock divider is

programmable by setting bits CRB:2–3. T able IV shows

the serial clock rate corresponding to the various bit set-

tings.

2

3

8

CONTROL

REGISTER

C

CONTROL

REGISTER

E

CONTROL

REGISTER

A

CONTROL

REGISTER

B

CONTROL

REGISTER

D

CONTROL

REGISTER

G

CONTROL

REGISTER

H

CONTROL

REGISTER

F

8

Figure 6. SPORT Block Diagram

SPORT 2 can work at four different serial clock (SCLK)

rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or

DMCLK/8, where DMCLK is the internal or device mas-

ter clock resulting from the external or pin master clock

being divided by the master clock divider. Care should be

taken when selecting Master Clock, Serial Clock and

Sample Rate divider settings to ensure that there is suffi-

cient time to read all the data from the AFE before the

next sample interval.

Table IV. SCLK Rate D ivider Settings

SCD 1

SCD 0

SCLK2 Rate

0

1

0

1

0

1

D M C L K /8

D M CLK/4

D M CLK/2

D M C LK

D ecim a tion Ra te D ivider

T he AFE features a programmable decimation rate divider

that allows users flexibility in matching the AFE’s ADC

sample rates to the needs of the DSP software. T he maximum

sample rate available is D MCLK/256 and the other avail-

able rates are: DMCLK/512, DMCLK/1024 and

DMCLK/2048. T he slowest rate (DMCLK/2048) is the

default sample rate. The sample rate divider is program-

mable by setting bits CRB:0-1. T able V shows the sample

rate corresponding to the various bit settings.

SP O RT Register Maps

T here are eight control registers for the AFE, each

eight bits wide. T able V shows the control register map

for the AFE. T he first two control registers, CRA and

CRB, are reserved for controlling SPORT 2. T hey hold

settings for parameters such as bit rate, internal master

clock rate and device count. If multiple AFE’s are cas-

caded, registers CRA and CRB on each device must be

programmed with the same setting to ensure correct op-

eration. T he other six registers; CRC through CRH are

used to hold control settings for the Reference, Power

Control, ADC channel and PGA sections of the device.

It is not necessary that the contents of CRC through

C RH on each AFE are similar. C ontrol registers are

written to on the negative edge of SCLK2.

Table V. D ecim ation Rate D ivider Settings

DR1

DR0

SCLK2 Rate

0

1

0

1

0

1

D M C LK /2048

D M C LK /1024

D M C LK /512

D M C LK /256

Master C lock D ivider

T he AFE features a programmable master clock divider

that allows the user to reduce an externally available mas-

ter clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or

5 to produce an internal master clock signal (DMCLK)

that is used to calculate the sampling and serial clock

rates. T he master clock divider is programmable by set-

ting CRB:4-6. T able III shows the division ratio corre-

REV. PrA

–1 3 –

AD73560

Table VI. C ontr ol Register Map

Address (Binary)

Nam e

Description

Type

Width

Reset Setting (H ex)

000

001

010

011

100

101

110

111

C RA

CRB

CRC

CRD

CRE

CRF

CRG

CRH

Control Register A

Control Register B

Control Register C

Control Register D

Control Register E

Control Register F

Control Register G

Control Register H

R /W

R/W

8

0x00

T able VII. C ontr ol Wor d D escr iption

15

14

R/

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DEVICE ADDRESSS

REGISTER ADDRESS

REGISTER DATA

C/D

W

C ontr ol

Fr am e

Description

Bit 15

C on trol/Data

When set high, it signifies a control word in Program or Mixed Program/Data Modes.

When set low, it signifies an invalid control word in Program Mode.

Bit 14

Read /Write

When set low, it tells the device that the data field is to be written to the register se-

lected by the register field setting provided the address field is zero. When set high, it

tells the device that the selected register is to be written to the data field in the serial

register and that the new control word is to be output from the device via the serial

output.

Bits 13–11

D evice Address

T his 3-bit field holds the address information. Only when this field is zero is a device

selected. If the address is not zero, it is decremented and the control word is passed out

of the device via the serial output.

Bits 10–8

Bits 7–0

Register Address T his 3-bit field is used to select one of the eight control registers on the AD73560.

Register D ata

T his 8-bit field holds the data that is to be written to or read from the selected register

provided

the address field is zero.

C O NT RO L RE G IST E R

A

Table VIII. C ontr ol Register A D escr iption

7

6

5

4

3

2

1

0

PG M

DAT A/

RESET

DC2

DC1

DC0

SLB

–

MM

Bit Nam e

Description

0

1

2

3

4

5

6

7

D AT A/PGM Operating Mode (0 = Program; 1 = Data Mode)

M M

Reserved

S L B

Mixed Mode (0 = OFF; 1 = Enabled)

Must Be Programmed to Zero (0)

SPORT Loop-Back Mode (0 = OFF; 1 = Enabled)

Device Count (Bit 0)

D C 0

D C 1

Device Count (Bit 1)

D C 2

Device Count (Bit 2)

RE SE T

Software Reset (0 = OFF; 1 = Initiates Reset)

REV. PrA

–1 4 –

Preliminary Technical Data

AD73560

Table IX. Contr ol Register B D escr iption

C O NT RO L RE G IST E R

B

7

6

5

4

3

2

1

0

CEE

MCD2

MCD1

MCD0

SCD1

SCD0

DR1

DR0

Bit Nam e

Description

0

1

2

3

4

5

6

7

D R0

D R1

Decimation Rate (Bit 0)

Decimation Rate (Bit 1)

SC D 0

SC D 1

M C D 0

M C D 1

M C D 2

C E E

Serial Clock Divider (Bit 0)

Serial Clock Divider (Bit 1)

Master Clock Divider (Bit 0)

Master Clock Divider (Bit 1)

Master Clock Divider (Bit 2)

Control Echo Enable (0 = OFF; 1 = Enabled)

Table X. Contr ol Register C D escr iption

C O NT RO L RE GIST E R C

7

6

5

4

3

2

1

0

–

R U

P U R E F

–

G P U

Bit Nam e

Description

0

1

2

3

4

5

6

7

G P U

Global Power-Up Device (0 = Power Down; 1 = Power Up)

Must Be Programmed to Zero (0)

REF Power (0 = Power Down; 1 = Power Up)

REFOUT Use (0 = Disable REFOUT ; 1 = Enable REFOUT )

Must Be Programmed to Zero (0)

Reserved

P U RE F

R U

Reserved

Table XI. Contr ol Register

D

D escr iption

7

6

5

4

3

2

1

0

C O NT RO L RE G IST E R

D

PUI2

I2GS2

I2GS1

I2GS0

PUI1

I1GS2

I1GS1

I1GS0

Bit Nam e

Description

0

1

2

3

4

5

6

7

I1G S0

I1G S1

I1G S2

P U I1

I2G S0

I2G S1

I2G S2

P U I2

ADC1:Input Gain Select (Bit 0)

ADC1:Input Gain Select (Bit 1)

ADC1:Input Gain Select (Bit 2)

Power Control (ADC1); 1 = ON, 0 = OFF

ADC2:Input Gain Select (Bit 0)

ADC2:Input Gain Select (Bit 1)

ADC2:Input Gain Select (Bit 2)

Power Control (ADC2); 1 = ON, 0 = OFF

REV. PrA

–1 5 –

AD73560

Table XIII. C ontr ol Register E D escr iption

C O NT RO L RE G IST E R

E

7

6

5

4

3

2

1

0

PUI4

I4GS2

I4GS1

I4GS0

PUI3

I3GS2

I3GS1

I3GS0

Bit Nam e

Description

0

1

2

3

4

5

6

7

I3G S0

I3G S1

I3G S2

P U I3

I4G S0

I4G S1

I4G S2

P U I4

ADC3:Input Gain Select (Bit 0)

ADC3:Input Gain Select (Bit 1)

ADC3:Input Gain Select (Bit 2)

Power Control (ADC3); 1 = ON, 0 = OFF

ADC4:Input Gain Select (Bit 0)

ADC4:Input Gain Select (Bit 1)

ADC4:Input Gain Select (Bit 2)

Power Control (ADC4); 1 = ON, 0 = OFF

Table XIV. Contr ol Register F D escr iption

C O NT RO L RE G IST E R

F

7

6

5

4

3

2

1

0

PUI6

I6GS2

I6GS1

I6GS0

PUI5

I5GS2

I5GS1

I5GS0

Bit Nam e

Description

0

1

2

3

4

5

6

7

I5G S0

I5G S1

I5G S2

P U I5

I6G S0

I6G S1

I6G S2

P U I6

ADC5:Input Gain Select (Bit 0)

ADC5:Input Gain Select (Bit 1)

ADC5:Input Gain Select (Bit 2)

Power Control (ADC5); 1 = ON, 0 = OFF

ADC6:Input Gain Select (Bit 0)

ADC6:Input Gain Select (Bit 1)

ADC6:Input Gain Select (Bit 2)

Power Control (ADC6); 1 = ON, 0 = OFF

Table XV. Contr ol Register G D escr iption

C O NT RO L RE G IST E R

G

7

6

5

4

3

2

1

0

SEEN

RMOD

CH6

CH5

CH4

CH3

CH2

CH1

Bit Nam e

Description

0

1

2

3

4

5

6

7

C H 1

C H 2

C H 3

C H 4

C H 5

C H 6

Channel 1 Select

Channel 2 Select

Channel 3 Select

Channel 4 Select

Channel 5 Select

Channel 6 Select

R M O D

S E E N

Reset Analog Modulator

Enable Single-Ended Input Mode

REV. PrA

–1 6 –

Preliminary Technical Data

AD73560

Table XVI. C ontr ol Register

H

D escr iption

7

6

5

4

3

2

1

0

C O NT RO L RE G IST E R

H

INV

TME

CH6

CH5

CH4

CH3

CH2

CH1

Bit Nam e

Description

0

1

2

3

4

5

6

7

C H 1

C H 2

C H 3

C H 4

C H 5

C H 6

T M E

IN V

Channel 1 Select

Channel 2 Select

Channel 3 Select

Channel 4 Select

Channel 5 Select

Channel 6 Select

T est Mode Enable

Enable Invert Channel Mode

O p er a tin g M od es

O P E R A T I O N

T here are three operating modes available on the AFE.

T hey are Control (Program), Data and Mixed Control/

D ata. T he device configuration—register settings—can be

changed only in Program and Mixed Program/Data

Modes. In all modes, transfers of information to or from

the device occur in 16-bit packets, therefore the DSP

engine’s SPORT will be programmed for 16-bit transfers.

Resetting the AFE

T he ARESET pin resets all the control registers. All the

AFE registers are reset to zero indicating that the default

SCLK2 rate (DMCLK/8) and sample rate (DMCLK/

2048) are at a minimum. As well as resetting the control

registers of the AFE using the ARESET pin, the device

can be reset using the RESET bit (CRA:7) in Control

Register A. Both hardware and software resets require four

DMCLK cycles. On reset, DAT A/PGM (CRA:0) is set to

0 (default condition) thus enabling Control Mode. T he

reset conditions ensure that the device must be pro-

grammed to the correct settings after power-up or reset.

Following a reset, the SDOFS will be asserted approxi-

mately 2070 master (AMCLK) cycles after ARESET goes

high. T he data that is output following the reset and dur-

ing Control Mode is random and contains no valid infor-

mation until either data or mixed mode is set.

C on tr ol M od e

In Control Mode, CRA:0 = 0, the user writes to the con-

trol registers to set up the device for desired operation—

SPORT 2 operation, cascade length, power management,

input/output gain, etc. In this mode, the 16-bit informa-

tion packet sent to the device by the DSP is interpreted as

a control word whose format is shown in T able VII. In

this mode, the user must address the device to be pro-

grammed using the address field of the control word. T his

field is read by the device and if it is zero (000 bin), the

device recognizes the word as being addressed to it. If the

address field is not zero, it is then decremented and the

control word is passed out of the device—either to the

next device in a cascade or back to the DSP. T his 3-bit

address format allows the user to uniquely address any one

of up to eight devices in a cascade. If the AFE is used in a

stand-alone configuration connected to the DSP, the de-

vice address corresponds to 0.

P ower M a n a gem en t

T he individual functional blocks of the AFE can be en-

abled separately by programming the power control regis-

ter CRC (T he Power Management functions of the DSP

section are seperate and will be referred to later). It allows

certain sections to be powered down if not required, which

adds to the device’s flexibility in that the user need not

incur the penalty of having to provide power for a certain

section if it is not necessary to their design. T he power

control registers provide individual control settings for the

major functional blocks on each analog front end unit and

also a global override that allows all sections to be pow-

ered up/down by setting/clearing the bit. Using this

method the user could, for example, individually enable a

certain section, such as the reference (CRC:5), and disable

all others. T he global power-up (CRC:0) can be used to

enable all sections but if power-down is required using the

global control, the reference will still be enabled; in this

case, because its individual bit is set. Refer to T able X for

details of the settings of CRC. CRD–CRF can be used to

control the power status of individual channels allowing

multiple channels to be powered down if required.

Following reset, when the SE pin is enabled, the AFE

responds by raising the SDOFS pin to indicate that an

output sample event has occurred. Control words can be

written to the device to coincide with the data being sent out

of SPORT2, as shown in Figure 12 (Directly Coupled), or

they can lag the output words by a time interval that

should not exceed the sample interval (Indirectly

REV. PrA

–1 7 –

AD73560

Coupled). Refer to the Digital Interface section for more

information. After reset, output frame sync pulses will

occur at a slower default sample rate, which is DMCLK/

2048, until Control Register B is programmed, after

which the SDOFS will be pulsed at the selected rate.

While the AFE is in Control Mode, the data output by the

device is random and should not be interpreted as ADC

data.

data connected to the AFE’s SDI and SDO, respectively,

while the DSP’s T x and Rx frame syncs are connected to

the AD73560’s SDIFS and SDOFS. In this configura-

tion, referred to as directly coupled or frame sync loop-

back, the frame sync signals are connected together and

the input data to the AFE is forced to be synchronous with

the output data from the AFE. T he DSP must be pro-

grammed so that both the T x and Rx frame syncs are in-

puts as the AFE’s SDOFS will be input to both. T his

configuration guarantees that input and output events oc-

cur simultaneously and is the simplest configuration for

operation in normal Data Mode. N ote that when pro-

gramming the D SP in this configuration it is advisable to

preload the T x register with the first control word to be

sent before the AFE is taken out of reset. T his ensures

that this word will be transmitted to coincide with the first

output word from the device(s).

D a ta M ode

Once the device has been configured by programming the

correct settings to the various control registers, the device

may exit Program Mode and enter Data Mode. T his is

done by programming the DAT A/PGM (CRA:0) bit to a

1 and MM (CRA:1) to 0. Once the device is in Data

Mode, the input data is ignored. When the device is in

normal Data Mode (i.e., mixed mode disabled), it must

receive a hardware reset to reprogram any of the control

register settings.

M ixed P r ogr a m /D a ta M ode

T his mode allows the user to send control words to the

device while receiving ADC words. T his permits adaptive

control of the device whereby control of the input gains

can be affected by reprogramming the control registers.

T he standard data frame remains 16 bits, but now the

MSB is used as a flag bit to indicate that the remaining 15

bits of the frame represents control information. Mixed

mode is enabled by setting the MM bit (CRA:1) to 1 and

the DAT A/PGM bit (CRA:0) to 1. In the case where con-

trol setting changes will be required during normal opera-

tion, this mode allows the ability to load control

SDIFS

TFS(0/1)

SDI

DT(0/1)

DSP

SCLK(0/1)

SCLK

AFE

SECTION

DR(0/1)

SDO

RFS(0/1)

SDOFS

Figure 7. Indirectly Coupled or Nonfram e Sync Loop-Back

Configuration

information with the slight inconvenience of formatting

the data. Note that the output samples from the ADC will

also have the MSB set to zero to indicate it is a data word.

SDIFS

TFS(0/1)

SDI

DT(0/1)

INT E R F AC ING

T he AFE section SPORT (SPORT 2) can be interfaces to

either SPORT 0 or SPORT 1 of the DSP section.. Both

serial input and output data use an accompanying frame

synchronization signal which is active high one clock cycle

before the start of the 16-bit word or during the last bit of

the previous word if transmission is continuous. T he serial

clock (SCLK) is an output from the AFE and is used to

define the serial transfer rate to the DSP’s T x and Rx

ports. T wo primary configurations can be used: the first is

shown in Figure 7 where the DSP’s T x data, T x frame

sync, Rx data and Rx frame sync are connected to the

AD 73560’s SD I, SD IFS, SD O and SD OFS respectively.

T his configuration, referred to as indirectly coupled or

nonframe sync loop-back, has the effect of decoupling the

transmission of input data from the receipt of output data.

When programming the DSP serial port for this configu-

ration, it is necessary to set the Rx frame sync as an input

to the DSP and the T x frame sync as an output generated

by the DSP. T his configuration is most useful when oper-

ating in mixed mode, as the DSP has the ability to decide

how many words can be sent to the AFE(s). This means

that full control can be implemented over the device con-

figuration in a given sample interval. The second configu-

ration (shown in Figure 8) has the DSP’s Tx data and Rx

DSP

SCLK(0/1)

SCLK

AFE

SECTION

DR(0/1)

SDO

RFS(0/1)

SDOFS

Figure 8. Directly Coupled or Fram e Sync Loop-

Back Configuration

C a sca d e O p er a tion

T he AD73560 has been designed to support cascading of

external AFEs from either SPORT 0 or SPORT 1. T he

SPORT 2 interface protocol has been designed so that

device addressing is built into the packet of information

sent to the device. T his allows the cascade to be formed

with no extra hardware overhead for control signals or

addressing. A cascade can be formed in either of the two

modes previously discussed.

REV. PrA

–1 8 –

Preliminary Technical Data

AD73560

T here may be some restrictions in cascade operation due

to the number of devices configured in the cascade and the

serial clock rate chosen. T he formula below gives an indi-

cation of whether the combination of sample rate, serial

clock and number of devices can be successfully cascaded.

T his assumes a directly coupled frame sync arrangement

as shown in Figure 8 and does not take any interrupt la-

tency into account.

F U NC T IO NAL D E SC RIP T IO N - D SP

T he AD73560 instruction set provides flexible data moves

and multifunction (one or two data moves with a compu-

tation) instructions. Every instruction can be executed in a

single processor cycle. T he AD73560 assembly language

uses an algebraic syntax for ease of coding and readabil-

ity. A comprehensive set of development tools supports

program development.

1

6

[(( De vic eCo unt 1) 16 ) 17]

× − × +

POWER-DOWN

CONTROL

≥

f_S

SCLK

MEMORY

DATA ADDRESS

GENERATORS

PROGRAMMABLE

PROGRAM

SEQUENCER

I/O

16K PM

16K DM

(OPTIONAL 8K)

AND

FLAGS

(OPTIONAL 8K)

FULL MEMORY

MODE

DAG

2

DAG

1

When using the indirectly coupled frame sync configura-

tion in cascaded operation it is necessary to be aware of

the restrictions in sending control word data to all devices

in the cascade. T he user should ensure that there is suffi-

cient time for all the control words to be sent between

reading the last ADC sample and the start of the next

sample period.

In Cascade Mode, each device must know the number of

devices in the cascade to be able to output data at the cor-

rect time. Control Register A contains a 3-bit field (DC0–

2) that is programmed by the DSP during the

EXTERNAL

ADDRESS

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

EXTERNAL

DATA

BUS

PROGRAM MEMORY DATA

DATA MEMORY DATA

BYTE DMA

CONTROLLER

Byt

6

SERIAL PORTS

SPORT 0 SPORT 1

ARITHMETIC UNITS

TIMER

ALU

SHIFTER

MAC

ADSP-2100 BASE

ARCHITECTURE

programming phase. T he default condition is that the field

contains 000b, which is equivalent to a single device in

cascade (see T able XVII). However, for cascade operation

this field must contain a binary value that is one less than

the number of devices in the cascade. With a number of

AD73560s in cascade each device takes a turn to send an

ADC result to the DSP. For example, in a cascade of two

devices the data will be output as Device 2-Channel 1,

Device 1-Channel 1, Device 2-Channel 2, Device 1-

Channel 2 etc. When the first device in the cascade has

transmitted its channel data there is an additional SCLK

period during which the last device asserts its SDOFS as

it begins its transmission of the next channel. T his will

not cause a problem for most DSPs as they count clock

edges after a frame sync and hence the extra bit will be

ignored.

When multiple devices are connected in cascade there are

also restrictions concerning which ADC channels can be

powered up. In all cases the cascaded devices must all

have the same channels powered up (i.e., for a cascade of

two devices requiring Channels 1 and 2 on Device 1 and

Channel 5 on Device 2, Channels 1, 2 and 5 must be pow-

ered up on both devices to ensure correct operation).

SERIAL PORT

REF

SPORT

2

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ANALOG FRONT END

SECTION

Figure 9. Functional Block Diagram

Figure 9 is an overall block diagram of the AD73560.

T he processor contains three independent computational

units: the ALU, the multiplier/accumulator (MAC) and

the shifter. T he computational units process 16-bit data

directly and have provisions to support multiprecision

computations. T he ALU performs a standard set of arith-

metic and logic operations; division primitives are also

supported. T he MAC performs single-cycle multiply,

multiply/add and multiply/subtract operations with 40 bits

of accumulation. T he shifter performs logical and arith-

metic shifts, normalization, denormalization and derive

exponent operations.

T he shifter can be used to efficiently implement numeric

format control including multiword and block floating-

point representations.

T he internal result (R) bus connects the computational

units so that the output of any unit may be the input of

any unit on the next cycle.

Table XVII. D evice Count Settings

D C2

D C1

D C0

Cascade Length

A powerful program sequencer and two dedicated data

address generators ensure efficient delivery of operands to

these computational units. T he sequencer supports condi-

tional jumps, subroutine calls and returns in a single

cycle. With internal loop counters and loop stacks, the

AD73560 executes looped code with zero overhead; no

explicit jump instructions are required to maintain loops.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

REV. PrA

–1 9 –

AD73560

T wo data address generators (DAGs) provide addresses

for simultaneous dual operand fetches (from data memory

and program memory). Each DAG maintains and updates

four address pointers. Whenever the pointer is used to

access data (indirect addressing), it is post-modified by the

value of one of four possible modify registers. A length

value may be associated with each pointer to implement

automatic modulo addressing for circular buffers.

Efficient data transfer is achieved with the use of five in-

ternal buses:

flag. In addition, there are eight flags that are program-

mable as inputs or outputs and three flags that are always

outputs.

A programmable interval timer generates periodic inter-

rupts. A 16-bit count register (T COUNT ) is

decremented every n processor cycle, where n is a scaling

value stored in an 8-bit register (T SCALE). When the

value of the count register reaches zero, an interrupt is

generated and the count register is reloaded from a 16-bit

period register (T PERIOD ).

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

Ser ial P or ts

T he AD73560 incorporates two complete synchronous

serial ports (SPORT 0 and SPORT 1) for serial communi-

cations and multiprocessor communication.

Here is a brief list of the capabilities of the AD73560

SPORT s. For additional information on Serial Ports,

refer to the ADSP-2100 Family User’s Manual, T hird Edition.

• SPORT s are bidirectional and have a separate, double-

buffered transmit and receive section.

• Result (R) Bus

T he two address buses (PMA and DMA) share a single

external address bus, allowing memory to be expanded

off-chip, and the two data buses (PMD and DMD) share a

single external data bus. Byte memory space and I/O

memory space also share the external buses.

Program memory can store both instructions and data,

permitting the AD73560 to fetch two operands in a single

cycle, one from program memory and one from data

memory. T he AD73560 can fetch an operand from pro-

gram memory and the next instruction in the same cycle.

In lieu of the address and data bus for external memory

connection, the AD73560 may be configured for 16-bit

Internal DMA port (IDMA port) connection to external

systems. T he IDMA port is made up of 16 data/address

pins and five control pins. T he IDMA port provides trans-

parent, direct access to the DSPs on-chip program and

data RAM.

An interface to low cost byte-wide memory is provided by

the Byte DMA port (BDMA port). T he BDMA port is

bidirectional and can directly address up to four mega-

bytes of external RAM or ROM for off-chip storage of

program overlays or data tables.

T he byte memory and I/O memory space interface sup-

ports slow memories and I/O memory-mapped peripherals

with programmable wait state generation. External devices

can gain control of external buses with bus request/grant

signals (BR, BGH, and BG). One execution mode (Go

Mode) allows the AD73560 to continue running from on-

chip memory. Normal execution mode requires the pro-

cessor to halt while buses are granted.

• SPORT s can use an external serial clock or generate

their own serial clock internally.

• SPORT s have independent framing for the receive and

transmit sections. Sections run in a frameless mode or

with frame synchronization signals internally or externally

generated. Frame sync signals are active high or inverted,

with either of two pulsewidths and timings.

• SPORT s support serial data word lengths from 3 to 16

bits and provide optional A-law and µ-law companding

according to CCIT T recommendation G.711.

• SPORT receive and transmit sections can generate

unique interrupts on completing a data word transfer.

• SPORT s can receive and transmit an entire circular

buffer of data with only one overhead cycle per data word.

An interrupt is generated after a data buffer transfer.

• SPORT 0 has a multichannel interface to selectively

receive and transmit a 24- or 32-word, time-division mul-

tiplexed,

serial bitstream.

• SPORT 1 can be configured to have two external inter-

rupts (IRQ0 and IRQ1) and the Flag In and Flag Out

signals. T he internally generated serial clock may still be

used in this

configuration.

D SP SE C T IO N P IN D E SC R IP T IO NS

T he AD73560 can respond to eleven interrupts. T here can

be up to six external interrupts (one edge-sensitive, two

level-sensitive and three configurable) and seven internal

interrupts generated by the timer, the serial ports

(SPORT s), the Byte DMA port and the power-down cir-

cuitry. T here is also a master RESET signal. T he two

serial ports provide a complete synchronous serial inter-

face with optional companding in hardware and a wide

variety of framed or frameless data transmit and receive

modes of operation.

Each port can generate an internal programmable serial

clock or accept an external serial clock.

T he AD73560 provides up to 13 general-purpose flag

pins. T he data input and output pins on SPORT 1 can be

alternatively configured as an input flag and an output

T he AD73560 will be available in a 119 ball PBGA pack-

age. In order to maintain maximum functionality and

reduce package size and pin count, some serial port, pro-

grammable flag, interrupt and external bus pins have

dual, multiplexed functionality. T he external bus pins

are configured during RESET only, while serial port

pins are software configurable during program execution.

Flag and interrupt functionality is retained concurrently

on multiplexed pins. In cases where pin functionality is

reconfigurable, the default state is shown in plain text;

alternate functionality is shown in italics. See Pin De-

scriptions on Page 10.

REV. PrA

–2 0 –

Preliminary Technical Data

AD73560

Mem or y In ter face P in s

P in T er m in a tion s

T he AD73560 processor can be used in one of two modes,

Full Memory Mode, which allows BDMA operation with

full external overlay memory and I/O capability, or Host

Mode, which allows IDMA operation with limited exter-

nal addressing capabilities. T he operating mode is deter-

mined by the state of the Mode C pin during RESET and

cannot be changed while the processor is running. See

tables for Full Memory Mode Pins and Host Mode Pins

for descriptions.

I/O

H i- Z*

C a u sed

B y

P in

Na m e

3-State Reset

( Z )

U n u sed

C onfigur ation

State

XT AL

I

O

I

O

H i- Z

Float

C L KO U T

A13:1 or

IAD 12:0

A 0

O (Z)

I/O (Z) H i- Z

O (Z) H i- Z

BR, EBR Float

IS Float

BR, EBR Float

D 23:8

I/O (Z) H i- Z

Full Mem or y Mode P ins (Mode C = 0)

D 7 or

IWR

D 6 or

IRD

D 5 or

IAL

I/O (Z) H i- Z

I

I/O (Z) H i- Z

I

I/O (Z) H i- Z

I

I/O (Z) H i- Z

I

P in

# of Input/

I

H igh (In active)

Nam e(s) P ins Output Function

BR, EBR Float

BR, EBR H igh (In active)

Float

Low (Inactive)

BR, EBR Float

H igh (In active)

BR, EBR Float

Float

A13:0

D 23:0

14

24

O

Address Output Pins for Pro-

gram, Data, Byte and I/O Spaces

I

I /O

Data I/O Pins for Program,

Data, Byte and I/O Spaces (8

MSBs are also used as Byte

Memory addresses)

I

D 4 or

IS

I

D 3 or

IACK

D 2:0 or

IAD 15:13

PMS

DMS

BMS

IOMS

CMS

RD

I/O (Z) H i- Z

BR, EBR Float

IS

H ost Mode P ins (Mode C = 1)

Float

O (Z)

I

O

I

BR, E BR Float

BR, EBR Float

P in

# of Input/

Nam e(s) P ins Output Function

IAD 15:0 16

I /O

O

IDMA Port Address/Data Bus

A0

1

Address Pin for External I/O,

Program, Data or Byte access

W R

BR

B G

BGH

D 23:8

16

I /O

Data I/O Pins for Program, Data

Byte and I/O spaces

H igh (In active)

Float

O (Z)

O

I

E E

IWR

IRD

IAL

IS

1

I

ID M A Write Enable

IDMA Read Enable

IDMA Address Latch Pin

ID M A Select

I

IRQ2/P F 7 I/O (Z)

Input = H igh (Inac-

I

tive)

or P r ogr am as O ut-

I

p u t,

IACK

O

ID MA Port Acknowledge

Configur-able in Mode D; Open

Source

Set to 1, Let Float

Input = H igh (Inac-

IRQL1/P F 6 I/O (Z)

I

tive)

In Host Mode, external peripheral addresses can be decoded using the A0, CMS,

PMS, DMS and IOMS signals

or P r ogr am as O ut-

p u t,

Set to 1, Let Float

Input = H igh (Inac-

T er m in a tin g Un u sed P in

T he following table shows the recommendations for ter-

minating unused pins.

IRQL0/P F 5 I/O (Z)

tive)

or P r ogr am as O ut-

p u t,

Set to 1, Let Float

Input = H igh (Inac-

IRQE/P F 4 I/O (Z)

tive)

or P r ogr am as O ut-

p u t,

Set to 1, Let Float

Input = H igh or

S C LK0

Low,

I/O

O utput = Float

H igh or Low

RF S0

D R 0

I/O

I

REV. PrA

–2 1 –

AD73560

P in T er m in a tion s

T able XIX. Inter r upt P r ior ity and Inter r upt

Vector Addresses

I/O

H i- Z*

C a u sed

B y

P in

3-State Reset

U n u sed

C onfigur ation

Interrupt Vector

Na m e

( Z )

State

Source of Interrupt

Address (H ex)

T F S0

D T 0

S C LK1

I/O

O

I/O

O

I

H igh or Low

Float

RESET (or Power-Up with PUCR = 1)

Priority)

0000 (Highest

Input = H igh or Low,

O utput = Float

H igh or Low

Float

Power-D own (N onmaskable)

IRQ2

IRQL1

002C

0004

0008

000C

0010

0014

0018

001C

0020

0024

R F S 1/RQ0 I/O

D R1/FL1

T F S 1/RQ1 I/O

D T 1/F O

E E

EBR

EBG

ERESET

EMS

EINT

I

O

I

O

I

O

I

IRQL0

SPORT 0 T ransmit

SPORT 0 Receive

IRQE

BD M A Interrupt

SPORT 1 T ransmit or IRQ1

SPORT 1 Receive or IRQ0

T im er

O

I

O

I

O

I

0028 (Lowest Priority)

E C LK

E LIN

E LO U T

I

O

I

O

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially.

Interrupts can be masked or unmasked with the IMASK

register. Individual interrupt requests are logically

ANDed with the bits in IMASK; the highest priority un-

masked interrupt is then selected. T he power-down in-

terrupt is nonmaskable.

NOTES

**Hi-Z = High Impedance.

1. If the CLKOUT pin is not used, turn it OFF.

2. If the Interrupt/Programmable Flag pins are not used, there are two options:

Option 1: When these pins are configured as INPUT S at reset and function as

interrupts and input flag pins, pull the pins High (inactive).

Option 2: Program the unused pins as OUT PUT S, set them to 1, and let them

float.

3. All bidirectional pins have three-stated outputs. When the pins is configured as

an output, the output is Hi-Z (high impedance) when inactive.

4. CLKIN, RESET , and PF3:0 are not included in the table because these pins

must be used.

T he AD73560 masks all interrupts for one instruction

cycle following the execution of an instruction that modi-

fies the IMASK register. T his does not affect serial port

auto-buffering or DMA transfers.

T he interrupt control register, ICNT L, controls interrupt

nesting and defines the IRQ0, IRQ1 and IRQ2 external

interrupts to be either edge- or level-sensitive. T he IRQE

pin is an external edge-sensitive interrupt and can be

forced and cleared. T he IRQL0 and IRQL1 pins are ex-

ternal level-sensitive interrupts.

In t er r u p t s

T he interrupt controller allows the processor to respond

to the eleven possible interrupts and RESET with mini-

mum overhead. T he AD73560 provides four dedicated

external interrupt

input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addi-

tion, SPORT 1 may be reconfigured for IRQ0, IRQ1,

FLAG_IN and FLAG_OUT , for a total of six external

interrupts. T he AD73560 also supports internal interrupts

from the timer, the byte DMA port, the two serial ports,

software and the power-down control circuit. T he inter-

rupt levels are internally prioritized and individually

maskable (except power down and reset). T he IRQ2,

IRQ0 and IRQ1 input pins can be programmed to be

either level- or edge-sensitive. IRQL0 and IRQL1 are

level-

T he IFC register is a write-only register used to force and

clear interrupts. On-chip stacks preserve the processor

status and are automatically maintained during interrupt

handling. The stacks are twelve levels deep to allow inter-

rupt, loop and subroutine nesting. T he following instruc-

tions allow global enable or disable servicing of the

interrupts (including power down), regardless of the state

of IMASK. Disabling the interrupts does not affect serial

port autobuffering or DMA.

ENAINTS;

DIS INTS;

sensitive and IRQE is edge sensitive. T he priorities and

vector addresses of all interrupts are shown in T able XIX.

When the processor is reset, interrupt servicing is enabled.

LO W P O WE R O P E RAT IO N

T he AD73560 has three low power modes that signifi-

cantly reduce the power dissipation when the device oper-

ates under standby conditions. T hese modes are:

• Power-D own

• Idle

• Slow Idle

T he CLKOUT pin may also be disabled to reduce exter-

nal power dissipation.

REV. PrA

–2 2 –

Preliminary Technical Data

AD73560

P ower - D own

When the IDLE (n) instruction is used, it effectively slows

down the processor’s internal clock and thus its response

time to incoming interrupts. T he one-cycle response time

of the standard idle state is increased by n, the clock divi-

sor. When an enabled interrupt is received, the AD73560

will remain in the idle state for up to a maximum of n

processor cycles (n = 16, 32, 64 or 128) before resuming

normal operation.

T he AD73560 processor has a low power feature that lets

the processor enter a very low power dormant state

through hardware or software control. Here is a brief list

of power-down features. Refer to the ADSP-2100 Family User’s

Manual, T hird Edition, “System Interface” chapter, for

detailed information about the power-down feature.

• Quick recovery from power-down. T he processor begins

executing instructions in as few as 400 CLKIN cycles.

When the IDLE (n) instruction is used in systems that have

an externally generated serial clock (SCLK), the serial

clock rate may be faster than the processor’s reduced in-

ternal clock rate. Under these conditions, interrupts must

not be generated at a faster rate than can be serviced, due

to the additional time the processor takes to come out of

the idle state (a maximum of n processor cycles).

• Support for an externally generated T T L or CMOS

processor clock. T he external clock can continue run-

ning during power-down without affecting the 400

CLKIN cycle recovery.

• Support for crystal operation includes disabling the

oscillator to save power (the processor automatically waits

4096 CLKIN cycles for the crystal oscillator to start and

stabilize), and letting the oscillator run to allow 400

CLKIN cycle start up.

S YS T E M INT E R F AC E

Figure 10 shows a typical basic system configuration

with the AD 73560, two serial devices, a byte-wide

EPROM , and

• Power-down is initiated by either the power-down pin

(PWD) or the software power-down force bit Interrupt

support allows an unlimited number of instructions to

be executed before optionally powering down. T he

power-down interrupt also can be used as a non-

maskable, edge-sensitive interrupt.

optional external program and data overlay memories

(mode selectable). Programmable wait state generation

allows the processor to connect easily to slow peripheral

devices. The AD73560 also provides four external inter-

rupts and two serial ports or six external interrupts and

one serial port. Host Memory Mode allows access to the

full external data bus, but limits addressing to a single

address bit (A0) Additional system peripherals can be

added in this mode through the use of external hardware

to generate and latch address signals.

• Context clear/save control allows the processor to con-

tinue where it left off or start with a clean context when

leaving the power-down state.

• T he RESET pin also can be used to terminate power-

down.

C lock Sign a ls

• Power-down acknowledge pin indicates when the pro-

cessor has entered power-down.

T he AD73560 can be clocked by either a crystal or a

T T L-compatible clock signal.

Id le

T he CLKIN input cannot be halted, changed during op-

eration or operated below the specified frequency during

normal operation. T he only exception is while the proces-

sor is in the power-down state. For additional informa-

tion, refer to Chapter 9, ADSP-2100 Family User’s Manual,

Third Edition, for detailed information on this power-down

feature.

When the AD73560 is in the Idle Mode, the processor

waits indefinitely in a low power state until an interrupt

occurs. When an unmasked interrupt occurs, it is serviced;

execution then continues with the instruction following the

IDLE instruction. In Idle Mode IDMA, BDMA and

autobuffer cycle steals still occur.

Slow Idle

If an external clock is used, it should be a T T L-compat-

ible signal running at half the instruction rate. T he signal

is connected to the processor’s CLKIN input. When an

external clock is used, the XT AL input must be left un-

connected.

The IDLE instruction on the AD73560 slows the processor’s

internal clock signal, further reducing power consump-

tion. T he reduced clock frequency, a programmable frac-

tion of the normal clock rate, is specified by a selectable

divisor given in the IDLE instruction. T he format of the

instruction is

IDLE (n);

where n = 16, 32, 64 or 128. T his instruction keeps the

processor fully functional, but operating at the slower

clock rate. While it is in this state, the processor’s other

internal clock signals, such as SCLK, CLKOUT and

timer clock, are reduced by the same ratio. T he default

form of the instruction, when no clock divisor is given, is

the standard IDLE instruction.

REV. PrA

–2 3 –

AD73560

fied by the crystal manufacturer. A parallel-resonant,

fundamental frequency, microprocessor-grade crystal

should be used.

FULL MEMORY MODE

AD73422

14

A

13-0

1/2x CLO CK

OR

CRYSTAL

ADDR13-0

CLKIN

D

A0-A21

23-16

XTAL

BYTE

MEMORY

A clock output (CLKOUT ) signal is generated by the

processor at the processor’s cycle rate. T his can be en-

abled and disabled by the CLK0DIS bit in the SPORT0

Autobuffer Control Register.

D

24

15-8

FL0-2

DATA

DATA23-0

PF3

BM S

CS

IRQ2/PF7

IRQE/PF4

A

10-0

IRQL0/PF5

IRQL1/PF6

ADDR

W R

RD

I/O SPACE

(PERIPHERALS)

D

23-8

MODE C/PF2

MODE B/PF1

MODE A/PF0

DATA

2048

LOCATIONS

IOM S

CS

A

D

13-0

OVERLAY

MEMORY

XTAL

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

CLKIN

CLKOUT

ADDR

DATA

AFE*

SECTION

OR

SERIAL

DEVICE

23-0

TWO 8K

PM SEGMENTS

DSP

PM S

DM S

CM S

TWO 8K

DM SEGMENTS

SPORT0

BR

BG

SCLK0

RFS0

TFS0

DT0

AFE*

SECTION

OR

Figure 11. External Crystal Connections

BGH

SERIAL

DEVICE

Reset

DR0

PW D

T he RESET signal initiates a master reset of the

AD73560. T he RESET signal must be asserted during the

power-up sequence to assure proper initialization. RESET

during initial power-up must be held long enough to allow

the internal clock to stabilize. If RESET is activated any

time after power-up, the clock continues to run and does

not require stabilization time.

PWDACK

HOST MEMORY MODE

AD73422

1

1/2x CLOCK

OR

CRYSTAL

CLKIN

A0

16

XTAL

DATA23-8

FL0-2

PF3

BM S

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

T he power-up sequence is defined as the total time re-

quired for the crystal oscillator circuit to stabilize after a

valid V_DDis applied to the processor, and for the internal

phase-locked loop (PLL) to lock onto the specific crystal

frequency. A minimum of 2000 CLKIN cycles ensures

that the PLL has locked, but does not include the crystal

oscillator start-up time. During this power-up sequence

the RESET signal should be held low. On any subsequent

resets, the RESET signal must meet the minimum

MODE C/PF2

MODE B/PF1

MODE A/PF0

W R

RD

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

IOM S

AFE*

SECTION

OR

SERIAL

DEVICE

PM S

DM S

CM S

DR1 OR FI

SPORT0

pulsewidth specification, t_RSP

.

BR

BG

AFE*

SECTION

OR

SERIAL

DEVICE

SCLK0

RFS0

TFS0

DT0

T he RESET input contains some hysteresis; however, if

an RC circuit is used to generate the RESET signal, an

external Schmidt trigger is recommended.

BGH

DR0

PW D

PWDACK

IDMA PORT

IRD/D6

T he master reset sets all internal stack pointers to the

empty stack condition, masks all interrupts and clears the

MST AT register. When RESET is released, if there is no

pending bus request and the chip is configured for boot-

ing, the boot-loading sequence is performed. T he first

instruction is fetched from on-chip program memory

location 0x0000 once boot loading completes.

IW R/D7

IS/D4

IAL/D5

IACK/D3

SYSTEM

INTERFACE

OR

*AFE SECTION CAN BE

CONNECTED TO EITHER

SPORT0 OR SPORT1

␮CONTROLLER

16

IAD15-0

Figure 10. AD73560 Basic System Configuration

T he AD73560 uses an input clock with a frequency equal

to half the instruction rate; a 26.00 MHz input clock

yields a 19 ns processor cycle (which is equivalent to 52

MH z). Normally, instructions are executed in a single

processor cycle. All device timing is relative to the inter-

nal instruction clock rate, which is indicated by the

CLKOUT signal when enabled.

M O D E S O F O P E R AT IO N

T able XX summarizes the AD73560 memory modes.

Settin g M em or y M ode

Memory Mode selection for the AD73560 is made during

chip reset through the use of the Mode C pin. T his pin is

multiplexed with the DSP’s PF2 pin, so care must be

taken in how the mode selection is made. T he two meth-

ods for selecting the value of Mode C are active and pas-

sive.

Because the AD73560 includes an on-chip oscillator cir-

cuit, an external crystal may be used. The crystal should be

connected across the CLKIN and XTAL pins, with two

capacitors connected as shown in Figure 11. Capacitor

values are dependent on crystal type and should be speci-

P assive configur ation involves the use a pull-up or pull-

down resistor connected to the Mode C pin. T o minimize

REV. PrA

–2 4 –

Preliminary Technical Data

AD73560

Table XXI. Modes of O per ations¹

MO D E C²MO D E B³MO D E A⁴Booting Method

0

1

0

1

0

BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have been

loaded. Chip is configured in Full Memory Mode.⁵

No Automatic boot operations occur. Program execution starts at external

memory location 0. Chip is configured in Full Memory Mode. BDMA can still

be used, but the processor does not automatically use or wait for these operations.

BDMA feature is used to load the first 32 program memory words from the

byte memory space. Program execution is held off until all 32 words have been

loaded. Chip is configured in H ost Mode. (RE Q UIRE S AD D IT IO NAL

H ARD WARE .)

1

0

1

IDMA feature is used to load any internal memory as desired. Program execu-

tion is held off until internal program memory location 0 is written to. Chip is

configured in Host Mode.⁵

NOTES

¹All mode pins are recognized while RESET is active (low).

²When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.

³When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.

⁴When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.

⁵Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

power consumption, or if the PF2 pin is to be used as an

AD73560-80 has 16K words of Program Memory RAM

output in the DSP application, a weak pull-up or pull-

down, on the order of 100 ký, can be used. T his value

should be sufficient to pull the pin to the desired level and

still allow the pin to operate as

a programmable flag output without undue strain on the

processor’s output driver. For minimum power consump-

tion during power-down, reconfigure PF2 to be an input,

as the pull-up or pull-down will hold the pin in a known

state, and will not switch.

on chip (the AD73560-40 has 8K words of Program

Memory RAM on chip), and the capability of accessing up

to two 8K external memory overlay spaces using the exter-

nal data bus.

P r ogr am Mem or y (H ost Mode) allows access to all inter-

nal memory. External overlay access is limited by a single

external address line (A0). External program execution is

not available in host mode due to a restricted data bus that

is 16-bits wide only.

Active configur ation involves the use of a three-statable

external driver connected to the Mode C pin. A driver’s

output enable should be connected to the DSP’s RESET

signal such that it only drives the PF2 pin when RESET is

active (low). When RESET is deasserted, the driver

should three-state, thus allowing full use of the PF2 pin as

either an input or output. T o minimize power consump-

tion during power-down, configure the programmable flag

as an output when connected to a three-stated buffer. T his

ensures that the pin will be held at a constant level and not

oscillate should the three-state driver’s level hover around

the logic switching point.

Table XXI. P MO VLAY Bits

P MO VLAY Mem or y A13

A12:0

0,

1

Internal

External

N ot Applicable N ot Applicable

0

1

13 LSBs of Ad

dress

Between 0x2000

and 0x3FFF

Overlay 1

2

External

13 LSBs of Ad

dress

Overlay 2

Between 0x2000

and 0x3FFF

M E M O R Y AR C H IT E C T U R E

T he AD73560 provides a variety of memory and periph-

eral interface options. T he key functional groups are Pro-

gram Memory, Data Memory, Byte Memory, and I/O.

Refer to the following figures and tables for PM and DM

memory allocations in the AD73560.

P R O G R AM M E M O R Y

P r ogr am Mem or y (Full Mem or y Mode) is a 24-bit-wide

space for storing both instruction opcodes and data. T he

REV. PrA

–2 5 –

AD73560

1

PM (MODE

B = 0)

PM (MODE B = 1)

RESERVED

Table XXII. D MO VLAY Bits

ALWAYS

ACCESSIBLE

AT ADDRESS

D MO VLAY Mem ory A13

A12:0

0x 2 0 0 0 -

INTERNAL

MEMORY

0x 0000 -0 x 1FFF

INTERNAL

MEMORY

0 x 3 F F F

ACCESSIBLE WHEN

0x 2 0 0 0 -

0,

Internal N ot Applicable N ot Applicable

3

PMOVLAY = 0

0x 0 0 0 0 -

0 x 3 F FF

ACCESSIBLE WHEN

2

0 x 1 F F F

3

PMOVLAY = 0

1

External

0

1

13 LSBs of Ad-

0x 2 0 0 0 -

ACCESSIBLE WHEN

PMOVLAY = 0

2

0 x 3 F F F

dress

ACCESSIBLE WHEN

PMOVLAY = 1

0x 2 0 0 0 -

EXTERNAL

MEMORY

RESERVED

Overlay 1

Between 0x2000

and 0x3FFF

2

0 x 3 F F F

EXTERNAL

MEMORY

ACCESSIBLE WHEN

PMOVLAY = 2

1

2

WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0

SEE TABLE III FOR PMOVLAY BITS

2

External

13 LSBs of Ad-

3

NOT ACCESSIBLE ON AD73422-40

dress

PROGRAM MEMORY

MODE

PROGRAM MEMORY

Overlay 2

Between 0x2000

and 0x3FFF

ADDRESS

B

=

0

ADDRESS

MODE B = 1

0x 3FFF

8K INTERNAL

3

PMOVLAY

OR

=

0

8K INTERNAL

3

I/O Space (Full Mem or y Mode)

PMOVLAY

= 0

8K EXTERNAL

PMOVLAY OR 2

=

1

T he AD73560 supports an additional external memory

space called I/O space. T his space is designed to support

simple connections to peripherals (such as data converters

and external registers) or to bus interface ASIC data reg-

isters. I/O space supports 2048 locations of 16-bit wide

data. T he lower eleven bits of the external address bus are

used; the upper three bits are undefined. T wo instructions

were added to the core ADSP-2100 Family instruction set

to read from and write to I/O memory space. T he I/O

space also has four dedicated 3-bit wait state registers,

IOWAIT 0-3, that specify up to seven wait states to be

automatically generated for each of four regions. T he wait

states act on address ranges as shown in T able XXIII.

0x 2000

0x 1FFF

0x 2000

0x 1FFF

8K EXTERNAL

8K INTERNAL

0x 0000

Figure 12. Program Mem ory Map

D AT A M E M O R Y

D ata Mem or y (Full Mem or y Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-

mapped control registers. T he AD73560-80 has 16K

words on Data Memory RAM on chip (the AD73560-40

has 8K words on Data Memory RAM on chip), consisting

of 16,352 user-accessible locations in the case of the

AD73560-80 ( 8,160 user-accessible locations in the case

of the AD73560-40) and 32 memory-mapped registers.

Support also exists for up to two 8K external memory

overlay spaces through the external data bus. All internal

accesses complete in one cycle. Accesses to external

memory are timed using the wait states specified by the

D WAIT register.

Table XXIII. Wait States

Address Range

Wait State Register

0x000–0x1F F

0x200–0x3F F

0x400–0x5F F

0x600–0x7F F

IO W AIT 0

IO W AIT 1

IO W AIT 2

IO W AIT 3

C om p osite M em or y Select (CMS)

DATA MEMORY

ADDRESS

DATA MEMORY

T he AD73560 has a programmable memory select signal

that is useful for generating memory select signals for

memories mapped to more than one space. T he CMS

signal is generated to have the same timing as each of the

individual memory select signals (PMS, DMS, BMS,

IOMS) but can combine their functionality.

32 MEMORY

MAPPED

0

x

3FFF

ALWAYS

ACCESSIBLE

AT ADDRESS

REGISTERS

0

x

3FE0

3FDF

0

x

0x2000 - 0x3FFF

INTERNAL

8160

WORDS

INTERNAL

MEMORY

0

x

0000-

1FFF

0

x

2000

1FFF

ACCESSIBLE WHEN

DMOVLAY = 0

0

x

0x

0000-

1FFF

8K INTERNAL

DMOVLAY = 0

OR

EXTERNAL 8K

DMOVLAY = 1, 2

0

x

ACCESSIBLE WHEN

DMOVLAY = 1

0

x

0000-

1FFF

Each bit in the CMSSEL register, when set, causes the

CMS signal to be asserted when the selected memory

select is asserted. For example, to use a 32K word

memory to act as both program and data memory, set the

PMS and DMS bits in the CMSSEL register and use the

CMS pin to drive the chip select of the memory; use

either DMS or PMS as the additional address bit.

EXTERNAL

MEMORY

0

x

0000

ACCESSIBLE WHEN

DMOVLAY = 2

Figure 13. Data Mem ory Map

Data Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single

external address line (A0). T he DMOVLAY bits are de-

fined in T able XXII.

T he CMS pin functions like the other memory select

signals, with the same timing and bus request logic. A 1

in the enable bit causes the assertion of the CMS signal at

REV. PrA

–2 6 –

Preliminary Technical Data

AD73560

the same time as the selected memory select signal. All

enable bits default to 1 at reset, except the BMS bit.

memory space to build the word size selected. T able

XXIV shows the data formats supported by the BDMA

circuit.

Boot Mem or y Select (BMS) D isable

T he AD73560 also lets you boot the processor from one

external memory space while using a different external

memory space for BDMA transfers during normal opera-

tion. You can use the CMS to select the first external

memory space for BDMA transfers and BMS to select the

second external memory space for booting. T he BMS

signal can be disabled by setting Bit 3 of the System Con-

trol Register to 1. T he System Control Register is illus-

trated in Figure 14.

T able XXIV. D ata F or m ats

Internal

BTYP E

Mem ory Space

Word Size

Alignm ent

00

01

10

11

Program M emory 24

Full Word

M SBs

D ata M emory

16

8

L SBs

Unused bits in the 8-bit data memory formats are filled

with 0s. T he BIAD register field is used to specify the

starting address for the on-chip memory involved with the

transfer. T he 14-bit BEAD register specifies the starting

address for the external byte memory space. T he 8-bit

BMPAGE register specifies the starting page for the ex-

ternal byte memory space. T he BDIR register field selects

the direction of the transfer. Finally the 14-bit

SYSTEM CONTROL REGISTER

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

1

0

1

DM (0

؋

3FFF)

SPORT0 ENABLE

1 = ENABLED

PWAIT

PROGRAM MEMORY

WAIT STATES

0 = DISABLED

SPORT1 ENABLE

1 = ENABLED

BM S ENABLE

0 = ENABLED

1 = DISABLED

0 = DISABLED

SPORT1 CONFIGURE

1 = SERIAL PORT

0 = F I, FO, IRQ0,

IRQ1, SCLK

BWCOUNT register specifies the number of DSP words

to transfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequen-

tial addressing. A BDMA interrupt is generated on the

completion of the number of transfers specified by the

BWC O U N T register.

Figure 14. System Control Register

B yte M em or y

T he byte memory space is a bidirectional, 8-bit-wide,

external memory space used to store programs and data.

Byte memory is accessed using the BDMA feature. T he

BDMA Control Register is shown in Figure 15. T he byte

memory space consists of 256 pages, each of which is

16K X 8.

T he byte memory space on the AD73560 supports read

and write operations as well as four different data formats.

T he byte memory uses data bits 15:8 for data. T he byte

memory uses data bits 23:16 and address bits 13:0 to cre-

ate a 22-bit address. T his allows up to a 4 meg ´ 8 (32

megabit) ROM or RAM to be used without glue logic. All

byte memory accesses are timed by the BMWAIT register.

T he BWCOUNT register is updated after each transfer so

it can be used to check the status of the transfers. When it

reaches zero, the transfers have finished and a BDMA

interrupt is generated. T he BMPAGE and BEAD registers

must not be accessed by the DSP during BDMA opera-

tions.

T he source or destination of a BDMA transfer will always

be on-chip program or data memory.

When the BWCOUNT register is written with a nonzero

value, the BDMA circuit starts executing byte memory

accesses with wait states set by BMWAIT . T hese accesses

continue until the count reaches zero. When enough ac-

cesses have occurred to create a destination word, it is

transferred to or from on-chip memory. T he transfer takes

one DSP cycle. DSP accesses to external memory have

priority over BDMA byte memory accesses.

Byte Mem or y D MA (BD MA, Full Mem or y Mode)

T he Byte memory DMA controller allows loading and

storing of program instructions and data using the byte

memory space. T he BDMA circuit is able to access the

byte memory space while the processor is operating nor-

mally, and steals only one DSP cycle per 8-, 16- or 24-bit

word transferred.

T he BDMA Context Reset bit (BCR) controls whether or

not the processor is held off while the BDMA accesses are

occurring. Setting the BCR bit to 0 allows the processor

to continue operations. Setting the BCR bit to 1 causes

the processor to stop execution while the BDMA accesses

are occurring, to clear the context of the processor and

start execution at address 0 when the BDMA accesses have

completed.

BDMA CONTROL

15 14 13 12 11 10

9

8

7

6

5

0

4

0

3

1

2

0

1

0

DM (0

؋

3FE3)

0

BTYPE

BDIR

BMPAGE

0 = LOAD FROM BM

1 = STORE TO BM

T he BDMA overlay bits specify the OVLAY memory

blocks to be accessed for internal memory.

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

Inter n a l M em or y D M A P or t (ID M A P or t; H ost

M em or y M od e)

Figure 15. BDMA Control Register

T he IDMA Port provides an efficient means of communi-

cation between a host system and the AD73560. T he port

is used to access the on-chip program memory and data

memory of the DSP with only one DSP cycle per word

T he BDMA circuit supports four different data formats

that are selected by the BT YPE register field. T he appro-

priate number of 8-bit accesses are done from the byte

REV. PrA

–2 7 –

AD73560

overhead. T he IDMA port cannot be used, however, to

write to the DSP’s memory-mapped control registers. A

typical IDMA transfer process is described as follows:

T he IDMA OVLAY and address are stored in separate

memory-mapped registers. T he IDMAA register, shown

below, is memory mapped at address DM (0x3FE0). Note

that the latched address (IDMAA) cannot be read back by

the host. T he IDM A OVLAY register is memory

mapped at address DM (0x3FE7). See Figure 16 for

more information on IDMA and DMA memory maps.

1. H ost starts IDMA transfer.

2. Host checks IACK control line to see if the DSP is

busy.

3. Host uses IS and IAL control lines to latch either the

DMA starting address (IDMAA) or the PM/DM

OVLAY selection into the DSP’s IDMA control regis-

ters.

IDMA CONTROL (U = UNDEFINED AT RESET)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DM(0

؋

3FE0)

U

IDMAA ADDRESS

If IAD[15] = 1, the value of IAD[7:0] represent the

IDMA overlay: IAD[14:8] must be set to 0.

IDMAD

DESTINATION MEMORY TYPE:

0 = PM

1 = DM

If IAD[15] = 0, the value of IAD[13:0] represent the

starting address of internal memory to be accessed and

IAD[14] reflects PM or DM for access.

Figure 16. IDMA Control/OVLAY Registers

B ootstr a p Loa d in g (B ootin g)

4. Host uses IS and IRD (or IWR) to read (or write) DSP

T he AD73560 has two mechanisms to allow automatic

loading of the internal program memory after reset. T he

method for booting after reset is controlled by the Mode

A, B and C configuration bits.

internal memory (PM or DM).

5. Host checks IACK line to see if the DSP has completed

the previous IDMA operation.

6. Host ends IDMA transfer.

When the mode pins specify BDMA booting, the

AD73560 initiates a BDMA boot sequence when reset is

released.

T he IDMA port has a 16-bit multiplexed address and data

bus and supports 24-bit program memory. T he ID M A

port is

completely asynchronous and can be written to while the

AD73560 is operating at full speed.

T he BDMA interface is set up during reset to the follow-

ing defaults when BDMA booting is specified: the BDIR,

BMPAGE, BIAD and BEAD registers are set to 0, the

BT YPE register is set to 0 to specify program memory

24-bit words, and the BWCOUNT register is set to 32.

T his causes 32 words of on-chip program memory to be

loaded from byte memory. T hese 32 words are used to set

up the BDMA to load in the remaining program code.

T he BCR bit is also set to 1, which causes program ex-

ecution to be held off until all 32 words are loaded into

on-chip program memory. Execution then begins at ad-

dress 0.

T he DSP memory address is latched and then automati-

cally incremented after each IDMA transaction. An exter-

nal device can therefore access a block of sequentially

addressed memory by specifying only the starting address

of the block. T his increases throughput as the address does

not have to be sent for each memory access.

IDMA Port access occurs in two phases. T he first is the

IDMA Address Latch cycle. When the acknowledge is

asserted, a

T he AD SP-2100 Family D evelopment Software (Revision

5.02 and later) fully supports the BDMA booting feature

and can generate byte memory space compatible boot

code.

14-bit address and 1-bit destination type can be driven

onto the bus by an external device. T he address specifies

an on-chip memory location; the destination type specifies

whether it is a DM or PM access. T he falling edge of the

address latch signal latches this value into the IDMAA

register.

T he IDLE instruction can also be used to allow the pro-

cessor to hold off execution while booting continues

through the BDMA interface. For BDMA accesses while

in Host Mode, the addresses to boot memory must be

constructed externally to the AD73560. T he only memory

address bit provided by the processor is A0.

Once the address is stored, data can either be read from or

written to the AD73560’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD

and IWR respectively) signals the AD73560 that a particu-

lar transaction is required. In either case, there is a one-

processor-cycle delay for synchronization. T he memory

access consumes one additional processor cycle.

ID M A P or t Bootin g

T he AD73560 can also boot programs through its Internal

DMA port. If Mode C = 1, Mode B = 0 and Mode A =

1, the AD73560 boots from the IDMA port. IDMA fea-

ture can load as much on-chip memory as desired. Pro-

gram execution is held off until on-chip program memory

location 0 is written to.

Once an access has occurred, the latched address is auto-

matically incremented and another access can occur.

T hrough the IDMAA register, the DSP can also specify

the starting address and data format for DMA operation.

Asserting the IDMA port select (IS) and address latch

enable (IAL) directs the AD73560 to write the address

onto the IAD0–14 bus into the ID M A Control Register.

If IAD[15] is set to 0, IDMA latches the address. If

IAD [15] is set to 1, ID M A latches OVLAY memory.

Bus Request and Bus Gr ant (Full Mem or y Mode)

T he AD73560 can relinquish control of the data and ad-

dress buses to an external device. When the external de-

vice requires access to memory, it asserts the bus request

(BR) signal. If the AD73560 is not performing an external

REV. PrA

–2 8 –

Preliminary Technical Data

AD73560

memory access, it responds to the active BR input in the

following processor cycle by:

arithmetic add instruction, such as AR = AX0 + AY0,

resembles a simple equation.

• three-stating the data and address buses and the PMS,

DMS, BMS, CMS, IOMS, RD, WR output drivers,

• Every instruction assembles into a single, 24-bit word

that can execute in a single instruction cycle.

• asserting the bus grant (BG) signal, and

• T he syntax is a superset ADSP-2100 Family assembly

language and is completely source and object code compat-

ible with other family members. Programs may need to be

relocated to utilize on-chip memory and conform to the

AD73560’s interrupt vector and reset vector map.

• halting program execution.

If Go Mode is enabled, the AD73560 will not halt pro-

gram execution until it encounters an instruction that

requires an external memory access.

• Sixteen condition codes are available. For conditional

jump, call, return or arithmetic instructions, the condition

can be checked and the operation executed in the same

instruction cycle.

If the AD73560 is performing an external memory access

when the external device asserts the BR signal, it will not

three-state the memory interfaces or assert the BG signal

until the processor cycle after the access completes. T he

instruction does not need to be completed when the bus is

granted. If a single instruction requires two external

memory accesses, the bus will be granted between the two

accesses.

• Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches or one write

to processor memory space during a single instruction

cycle.

When the BR signal is released, the processor releases the

BG signal, reenables the output drivers and continues

program execution from the point at which it stopped.

D E SIG NING AN E Z- IC E - C O M P AT IB LE SYST E M

T he AD73560 has on-chip emulation support and an ICE-

Port, a special set of pins that interface to the EZ-ICE.

T hese features allow in-circuit emulation without replacing

the target system processor by using only a 14-pin connec-

tion from the target system to the EZ-ICE. T arget systems

must have a 14-pin connector to accept the EZ-ICE’s in-

circuit probe, a 14-pin plug. See the ADSP-2100 Family

EZ-T ools data sheet for complete information on ICE

products.

Issuing the chip reset command during emulation causes

the DSP to perform a full chip reset, including a reset of

its memory mode. T herefore, it is vital that the mode pins

are set correctly PRIOR to issuing a chip reset command

from the emulator user interface. If you are using a passive

method of maintaining mode information (as discussed in

Setting Memory Modes) then it does not matter that the

mode information is latched by an emulator reset. How-

ever, if you are using the RESET pin as a method of set-

ting the value of the mode pins, then you have to take into

consideration the effects of an emulator reset.

T he bus request feature operates at all times, including

when the processor is booting and when RESET is active.

T he BGH pin is asserted when the AD73560 is ready to

execute an instruction, but is stopped because the external

bus is already granted to another device. T he other device

can release the bus by deasserting bus request. Once the

bus is released, the AD73560 deasserts BG and BGH and

executes the external memory access.

Flag I/O P ins

T he AD73560 has eight general purpose programmable

input/output flag pins. T hey are controlled by two

memory mapped registers. T he PFT YPE register deter-

mines the direction, 1 = output and 0 = input. T he

PFDAT A register is used to read and write the values on

the pins. Data being read from a pin configured as an input

is synchronized to the AD73560’s clock. Bits that are pro-

grammed as outputs will read the value being output. T he

PF pins default to input during reset.

One method of ensuring that the values located on the

mode pins are those desired is to construct a circuit like

the one shown in Figure 17. T his circuit forces the value

located on the Mode A pin to logic high; regardless if it

latched via the RESET or ERESET pin.

In addition to the programmable flags, the AD 73560

has five fixed-mode flags, FLAG_IN , FLAG_OUT ,

FL0, FL1 and FL2. FL0-FL2 are dedicated output

flags. FLAG _IN and FLAG_OUT are available as an

alternate configuration of SPORT 1.

ERES ET

RESET

Note: Pins PF0, PF1, PF2 and PF3 are also used for

device configuration during reset.

AD73560

INS T R U C T IO N S E T D E S C R IP T IO N

1KΩ

T he AD73560 assembly language instruction set has an

algebraic syntax that was designed for ease of coding and

readability. T he assembly language, which takes full ad-

vantage of the processor’s unique architecture, offers the

following benefits:

MODE A /PFO

PROG RAMMABLE I/O

Figure 17. Mode A Pin/EZ-ICE Circuit

• T he algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical

REV. PrA

–2 9 –

AD73560

T a r get M em or y In ter fa ce

T he ICE-Port interface consists of the following

AD 73560 pins:

For your target system to be compatible with the EZ-ICE

emulator, it must comply with the memory interface

guidelines listed below.

E BR

E BG

E R E SE T

E IN T

E L IN

E E

E M S

E C L K

E L O U T

P M, D M, BM, IO M and C M

Design your Program Memory (PM), Data Memory

(DM), Byte Memory (BM), I/O Memory (IOM) and

Composite Memory (CM) external interfaces to comply

with worst case

device timing requirements and switching characteristics

as specified in the DSP’s data sheet. T he performance of

the EZ-ICE may approach published worst case specifica-

tion for some memory access timing requirements and

switching

T hese AD73560 pins must be connected only to the EZ-

ICE connector in the target system. T hese pins have no

function except during emulation, and do not require

pull-up or pull-down resistors. T he traces for these signals

between the AD73560 and the connector must be kept as

short as possible, no longer than three inches.

T he following pins are also used by the EZ-ICE:

BR

B G

characteristics.

RE SE T

G N D

Note: If your target does not meet the worst case chip

specification for memory access parameters, you may not

be able to emulate your circuitry at the desired CLKIN

frequency. Depending on the severity of the specification

violation, you may have trouble manufacturing your sys-

tem as DSP components statistically vary in switching

characteristic and timing requirements within published

lim its.

T he EZ-ICE uses the EE (emulator enable) signal to take

control of the AD73560 in the target system. T his causes

the processor to use its ERESET , EBR and EBG pins

instead of the RESET, BR and BG pins. T he BG output

is three-stated. T hese signals do not need to be jumper-

isolated in your system.

T he EZ-ICE connects to your target system via a ribbon

cable and a 14-pin female plug. T he ribbon cable is 10

inches in length with one end fixed to the EZ-ICE. T he

female plug is plugged onto the 14-pin connector (a pin

strip header) on the target board.

Restr iction: All memory strobe signals on the AD73560

(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in

your target system must have 10 kW pull-up resistors con-

nected when the EZ-ICE is being used. T he pull-up resis-

tors are necessary because there are no internal pull-ups to

guarantee their state during prolonged three-state condi-

tions resulting from typical EZ-ICE debugging sessions.

T hese resistors may be removed at your option when the

EZ-ICE is not being used.

Tar get Boar d C onnector for E Z-IC E P r obe

T he EZ-ICE connector (a standard pin strip header) is

shown in Figure 18. You must add this connector to your

target board design if you intend to use the EZ-ICE. Be

sure to allow enough room in your system to fit the EZ-

ICE probe onto the 14-pin connector.

T ar get System In ter face Sign als

When the EZ-ICE board is installed, the performance on

some system signals changes. Design your system to be

compatible with the following system interface signal

changes introduced by the EZ-ICE board:

1

3

5

2

4

BG

GND

EBG

BR

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the RE-

SET

signal.

6

EBR

EINT

ELIN

7

؋

8

KEY (NO PIN)

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the BR

signal.

10

12

14

9

ELOUT

EE

ECLK

11

13

EMS

• EZ-ICE emulation ignores RESET and BR when single-

stepping.

RESET

ERESET

• EZ-ICE emulation ignores RESET and BR when in

Emulator Space (DSP halted).

TOP VIEW

• EZ-ICE emulation ignores the state of target BR in

certain modes. As a result, the target system may take

control of the DSP’s external memory bus only if bus

grant (BG) is asserted by the EZ-ICE board’s DSP.

Figure 18. Target Board Connector for EZ-ICE

T he 14-pin, 2-row pin strip header is keyed at the Pin 7

location—you must remove Pin 7 from the header. T he

pins must be 0.025 inch square and at least 0.20 inch in

length. Pin spacing should be 0.1 x 0.1 inches. T he pin

strip header must have at least 0.15 inch clearance on all

sides to accept the EZ-ICE probe plug.

Pin strip headers are available from vendors such as 3M,

McKenzie and Samtec.

REV. PrA

–3 0 –

Preliminary Technical Data

AD73560

D evice O p er a tion

F LASH M E M O R Y D E SC R IP T IO N

T he AD73560’s page mode EEPROM offers in-circuit

electrical write capability. T he AD73560 does not require

separate erase and program operations. T he internally

timed write cycle executes both erase and program trans-

parently to the user. T he AD73560 has industry standard

optional Software Data Protection, which is recommended

to be always enabled.

T he AD73560 features a 64K x 8 CMOS page mode

EEPROM which can be written with a 3.0-volt-only

power supply. Internal erase/program is transparent to the

user.

Featuring high performance page write, the AD73560’s

flash memory provides a typical byte-write time of 39

µsec. T he entire memory, i.e., 64K bytes, can be written

page by page in as little as 2.5 seconds, when using inter-

face features such as T oggle Bit or Data Polling to indi-

cate the completion of a write cycle. T o protect against

inadvertent write, the AD73560 has on-chip hardware and

software data protection schemes.

Rea d

T he read operation of the AD73560 is controlled by BMS

and RD, both have to be low for the DSP section to obtain

data from the flash section. BMS is used for device selec-

tion. When BMS is high, the flash memory is deselected

and only standby power is consumed. RD is the output

control and is used to gate data from the flash output pins.

T he data bus is in high impedance state when either BMS

or RD is high. Refer to the read cycle timing diagram

(Figure 21) for further details.

T he AD73560’s flash memory has a guaranteed page-

write endurance of 10⁴or 10³cycles. Data retention is

rated at greater than 100 years. T he AD73560 is suited

for applications that require convenient and economical

updating of program, configuration, or data memory.

Wr it e

F la sh M em or y C on n ection

T he write operation consists of three steps. T he first step

is the optional three byte load sequence for Software Data

Protection. T his is an optional first step in the write op-

eration, but highly recommended to ensure proper data

integrity. Step 2 is the byte-load cycle to a page buffer of

the flash. Step 3 is an internally controlled write cycle for

writing the data loaded in the page buffer into the memory

array for nonvolatile storage. During the byte-load cycle,

the addresses are latched by the falling edge of either

BMS or WR, whichever occurs last. T he data is latched by

the rising edge of either BMS or WR, whichever occurs

first. T he internal write cycle is initiated by a timer after

the rising edge of WR or BMS, whichever occurs first.

T he write cycle, once initiated, will continue to comple-

tion, typically within 5 ms. See Figures 22 and 23 for WR

and BMS controlled page write cycle timing diagrams.

T he write operation has three functional cycles: the op-

tional Software Data Protection load sequence, the page

T he flash memory section of the AD73560 is configured

on the byte-wide DMA bus (BDMA) of the DSP section

as shown in Figure 19. Hence if boot operation is re-

quired from the AD73560’s internal flash memory, the

boot mode selection pins Mode A, Mode B and Mode C

should be set to zero (0).

AD73560

A

D

15

14

17

ADDRESS [14-15]

ADDRESS [0-13]

A

D

A

16

13

DSP

BYTE

A

0

SECTION

MEMORY

-FLASH

D

DB

15

7

0

DATA [0-7]

D

8

64 kbytes

BM S

W R

RD

CE

WE

OE

Figure 19. Flash Interface to DSP section

X-Decoder

512 kbit

EEPROM

Cell Array

Address Bus (A

)

0-15

Address Buffer

& Latches

Y-Decoder

& Page Latches

CE

O E

W E

Control Block

I/O Buffers

& Data Latches

Data Bus (DB

)

0-7

Figure 20. Flash Mem ory Organisation

–3 1 –

REV. PrA

AD73560

load cycle and the internal write cycle. T he Software Data

Protection consists of a specific three byte load sequence

that will leave the AD73560 protected at the end of the

page write. T he page load cycle consists of loading 1 to

128 bytes of data into the page buffer. T he internal write

cycle consists of the T_BLCOtimeout and the write timer

operation. During the write operation, the only valid reads

are Data Polling and T oggle Bit. T he page-write opera-

tion allows the loading of up to 128 bytes of data into the

page buffer of the AD73560 flash before the initiation of

the internal write cycle. During the internal write cycle,

all the data in the page buffer is written simultaneously

into the memory array. Hence, the page-write feature of

AD73560 allows the entire memory to be written in as

little as 2.5 seconds. During the internal write cycle, the

host is free to perform additional tasks, such as to fetch

data from other locations in the system to set up the write

to the next page. In each page-write operation, all the

bytes that are loaded into the page buffer must have the

same page address, i.e., A7 through A15. Any byte not

loaded with user data will be written to FF. See Figures

22 and 23 for the page-write cycle timing diagrams. If

after the initial byte-load cycle, the host loads a second

byte into the page buffer within a byte-load cycle time

(T_BLC) of 100 µs, the AD73560 will stay in the page load

cycle. Additional bytes are then loaded consecutively. T he

page load cycle will be terminated if no additional byte is

loaded into the page buffer within 200 µs (T _BLCO) from the

last byte-load cycle, i.e., no subsequent WR or BMS high-

to-low transition after the last rising edge of WR or BMS.

Data in the page buffer can be changed by a subsequent

byte-load cycle. T he page load period can continue indefi-

nitely, as long as the host continues to load the device

within the byte-load cycle time of 100 µs. T he page to be

loaded is determined by the page address of the last byte

loaded.

true data. T he device is then ready for the next operation.

See Figure 24 for Data Polling timing diagram.

Toggle Bit (D Q 6)

During the internal write cycle, any consecutive attempts

to read DQ6 will produce alternating 0’s and 1’s, i.e.,

toggling between 0 and 1. When the write cycle is com-

pleted, the toggling will stop. T he device is then ready for

the next operation. See Figure 25 for T oggle Bit timing

diagram. T he initial read of the T oggle Bit will be a “1”.

D a t a P r ot ect ion

T he AD73560 provides both hardware and software fea-

tures to protect nonvolatile data from inadvertent writes.

H a r d wa r e D a ta P r otection

Noise/Glitch Protection: A WR or BMS pulse of less than

5 ns will not initiate a write cycle. VDD Power Up/Down

Detection: T he write operation is inhibited when VDD is

less than 2.5V.

Write Inhibit Mode: Forcing RD low, BMS high, or WR

high will inhibit the write operation. T his prevents inad-

vertent writes during power-up or power-down.

Softwa r e Da ta Pr otection (SDP)

T he AD73560 flash-memory provides the JEDEC ap-

proved optional software data protection scheme for all

data alteration operations, i.e., write and chip erase. With

this scheme, any write operation requires the inclusion of

a series of three byte-load operations to precede the data

loading operation. T he three byte-load sequence is used

to initiate the write cycle, providing optimal protection

from inadvertent write operations, e.g., during the system

power-up or power-down. T he AD73560 is shipped with

the software data protection disabled. T he software pro-

tection scheme can be enabled by applying a three-byte

sequence to the device, during a page-load cycle (Figures

22 and 23). T he device will then be automatically set into

the data protect mode. Any subsequent write operation

will require the preceding three-byte sequence. See Fig-

ures 22 and 23 for the timing diagrams. T o set the device

into the unprotected mode, a six-byte sequence is re-

quired. See Figure 26 for the timing diagram. If a write

is attempted while SDP is enabled the device will be in a

non-accessible state for ~ 300 µs. It is recommended that

Software Data Protection always be enabled.

Wr ite O per ation Statu s D etection

T he AD73560 provides two software means to detect the

completion of a write cycle, in order to optimize the sys-

tem write cycle time. T he software detection includes two

status bits: Data Polling (DQ7) and T oggle Bit (DQ6).

T he end of write detection mode is enabled after the rising

WE or CE whichever occurs first, which initiates the in-

ternal write cycle. T he actual completion of the nonvola-

tile write is asynchronous with the system; therefore, either

a Data Polling or T oggle Bit read may be simultaneous

with the completion of the write cycle. If this occurs, the

system may possibly get an erroneous result, i.e., valid

data may appear to conflict with either DQ7 or DQ6. In

order to prevent spurious rejection, if an erroneous result

occurs, the software routine should include a loop to read

the accessed location an additional two (2) times. If both

reads are valid, then the device has completed the write

cycle, otherwise the rejection is valid.

T he AD73560 Software Data Protection is a global com-

mand, protecting (or unprotecting) all pages in the entire

memory array once enabled (or disabled). T herefore us-

ing SDP for a single page write will enable SDP for the

entire array. Single pages by themselves cannot be SDP

enabled or disabled. Single power supply

reprogrammable nonvolatile memories may be uninten-

tionally altered. SST strongly recommends that Software

Data Protection (SDP) always be enabled. T he AD73560

should be programmed using the SDP command se-

quence. It is recommended that the SDP Disable Com-

mand Sequence not be issued to the device prior to

writing.

D a ta P ollin g (D Q 7)

When the AD73560 is in the internal write cycle, any

attempt to read DQ7 of the last byte loaded during the

byte-load cycle will receive the complement of the true

data. Once the write cycle is completed, DQ7 will show

REV. PrA

–3 2 –

Preliminary Technical Data

AD73560

Flash-Erase operation is initiated by using a specific six

byte-load sequence. After the load sequence, the device

enters into an internally timed cycle similar to the write

cycle. During the erase operation, the only valid read is

T oggle Bit. See Figure 27 for timing diagram.

Softwa r e C h ip - E r a se

T he AD73560 provides a flash-erase operation, which

allows the user to simultaneously clear the entire flash-

memory array to the “1” state. T his is useful when the

entire flash memory must be quickly erased. T he Software

T

RC

AA

ADDRESS A

15-0

T

CE

T

CE (BM S )

O E (R D)

OE

T

OHZ

T

V

OLZ

IH

W E (W R)

T

CHZ

T

O H

CLZ

High-Z

DATA VALID

DB

7-0

Figure 21. Read Cycle Tim ing

THREE BYTE SEQUENCE

FOR ENABLING SDP

T

AH

T

AS

ADDRESS A

5555

2AAA

5555

15-0

T

CH

CS

CE (BM S)

T

OEH

OES

O E (R D)

W E (W R)

T

WP

T

BLC

BLCO

T

DH

DB

7-0

DATA VALID

AA

A0

55

T

SW0

SW2

WC

SW1

T

DS

BYTE 127

BYTE 1

BYTE 0

Figure 22. WR Controlled Page Mode Write Cycle Tim ing

REV. PrA

–3 3 –

AD73560

THREE BYTE SEQUENCE FOR

ENABLING SDP

TAH

T

AS

ADDRESS A

5555

2AAA 5555

15-0

T

CP

T

BLCO

BLC

T

CE (BM S)

T

OES

OEH

O E (RD)

W E (W R)

T

CH

T

CS

DH

DB

7-0

DATA VALID

55

A0

AA

T

WC

SW 0

SW2

SW 1

T

DS

BYTE 1

BYTE 0

BYTE 127

Figure 23. BMS Controlled Page Mode Write Cycle Tim ing

ADDRESS A

15-0

T

CE

CE (BM S)

O E (RD)

T

OES

OEH

T

OE

W E (W R)

D

D#

D

DB

7-0

T

+ T

BLCO

WC

Figure 24. Data/Polling Tim ing

REV. PrA

–3 4 –

Preliminary Technical Data

AD73560

ADDRESS A

15-0

T

CE

CE (BM S)

T

OES

OE

T

OEH

OE (RD)

W E (W R )

DB7-0

T

+

T

BLCO

WC

TWO READ CYCLES

WITH SAM E OUTPUTS

Figure 25. Toggle Bit Tim ing

SIX-BYTE SEQUENCE FOR DISABLING

SOFTWARE DATA PROTECTION

T

WC

ADDRESS A

5555

2AAA

5555

2AAA

15-0

AA

55

80

20

CE (BM S )

O E (RD)

AA

55

W E (W R)

TBLCO

T

WP

DB

7-0

T

BLC

SW0

SW1

SW2

SW3

SW4

SW5

Figure 26. Software Data Protection Disable Tim ing

REV. PrA

–3 5 –

AD73560

SIX-BYTE CODE FOR SOFTWARE CHIP ERASE

T

SCE

ADDRESS A

2AAA

5555

2AAA

5555

15-0

55

80

10

AA

55

CE (B M S)

O E (RD)

W E (W R)

T

BLCO

T

WP

DB

7-0

T

BLC

SW0

SW1

SW2

SW 3

SW4

SW5

Figure 27. Software Flash-Mem ory Erase Tim ing

ANALO G F RO NT E ND (AF E ) INT E RF AC ING

T he AFE section of the AD73560 features 6 input chan-

nels each with 16-bit linear resolution. Connectivity to the

AFE section from the DSP is uncommitted thus allowing

the user the flexibility of connecting in the mode or con-

figuration of their choice. T his section will detail several

configurations - with no extra AFE channels configured

and with an extra AFE section configured (using an exter-

nal AD 73360 AFE).

SDIFS

SDI

TFS

DT

SCLK

SDO

AFE

DR

DSP

SECTION

RFS

SDOFS

ARESET

FL0

FL1

D SP SP O RT T O AF E INT E RF AC ING

SE

T he SCLK, SDO, SDOFS, SDI and SDIFS must be

connected to the SCLK, DR, RFS, DT and T FS pins of

the DSP respectively. T he SE pin may be controlled from

a parallel output pin or flag pin such as FL0–2 or, where

SPORT power-down is not required, it can be perma-

nently strapped high using a suitable pull-up resistor. T he

ARESET pin may be connected to the system hardware

reset structure or it may also be controlled using a dedi-

cated control line. In the event of tying it to the global

system reset, it is necessary to operate the device in mixed

mode, which allows a software reset, otherwise there is no

convenient way of resetting the device.

Figure 24. AD73560 AFE to DSP Connection

C AS C AD E O P E R AT IO N

Where it is required to configure extra analog input chan-

nels to the existing six channels on the AD73560 it is

possible to cascade up to 42 more channels (using external

AD73360 AFE’s) by using the scheme described in Fig-

ure 26. It is necessary however to ensure that the timing of

the SE and RESET signals is synchronized at each device

in the cascade. A simple D type flip-flop is sufficiend to

sync each signal to the master clock MCLK as shown in

25.

REV. PrA

–3 6 –

Preliminary Technical Data

AD73560

SE SIGNAL SYNCHRONIZED

DSP CONTROL

TO SE

TO MCLK

D

Q

SDIFS

SDI

TFS

DT

1/2

MCLK

SE

74HC74

MCLK

CLK

AFE

DSP

SCLK

DR

SCLK

SDO

SECTION

DEVICE 1

RESET

ARESET SIGNAL SYNCHRONIZED

SDOFS

RFS

DSP CONTROL

TO MCLK

TO ARESET

D

Q

1/2

74HC74

FL0

FL1

SDIFS

SDI

MCLK

CLK

Additional

AD73360

SE

SCLK

SDO

AFE

DEVICE 2

Figure 25 SE and RESET Sync Circuit for Cascaded

Operation

RESET

SDOFS

T here may be some restrictions in cascade operation due

to the number of devices configured in the cascade and the

serial clock rate chosen. T he formula below gives an indi-

cation of whether the combination of sample rate, serial

clock and number of devices can be successfully cascaded.

T his assumes a directly coupled frame sync arrangement

as shown in Figure 24 and does not take any interrupt

latency into account.

Q0

Q1

D0

D1

74HC74

CLK

Figure 26. Connection of an AD73360 Cascaded to the

AD 73560

1

6

[(( De vic eCo unt 1) 16 ) 17]

× − × +

≥

f_S

SCLK

When using the indirectly coupled frame sync configura-

tion in cascaded operation it is necessary to be aware of

the restrictions in sending control word data to all devices

in the cascade. T he user should ensure that there is suffi-

cient time for all the control words to be sent between

reading the last ADC sample and the start of the next

sample period.

Inter facing to the AD E ’s Analog Inputs

T he AD73560 features six signal conditioning inputs.

Each signal conditioning block allows the AD73560 to be

used with either a single-ended or differential signal. T he

applied signal can also be inverted internally by the

AD73560 if required. T he analog input signal to the

AD73560 can be dc-coupled, provided that the dc bias

level of the input signal is the same as the internal refer-

ence level (REFOUT ). Figure 27 shows the recom-

mended differential input circuit for the AD73560. T he

circuit of Figure 27 implements first-order low-pass filters

Connection of a cascade of devices to a DSP, as shown in

Figure 26, is no more complicated than connecting a

single device. Instead of connecting the SDO and SDOFS

to the DSP’s Rx port, these are now daisy-chained to the

SDI and SD IFS of the next device in the cascade. T he

SD O and SDOFS of the final device in the cascade are

connected to the DSP’s Rx port to complete the cascade.

SE and RESET on all devices are fed from the signals that

were synchronized with the MCLK using the circuit of

Figure . T he SCLK from only one device need be con-

nected to the DSP’s SCLK input(s) as all devices will be

running at the same SCLK frequency and phase.

CIN

100⍀

VINPx

10k⍀

VIN

CIN

100⍀

VINNx

10k⍀

0.047␮F

TO INPUT BIAS

CIRCUITRY

REFOUT

VOLTAGE

REFERENCE

REFCAP

0.1␮F

Figure 27. Exam ple Circuit for Differential Input

(DCCoupling)

with a 3 dB point at 34 kHz; these are the only filters that

must be implemented external to the AD 73560 to pre-

vent aliasing of the sampled signal. Since the ADC uses a

highly oversampled approach that transfers the bulk of the

antialiasing filtering into the digital domain, the off-chip

antialiasing filter need only be of a low order. It is recom-

mended that for optimum performance the capacitors used

for the antialiasing filter be of high quality dielectric

(N P O ).

REV. PrA

–3 7 –

AD73560

T he AD73560’s on-chip 38 dB preamplifier can be en-

abled when there is not enough gain in the input circuit

for a particular channel; the preamplifier is configured by

bits IXGS0–2 of CRD to CRF. T he total gain must be

configured to ensure that a full-scale input signal pro-

duces a signal level at the input to the sigma-delta modu-

lator of the ADC that does not exceed the maximum input

range.

(typ <50 ý) in series with the digital input and output

lines. T he noise can be minimized by good grounding and

layout. T ypically the best performance is achieved by se-

lecting the slowest sample rate and SCLK frequency for

the required application as this will produce the least

amount of digital noise. Figure 31 shows combinations of

sample rate and SCLK frequency which will allow data to

be read from all six channels in one sample period. These

figures correspond to setting DMCLK = MCLK.

T he dc biasing of the analog input signal is accomplished

with an on-chip voltage reference. If the input signal is

not biased at the internal reference level (via

REFOUT ), then it must be ac-coupled with external

coupling capacitors. CIN should be 0.1 µF or larger. T he

dc biasing of the input can then be accomplished using

resistors to REFOUT as in Figure 28.

CIN

100⍀

VINPx

VINNx

10k⍀

VIN

CIN

10k⍀

0.047␮F

TO INPUT BIAS

CIRCUITRY

REFOUT

VOLTAGE

CIN

100⍀

VINPx

VINNx

REFERENCE

REFCAP

0.1␮F

10k⍀

VIN

CIN

10k⍀

0.047␮F

Figure 31. SCLK and Sam ple Rates

0.047␮F

TO INPUT BIAS

CIRCUITRY

REFOUT

VOLTAGE

REFERENCE

REFCAP

0.1␮F

Figure 28. Exam ple Circuit for Differential Input

(ACCoupling)

Figures 29 and 20 detail ac- and dc-coupled input circuits

for single-ended operation respectively.

CIN

100⍀

VINPx

VINNx

VIN

10k⍀

0.047␮F

REFOUT

VOLTAGE

REFERENCE

REFCAP

0.1␮F

Figure 29. Exam ple Circuit for Single-Ended Input

(ACCoupling)

100⍀

VINPx

VINNx

VIN

0.047␮F

REFOUT

VOLTAGE

REFERENCE

REFCAP

0.1

F

␮

Figure 30. Exam ple Circuit for Differential Input

(DCCoupling)

D igita l In ter fa ce

As there are a number of variations of sample rate and

clock speeds that can be used with the AD73560 in a par-

ticular application, it is important to select the best com-

bination to achieve the desired performance. High speed

serial clocks will read the data from the AD73560 in a

shorter time, giving more time for processing by at the

expense of injecting some digital noise into the circuit.

Digital noise can also be reduced by connecting resistors

REV. PrA

–3 8 –

Preliminary Technical Data

AD73560

O u tlin e D im en sion s

D imensions shown in inches and (mm).

119 Ball P lastic Ball Gr id Ar r ay (P BGA)

B-119

0.300 (7.62) BSC

0.559 (14.20)

BOTTOM

0.543 (13.80)

7

6 5 4 3 2 1

VIEW

A

B

C

D

E

F

A1

G

H

J

K

L

0.050

(1.27)

BSC

0.800

(20.32)

BSC

0.874 (22.20)

0.858 (21.80)

TOP VIEW

M

N

P

R

T

0.033

(0.84)

U

REF

0.050 (1.27)

BSC

0.126 (3.19)

REF

0.037 (0.95)

0.033 (0.85)

DETAIL A

0.028 (0.70)

0.020 (0.50)

0.089 (2.27)

0.073 (1.85)

0.022 (0.56)

REF

0.035 (0.90)

SEATING

PLANE

0.024 (0.60)

BALL DIAMETER

REV. PrA

–3 9 –


型号：	AD73560BB-80
厂家：	ADI
描述：	IC 0-BIT, 16.384 MHz, OTHER DSP, PBGA119, PLASTIC, BGA-119, Digital Signal Processor 时钟外围集成电路
文件：	总39页 (文件大小：641K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD73560BB-80 [ADI]

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