AD7366ARUZ [ADI]
True Bipolar Input, Dual 1us, 12-Bit, 2-Channel SAR ADC; 真双极性输入，双1us的， 12位，双通道SAR ADC
| 型号： | AD7366ARUZ |
| 厂家： | 
ADI |
| 描述： | True Bipolar Input, Dual 1us, 12-Bit, 2-Channel SAR ADC |
| 文件： | 总17页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
True Bipolar Input, Dual
1μs, 12-Bit, 2-Channel SAR ADC
AD7366
Preliminary Technical Data
FEATURES
Dual 12-bit, 2-channel ADC
True Bipolar Analog Inputs
Programmable Input Ranges
±10, ±±, 0 to 10 V
FUNCTIONAL BLOCK DIAGRAM
D
A
DV
AV
V
CAP
CC
CC
DD
BUF
REF
AD7366
Throughput rate: 1 MSPS
Simultaneous conversion with read in less than 1μs
Specified for VCC of ± V±±%
Low current consumption: ±.6± mA max
Wide input bandwidth
12-BIT
V
V
A1
A2
OUTPUT
DRIVERS
SUCCESSIVE
APPROXIMATION
ADC
D
A
OUT
T/H
MUX
SCLK
CONVST
CS
70 dB SNR at ±0 kHz input frequency
On-chip reference: 2.± V
–40°C to +8±°C operation
High speed serial interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
iCMOSTM Process Technology
BUSY
CONTROL
LOGIC
ADDR
RANGE0
RANGE1
REFSEL
V
DRIVE
V
B1
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
24-lead TSSOP package
For 14 bit version see AD7367
OUTPUT
DRIVERS
MUX
D
B
OUT
T/H
V
B2
GENERAL DESCRIPTION
BUF
The AD73661 is a dual, 12-bit, high speed, low power, successive
approximation ADC that features throughput rates up to 1
MSPS. The device contains two ADCs, each preceded by a 2-
channel multiplexer, and a low noise, wide bandwidth track-
and-hold amplifier that can handle input frequencies in excess
of 10 MHz.
AGND AGND
V
SS
D
B
DGND
CAP
Figure 1
Table 1.Related Products
Device
Resolution Throughput Number of
The AD7366 is fabricated on Analog Devices’ Industrial CMOS
process, iCMOS, a technology platform combining the
advantages of low and high voltage CMOS, bipolar and high
voltage DMOS processes. The process allows the AD7366 to
accept high voltage bipolar signals in addition to reducing
power consumption and package size. The AD7366 can accept
true bipolar analog input signals in the ±10 ꢀ range, ±± ꢀ range
and 0 to 10 ꢀ range.
Number
Rate
Channels
Dual, 2-ch
Dual, 2-ch
Dual, 2-ch
AD7367
14-Bit
12-Bit
14-Bit
1 MSPS
±00 KSPS
±00 KSPS
AD7366-±
AD7367-±
The AD7366 has an on-chip 2.± ꢀ reference that can be
overdriven if an external reference is preferred. The AD7366 is
available in a 24-lead TSSOP package.
iCMOSTM Process Technology
For analog systems designers within industrial/instrumentation equipment
OEMs who need high performance ICs at higher-voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of
30V and operating at +/- 15V supplies while allowing dramatic reductions in
power consumption and package size, and increased AC and DC
performance.
1Protected by U.S. Patent No. 6,681,332.
Rev. PrG
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD7366
Preliminary Technical Data
TABLE OF CONTENTS
FEATURES........................................................................................ 1
GENERAL DESCRIPTION ............................................................ 1
FUNCTIONAL BLOCK DIAGRAM............................................. 1
Specifications..................................................................................... 3
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 10
Theory of operation ................................................................... 11
Analog Inputs.............................................................................. 12
ꢀDRIꢀE ............................................................................................ 13
Reference ..................................................................................... 13
Modes of Operation ....................................................................... 14
NORMAL MODE ...................................................................... 14
Shut-down Mode........................................................................ 14
POWER-UP TIMES................................................................... 1±
Serial Interface ................................................................................ 16
Outline Dimensions ....................................................................... 17
Ordering Guide............................................................................... 17
Rev. PrG | Page 2 of 17
Preliminary Technical Data
SPECIFICATIONS
AD7366
AꢀCC = DꢀCC =4.7± ꢀ to ±.2± ꢀ, ꢀDD = 11.± ꢀ to 16.± ꢀ, ꢀSS = -11.± ꢀ to −16.± ꢀ, ꢀDRIꢀE = 2.7 ꢀ to ±.2±ꢀ, fSAMPLE = 1.12MSPS, fSCLK
48MHz, ꢀREF = 2.± ꢀ Internal/External; TA = TMIN to TMAX, unless otherwise noted1.
=
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/
Comments
fIN = 50 kHz sine wave;
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)2
Signal-to-Noise + Distortion Ratio
(SINAD)2
71
70
dB
dB
Total Harmonic Distortion (THD) 2
Spurious Free Dynamic Range (SFDR) 2
Intermodulation Distortion (IMD) 2
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation2
-77
-75
dB
dB
fa = 49 kHz, fb = 51 kHz
-88
-88
-88
dB
dB
dB
SAMPLE AND HOLD
Aperture Delay3
10
ns
ps
ps
MHz
MHz
Aperture Jitter3
40
100
50
Aperture Delay Matching3
Full Power Bandwidth
@ 3 dB, 10 V range
@ 0.1 dB, 10 V range
15
DC ACCURACY
Resolution
12
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity2
Differential Nonlinearity2
Positive Full Scale Error2
Positive Full Scale Error Match2
Zero Code Error2
1
0.99
2
Guaranteed no missed codes to 12 bits
0.5
1
5
2
Zero Code Error Match2
Negative Full Scale Error2
Negative Full Scale Error Match2
ANALOG INPUT
0.5
Input Voltage Ranges
10
V
V
V
VDD = +11.5V min, VSS = −11.5V min, VCC
4.75V to 5.25V
VDD = +11.5V min, VSS = −11.5V min, VCC
4.75V to 5.25V
=
=
(Programmed via RANGE Pins)
5
0 to 10V
1
VDD = +11.5V min, VSS = -11.5 min, VCC
4.75V to 5.25V
=
DC Leakage Current
Input Capacitance
µA
p
12
When in track, 10 V range
15
3
pF
pF
When in track, 5 V or 0 to 10 V range
When in hold
Input impedance
260
2.3
125
1.1
KΩ
MΩ
KΩ
MΩ
For 10V @1.12 Msps
For 10V @100 Ksps
For 5 / 0-10V @1.12 Msps
For 5 / 0-10V @100Ksps
Rev. PrG | Page 3 of 17
AD7366
Preliminary Technical Data
Parameter
Min
Typ Max Unit
Test Conditions/ Comments
REFERENCE INPUT/OUTPUT
Reference Output Voltage4
Reference Input Voltage Range
DC Leakage Current
2.5
+2.5
2.5
3.0
1
V
V
µA
0.2ꢀ maꢁ @ 25ꢂC
Eꢁternal reference applied to Pin VREFA/Pin VREFB
Input Capacitance
VREFA, VREFB Output Impedance
25
8
pF
Ω
Reference Temperature
20
ppm/ꢂC
Coefficient
10
20
ppm/ꢂC
µVRMS
VREF Noise
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7× VDRIVE
V min
0.8
1
V maꢁ
µA maꢁ
pF typ
VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
VDRIVE − 0.2
V
V
µA
pF
0.4
1
Floating State Output
Capacitance3
10
CONVERSION RATE
Conversion Time
610
140
1.12
ns
ns
MSPS
MSPS
Track/Hold Acquisition Time3
Full-scale step input;
For 4.75V≤VDRIVE≤5.25V, fSCLK = 48MHz
For 2.7V≤VDRIVE<4.75V , fSCLK = 35MHz
Digital I/Ps = 0 V or VDRIVE
See Table 6
Throughput Rate
1
POWER REQUIREMENTS
VCC
VDD
VSS
4.75
+11.5
-16.5
2.7
5.25
V
V
V
V
+16.5
-11.5
5.25
See Table 6
See Table 6
VDRIVE
Normal Mode (Static)
IDD
ISS
ICC
1
1
1.8
µA
µA
mA
VDD = +16.5 V
VSS = −16.5 V
VCC = 5.5 V
Normal Mode (Operational)
fs = 1.12 MSPS
IDD
ISS
ICC
925
725
4
µA
µA
mA
VDD = +16.5 V
VSS = −16.5 V
VCC = 5.25 V, internal reference enabled
Shut-Down Mode
IDD
ISS
ICC
1
1
1
µA
µA
µA
VDD = +16.5 V
VSS = −16.5 V
VCC = 5.25 V
Power Dissipation
Normal Mode (Operational)
Shut-Down
48.23
15
38.25
mW
µW
µW
VDD = +16.5V, VSS = −16.5V, VCC = 5.25V
VDD = +5V, VSS = −5V, VCC = 5V
VDD = +16.5V, VSS = −16.5V, VCC = 5.25
Shut-Down
1 Temperature range is −40ꢂC to +85ꢂC
2 See Terminology section.
Rev. PrG | Page 4 of 17
Preliminary Technical Data
AD7366
3 Sample tested during initial release to ensure compliance.
4 Refers to pins VREFA or VREFB.
Rev. PrG | Page 5 of 17
AD7366
Preliminary Technical Data
TIMING SPECIFICATIONS
AꢀCC = DꢀCC =4.7± ꢀ to ±.2± ꢀ, ꢀDD = 11.± ꢀ to 16.± ꢀ, ꢀSS = −11.± ꢀ to −16.± ꢀ, ꢀDRIꢀE = 2.7 ꢀ to ±.2±ꢀ, TA = TMIN to TMAX, unless
otherwise noted1.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Test Conditions / Comments
2.7V≤VDRIVE<4.75V 4.75V≤VDRIVE≤5.25V
tCONVERT
fSCLK
610
610
ns maꢁ
Conversion time, Internal clock. CONVST falling edge to BUSY falling
edge
10
35
10
48
kHz min Frequency of serial read clock.
MHz
maꢁ
tQUIET
30
30
ns min
Minimum quiet time required between end of serial read and start of
neꢁt conversion
Minimum CONVST Low pulse.
t1
t2
t3
10
5
10
5
ns min
ns min
ns min
CONVST falling edge to BUSY rising edge.
0
0
CS
is low for t4 prior to BUSY going
BUSY falling edge to MSB valid once
Low
t4
10
10
ns maꢁ
Delay from CS falling edge until DOUTA and DOUTB are three-state
disabled
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK low pulse width
SCLK high pulse width
2
t5
20
5
0.1 tSCLK
0.1 tSCLK
10
14
5
0.1 tSCLK
0.1 tSCLK
10
ns maꢁ
ns min
ns min
ns min
ns maꢁ
ns min
ns maꢁ
μs
t6
t7
t8
t9
t10
CS rising edge to DOUTA, DOUTB, high impedance
5
10
70
5
10
70
SCLK falling edge to DOUTA, DOUTB, high impedance
SCLK falling edge to DOUTA, DOUTB, high impedance
Power up time from shutdown mode. Time required between CONVST
rising edge and CONVST falling edge.
tPOWER-UP
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See
Terminology section and Figure 9.
2 The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrG | Page 6 of 17
Preliminary Technical Data
AD7366
ABSOLUTE MAXIMUM RATINGS
Table 4
Parameter
Rating
VDD to AGND, DGND
VSS to AGND, DGND
VDRIVE to DGND
−0.3 V to +16.5 V
−0.3 V to +16.5 V
−0.3 V to DVDD
VDD to AVcc
AVCC to AGND, DGND
DVCC to AVCC
Vcc – 0.3V to +16.5V
-0.3V to +7V
-0.3 V to + 0.3V
DVCC to DGND
-0.3 V to + 7V
VDRIVE to AGND
−0.3 V to DVCC
AGND to DGND
−0.3 V to +0.3 V
VSS −0.3 V to VDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVCC + 0.3 V
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to GND
VREFA, VREFB input to AGND
Input Current to Any Pin
Eꢁcept Supplies1
10 mA
Operating Temperature Range
Storage Temperature Range
Junction Temperature
TSSOP Package
−40ꢂC to +85ꢂC
−65ꢂC to +150ꢂC
150ꢂC
θJA Thermal Impedance
θJC Thermal Impedance
Pb-free Temperature, Soldering
Reflow
128ꢂC/W
42ꢂC/W
260(+0)ꢂC
TBD kV
ESD
1 Transient currents of up to 100 mA will not cause latch up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrG | Page 7 of 17
AD7366
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D
A
1
24 DGND
OUT
V
2
D
B
23
22
DRIVE
OUT
DV
3
BUSY
CC
4
21 CNVST
20 SCLK
19 CS
RANGE1
RANGE0
ADDR
AD7366
TOP VIEW
(Not to Scale)
5
6
AGND
7
18 REFSEL
AV
CC
17
16
15
14
13
8
AGND
D
A
D
B
9
CAP
V
CAP
V
10
11
12
SS
DD
V
V
V
A1
B1
B2
V
A2
Figure 2 24-Lead RU-24.
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 23
DOUTA,
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input and 12 SCLK cycles are required to access the data. The data
simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream
DOUTB
CS
consists of the 12 bits of conversion data and is provided MSB first. If
is held low for a further 12 SCLK
cycles on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data
from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUT
using only one serial port. See the Serial Interface section.
B
2
3
ꢀDRIꢀE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will
operate. This pin should be decoupled to DGND. The voltage range on this pin is 2.7ꢀ to ±.2±ꢀ and may be
different to that at AꢀCC and DꢀCC but should never exceed either by more than 0.3ꢀ. To achieve a
throughput rate of 1.12Msps ꢀDRIꢀE must be greater than or equal to 4.7±ꢀ
DꢀCC
Digital Supply ꢀoltage, 4.7±ꢀ to ±.2±ꢀ. The DꢀCC and AꢀCC voltages should ideally be at the same potential.
For best performance it is recommended that DꢀCC and AꢀCC pins be shorted together, to ensure the voltage
difference between them never exceed 0.3 ꢀ even on a transient basis. This supply should be decoupled to
DGND. 10 µF and 100 nF decoupling capacitors should be placed on the DꢀCC pin.
Analog Input Range Selection. Logic inputs. The polarity on these pins determines the input range of
the analog input channels. See Analog Inputs section and
4,±
6
RANGE0,
RANGE1
Table 7 for details
ADDR
AGND
Multiplexer Select. Logic input. This input is used to select the pair of channels to be simultaneously
converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADCB. The logic
state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion.
7,17
Analog Ground. Ground reference point for all analog circuitry on the AD7366. All analog input signals and
any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and
must not be more than 0.3 ꢀ apart, even on a transient basis.
Analog Supply ꢀoltage, 4.7± ꢀ to ±.2± ꢀ. This is the supply voltage for the ADC cores. The AꢀCC and DꢀCC
voltages ideally should be at the same potential. For best performance it is recommended that DꢀCC and
AꢀCC pins be shorted together, to ensure the voltage difference between them never exceed 0.3 ꢀ even on a
transient basis. This supply should be decoupled to AGND. 10 µF and 100 nF decoupling capacitors should
8
AꢀCC
Rev. PrG | Page 8 of 17
Preliminary Technical Data
AD7366
be placed on the AꢀCC pins.
9,16
DCAPA,DCAP
B
Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference
buffer for each respective ADC. For best performance it is recommended to use 680nF decoupling capacitor
on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and
applied externally to the rest of a system.
10
ꢀSS
Negative power supply voltage. This is the negative supply voltage for the Analog Input section. The supply
must be less than a maximum voltage of -11.±ꢀ for all input ranges. See Table 6 for further details. 10 µF
and 100 nF decoupling capacitors should be placed on the ꢀSS pin.
11,12
13,14
1±
ꢀA1, ꢀA2
ꢀB2, ꢀB1
ꢀDD
Analog Inputs of ADC A. These are both single-ended analog inputs. The Analog input range on these
channels is determined by the RANGE0 and RANGE1 pins.
Analog Inputs of ADC B. These are both single-ended analog inputs. The Analog input range on these
channels is determined by the RANGE0 and RANGE1 pins.
Positive power supply voltage. This is the positive supply voltage for the Analog Input section. The supply
must be greater than a minimum voltage of 11.±ꢀ for all the analog input ranges. See Table 6 for further
details. 10 µF and 100 nF decoupling capacitors should be placed on the ꢀDD pin.
18
REFSEL
CS
Internal/External Reference Selection. Logic input. If this pin is tied to a logic high, the on-chip 2.± ꢀ
reference is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAP
must be tied to decoupling capacitors. If the REF SELECT pin is tied to GND, an external reference can be
supplied to the AD7366 through the DCAPA and/or DCAPB pins.
B
19
CS
Chip Select. Active low logic input. This input frames the serial data transfer. When
output bus is enabled and the conversion result is output on DOUTA, and DOUTB.
is logic low the
20
21
SCLK
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7366.
CONꢀST
Conversion Start. Edge triggered logic input. On the falling edge of this input the track/hold goes into hold
mode and conversion is initiated. If is low at the end of a conversion, the part goes into power-
CONꢀST
down mode. In this case, the rising edge of
will instruct the part to power up again.
CONꢀST
22
24
BUSY
BUSY Output. Transitions high when a conversion is started and remains high until the conversion is
complete.
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7366. The DGND pin
should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the
same potential and must not be more than 0.3 ꢀ apart, even on a transient basis.
Rev. PrG | Page 9 of 17
AD7366
Preliminary Technical Data
TERMINOLOGY
the smaller the quantization noise. The theoretical signal to
(noise + distortion) ratio for an ideal N-bit converter with a sine
wave input is given by:
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes in
the ADC.
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Integral Nonlinearity
Thus for a 12-bit converter, this is 74 dB.
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a single
(1) LSB point below the first code transition and full scale, a
point 1 LSB above the last code transition.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. For the AD7366, it is defined as:
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD(dB) = 20 log
Zero Code Error
V1
It is the deviation of the midscale transition (all 1s to all 0s)
from the ideal ꢀIN voltage, i.e., AGND – 1/2 LSB for bipolar
ranges and 2×ꢀREF−1LSB for the unipolar range.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Positive Full Scale Error
It is the deviation of the last code transition (011…110) to
(011…111) from the ideal ( +4 × ꢀREF - 1 LSB or + 2 x ꢀREF – 1
LSB) after the Zero Code Error has been adjusted out.
Peak Harmonic or Spurious Noise
Peak harmonic, or spurious noise, is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Negative Full Scale Error
This is the deviation of the first code transition (10…000) to
(10…001) from the ideal (i.e., - 4 x ꢀREF + 1 LSB, - 2 x ꢀREF + 1
LSB or AGND + 1LSB) after the Zero Code Error has been
adjusted out.
Channel-to-Channel Isolation
Zero Code Error Match
This is the difference in zero code error across all 12 channels.
Channel-to-channel isolation is a measure of the level of
crosstalk between any two channels when operating in the +/-
10 ꢀ Range. It is measured by applying a full-scale, 1±0 kHz
sine wave signal to all unselected input channels and
determining how much that signal is attenuated in the selected
channel with a ±0 kHz signal. The figure given is the worst-case
across all four channels for the AD7366. See also Typical
Performance Characteristics.
Positive Full Scale Error Match
This is the difference in positive full scale error across all
channels.
Negative Full Scale Error Match
This is the difference in negative full scale error across all
channels.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum, and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second order terms include (fa + fb) and (fa − fb),
while the third order terms include (2fa + fb), (2fa − fb), (fa +
2fb) and (fa − 2fb).
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This ratio is the measured ratio of signal to (noise + distortion)
at the output of the A/D converter. The signal is the rms
amplitude of the fundamental. Noise is the sum of all non-
fundamental signals up to half the sampling frequency (fS/2),
excluding dc. The ratio is dependent on the number of
quantization levels in the digitization process; the more levels,
The AD7366 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves, while the third order
Rev. PrG | Page 10 of 17
Preliminary Technical Data
AD7366
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
and-hold will return to track mode. Once the conversion is
finished, the serial clock input accesses data from the part.
The AD7366 has an on-chip 2.± ꢀ reference that can be
overdriven when an external reference is preferred. If the
internal reference is to be used elsewhere in a system, then the
output from DCAPA & DCAPB must first be buffered. On Power
up the REFSEL pin must be tied to either a high or low logic
state to select either the internal or external reference option. If
the internal reference is the preferred option, the user must tie
the REFSEL pin logic high. Alternatively, if REFSEL is tied to
GND then an external reference can be supplied to both ADC’s
through DCAPA & DCAPB pins.
PSRR (Power Supply Rejection)
ꢀariations in power supply affect the full-scale transition but
not the converter’s linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value (see
figure x).
The analog inputs are configured as two single ended inputs
for each ADC. The various different input voltage ranges
can be selected by programming the RANGE bits as shown in
THEORY OF OPERATION
Circuit Information
Table 7.
The AD7366 is a fast, dual, 2-Channel, 12-bit, Bipolar Input,
Serial A/D converter. The AD7366 can accept bipolar input
ranges of ±10ꢀ and ±±ꢀ. It can also accept a 0 to 10ꢀ unipolar
input range. The AD7366 requires ꢀDD and ꢀSS dual supplies for
the high voltage analog input structure. These supplies must be
equal to or greater than 11.±ꢀ. See Table 6 for the minimum
requirements on these supplies for each Analog Input Range.
The AD7366 requires a low voltage 4.7±ꢀ to ±.2± ꢀ ꢀCC supply
to power the ADC core.
Converter Operation
The AD7366 has two successive approximation analog-to-
digital converters, each based around two capacitive DACs.
Figure 3 and Figure 4 show simplified schematics of one of
these ADCs in acquisition and conversion phase, respectively.
The ADC is comprised of control logic, a SAR, and two
capacitive DACs. In Figure 3 (the acquisition phase), SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition, and the sampling capacitor arrays acquire
the signal on the input.
Table 6. Reference and Supply Requirements for each Analog
Input Range
Selected
Analog
Input
Reference Full
AVCC
(V)
Minimum
VDD/VSS (V)
Voltage
(V)
Scale
Input
Range(V)
Range (V)
CAPACITIVE
DAC
2.5
3.0
10
5
5
11.5
12
10
A
V
12
IN
CONTROL
LOGIC
SW1
B
2.5
3.0
2.5
3.0
5
5
5
5
5
11.5
11.5
11.5
12
SW2
5
COMPARATOR
6
0 to 10
0 to 10
0 to 12
AGND
Figure 3 ADC Acquisition Phase
The AD7366 contains two on-chip differential track-and-hold
amplifiers, two successive approximation A/D converters, and a
serial interface with two separate data output pins. It is housed
in a 24-lead TSSOP package, offering the user considerable
space-saving advantages over alternative solutions. The AD7366
requires a CONꢀST signal to start conversion. On the falling
edge of CONꢀST both track-and-holds will be placed into hold
mode and the conversions are initiated. The BUSY signal will go
high to indicate the conversions are taking place. The clock
source for each successive approximation ADC is provided by
an internal oscillator. The BUSY signal will go low to indicate
the end of conversion. On the falling edge of BUSY the track-
When the ADC starts a conversion (Figure 4), SW2 opens and
SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
Rev. PrG | Page 11 of 17
AD7366
Preliminary Technical Data
1
1
Do not program
CAPACITIVE
DAC
The AD7366 requires ꢀDD and ꢀSS dual supplies for the high
voltage analog input structures. These supplies must be equal to
or greater than ±11.±ꢀ. See Table 6 for the requirements on
these supplies. The AD7366 requires a low voltage 4.7±ꢀ to
±.2±ꢀ AꢀCC supply to power the ADC core, a 4.7±ꢀ to ±.2±ꢀ
DꢀCC supply for the Digital Power and a 2.7ꢀ to ±.2±ꢀ ꢀDRIꢀE
supply for the interface power.
A
V
IN
CONTROL
LOGIC
SW1
B
SW2
COMPARATOR
AGND
Figure 4 ADC Conversion Phase
Channel selection is made via the ADDR pin as shown in Table
8. The logic level on the ADDR pin is latched on the rising edge
of BUSY for the next conversion, not the one in progress. When
power is first supplied to the AD7366 the default channel
selection will be ꢀA1 and ꢀB1.
ANALOG INPUTS
Each ADC in the AD7366 has two Single Ended Analog Inputs.
Figure ± shows the equivalent circuit of the analog input
structure of the AD7366. The two diodes provide ESD
protection. Care must be taken to ensure that the analog input
signals never exceed the supply rails by more than 300 mꢀ. This
causes these diodes to become forward-biased and starts
conducting current into the substrate. These diodes can
conduct up to 10 mA without causing irreversible damage to
the part. Capacitor C1 in Figure ± is typically ± pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about TBD Ω.
Capacitor C2 is the ADC’s sampling capacitors with a
capacitance of approximately TBDpF for the ±10ꢀ input range
and approximately TBDpF for all other input ranges.
Table 8. Channel Selection
ADDR
Channels Selected
ꢀA1, ꢀB1
0
1
ꢀA2, ꢀB2
Transfer Function
The AD7366 output coding is two’s complement. The designed
code transitions occur at successive integer LSB values (i.e. 1
LSB, 2 lSB, and so on). The LSB size is dependant on the analog
input range selected.
V
DD
D
C2
R1
Table 9 LSB sizes for each Analog Input Range.
V
0
IN
C1
Input Range
±10 ꢀ
Full Scale Range/4ꢀ96
20 ꢀ/4096
LSB Size
4.88mꢀ
2.44mꢀ
2.44mꢀ
D
V
SS
Figure 5 Equivalent Analog Input Structure
±± ꢀ
10 ꢀ/4096
The AD7366 can handle true bipolar input voltages. The
Analog input can be set to one of three ranges; 1ꢀ0, 50, ꢀ-
1ꢀ0. The logic levels on pins RANGEꢀ and RANGE1
determine which input range is selected as outlined in
0 to 10 ꢀ
10ꢀ/4096
The ideal transfer characteristic is shown in Figure 6
Table 7. These range bits should not be changed during the
acquisition time prior to a conversion but may change at any
other time.
011...111
011...110
Table 7. Analog Input Range Selection
000...001
000...000
111...111
RANGE1
RANGEꢀ
Range Selected
±10ꢀ
100...010
100...001
100...000
0
0
1
0
1
0
±±ꢀ
-FSR/2 + 1LSB
+FSR/2 - 1LSB
0V
ANALOG INPUT
0 to 10ꢀ
Figure 6.Transfer Characteristic
Rev. PrG | Page 12 of 17
Preliminary Technical Data
AD7366
tied to either a low or high logic state for the part to operate.
Suitable reference sources for the AD7366 include AD780,
0DRI0E
The AD7366 also has a ꢀDRIꢀE feature to control the voltage at
which the serial interface operates. ꢀDRIꢀE allows the ADC to
easily interface to both 3 ꢀ and ± ꢀ processors. For example, if
the AD7366 was operated with a ꢀCC of ± ꢀ, the ꢀDRIꢀE pin could
be powered from a 3 ꢀ supply, allowing a large dynamic range
with low voltage digital processors. Thus, the AD7366 could be
used with the ±10 ꢀ input range while still being able to
interface to 3 ꢀ digital parts.
AD1±82, ADR431, REF193, and ADR391.
The internal reference circuitry consists of a 2.± ꢀ band gap
reference and a reference buffer. When operating the AD7366
in internal reference mode, the 2.± ꢀ internal reference is
available at DCAPA and DCAPB pins, which should be decoupled
to AGND using a 680nF capacitor. It is recommended that the
internal reference be buffered before applying it elsewhere in
the system. The internal reference is capable of sourcing up to
1±0 μA with an analog input range of ±10 and 60 μA for both
the ±±ꢀ and 0-10ꢀ ranges.
To achieve the maximum throughput rate of 1.12Msps ꢀDRIꢀE
must be greater than or equal to 4.7±ꢀ, see table 3. The
maximum throughput rate for the AD7366 with the ꢀDRIꢀE
voltage set to less than 4.7± and greater than 2.7 is 1 Msps.
If the internal reference operation is required for the ADC
conversion, the REFSEL pin must be tied to logic high on
power-up. The reference buffer requires ±00 µs to power up and
charge the 680nF decoupling capacitor during the power-up
time.
REFERENCE
The AD7366 can operate with either the internal 2.± ꢀ on-chip
reference or an externally applied reference. The logic state of
the REFSEL pin determines whether the internal reference is
used. The internal reference is selected for both ADC when the
REFSEL pin is tied to logic high. If the REFSEL pin is tied to
GND then an external reference can be supplied through the
DCAPA and DCAPB pins. On power-up, the REFSEL pin must be
The AD7366 is specified for a 2.± ꢀ to 3 ꢀ reference range.
When a 3ꢀ reference is selected, the ranges are ±12 ꢀ, ±6 ꢀ, and
0 ꢀ to +12 ꢀ. For these ranges, the ꢀDD and ꢀSS supply must be
equal to or greater than the +12ꢀ &-12ꢀ respectively.
Rev. PrG | Page 13 of 17
AD7366
Preliminary Technical Data
MODES OF OPERATION
The mode of operation of the AD7366 is selected by the (logic) state of the
signal at the end of a conversion. There are two
CONꢀST
possible modes of operation: normal mode and shut-down mode. These modes of operation are designed to provide flexible power
management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application
requirements.
CS
return to three-state when
is brought high and not after 12
CS
NORMAL MODE
SCLK cycles has elapsed. If
is left low for a further 12 SCLK
This mode is intended for applications needing fast throughput
rates since the user does not have to worry about any power-up
times with the AD7366 remaining fully powered at all times.
Figure 7 shows the general mode of operation of the AD7366 in
this mode.
cycles, the result from the other on chip ADC is also accessed
on the same DOUT line, as shown in Figure 10 (see the Serial
Interface section)
Once 24 SCLK cycles have elapsed, the DOUT line returns to
th
CS
three-state when
is brought high and not on the 24 SCLK
is brought high prior to this, the DOUT line
returns to three-state at that point. Thus,
high once the read is completed, as the bus does not
automatically return to three-state upon completion of the dual
result read.
The conversion is initiated on the falling edge of
described in the Circuit Information section. To ensure that the
part remains fully powered up at all times,
logic state high prior to the BUSY signal going low. If
is at logic state low when the BUSY signal goes low, the
analogue circuitry will power down and the part will cease
converting. The BUSY signal remains high for the duration of
as
CONꢀST
CS
falling edge. If
CS
must be brought
must be at
CONꢀST
CONꢀST
Once a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
CS
the conversion. The
pin must be brought low to bring the
data bus out of three-sate, subsequently twelve serial clock
cycles are required to read the conversion result. The DOUT lines
the quiet time, tQUIET, has elapsed by bringing
again.
low
CONꢀST
t
1
CONVST
t
quiet
t
2
BUSY
t
convert
t
3
CS
SCLK
SERIAL READ OPERATION
1
12
Figure 7. Normal Mode Operation
end of the conversion phase. While the part is in shut-down
mode the digital output code from the last conversion on each
ADC can still be read from the DOUT pins. To read the DOUT data
SHUT-DOWN MODE
This mode is intended for use in applications where slow
throughput rates are required. This mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period of
inactivity and thus, shut-down. When the AD7366 is in full
power-down, all analog circuitry is powered down. As already
stated, the falling edge of
The BUSY output subsequently goes high to indicate that the
conversion is in progress. Once the conversion is completed, the
CS
must be brought low as described in the Serial Interface
CS
Section. The DOUT pins return to three-state once
back to logic high.
is brought
To exit full power-down and power up the AD7366, A rising
edge of is required. After the required power up time
initiates the conversion.
CONꢀST
CONꢀST
has elapsed,
may be brought low again to initiate
CONꢀST
another conversion, as shown in Figure 8 See the Power up time
section for power-up times associated with the AD7366.
BUSY output returns low. If the
when BUSY goes low then the part will enter shut-down at the
signal is at logic low
CONꢀST
Rev. PrG | Page 14 of 17
AD7366
Preliminary Technical Data
t
power-up
ENTERS SHUT-DOWN
CONVST
BUSY
t
2
t
convert
t
CS
3
SERIAL READ OPERATION
SCLK
1
12
Figure 8. Auto-Shutdown Mode
With the AD7366 no dummy conversion is required before
valid data can be read from the DOUT pins. If it is intended to
place the part in shut-down mode when the supplies are first
applied, then the AD7366 must be powered up as explained
POWER-UP TIMES
The AD7366 has one power down mode, which has already
been described in detail. This section deals with the power-up
time required when coming out of this modes. It should be
noted that the power-up time, as explained in this section,
applies with the recommended capacitors in place on the DCAP
about and a conversion initiated, but
should remain
CONꢀST
in the logic low state and when the BUSY signal goes low thus
the part enters shut-down.
A
must
and DCAPB pins. To power up from shut-down,
CONꢀST
be brought high and remain high for a minimum of 100μs, as
shown in Figure 8.
Once supplies are applied to the AD7366, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final values.
When power supplies are first applied to the AD7366, the ADC
may power up with in either the low or high logic
CONꢀST
state. Before attempting a valid conversion
must be
CONꢀST
brought high and remain high for the recommended power up
time of 70μs, it can then be brought low to initiate a conversion.
Rev. PrG | Page 15 of 17
AD7366
Preliminary Technical Data
SERIAL INTERFACE
9 shows how a 12 SCLK read is used to access the conversion
results.
Figure 9 shows the detailed timing diagram for serial inter-
CONꢀST
facing to the AD7366. On the falling edge of
the
AD7366 will simultaneously convert the selected channels.
These conversions are performed using the on-chip oscillator.
CS
, the conversion will be terminated
On the rising edge of
CS
and DOUTA and DOUTB go back into three-state. If
is not
CONꢀST
After the falling edge of
the BUSY signal goes high,
brought high, but is instead held low for a further 12 SCLK
cycles on either DOUTA or DOUTB, the data from the other
ADC follows on the DOUT pin. This is illustrated in Figure 10
where the case for DOUTA is shown. In this case, the DOUT
indicating the conversion has started. It returns low once the
conversion has been completed. The data can now be read from
the DOUT pins.
CS
and SCLK signals are required to transfer data from the
CS
line in use goes back into three-state on the rising edge of
AD7366. The AD7366 has two output pins corresponding to
each ADC. Data can be read from the AD7366 using both
If the falling edge of SCLK coincides with the falling edge of
CS
, then the falling edge of SCLK is not acknowledged by
D
OUTA & DOUTB, alternatively a single output pin of your
choice can be used. The SCLK input signal provides the
CS
the AD7366, and the next falling edge of the SCLK will be
CS
the first registered after the falling edges of the
CS
.
clock source for the serial interface. The
access data from the AD7366. The falling edge of
goes low to
CS
takes
The
low to indicate the end of a conversion. The data bus is bought
CS
pin can be brought low before the BUSY signal goes
the bus out of three-state and clocks out the MSB of the
conversion result. The data stream consists of 12 bits of data
MSB first. The first bit of the conversion result is valid on the
out of three-state by taking the
utilized to ensure that the MSB is valid on the falling edge of
CS
pin low. This feature can be
CS
first SCLK falling edge after the
falling edge. The
BUSY by bring
low a minimum of t4 nanoseconds before the
subsequent 11 bits of data are clocked out on the falling edge
of the SCLK signal. A minimum of 12 Clock pulses must be
provided to AD7366 to access each conversion result. Figure
CS
BUSY signal goes low. The dotted
this.
line in Figure 7 illustrates
CS
t8
12
SCLK
3
4
5
1
2
t7
t9
t6
t5
t4
D
D
A
DB10
DB9
DB8
DB2
OUT
DB1
DB0
3-STATE
3-STATE
B
OUT
DB11
Figure 9. Serial Interface Timing diagram
CS
t8
SCLK
3
4
5
1
2
10
11
12
13
24
t7
t10
t4
t5
t6
DB1
DB0
DB11
B
DB10
B
DB1
B
DB0
B
DB9
DB10
D
A
A
A
A
A
OUT
THREE-
STATE
THREE-
STATE
DB11
A
Figure 10. Reading Data from Both ADC’s on ONE DOUT Line with 28 SCLK’s
Rev. PrG | Page 16 of 17
Preliminary Technical Data
OUTLINE DIMENSIONS
AD7366
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 11. 24-Lead TSSOP
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
RU-24
AD7366ARUZ1
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
Thin Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Shrink Small Outline Package
AD7366ARUZ-REEL71
AD7366BRUZ1
RU-24
RU-24
AD7366BRUZ-REEL71
AD7366-±ARUZ1
RU-24
RU-24
AD7366-±ARUZ-REEL71
AD7366-±BRUZ1
RU-24
RU-24
AD7366-±BRUZ-REEL71
RU-24
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06092-0-11/06(PrG)
相关型号：
AD7366BRUZ-5500RL7
2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24, ROHS COMPLIANT, MO-153AD, TSSOP-24
ADI
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