AD7376AR10-REEL_技术文档

+30 V/± ±1 V ꢀOperatio

±28-Pistatio Dtgtarl Piapoatimpape

AD7376

FUNCTIONAL BLOCK DIAGRAM

FEATURES

128 positions

10 kΩ, 50 kΩ, 100 kΩ

5 V to 30 V single-supply operation

5 V to 15 V dual-supply operation

3-wire SPI®-compatible serial interface

THD 0.006% typical

Programmable preset

Power shutdown: less than 1 μA

iCMOS™ process technology

V

AD7376

DD

SDO

SDI

Q

A

7-BIT

7

7-BIT

SERIAL

LATCH

REGISTER

W

B

D

CK

SHDN

R

CLK

CS

V

SS

APPLICATIONS

High voltage DAC

GND

RS

SHDN

Programmable power supply

Programmable gain and offset adjustment

Programmable filters, delays

Actuator control

Figure 1.

Audio volume control

Mechanical potentiometer replacement

GENERAL DESCRIPTION

The AD7376¹is one of the few high voltage, high performance

digital potentiometers²in the market at present. This device can

be used as a programmable resistor or resistor divider. The

AD7376 performs the same electronic adjustment function as

mechanical potentiometers, variable resistors, and trimmers

with enhanced resolution, solid-state reliability, and

programmability. With digital rather than manual control,

AD7376 provides layout flexibility and allows close-loop

dynamic controllability.

The AD7376 features sleep-mode programmability in shutdown

that can be used to program the preset before device activation,

thus providing an alternative to costly EEPROM solutions.

The AD7376 is available in 14-lead TSSOP and 16-lead wide

body SOIC packages in 10 kΩ, 50 kΩ, and 100 kΩ options. All

parts are guaranteed to operate over the −40°C to +85°C

extended industrial temperature range.

¹Patent number: 54952455.

²The terms digital potentiometer and RDAC are used interchangeably.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7376

TABLE ꢀF CꢀNTENTS

Features .............................................................................................. 1

Programming the Variable Resistor......................................... 12

Programming the Potentiometer Divider............................... 13

3-Wire Serial Bus Digital Interface.......................................... 13

Daisy-Chain Operation ............................................................. 14

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range ......................................... 14

Power-Up and Power-Down Sequences.................................. 14

Layout and Power Supply Biasing............................................ 15

Applications..................................................................................... 16

High Voltage DAC...................................................................... 16

Programmable Power Supply ................................................... 16

Audio Volume Control .............................................................. 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 19

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—10 kΩ Version................................ 3

Electrical Characteristics—50 kΩ, 100 kΩ Versions ............... 4

Timing Specifications .................................................................. 5

3-Wire Digital Interface................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

REVISION HISTORY

11/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Deleted DIP Package..........................................................Universal

Changes to Features.......................................................................... 1

Separated Electrical Characteristics into Table 1 and Table 2 .... 3

Separated Interface Timing into Table 3 ....................................... 5

Changes to Table 1 Through Table 3.............................................. 3

Added Table 4.................................................................................... 6

Added Figure 2.................................................................................. 6

Changes to Absolute Maximum Ratings Section......................... 7

Deleted Parametric Test Circuits Section...................................... 7

Changes to Typical Performance Characteristics......................... 9

Added Daisy-Chain Operation Section....................................... 14

Added ESD Protection Section..................................................... 14

Added Terminal Voltage Operating Range Section................... 14

Added Power-Up and Power-Down Sequences Section ........... 14

Added Layout and Power Supply Biasing Section...................... 15

Added Applications Section.......................................................... 16

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide .......................................................... 19

10/97—Revision 0: Initial Version

Rev. A | Page 2 of 20

AD7376

SPECIFICATIꢀNS

ELECTRICAL CHARACTERISTICS—10 kΩ VERSION

V_DD/V_SS

= 15 V 10ꢀ, V_A= V_DD, V_B= V_SS/0 V, −40°C < T_A< +85°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—

RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Nonlinearity²

Nominal Resistor Tolerance

Resistance Temperature Coefficient³(∆R_AB/R_AB)/∆T × 10⁶V_AB= V_DD, wiper = no connect

Wiper Resistance

R-DNL

R-INL

∆R_AB

R_WB, V_A= NC, V_DD/V_SS

T_A= 25°C

=

15 V

−1

−30

0.5

+1

+30

LSB

%

ppm/°C

Ω

−300

120

260

R_W

V_DD/V_SS

=

15 V

5 V

200

Ω

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE

Integral Nonlinearity⁴

INL

DNL

V_DD/V_SS

Code = 0x40

=

15 V

−1

0.5

5

+1

LSB

ppm/°C

Differential Nonlinearity⁴

Voltage Divider Temperature

Coefficient

(∆V_W/V_W)/∆T × 10⁶

Full-Scale Error

Zero-Scale Error

V_WFSE

V_WZSE

Code = 0x7F, V_DD/V_SS

Code = 0x00, V_DD/V_SS

=

15 V

−3

0

−1.5

1.5

0

3

LSB

RESISTOR TERMINALS

Voltage Range⁵

V_{A, B, W}

C_{A, B}

V_SS

V_DD

V

pF

Capacitance⁶A, B

f = 1 MHz, measured to GND,

code = 0x40

f = 1 MHz, measured to GND,

code = 0x40

45

60

Capacitance⁶

C_W

pF

Shutdown Supply Current⁷

Shutdown Wiper Resistance

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Output Logic High

Output Logic Low

I_{A_SD}

R_{W_SD}

I_CM

V_A= V_DD, V_B= 0 V, SHDN = 0

V_A= V_DD, V_B= 0 V, SHDN = 0, V_DD= 15 V

V_A= V_B= V_W

0.02

170

1

μA

Ω

400

nA

V_IH

V_IL

V_OH

V_OL

I_IL

V_DD= 5 V or 15 V

R_Pull-up= 2.2 kΩ to 5 V

I_OL= 1.6 mA, V_LOGIC= 5 V, V_DD= 15 V

V_IN= 0 V or 5 V

2.4

4.9

V

μA

pF

0.8

0.4

1

Input Current

Input Capacitance⁶

C_IL

5

POWER SUPPLIES

Power Supply Range

Positive Supply Current

V_DD/V_SS

V_DD

I_DD

Dual-supply range

Single-supply range, V_SS= 0

4.5

16.5

33

V

V_IH= 5 V or V_IL= 0 V, V_DD/V_SS

=

15 V

5 V

15 V

5 V

2

mA

μA

mA

mW

%/%

12

25

Negative Supply Current

I_SS

−0.1

31.5

Power Dissipation⁸

Power Supply Rejection Ratio

P_DISS

PSRR

15 V

ΔV_DD/ΔV_SS

=

15 V 10%

−0.2

0.05 +0.2

Rev. A | Page 3 of 20

AD7376

Parameter

DYNAMIC CHARACTERISTICS^{6, 9,10}

Symbol

Conditions

Min

Typ¹

Max

Unit

Bandwidth −3 dB

Total Harmonic Distortion

V_WSettling Time

BW

THD_W

t_S

Code = 0x40

470

0.006

4

kHz

%

μs

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= 10 V, V_B= 0 V, 1 LSB error band

R_WB= 5 kΩ, f = 1 kHz

Resistor Noise Voltage

e_{N_WB}

0.9

nV√Hz

¹Typical values represent average readings at 25°C, V_DD= 15 V, and V_SS= −15 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL

measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.

³Pb-free parts have a 35 ppm/°C temperature coefficient.

⁴INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. V_A= V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

⁵Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

⁶Guaranteed by design and not subject to production test.

⁷Measured at the A terminal. A terminal is open circuit in shutdown mode.

⁸P_DISSis calculated from (I_DD× V_DD) + abs(I_SS× V_SS). CMOS logic level inputs result in minimum power dissipation.

⁹Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

¹⁰All dynamic characteristics use V_DD= 15 V and V_SS= −15 V.

ELECTRICAL CHARACTERISTICS—50 kΩ, 100 kΩ VERSIONS

V_DD/V_SS

= 15 V 10ꢀ or 5 V 10ꢀ, V_A= V_DD, V_B= V_SS/0 V, −40°C < T_A< +85°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min

Typ¹Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Nonlinearity²

R-DNL

R-INL

R_WB, V_A= NC

−1

−1.5

−1

0.5

+1

+1.5

+1

LSB

%

R_WB, V_A= NC, R_AB= 50 kΩ

R_WB, V_A= NC, R_AB= 100 kΩ

T_A= 25°C

Nominal Resistor Tolerance

Resistance Temperature Coefficient³

∆R_AB

(∆R_AB/R_AB)/∆T ×

10⁶

−30

+30

V_AB= V_DD, wiper = no connect

−300

ppm/°C

Wiper Resistance

R_W

V_DD/V_SS

=

15 V

5 V

120

260

200

Ω

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE

Integral Nonlinearity⁴

INL

DNL

−1

0.5

5

+1

LSB

ppm/°C

Differential Nonlinearity⁴

Voltage Divider Temperature

Coefficient

(∆V_W/V_W)/∆T × 10⁶

Code = 0x40

Full-Scale Error

Zero-Scale Error

V_WFSE

V_WZSE

Code = 0x7F

Code = 0x00

−2

0

−0.5

0.5

0

1

LSB

RESISTOR TERMINALS

Voltage Range⁵

V_{A, B, W}

C_{A, B}

V_SS

V_DD

V

pF

Capacitance⁶A, B

f = 1 MHz, measured to GND,

code = 0x40

f = 1 MHz, measured to GND,

code = 0x40

45

60

Capacitance⁶

C_W

pF

Shutdown Supply Current⁷

Shutdown Wiper Resistance

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Output Logic High

Output Logic Low

I_{A_SD}

R_{W_SD}

I_CM

V_A= V_DD, V_B= 0 V, SHDN = 0

V_A= V_DD, V_B= 0 V, SHDN = 0, V_DD= 15 V

V_A= V_B= V_W

0.02

170

1

μA

Ω

400

nA

V_IH

V_IL

V_OH

V_OL

V_DD= 5 V or 15 V

R_Pull-up= 2.2 kΩ to 5 V

I_OL= 1.6 mA, V_LOGIC= 5 V, V_DD= 15 V

2.4

4.9

V

0.8

0.4

Rev. A | Page 4 of 20

AD7376

Parameter

Symbol

Conditions

Min

Typ¹Max

Unit

μA

Input Current

I_IL

V_IN= 0 V or 5 V

1

Input Capacitance⁶

POWER SUPPLIES

Power Supply Range

Positive Supply Current

C_IL

5

pF

V_DD/V_SS

V_DD

I_DD

Dual-supply range

Single-supply range, V_SS= 0

4.5

16.5

33

V

V_IH= 5 V or V_IL= 0 V, V_DD/V_SS

=

15 V

5 V

15 V

5 V

2

mA

μA

mA

mW

=

12

25

Negative Supply Current

I_SS

−0.1

31.5

Power Dissipation⁸

P_DISS

15 V

Power Supply Rejection Ratio

DYNAMIC CHARACTERISTICS^{6, 9, 10}

Bandwidth −3 dB

PSRR

−0.25

0.1

+0.25 %/%

BW

R_AB= 50 kΩ, code = 0x40

R_AB= 100 kΩ, code = 0x40

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= 10 V, V_B= 0 V, 1 LSB error band

R_WB= 25 kΩ, f = 1 kHz

90

50

0.002

4

kHz

%

μs

nV√Hz

Total Harmonic Distortion

V_WSettling Time

Resistor Noise Voltage

THD_W

t_S

e_{N_WB}

2

¹Typical values represent average readings at 25°C, V_DD= 15 V, and V_SS= −15 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL

measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.

³Pb-free parts have a 35 ppm/°C temperature coefficient.

⁴INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. V_A= V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

⁵Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

⁶Guaranteed by design; not subject to production test.

⁷Measured at the A terminal. A terminal is open circuit in shutdown mode.

⁸P_DISSis calculated from (I_DD× V_DD) + abs(I_SS× V_SS). CMOS logic level inputs result in minimum power dissipation.

⁹Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

¹⁰All dynamic characteristics use V_DD= 15 V and V_SS= −15 V.

TIMING SPECIFICATIONS

Table 3.

Parameter

INTERFACE TIMING CHARACTERISTICS^{1, 2}

Symbol

Conditions

Min

Typ

Max

Unit

Clock Frequency

Input Clock Pulse Width

Data Set-up Time

Data Hold Time

CLK to SDO Propagation Delay³

f_CLK

t_CH, t_CL

t_DS

t_DH

t_PD

t_CSS

t_CSW

t_RS

t_CSH0

t_CSH

t_CS1

4

MHz

ns

Clock level high or low

R_Pull-up= 2.2 kΩ, C_L< 20 pF

120

30

20

10

100

CS Set-up Time

120

150

120

10

CS High Pulse Width

Reset Pulse Width

CLK Fall to CS Fall Hold Time

CLK Rise to CS Rise Hold Time

CS Rise to Clock Rise Setup

120

¹Guaranteed by design and not subject to production test.

²See Figure 3 for the location of the measured values. All input control voltages are specified with t_R= t_F= 1 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V.

Switching characteristics are measured using V_DD= 15 V and V_SS= −15 V.

³Propagation delay depends on value of V_DD, R_Pull-up, and C_L.

Rev. A | Page 5 of 20

AD7376

3-WIRE DIGITAL INTERFACE

Table 4.AD7376 Serial Data-Word Format¹

MSB

LSB

D0

2⁰

D6

D5

D4

D3

D2

D1

2⁶

¹Data is loaded MSB first.

1

SDI

D6 D5 D4 D3 D2 D1

D0

0

1

0

1

0

1

0

CLK

CS

RDAC REGISTER LOAD

V

OUT

Figure 2. AD7376 3-Wire Digital Interface Timing Diagram

(V_A= V_DD, V_B= 0 V, V_W= V_OUT

)

1

0

SDI

(DATA IN)

D

X

t_DS

t_DH

1

0

SDO

(DATA OUT)

D'

X

t_{PD_MAX}

t_CH

1

0

t_CS1

CLK

t_CSH0

t_CL

t_CSH

t_CSS

1

t_CSW

t_S

CS

0

V

DD

V

OUT

±1 LSB ERROR BAND

0V

±1 LSB

Figure 3. Detail Timing Diagram

Rev. A | Page 6 of 20

AD7376

ABSꢀLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

V_SSto GND

V_DDto V_SS

V_A, V_B, V_Wto GND

Maximum Current

I_WB, I_WAPulsed

−0.3 V to +35 V

+0.3 V to −16.5 V

−0.3 V to +35 V

V_SSto V_DD

20 mA

5 mA

I_WBContinuous (R_WB≤ 6 kΩ, A open,

V

_DD/V_SS= 30 V/0 V)¹

I_WAContinuous (R_WA≤ 6 kΩ, B open,

V_DD/V_SS= 30 V/0 V)¹

5 mA

Digital Input and Output Voltages to GND

0 V to 7 V

Operating Temperature Range

Maximum Junction Temperature (T_JMAX

Storage Temperature

Lead Temperature (Soldering, 10 sec)

Package Power Dissipation

Thermal Resistance θ_JA

−40°C to +85°C

150°C

−65°C to +150°C

300°C

2

)

(T_JMAX− T_A)/θ_JA

16-Lead SOIC_W

14-Lead TSSOP

120°C/W

240°C/W

¹Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

²Package power dissipation = (T_JMAX– T_A)/θ_JA

.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 7 of 20

AD7376

PIN CꢀNFIGURATIꢀNS AND FUNCTIꢀN DESCRIPTIꢀNS

A

B

1

2

3

4

5

6

7

8

16

15 NC

14

W

A

B

1

2

3

4

5

6

7

14

13 NC

12

W

V

SS

DD

AD7376

TOP VIEW

(Not to Scale)

GND

CS

13 SDO

12 SHDN

11 SDI

TOP VIEW

V

SS

DD

(Not to Scale)

GND

CS

11 SDO

RS

10 SHDN

CLK

NC

10 NC

RS

9

8

SDI

NC

9

NC

CLK

NC = NO CONNECT

Figure 4. 14-Lead TSSOP Pin Configuration

Figure 5. 16-Lead SOIC_W Pin Configuration

Table 6.Pin Function Descriptions

Pin No.

16-Lead

14-Lead

TSSOP

SOL

Mnemonic Description

1

A

A Terminal. V_SS≤ V_A≤ V_DD.

2

3

4

5

2

3

4

5

B

V_SS

GND

CS

B Terminal. V_SS≤ V_B≤ V_DD

Negative Power Supply.

Digital Ground.

Chip Select Input, Active Low. When CS returns high, data is loaded into the wiper register.

Reset to Midscale.

.

6

RS

7

8

9

10

7

CLK

NC

SDI

SHDN

Serial Clock Input. Positive-edge triggered.

No Connect. Let it float or ground.

Serial Data Input (data loads MSB first).

Shutdown. A terminal open ended; W and B terminals shorted. Can be used as programmable

preset.¹

8, 9, 10

11

12

11

12

13

14

13

14

15

16

SDO

V_DD

NC

W

Serial Data Output.

Positive Power Supply.

No Connect. Let it float or ground.

Wiper Terminal. V_SS≤ V_W≤ V_DD

.

¹Assert shutdown and program the device during power-up. Then deassert the shutdown to achieve the desirable preset level.

Rev. A | Page 8 of 20

AD7376

TYPICAL PERFꢀRMANCE CHARACTERISTICS

0.5

0.4

0.3

0.2

0.1

0

V

= +15V

= –15V

V

= +15V

= –15V

DD

V

SS

0.4

0.3

+85°C

+25°C

0.2

+85°C

0.1

+25°C

0

–40°C

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–40°C

0

16

32

48

64

80

96

112

128

0

16

32

48

64

80

96

112

128

CODE (Decimal)

Figure 9. Potentiometer Divider Differential Nonlinearity Error vs. Code

Figure 6. Resistance Step Position Nonlinearity Error vs. Code

20

0.5

V

= +15V

= –15V

DD

SS

0.4

0.3

I

@ V /V = 30V/0V

DD SS

DD

16

12

8

+85°C

I

@ V /V = ±15V

DD SS

DD

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–40°C

+25°C

4

I

@ V /V = 30V/0V

DD SS

SS

0

I

@ V /V = ±15V

DD SS

SS

–4

–40

–20

0

20

40

60

80

100

120

0

16

32

48

64

80

96

112

128

TEMPERATURE (°C)

CODE (Decimal)

Figure 10. Supply Current (I_DD, I_SS) vs. Temperature

Figure 7. Relative Resistance Step Change from Ideal vs. Code

0.5

0.4

V

= +15V

= –15V

DD

SS

0.4

0.3

+85°C

+25°C

0.2

0.1

0

–40°C

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

0

16

32

48

64

80

96

112

128

–40

–20

0

20

40

60

80

100

120

CODE (Decimal)

TEMPERATURE (°C)

Figure 8. Potentiometer Divider Nonlinearity Error vs. Code

Figure 11. Shutdown Current vs. Temperature

Rev. A | Page 9 of 20

AD7376

120

100

80

V

/V = ±15V

DD SS

120

100

80

V

/V = ±15V

DD SS

100kΩ

100k

10k

60

40

60

50kΩ

20

40

0

50k

20

10kΩ

–20

–40

0

–40

–20

0

20

40

60

80

100

120

0

16

32

48

64

80

96

112

128

TEMPERATURE (°C)

CODE (Decimal)

Figure 12. Total Resistance vs. Temperature

Figure 15. (ΔV_WB/V_WB)/ΔT Potentiometer Mode Tempco

350

300

250

200

150

100

50

0

0x40

0x20

–6

R

@ V /V = ±5V

DD SS

W

–12

–18

–24

–30

–36

–42

–48

–54

–60

0x10

0x08

0x04

0x02

0x01

R

@ V /V = ±15V

DD SS

W

0

–40

–20

0

20

40

60

80

100

120

1k

10k

100k

1M

TEMPERATURE (°C)

(Hz)

Figure 16. 10 kΩ Gain vs. Frequency vs. Code

Figure 13. Wiper Contact Resistance vs. Temperature

0

–6

120

100

80

V

/V = ±15V

0x40

DD SS

0x20

0x10

0x08

–12

–18

–24

–30

–36

–42

–48

–54

–60

60

10k

50k

0x04

0x02

0x01

40

20

0

100k

–20

–40

1k

10k

100k

1M

0

16

32

48

64

80

96

112

128

(Hz)

CODE (Decimal)

Figure 17. 50 kΩ Gain vs. Frequency vs. Code

Figure 14. (ΔR_WB/R_WB)/ΔT Rheostat Mode Tempco

Rev. A | Page 10 of 20

AD7376

1

0

–6

V

/V = ±15V

DD SS

0x40

0x20

CODE = MIDSCALE

= 1V

V

IN

RMS

–12

–18

–24

–30

–36

–42

–48

–54

–60

0x10

0x08

10kΩ

0.01

0x04

0x02

100kΩ

50kΩ

0x01

0.001

0.0001

10

100

1k

FREQUENCY (Hz)

10k

100k

1k

10k

100k

1M

(Hz)

Figure 21. Total Harmonic Distortion Plus Noise vs. Frequency

Figure 18. 100 kΩ Gain vs. Frequency vs. Code

1

V

/V = ±15V

DD SS

CODE = MIDSCALE

= 1kHz

f

IN

0.1

0.01

2

10kΩ

50kΩ

100kΩ

1

0.001

CH1 5V

CH2 5V

M2μs

T 50%

A CH1

4.20V

0.001

0.01

0.1

1

10

AMPLITUDE (V)

Figure 22. Total Harmonic Distortion Plus Noise vs. Amplitude

Figure 19. Midscale to Midscale-1 Transition Glitch

80

60

40

20

0

6

CODE = 40 , V = V , V = V

DD

H

A

B

SS

V

/V = 30V/0V

DD SS

= V

A

B

DD

= 0V

R

= 10kΩ

–PSRR @ Vdd/Vss = ±15V

DC ± 10% p-p AC

AB

5

4

3

2

1

0

+PSRR @ V /V

DD SS

DC ± 10% p-p AC

= ±15V

R

= 50kΩ

AB

–PSRR @ V /V = ±5V

DD SS

DC ± 10% p-p AC

+PSRR @ V /V = ±5V

DC ± 10% p-p AC

DD SS

R

= 100kΩ

AB

100

1k

10k

100k

1M

0

16

32

48

64

80

96

112

128

FREQUENCY (Hz)

CODE (Decimal)

Figure 20. Power Supply Rejection vs. Frequency

Figure 23. Theoretical Maximum Current vs. Code

Rev. A | Page 11 of 20

AD7376

THEꢀRY ꢀF ꢀPERATIꢀN

The AD7376 wiper switches are designed with the transmission

gate CMOS topology, and the gate voltage is derived from the

V_DD. Each switch’s on resistance, R_W, is a function of V_DDand

temperature (see Figure 13). Contrary to the temperature

coefficient of R_AB, the temperature coefficient of the wiper

resistance is significantly higher because the wiper resistance

doubles with every 100° increases. As a result, the user must take

into consideration the contribution of R_Won the desirable

resistance. On the other hand, each switch’s on resistance is

insensitive to the tap point potential and remains relatively flat

at 120 Ω typical at a V_DDof 15 V and a temperature of 25°C.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The part operates in rheostat mode when only two terminals

are used as a variable resistor. The unused terminal can be

floating or tied to the W terminal as shown in Figure 24.

A

W

B

Figure 24. Rheostat Mode Configuration

Assuming that a 10 kΩ part is used, the wiper’s first connection

starts at the B terminal for programming code of 0x00, where

SW_Bis closed. The minimum resistance between Terminals W

and B is therefore 120 Ω in general. The second connection is

the first tap point, which corresponds to 198 Ω (R_WB= 1/128 ×

R_AB+ R_W= 78 Ω + 120 Ω) for programming code of 0x01 and so

on. Each LSB data value increase moves the wiper up the

resistor ladder until the last tap point is reached at 10,042 Ω

(R_AB– 1 LSB + R_W). Regardless of which settings the part is

operating with, care should be taken to limit the current

conducted between any A and B, W and A, or W and B

terminals to a maximum dc current of 5 mA and a maximum

pulse current of 20 mA. Otherwise, degradation or possible

destruction of the internal switch contact can occur.

The nominal resistance between Terminals A and B, R_AB, is

available in 10 kΩ, 50 kΩ, and 100 kΩ with 30ꢀ tolerance and

has 128 tap points accessed by the wiper terminal. The 7-bit

data in the RDAC latch is decoded to select one of the 128

possible settings. Figure 25 shows a simplified RDAC structure.

A

SW

A

SHDN

SW_A

R

S

D6

D5

D4

D3

D2

D1

D0

0x7F

R

S

W

Similar to the mechanical potentiometer, the resistance of the

RDAC between the W and A terminals also produces a digitally

controlled complementary resistance, R_WA. When these

terminals are used, the B terminal can be opened. Setting the

resistance value for R_WAstarts at a maximum value of resistance

and decreases as the data loaded into the latch increases in

value. The general equation for this operation is

RDAC

LATCH

AND

DECODER

0x01

0x00

SW

B

R

SW_B

S

B

R

= R

/128

NOMINAL

S

128 − D

128

Figure 25. AD7376 Equivalent RDAC Circuit

R_WA(D) =

× R_AB+ R_W

(2)

The general equation determining the digitally programmed

output resistance between the W and the B terminals is

D

128

R_WB(D) =

×R_AB+ R_W

(1)

where:

D is the decimal equivalent of the binary code loaded in the

7-bit RDAC register from 0 to 127.

R_ABis the end-to-end resistance.

R_Wis the wiper resistance contributed by the on resistance of

the internal switch.

Rev. A | Page 12 of 20

AD7376

PROGRAMMING THE POTENTIOMETER DIVIDER

3-WIRE SERIAL BUS DIGITAL INTERFACE

Voltage Output Operation

The AD7376 contains a 3-wire digital interface ( , CLK, and

CS

SDI). The 7-bit serial word must be loaded MSB first. The

format of the word is shown in Figure 2. The positive-edge

sensitive CLK input requires clean transitions to avoid clocking

incorrect data into the serial input register. Standard logic

The digital potentiometer easily generates a voltage divider at

Wiper W to Terminal B and Wiper W to Terminal A that is

proportional to the input voltage at Terminal A to Terminal B.

Unlike the polarity of V_DDto GND, which must be positive,

voltage across Terminal A to Terminal B, Wiper W to Terminal A,

and Wiper W to Terminal B can be at either polarity.

families work well. When

is high, the clock loads data into

CS

the serial register upon each positive clock edge.

V

I

The data set-up and hold times in the specifications table

determine the valid timing requirements. The AD7376 uses a

7-bit serial input data register word that is transferred to the

A

W

V

O

internal RDAC register when the

line returns to logic high.

CS

B

Extra MSB bits are ignored.

Figure 26. Potentiometer Mode Configuration

The AD7376 powers up at a random setting. However, the

midscale preset or any desirable preset can be achieved by

If ignoring the effect of the wiper resistance for the purpose of

approximation, connecting the Terminal A to 30 V and the

Terminal B to ground produces an output voltage at the Wiper

W to Terminal B ranging from 0 V to 1 LSB less than 30 V. Each

LSB of voltage is equal to the voltage applied across Terminals A

and B divided by the 128 positions of the potentiometer divider.

The general equation defining the output voltage at V_Wwith

respect to ground for any valid input voltage applied to

Terminals A and B is

manipulating

or with an extra I/O.

RS SHDN

When the reset ( ) pin is asserted, the wiper resets to the

RS

midscale value. Midscale reset can be achieved dynamically or

during power-up if an extra I/O is used.

When the

pin is asserted, the AD7376 opens SW_Ato let

SHDN

the Terminal A float and to short Wiper W to Terminal B. The

AD7376 consumes negligible power during the shutdown mode

D

128

and resumes the previous setting once the

pin is released.

SHDN

V_W(D) =

V_A

(3)

On the other hand, the AD7376 can be programmed with any

settings during shutdown. With an extra programmable I/O

asserting shutdown during power up, this unique feature allows

the AD7376 with programmable preset at any desirable level.

A more accurate calculation that includes the effect of wiper

resistance, V_W, is

R_WB(D)

R_AB

R_WA(D)

R_AB

V_W(D) =

V_A+

V_B

(4)

Table 7 shows the logic truth table of all operation.

Table 7. Input Logic Control Truth Table¹

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

when in rheostat mode, the output voltage in divider mode is

primarily dependent on the ratio, not the absolute values, of the

internal resistors R_WAand R_WB. Therefore, the temperature drift

reduces to 5 ppm/°C.

CS RS SHDN

CLK

L

P

Register Activity

L

H

Enables SR, enables SDO pin.

Shifts one bit in from the SDI pin.

The seventh previously entered bit is

shifted out of the SDO pin.

Loads SR data into 7-bit RDAC latch.

No operation.

Sets 7-bit RDAC latch to midscale,

wiper centered, and SDO latch

cleared.

X

P

H

X

H

L

H

X

H

P

H

L

Latches 7-bit RDAC latch to 0x40.

Opens circuits resistor of Terminal A,

connects Wiper W to Terminal B,

turns off SDO output transistor.

¹P = positive edge, X = don’t care, and SR = shift register.

Rev. A | Page 13 of 20

AD7376

DAISY-CHAIN OPERATION

ESD PROTECTION

SHDN

All digital inputs are protected with a series input resistor and a

Zener ESD structure shown in Figure 29. These structures apply

CS

SDO

to digital input pins , CLK, SDI, SDO, , and

CS RS

SHDN

SERIAL

REGISTER

SDI

D

Q

CK RS

340Ω

LOGIC

CLK

RS

GND

Figure 27. Detail SDO Output Schematic of the AD7376

Figure 29. Equivalent ESD Protection Circuit

Figure 27 shows the details of the serial data output pin (SDO).

SDO shifts out the SDI content in the previous frame; therefore,

it can be used for daisy-chaining multiple devices. The SDO pin

contains an open-drain N-Channel MOSFET and requires a

pull-up resistor if the SDO function is used. Users need to tie

the SDO pin of one package to the SDI pin of the next package.

For example, in Figure 28 if two AD7376s are daisy-chained, a

total of 14 bits of data are required for each operation. The first

set of seven bits goes to U2; the second set of seven bits goes to

All analog terminals are also protected by Zener ESD protection

diodes, as shown in Figure 30.

V

DD

A

W

B

U1.

should be kept low until all 14 bits are clocked into their

CS

V

SS

respective serial registers. Then

is pulled high to complete

CS

the operation. When daisy-chaining multiple devices, users may

need to increase the clock period because the pull-up resistor

and the capacitive loading at the SDO-SDI interface may induce

a time delay to subsequent devices.

Figure 30. Equivalent ESD Protection Analog Pins

TERMINAL VOLTAGE OPERATING RANGE

The AD7376 V_DDand V_SSpower supplies define the boundary

conditions for proper 3-terminal digital potentiometer oper-

ation. Applied signals present on Terminals A, B, and W that

are more positive than V_DDor more negative than V_SSwill be

clamped by the internal forward-biased diodes (see Figure 30).

V

DD

U1

U2

R

PU

2.2kΩ

AD7376

μC

MOSI

SDO

SDI

SDO

SDI

SCLK SS

POWER-UP AND POWER-DOWN SEQUENCES

CS

CLK

CS

CLK

Because of the ESD protection diodes that limit the voltage

compliance at Terminals A, B, and W (see Figure 30), it is

important to power V_DD/V_SSbefore applying voltage to

Terminals A, B, and W. Otherwise, the diodes are forward

biased such that V_DD/V_SSare powered unintentionally and affect

the system. Similarly, V_DD/V_SSshould be powered down last.

The ideal power-up sequence is in the following order: GND,

V_DD, V_SS, digital inputs, and V_A/V_B/V_W. The order of powering

V_A, V_B, V_W, and the digital inputs is not important, as long as

they are powered after V_DD/V_SS.

Figure 28. Daisy-Chain Configuration

Rev. A | Page 14 of 20

AD7376

The ground pin of the AD7376 is a digital ground reference. To

minimize the digital ground bounce, the AD7376 digital

ground terminal should be joined remotely to the analog

ground (see Figure 31).

LAYOUT AND POWER SUPPLY BIASING

It is a good practice to employ a compact, minimum lead-length

layout design. The leads to the input should be as direct as

possible, with a minimum conductor length. Ground paths

should have low resistance and low inductance.

V

DD

V

DD

+

C1

C3

C4

Similarly, it is also good practice to bypass the power supplies

with quality capacitors. Low ESR (equivalent series resistance)

1 μF to 10 μF tantalum or electrolytic capacitors should be

applied at the supplies to minimize transient disturbances and

filter low frequency ripple. Figure 31 illustrates the basic supply

bypassing configuration for the AD7376.

10μF

0.1μF

AD7376

+

C2

10μF

V

SS

V

SS

GND

Figure 31. Power Supply Bypassing

Rev. A | Page 15 of 20

AD7376

APPLICATIꢀNS

HIGH VOLTAGE DAC

PROGRAMMABLE POWER SUPPLY

AD7376 can be configured as a high voltage DAC as high as

30 V. The circuit is shown in Figure 32. The output is

With a boost regulator such as ADP1611, AD7376 can be used

as the variable resistor at the regulator’s FB pin to provide the

programmable power supply (see Figure 33). The output is

R

[1.2 V×(1+ ²)]

R₁

D

128

V_O(D) =

(5)

D

(

₁₂₈)⋅R_AB

V_O=1.23 V×(1+

]

(6)

R₂

Where D is the decimal code from 0 to 127.

Note that the AD7376’s V_DDis derived from the output. Initially

L1 acts as a short, and V_DDis one diode voltage drop below +5 V.

The output slowly establishes to the final value.

V

DD

V

DD

R

BIAS

U2

U1A

The AD7376 shutdown sleep-mode programming can be used

to program a desirable preset level at power-up.

V+

AD7376

D1

AD8512

V–

U1B

100kΩ

ADR512

U1

V

5V

OUT

B

AD7376

AD8512

V

C

IN

ADP1611

DD

IN

U2

A

C1

0.1μF

L1

4.7μF

10μF

R2

W

R1

100kΩ

SD

R1

V

OUT

SW

RT

B

D1

1.23V

C

OUT

10μF

FB

SS

COMP

Figure 32. High Voltage DAC

R2

8.5kΩ

R

C

SS

GND

220kΩ

22nF

C

150pF

Figure 33. Programmable Power Supply

Rev. A | Page 16 of 20

AD7376

V

C1

IN

AUDIO VOLUME CONTROL

1μF

+5V

U1

+15V

R1

+5V

Because of its good THD performance and high voltage

capability, AD7376 can be used as a digital volume control. If

AD7376 is used directly as an audio attenuator or gain

amplifier, a large step change in the volume level at any

arbitrary time can lead to an abrupt discontinuity of the audio

signal, causing an audible zipper noise. To prevent this, a zero-

V

DD

100kΩ

C3

0.1μF

A

AD7376

U2

V+

C2

0.1μF

ADCM371

V–

R2

200Ω

+15V

U5

R4

V

SS

W

90kΩ

–15V

U4A

U4B

V+

V

OUT

4

5

100kΩ

6

1

2

+5V

7408

CS

R5

10kΩ

V–

U3

V+

ADCM371

V–

+5V

CLK

SDI

CLK

SDI

B

–15V

crossing window detector can be inserted to the

line to delay

CS

U6

V+

AD8541

V–

CS

GND

R3

100Ω

the device update until the audio signal crosses the window.

Since the input signal can operate on top of any dc levels rather

than absolute zero volt level, zero-crossing in this case means

the signal is ac-coupled and the dc offset level is the signal zero

reference point. The configuration to reduce zipper noise and

the result of using this configuration are shown in Figure 34 and

Figure 35, respectively. The input is ac-coupled by C1 and

attenuated down before feeding into the window comparator

formed by U₂, U₃, and U_4B. U₆is used to establish the signal zero

reference. The upper limit of the comparator is set above its

offset and, therefore, the output pulses high whenever the input

falls between 2.502 V and 2.497 V (or 0.005 V window) in this

example. This output is AND’ed with the chip select signal such

that the AD7376 updates whenever the signal crosses the

window. To avoid constant update of the device, the chip select

signal should be programmed as two pulses, rather than the one

shown in Figure 2.

Figure 34. Audio Volume Control with Zipper Noise Reduction

1

2

CHANNEL 1

FREQ = 20.25kHz

1.03V p-p

NOTES

In Figure 35, the lower trace shows that the volume level

changes from a quarter scale to full scale when a signal change

occurs near the zero-crossing window.

1. THE LOWER TRACE SHOWS THAT THE VOLUME LEVEL

CHANGES FROM QUARTER SCALE TO FULL SCALE, WITH THE

CHANGE OCCURRING NEAR THE ZERO-CROSSING WINDOW.

Figure 35. Input (Trace 1) and Output (Trace 2) of the Circuit in Figure 34

The AD7376 shutdown sleep-mode programming feature can

be used to mute the device at power up by holding

low

SHDN

and programming zero scale.

Rev. A | Page 17 of 20

AD7376

ꢀUTLINE DIMENSIꢀNS

5.10

5.00

4.90

14

8

7

4.50

4.40

4.30

6.40

BSC

1

PIN 1

0.65

BSC

1.05

1.00

0.80

0.20

0.09

1.20

MAX

0.75

0.60

0.45

8°

0°

0.15

0.05

0.30

0.19

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 36. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

10.50 (0.4134)

10.10 (0.3976)

16

1

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

1.27 (0.0500)

0.75 (0.0295)

0.25 (0.0098)

2.65 (0.1043)

2.35 (0.0925)

BSC

× 45°

0.30 (0.0118)

0.10 (0.0039)

8°

0°

0.51 (0.0201)

0.31 (0.0122)

SEATING

PLANE

COPLANARITY

0.10

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 37. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

Rev. A | Page 18 of 20

AD7376

ORDERING GUIDE

Model

AD7376AR10

AD7376AR10-REEL

AD7376ARU10

AD7376ARU10-REEL7

AD7376ARUZ10³

AD7376ARUZ10-R7³

AD7376ARWZ10³

AD7376ARWZ10-RL³

AD7376AR50

kΩ

10

50

100

10

Temperature Range

−40°C to +85°C

Package Description^{1, 2}Package Options

Quantity

16-Lead SOIC_W

14-Lead TSSOP

16-Lead SOIC_W

14-Lead TSSOP

16-Lead SOIC_W

14-Lead TSSOP

16-Lead SOIC_W

RW-16

RU-14

RW-16

RU-14

RW-16

RU-14

RW-16

47

1,000

96

1,000

96

1,000

47

1,000

47

1,000

96

1,000

96

47

AD7376AR50-REEL

AD7376ARU50

AD7376ARU50-REEL7

AD7376ARUZ50³

AD7376ARWZ50³

AD7376ARUZ100³

AD7376ARUZ100-R7³

AD7376ARWZ100³

AD7376EVAL

96

1,000

47

1

¹In SOICWB-16 package top marking, line 1 shows AD7376; line 2 shows the branding information, such that A10 = 10 kΩ, A50 = 50 kΩ, and A100 = 100 kΩ; line 3 shows

the date code in YYWW; line 4 shows the lot number.

²In TSSOP-14 package top marking, line 1 shows 7376; line 2 shows the branding information, such that A10 = 10 kΩ, A50 = 50 kΩ, and A100 = 100 kΩ; line 3 shows the

date code in YWW; back side shows the lot number.

³Z = Pb-free part with a “#” top marking on line 2 of the package.

Rev. A | Page 19 of 20

AD7376

NꢀTES

Pepltmtorey Tpchotcrl Drar

©

registered trademarks are the property of their respective owners.

C01119–0–11/05(A)

Rev. A | Page 20 of 20


型号：	AD7376AR10-REEL
厂家：	ADI
描述：	IC 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO16, MS-013AA, SOIC-16, Digital Potentiometer 光电二极管转换器电阻器
文件：	总20页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7376AR10-REEL [ADI]

相关型号：

AD7376AR10-REEL7

AD7376AR100

AD7376AR1M

AD7376AR1M-REEL

AD7376AR50

AD7376ARU10

AD7376ARU10-REEL

AD7376ARU100

AD7376ARU100-REEL7

AD7376ARU1M

AD7376ARU50

AD7376ARU50-REEL7