AD7400BRW [ADI]
Isolated Sigma-Delta Modulator; 隔离式Σ-Δ调制器
| 型号： | AD7400BRW |
| 厂家： | 
ADI |
| 描述： | Isolated Sigma-Delta Modulator |
| 文件： | 总10页 (文件大小：546K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated Sigma-Delta Modulator
AD7400/AD7401
Preliminary Technical Data
APPꢀꢂCATꢂOIS
FEATURES
AC Motor Control
Data Acquisition Systems
A/D + Opto-ꢂsolator Replacement
Up to 20 MHz Data Rate (AD7401)
10 MHz Data Rate (AD7400)
2nd Order Modulator
4 ꢀSꢁ ꢂIꢀ @16 ꢁits
Onboard Digital ꢂsolator
GEIERAꢀ DESCRꢂPTꢂOI
Onboard Reference
ꢀow Power Operation:
15 mA @ 5 V
-40ЊC to +105ЊC Operating Range
16-ld SOꢂC Package
The AD7400/AD7401 are 2nd order sigma-delta modulators
that convert an analog input signal into a high speed 1-bit data
stream with onboard digital isolation based on Analog Devices’
iCoupler® technology. The AD7400/AD7401 operate from a 5 V
power supply and accept a differential input signal of 200 mV.
The analog input is continuously sampled by the analog
modulator, eliminating the need for external sample and hold
circuitry. The input information is contained in the output
stream as a density of ones with data rates up to 20MHz. The
original information can be reconstructed with an appropriate
digital filter. The serial I/O may use a 5V or 3V supply (VDD2).
Safety and Regulatory Approvals
Uꢀ Recognition
3750 VRMS for 1 minute per Uꢀ 1577
CSA Component Acceptance Iotice ~5A
VDE Certificate of Conformity
DꢂI EI 60747-5-2 (VDE 0884 Part 2):2003-01
DꢂI EI 60950 (VDE 0805): 2001-12; EI 60950:2000
VꢂORM = 840VPEAK
The serial interface is digitally isolated. High-speed CMOS,
FUICTꢂOIAꢀ ꢁꢀOCK DꢂAGRAM
V
V
DD2
DD1
V
+
-
IN
T/H
Σ-∆ ADC
V
IN
UPDATE
ENCODE
WATCHDOG
DECODE
MDAT
BUF
CONTROL LOGIC
UPDATE
ENCODE
WATCHDOG
DECODE
REF
MCLKOUT*
GND
GND
2
1
*MCLKIN pin on AD7401
Rev. PrH
ꢂnformation furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. Io license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. ꢁox 9106, Iorwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, ꢂnc. All rights reserved.
AD7400/AD7401
Preliminary Technical Data
combined with monolithic air core transformer technology, means the onboard isolation provides outstanding performance
characteristics superior to alternatives such as optocoupler devices. The parts provide an on-chip 2.5V reference. The AD7400/AD7401
are offered in a 16-lead SOIC package and have an operating temperature range of -40°C to +105°C.
TABLE OF CONTENTS
AD7400—Specifications.................................................................. 3
AD7401—Specifications.................................................................. 4
TIMING SPECIFICATIONS1..................................................... 5
Absolute Maximum Ratings1,3......................................................... 6
Pin Functional Descriptions ........................................................8
Theory of Operation.....................................................................9
Outline Dimensions....................................................................... 10
REVꢂSꢂOI HꢂSTORY
Revision PrH: Preliminary Version
Rev. PrH | Page 2 of 10
Preliminary Technical Data
AD7400—SPECIFICATIONS1
AD7400/AD7401
Table 1. (VDD1 = VDD2 = 4.5V to 5.5V, , VꢂI+ = -200mV to +200mV and VꢂI- = 0V; TA = TMꢂI to TMAX, fMCꢀK = 10MHz unless
otherwise noted.)
Parameter
ꢁ Version1,5
Units
Test Conditions/Comments
When Tested with Sinc3 Filter4
Filter output trunctaed to 16 Bits
STATIC PERFORMANCE
Resolution
16
4
0.ꢀ
0.5
5
Bits min
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error2
LSB max
LSB max
mV max
Guaranteed No Missed Codes to 15 bits
Bipolar Input Range
Offset Drift vs. Temperature2
µV/ЊC max
µV/ЊC typ
mV/V typ
%min/max
%min/max
ppm/ЊC typ
% typ
2
2
Offset Drift vs. VDD1
0.05
1
TBD
60
Absolute Reference Voltage Tolerance
Reference Voltage Matching
VREF Drift vs. Temperature2
2
VREF Drift vs. VDD1
0.2
ANALOG INPUT
Input Voltage Ranges6
DC Leakage Current
200
1
mV min/max
µA max
DYNAMIC SPECIFICATIONS
Signal to Noise + Distortion Ratio (SINAD)2
When Tested with Sinc3 Filter4
VIN+ = 35Hz, 400mVpk-pk sine wave
70
76
-80
-70
12
15
20
20
24
dBmin
dB typ
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Effective number of bits
dB typ
dB typ
Bits
kV/µs min
kV/µs typ
µs typ
Isolation Transient Immunity
Signal Delay
Delay through filter varies with actual value of on-
board clock. Decimation by 2.
µs max
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2
0.8
1
V min
V max
µA max
pF max
3
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
POWER REQUIREMENTS
VDD1
VDD2 – 0.1
0.4
V min
V max
IO = -20 µA
IO = 20 µA
+4.5/+5.5
+4.5/+5.5
+2.7/+3.3
18.1
Vmin/Vmax
Vmin/Vmax
Vmin/Vmax
mA max
VDD2
7
IDD1
7
IDD2
1.ꢀ6
mA max
VDD1 = 5V, Digital I/Ps = 0 V or VDD1
NOTES
1 Temperature ranges as follows: -40ЊC to +105ЊC
2 See Terminology section.
3 Sample tested @ 25ЊC to ensure compliance.
4 Filter as defined by Verilog Code.
5 All voltages are relative to their respective ground.
6 Beyond the full-scale input range the output is either all zeroes or all ones.
Specifications subject to change without notice.
Rev. PrH | Page 3 of 10
AD7400/AD7401
Preliminary Technical Data
AD7401—SPECIFICATIONS3
Table 2. (VDD1 = VDD2 = 4.5V to 5.5V, , VꢂI+ = -200mV to +200mV and VꢂI- = 0V; TA = TMꢂI to TMAX, fMCꢀK = 20MHz unless
otherwise noted.)
Parameter
ꢁ Version1,5
Units
Test Conditions/Comments
When Tested with Sinc3 Filter4
Filter output trunctaed to 16 Bits
STATIC PERFORMANCE
Resolution
16
4
0.ꢀ
0.5
5
Bits min
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error2
LSB max
LSB max
mV max
Guaranteed No Missed Codes to 15 bits
Bipolar Input Range
Offset Drift vs. Temperature2
µV/ЊC max
µV/ЊC typ
mV/V typ
%min/max
%min/max
ppm/ЊC typ
% typ
2
2
Offset Drift vs. VDD1
0.05
1
TBD
60
Absolute Reference Voltage Tolerance
Reference Voltage Matching
VREF Drift vs. Temperature2
2
VREF Drift vs. VDD1
0.2
ANALOG INPUT
Input Voltage Ranges6
DC Leakage Current
200
1
mV min/max
µA max
DYNAMIC SPECIFICATIONS
Signal to Noise + Distortion Ratio (SINAD)4
When Tested with Sinc3 Filter4
VIN+ = 35Hz, 400mVpk-pk sine wave
70
76
-80
-70
12
15
20
10
12
dBmin
dB typ
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Effective number of bits
dB typ
dB typ
Bits
kV/µs min
kV/µs typ
µs typ
Isolation Transient Immunity
Signal Delay
Delay through filter varies with actual value of on-
board clock. Decimation by 2.
µs max
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2
0.8
1
V min
V max
µA max
pF max
3
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
POWER REQUIREMENTS
VDD1
VDD2 – 0.1
0.4
V min
V max
IO = -20 µA
IO = 20 µA
+4.5/+5.5
+4.5/+5.5
+2.7/+3.3
21.2
Vmin/Vmax
Vmin/Vmax
Vmin/Vmax
mA max
VDD2
7
IDD1
7
IDD2
3.ꢀ2
mA max
VDD1 = 5V, Digital I/Ps = 0 V or VDD1
NOTES
3 Temperature ranges as follows: -40ЊC to +105ЊC
4 See Terminology section.
3 Sample tested @ 25ЊC to ensure compliance.
4 Filter as defined by Verilog Code.
5 All voltages are relative to their respective ground.
6 Beyond the full-scale input range the output is either all zeroes or all ones.
Specifications subject to change without notice.
Rev. PrH | Page 4 of 10
Preliminary Technical Data
AD7400/AD7401
TꢂMꢂIG SPECꢂFꢂCATꢂOIS1
Table 3. AD7400/AD7401 Timing Specifications (VDD1 = VDD2 = 4.5V to 5.5V, TA = TMAX to TMꢂI unless otherwise noted.)
Parameter
ꢀimit at TMꢂI, TMAX Unit
Description
FMCLKOUT
10
MHz typ
AD7400
8.2/13.2
1
20
30
MHz min/max
MHz min
MHz max
ns max
2
TMCLKIN
AD7401
3
t1
Data Access Time after MCLK Rising Edge
Data Hold Time after MCLK Rising Edge
Master Clock Low Time
3
t2
15
ns min
ns max
ns max
t3
t4
0.4 x tMCLKIN
0.4 x tMCLKIN
Master Clock High Time
NOTES
1 Sample tested @ 25ЊC to ensure compliance. All input signals are specified with tr = tf = 5ns (10% to ꢀ0% of VDD1) and timed form a voltage level of 1.6 Volts. See Figure
1.
2 Mark Space ratio for the MCLKIN input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8V or 2.0V.
I
OL
200µA
TO
OUTPUT
PIN
+1.6V
C
L
50pF
200µA
I
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
t4
MCLKIN /
MCLKOUT
t3
t1
t2
MDAT
Figure 2. Data Timing
Rev. PrH | Page 5 of 10
AD7400/AD7401
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS1,3
Table 4. AD7400/AD7401 Absolute Maximum Ratings (TA = +25°C unless otherwise noted)
VDD1 to GND1
-0.3 V to +6.5V
-0.3 V to +6.5 V
-0.3 V to VDD1 +0.3V
-0.3 V to VDD2 +0.5 V
-0.3 V to VDD2 +0.3V
10mA
Capacitance (Input-Output), CI-O
Lead Temperature, Soldering
Vapor Phase (60 sec)
1pF
VDD2 to GND2
Analog Input Voltage to GND1
Digital Input Voltage to GND2
Output Voltage to GND2
Input Current to Any Pin Except Supplies2
Operating Temperature Range
Storage Temperature Range
Junction Temperature
+215°C
+220°C
TBD
Infared (15 sec)
ESD
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
-40°C to +105°C
-65°C to +150°C
+150°C
SOIC Package
2Transient currents of up to 100mA will not cause SCR latch up.
3 All voltages are relative to their respective ground.
θJA Thermal Impedance
θJC Thermal Impedance
Resistance (Input-Output), RI-O
8ꢀ.2 °C/W
55.6 °C/W
1012Ω
REGUꢀATORY ꢂIFORMATꢂOI
(PEIDꢂIG)
Table 5. ꢂnsulation and Safety Related Specifications
Parameter
Symbol Value
Units
Conditions
Input-Output Withstand Momentary
Withstand Voltage1
VISO
3750 min.
V
Note 1
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Internal Gap (Internal
Clearance)
Tracking Resistance (Comparative
Tracking Index)
L(I01)
L(I02)
8.4 min
8.1 min
0.025 min
>175
mm
mm
mm
V
Measured from input terminals to output terminals, shortest
distance through air.
Measured from input terminals to output terminals, shortest
distance path along body.
Insulation distance through insulation.
CTI
DINIEC112/VDE 0303Part1
Isolation Group
IIIa
MaterialGroup(DINVDE0110,1/8ꢀ,Table1)
Uꢀ1
2
CSA
VDE
Recognized under 1577
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN EN 60747-5-2
component recognition program1
(VDE 0884 Part 2):2003-012
Double insulation, 3750 V rms
isolation voltage
Reinforced insulation per
CSA 60ꢀ50-1-03 and IEC 60ꢀ50-1,
Basic insulation, 8ꢀ1 V peak
630 V rms maximum working voltage
Complies with DIN EN 60747-5-2 (VDE 0884 Part 2):2003-01,
DIN EN 60ꢀ50 (VDE 0805):2001-12; EN 60ꢀ50:2000
Reinforced insulation, 8ꢀ1 V peak
NOTES
1
In accordance with UL1577, each AD7400/AD7401 is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (current leakage detection limit =
5 µA).
2
In accordance with DIN EN 60747-5-2, each AD7400/AD7401 is proof tested by applying an insulation test voltage ≥ 1670 V peak for 1 second (partial discharge
detection limit = 5 pC).
Rev. PrH | Page 6 of 10
Preliminary Technical Data
AD7400/AD7401
DꢂI EI 60747-5-2 (VDE 0884 PART 2) ꢂISUꢀATꢂOI CHARACTERꢂSTꢂCS (PEIDꢂIG)
Table 6.
Description
Symbol
Characteristic
Unit
Installation classification per DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
I–IV
I–III
40/105/21
2
891
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b1
VIORM
VPR
Vpeak
V peak
1670
VIORM × 1.875 = VPR, 100% Production Test,
tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1)
VPR
Vpeak
Vpeak
1426
1069
V
IORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5p C
After Input and/or Safety Test Subgroup 2/3)
IORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5p C
V
Highest Allowable Overvoltage
VTR
6000
V peak
(Transient Overvoltage, tTR = 10 sec)
Safety-Limiting Values (Maximum value allowed in the event of a failure, also seeThermal
Derating Curve)
Case Temperature
Side 1 Current
Side 2 Current
TS
IS1
IS2
RS
150
°C
TBD
TBD
>10ꢀ
mA
mA
Ω
Insulation Resistance at TS, VIO = 500 V
This isolator is suitable for “basic electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by
means of protective circuits.
"*" marking on packages denotes DIN EN 60747-5-2 approval for 891 V peak working voltage.
Rev. PrH | Page 7 of 10
AD7400/AD7401
Preliminary Technical Data
V
V
DD1
GND
GND
1
2
3
4
5
6
1
2
3
4
5
6
DD1
16
15
16
15
2
2
V
+
-
V
+
-
NC
V
NC
V
IN
IN
V
V
AD7400
AD7401
IN
IN
DD2
DD2
MCLKIN
NC
14
13
12
11
14
13
12
11
NC
NC
NC
MCLKOUT
NC
NC
NC
NC
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
MDAT
MDAT
V
V
10 NC
GND
10 NC
GND
DD1
7
8
7
8
DD1
GND
GND
1
9
9
1
2
2
Pin Functional Descriptions
Table 7. AD7400/AD7401 Pin Function Descriptions
Pin
Iumber
AD7400
Pin
AD7401 Pin
Mnemonic
Description
Mnemonic
1,7
VDD1
VDD1
Supply Voltage, 5 V 10%. This is the supply voltage for the isolated side of the
AD7400/AD7401 and is relative to GND1.
2
3
VIN+
VIN-
VIN+
VIN-
Positive analog Input, range of 200 mV .
Negative analog input (normally connected to GND1).
18
MCLKIN
Master Clock. Logic Input. An external clock is applied at this pin. A serial clock input from
1MHz to 20MHz may be applied to this pin on the AD7401. The bit stream form the
modultaor is valid on the rising edge of MCLKIN.
18
MCLKOUT
VDD2
Master Clock. Logic Output, 10MHz typical. The bit stream form the modultaor is valid on the
rising edge of MCLKOUT on the AD7400.
Supply Voltage, 5 V 10% or 3V 10%. This is the supply voltage for the non-isolated side of
the AD7400/AD7401 and is relative to GND2.
14
VDD2
8
GND1
GND2
NC
GND1
GND2
NC
Ground. This is the ground reference point for all circuitry on the isolated side of the
AD7400/AD7401.
Ground. This is the ground reference point for all circuitry on the non-isolated side of the
AD7400/AD7401.
ꢀ,16
4-6,10,12,15
No Connect
Rev. PrH | Page 8 of 10
Preliminary Technical Data
AD7400/AD7401
Theory of Operation
input signal. Figure 4 shows a typical application circuit where
the AD7400/AD7401 is used to provide isolation between the
analog input, a current sensing resistor, and the digital output
which is then processed by a digital filter to provide an N-bit
word.
CꢂRCUꢂT ꢂIFORMATꢂOI
The AD7400/AD7401 Isolated Sigma-Delta Modulator converts
an analog input signal into a high-speed, (10MHz using on-
board MCLK on AD7400, or up to 20MHz using external
MCLK on AD7401), single-bit data stream; the time average of
the modulator’s single-bit data is directly proportional to the
ISOLATED
+5V
NON-ISOLATED
+5V/+3V
AD7400
V
DD1
V
V
DD
DD2
3
SINC FILTER
MDAT
SIGMA-
DELTA
MOD/
V
+
DECODER
ENCODER
IN
+
MDAT
CS
INPUT
CURRENT
V
-
ENCODER
IN
MCLKOUT
MCLK
SCLK
SDAT
R
SHUNT
CCLK
GND
MCLKIN
(UP TO 20MHz
with AD7401)
DECODER
GND
GND
2
1
Figure 4. Typical Application Circuit
Table 8. Analog ꢂnput Range
Analog ꢂnput
Voltage ꢂnput
Full Scale Range
+Full Scale
640 mV
+320 mV
+200 mV
0 mV
+ Specified Input range
Zero
-Specified Input range
-Full Scale
-200 mV
-320mV
Rev. PrH | Page ꢀ of 10
AD7400/AD7401
Preliminary Technical Data
OUTLINE DIMENSIONS
0.4134 (10.50)
0.3976 (10.10)
16
9
1
8
0.1043 (2.65)
0.0925 (2.35)
PIN 1
0.0295 (0.75)
0.0098 (0.25)
x 45°
0.0118 (0.30)
0.0039 (0.10)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0201 (0.51)
SEATING
PLANE
0.0126 (0.32)
0.0091 (0.23)
0.0130 (0.33)
Figure 2. 16-Lead Short Outline Package [SOIC] Wide Body (RW-16)—Dimensions shown in millimeters
ESD CAUTꢂOI
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Ordering Guide
AD7266 Products
AD7400BRW
Temperature Package
–40°C to +105°C
Package Description
Package Outline
RW-16
Short Outline I.C. Package
Short Outline I.C. Package
AD7401BRW
–40°C to +105°C
RW-16
© 2004 Analog Devices, ꢂnc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
PR04718-0-3/04(PrH)
Rev. PrH | Page 10 of 10
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