AD74322 [ADI]
Low Cost, Low Power Stereo Audio Analog Front End; 低成本,低功耗立体声音频模拟前端型号: | AD74322 |
厂家: | ADI |
描述: | Low Cost, Low Power Stereo Audio Analog Front End |
文件: | 总20页 (文件大小:122K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LowCost,LowPower
a
Preliminary Technical Data
StereoAudioAnalogFrontEnd
AD74322
FEATURES
FUNCTIONALBLOCKDIAGRAM
2.5V Stereo Audio Codec w ith 3.3 V Tolerant Digital
Interface
Supports 96 kHz Sam ple Rates
Supports 16/ 18 / 20/ 24-Bit Word Lengths
Multibit Sigm a Delta Modulators w ith
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scram bling DACs - Least Sensitive to J itter
Perform ance (20 Hz to 20 kHz)
DVDD1(EXT) DVDD2(INT) CLKIN
AVDD
VIN1P
ADC
CDIN
CDOUT
CCLK
CHANNEL 1
Control
SPI
VIN1N
Block
Port
VIN2P
ADC
CLATCH
CHANNEL 2
VIN2N
ASDATA/SDO
DSDATA/SDI
LRCLK/SDIFS
SDOFS
VOUT1P
VOUT1N
VOUT2P
VOUT2N
DAC
90 dB ADC and DAC SNR
CHANNEL 1
2
I S
Digitally Program m able Input/ Output Gain
On-chip Volum e Controls Per Output Channel
Hardw are and Softw are Controllable Clickless Mute
Supports 256xFs, 512xFs and 768xFs Master Mode Clocks
Master Clock Pre-Scaler for use w ith DSP m aster clocks
Flexible Serial Data Port w ith Right-J ustified, Left-
J ustified, I2S-Com patible and DSP Serial Port Modes
Supports Packed Data Mode (“TDM”) for cascading
devices.
Port
DAC
Reference
BCLK/SCLK
CHANNEL 2
REFCAP
AGND
AVDD
DGND
DVDD1(EXT) DVDD2(INT) CLKIN
ADC
CDIN
CDOUT
CCLK
VIN1
On-Chip Reference
16, 20 and 24-Lead SOIC, SSOP and TSSOP Package
options.
CHANNEL 1
Control
SPI
Block
Port
ADC
CLATCH
VIN2
CHANNEL 2
APPLICATIONS
Digital Video Cam corders (DVC)
Portable Audio Devices (Walkm an etc)
Audio Processing
Voice Processing
Conference Phones
ASDATA
DSDATA
LRCLK
DAC
VOUT1
VOUT2
CHANNEL 1
2
I S
Port
DAC
Reference
General Purpose Analog I/ O
BCLK
CHANNEL 2
G E NE R AL D E S C R IP T IO N
REFCAP
DGND
AGND
AVDD
T he AD74322 is a front-end processor for general purpose
audio and voice applications. It features two multi-bit Σ∆
A/D conversion channels and two multi-bit Σ∆ D/A
conversion channels. Each ADC channel provides >85 dB
signal-to-noise ratio while each DAC channel provides
>90 dB, both over an audio signal bandwidth.
DVDD1(EXT) DVDD2(INT) CLKIN
ADC
VIN1
CHANNEL 1
Control
Block
ADC
T he AD74322 is particularly suitable for a variety of ap-
plications where stereo input and output channels are
required, including audio sections of Digital Video
Camcorder, portable personal audio devices and the
analog front ends of conference phones . Its high quality
performance also make it suitable for speech and telephony
applications such as speech recognition and synthesis and
modern feature phones.
VIN2
CHANNEL 2
SDO
SDI
DAC
VOUT1
VOUT2
CHANNEL 1
Data
Port
SDIFS
SDOFS
SCLK
DAC
Reference
CHANNEL 2
REFCAP
AGND
DGND
REV. Pr D 03/00
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w.analog.com
Analog Devices, Inc., 1998
PRELIMINARY TECHNICAL DATA
AD74322
An on-chip reference voltage is included but can be
bypassed if required for use with an external reference
source.
T he AD74322 offers sampling rates which, depending on
MCLK selection and MCLK divider ratio, range from 8
kHz in the voiceband range to 96 kHz in the audio range.
T he digital interface to the AD74322 is configured as two
separate ports which allow separation of device control
and data streams. Control and status are monitored using
an SPI® compatible serial port while the input and output
data streams are controlled using an I2S® port. T he two
I2S streams are controlled by a common Bit-Clock and
Left/Right Clock pins. T here is also a DSP mode
available on the audio data port which will also allow both
control and data to be streamed through the same interface
where controller resources are limited.
T he AD74322 is available in various lead count package
options. T hese range from a 16-pin variant with single-
ended inputs/outputs and no SPI port through a 20-pin
variant with single-ended inputs/outputs and an SPI port
to a 24-pin variant with differential inputs/outputs and an
SPI port. T hese devices will be available in SOIC, SSOP
and T SSOP package options and are specified for the
industrial temperature range of -40°C to +85°C.
–2–
Pr D 03/00
AD74322
PRELIMINARY TECHNICAL DATA
AD74322A
Typ
PARAMETER
Min
Max
Units
Test Conditions
AN ALO G -T O -D IG IT AL C O N VERT ERS
ADC Resolution (all ADCs)
DynamicRange(20Hzto20kHz,-60dBInput)
No Filter
24
Bits
90
dB
dB
dB(%)
dB
dB
dB
WithA-WeightedFilter
TotalHarmonicDistortion+ Noise
InterchannelIsolation
InterchannelGainMismatch
ProgrammableInputGain
GainStepSize
92
-85(0.0056)
TBD
TBD
12
3
dB
OffsetError
0
LSB
Full Scale Input Voltage At Each Pin
Automatic Level Control
AttackTimeResolution
AttackTime
DecayTimeResolution
DecayTime
0.5 (1.414)
Vrms (Vpp) Single Ended
TBD
TBD
TBD
TBD
TBD
Bits
µs/Bit
Bits
µs/Bit
ppm/°C
kΩ
GainDrift
InputResistance
10
InputCapacitance
15
pF
Common Mode Input Volts
1.1V
V
D IG IT AL-T O -AN ALO G C O N VERT ERS
DynamicRange(20Hzto20kHz,-60dBInput)
No Filter
90
92
dB
dB
WithA-WeightedFilter
TotalHarmonicDistortion+ Noise
InterchannelIsolation
-85(0.0056)
TBD
dB(%)
dB
InterchannelGainMismatch
DCAccuracy
TBD
dB(%)
Gain Error
InterchannelGainMismatch
Gain Drift
InterchannelCrosstalk(EIAJmethod)
InterchannelPhaseDeviation
VolumeControlStepSize(1023LinearSteps)
VolumeControlRange (MaxAttenuation)
MuteAttenuation
TBD
TBD
TBD
TBD
TBD
0.098
60
%
ppm/°C
dB
dB
Degrees
%
dB
-100
dB
De-emphasisGainError
+/-0.1
??
dB
Full Scale Output Voltage At Each Pin
Output Resistance At Each Pin
CommonModeOutputVolts
0.5 (1.414)
Vrms(Vpp) Single Ended
??
2.25
Ω
V
REFERENCE(Internal)
AbsoluteVoltage,VREF
VREF TC
1.1
TBD
V
ppm/°C
ADCDECIMATIONFILTER
PassBand
0.xxxFs
±0.00xx
0.xxFs
Hz
dB
Hz
Hz
dB
ms
PassBandRipple
TransitionBand
StopBand
StopBandAttenuation
GroupDelay
0.xxFs
0.xxFs
70
lll/Fs
nnn/Fs
mmm/Fs
DACINTERPOLATIONFILTER
PassBand
0.xxxFs
±0.00xx
0.xxFs
Hz
dB
Hz
Hz
dB
ms
PassBandRipple
TransitionBand
StopBand
StopBandAttenuation
GroupDelay
0.xxFs
0.xxFs
70
lll/Fs
nnn/Fs
mmm/Fs
PR D 03/00
–3–
(AVDD = DVDD2 = +2.5V ±10%, DVDD1 = 3.0V ±10%, fCLKIN = 12.288 MHz,
SAMP = 48 kHz, T = TMIN to T , unless otherwise noted)
AD74322–SPECIFICATIONS f
A
MAX
AD74322A
Typ
P ARAMETER
Min
M a x
Units
Test Conditions
LOGICINPUT
V
INH,InputHighVoltage
DVDD1-0.8
DVDD1
0.8
+10
V
V
µA
pF
VINL,InputLowVoltage
InputCurrent
InputCapacitance
0
-10
10
LOGICOUTPUT
VOH,OutputHighVoltage
VOL,OutputLowVoltage
Three-StateLeakageCurrent
DVDD1-0.4
DVDD1
0.4
+10
V
V
µA
0
-10
POWERSUPPLIES
AVDD,DVDD2
DVDD1
2.25
2.7
2.5
3.0
2.75
3.3
V
V
POWERCONSUMPTION
AllSectionsOn
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
µA
ADCsOnOnly
DACsOnOnly
ReferenceOnOnly
PowerdownMode
Pr D 03/00
–4–
PRELIMINARY TECHNICAL DATA
AD74322
O R D E R ING G U ID E
Model
Range
P ackage
AD 74322D AR
AD 74322D ARU
AD 74322AAR
AD 74322AARU
AD 74322AAR
AD 74322AARU
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
R-16
RU -16
R-20
RU -20
R-24
RU -24
C AUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the XX0000 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
VINN1
1
2
24 VOUTN1
23 VOUTN2
VINN2
VINN1
VINP1
VOUTN1
3
4
22
21 VOUTP1
REFCAP
AGND
AVDD
5
6
20
19
RESET
DGND
18 SDO
7
8
9
DVDD2
17 SDFS
16 SDI
DVDD1
MCLK
SCLK
COUT
10
11
12
15
14
CCLK
CIN
13 CLATCH
VINP2 1
20 VOUTP2
19
VINP1
2
VOUTP1
VINP2 1
16 VOUTP2
15
REFCAP
AGND
3
4
18 AVDD
VINP1
2
VOUTP1
17 RESET
REFCAP
AGND
3
4
14 AVDD
DGND
5
6
16 SDO
13 RESET
DVDD2
15
14
SDFS
SDI
DGND
5
6
12 SDO
DVDD1
MCLK
7
8
9
DVDD2
11
10
SDFS
SDI
13 SCLK
12 COUT
DVDD1
MCLK
7
8
CCLK
CIN
9
SCLK
CLATCH
11
10
Pr D 03/00
–5–
PRELIMINARY TECHNICAL DATA
AD74322
P IN FUNC TIO N D E SC RIP TIO N (SINGLE -E ND E D I/O ; NO SP I P O RT)
Mnem onic
I/O
Function
VIN 1
I
Analog Input - Channel 1
VIN 2
I
Analog Input - Channel 2
VO U T 1
VO U T 2
RE F C AP
AVDD
O
O
I/O
Analog Output - Channel 1
Analog Output - Channel 2
Internal Reference - Can also be used for connection of an external reference
AnalogPowerSupplyConnection
AGND
AnalogGround/SubstrateConnection
DigitalPowerSupplyConnection(Interface)
DigitalPowerSupplyConnection (Core)
DigitalGround/SubstrateConnection
DVDD1
DVDD2
DGND
MCLK
I
ExternalClockConnection
S D O
SD I
S D F S
RESET
SC L K
O
I
I /O
I
I/O
ADC Serial Data Out - DSP Mode
DAC Serial Data In - DSP Mode
Serial Data Input Frame Sync - DSP Mode
Powerdown/Reset Input
Serial Clock - DSP Mode
P IN F UNC T IO N D E SC RIP T IO N (SINGLE - E ND E D I/O WIT H SP I P O RT )
Function
Mnem onic
I/O
VIN 1
I
Analog Input - Channel 1
VIN 2
I
Analog Input - Channel 2
VO U T 1
VO U T 2
RE F C AP
AVD D
O
O
I/O
Analog Output - Channel 1
Analog Output - Channel 2
Internal Reference - Can also be used for connection of an external reference
Analog Power Supply Connection
Analog Ground/Substrate Connection
Digital Power Supply Connection (Interface)
Digital Power Supply Connection (Core)
D igital Ground/Substrate C onnection
External Clock Connection
AG N D
D VD D 1
D VD D 2
D G N D
M C L K
I
C D IN
C D O U T
C C L K
C L AT C H
ASD AT A
D SD AT A
L RC L K /
BC L K
I
O
I
I
O
I
I/O
I/O
I
Serial Data In on SPI Control Port
Serial Data Out on SPI Control Port
Serial Clock on SPI Control Port
Serial Data Latch on SPI Control Port
ADC Serial Data Out - I2S
DAC Serial Data In - I2S
Left/Right Channel Select - I2S
Bit Clock - I2S
R E SE T
Powerdown/Reset Input
–6–
Pr D 03/00
PRELIMINARY TECHNICAL DATA
AD74322
P IN F UNC T IO N D E SC RIP T IO N (D IF F E RE NT IAL I/O WIT H SP I P O RT )
Mnem onic
I/O
Function
VIN P1
VIN N 1
VIN P2
VIN N 2
VO U T P 1
VO U T N 1
VO U T P 2
VO U T N 2
RE F C AP
AVD D
I
I
I
I
Analog Input - Channel 1 Positive
Analog Input - Channel 1 Negative
Analog Input - Channel 2 Positive
Analog Input - Channel 2 Negative
Analog Output - Channel 1 Positive
Analog Output - Channel 1 Negative
Analog Output - Channel 2 Positive
Analog Output - Channel 2 Negative
Internal Reference - Can also be used for connection of an external reference
Analog Power Supply Connection
Analog Ground/Substrate Connection
Digital Power Supply Connection (Interface)
Digital Power Supply Connection (Core)
D igital Ground/Substrate C onnection
External Clock Connection
O
O
O
O
I/O
AG N D
D VD D 1
D VD D 2
D G N D
M C L K
I
C D IN
C D O U T
C C L K
C L AT C H
ASD AT A
D SD AT A
L RC L K /
BC L K
I
O
I
I
O
I
I/O
I/O
I
Serial Data In on SPI Control Port
Serial Data Out on SPI Control Port
Serial Clock on SPI Control Port
Serial Data Latch on SPI Control Port
ADC Serial Data Out - I2S
DAC Serial Data In - I2S
Left/Right Channel Select - I2S
Bit Clock - I2S
R E SE T
Powerdown/Reset Input
Pr D 03/00
–7–
PRELIMINARY TECHNICAL DATA
AD74322
F U NC T IO NAL D E S C R IP T IO N
R efer en ce
T he AD74322 features an on-chip reference whose
nominal value is 1.125 V.A __ nF capacitor applied at the
REFCAP pin is necessary to stabilise the referrence. (See
F igure < REF C AP_Int> )
ADCSection
TherearetwoADC channelsin theAD74322,configured asastereo
pair.EachADC channelcanbeindependentlymuted. Theinputpins
areswitchedbetweendifferentialinputsorfoursingleendedinputs
accordingly. Thegainblockcanbeprogrammedforindependentleftand
rightgains,in stepsof+3dB,from 0dBto+12dB. TheADC operatesat
anoversamplingratioof128andthedecimationfilterreducestheoutput
to the standard sample rates. T he output maximum
sample rate is 96 kHz at ASDAT A.
AD743xx
REFCAP
Autom aticLevelControl
AnalogSigm a Delta Modulator
Decim ator Section
Thedigitaldecimation filterhasapassband rippleof ±0.01dBand a
stopband attenuation of70dB. Thefilterisan FIRtypewithalinear
phaseresponse. Thegroup delayat48kHzis ??us. Outputsamplerates
up to 96 kHz are supported.
Figure <REFCAP_Int>
Ifit isrequired tousean externalreference, becauseofitsvalueorits
referencetempco,theinternalreferencecanbedisabledviaControl
Register__andtheexternalreferenceappliedattheREFCAP pin(See
Figure<REFCAP_Ext>).
InputSignalswing
Each ADC input hasan input rangeof0.5 VRMS /1.414 VP-P (Single-
Ended) about abiaspoint equaltoVREFCAP (SeeFigure
<Input_Swing>)
AD743xx
VINPx
AD743xx
V
1.414 V
1.414 V
REFCAP
REFCAP
P-P
P-P
1.0 V
REFCAP
V
EXTERNAL
REFERENCE
VINNx
Figure <Input_Swing>
DACSection
Figure <REFCAP_Ext>
Master ClockingScheme
TheAD74322hastwoDAC channelsarranged asastereopair,withtwo,
fullydifferentialvoltage,analogoutputsforimprovednoiseanddistortion
performance. Eachchannelhasit’sownindependentlyprogrammable
attenuatorwithamaximum attenuationof63dB,adjustablein1dBsteps.
Digitalinputsareviaaserialdatainputpin and acommon frame
(DLRCLK)andbit(DBLCK)clockorusinga‘packeddata’mode,both
channelscanbeinputusingasingledatapin.
TheupdaterateoftheAD74322’sADC andDAC channelsrequirean
internalmasterclock(IMCLK)whichis256timesthatsampleupdate
rate(IMCLK = 256*FS).In ordertoprovidesomeflexibilityin
selecting sample rates, the device has a series of three
master clock pre-scalers which are programmable and
allow the user to choose a range of convenient sample
rates from a single external master clock. T he master
clock signal to the AD74322 is applied at the MCLK pin.
T he MCLK signal is passed through a series of two
programmable M CLK pre-scalers (divider) circuits which
can be selected to reduce the resulting Internal MCLK
(IMCLK) frequency if required. T he first MCLK pre-
scaler provides divider ratios of /1 (pass through), /2, /3
while the second pre-scaler provides divider ratios of ./1
(pass through), /2, /4 and the third pre-scaler provides
ratios of /1 (pass through), /2 and /5..
Interpolator Section
DigitalSigm a Delta Modulator
DAC
AnalogOutputFilter
OutputSignalswing
Each ADC input hasan output rangeof0.5 VRMS /1.414 VP-P (Single-
Ended) about abiaspoint equaltoVREFCAP (SeeFigure
<Output_Swing>)
Programmable
MCLK
Divider
AD743xx
VOUTPx
V
1.414 V
1.414 V
REFCAP
REFCAP
P-P
P-P
Pre-Scaler 1
Pre-Scaler 2
/1
/2
/3
/1
/2
/4
MCLK
IMCLK
V
VOUTNx
Control Reg
Figure <Output_Swing>
–8–
Pr D 03/00
PRELIMINARY TECHNICAL DATA
AD74322
2.4 V
3.3 V
5.0 V
FILTER
DUAL
REGULATOR
DVDD
AVDD
VDD2
VDD1
4
4
AD743xx
DSP
AGND
DGND
DGND
Figure <PSU_Connection>
Figure <MCLK_Divider>
a known state following the power-up of the device. T here
is also a software reset capability available by setting the
RESET bit in Control Register _. T his control register is
accessed through the Control Port.
T he divider ratios will allow more convenient sample rate
selection from a common MCLK which may be required
in many voice related applications.
Exa m ple 1: fSAMP = 48 kHz a nd 8 kHz r equir ed
P ower Supplies and Gr ounds
T he AD74322 features three separate supplies: AVDD,
D VD D 1 and D VD D 2.
MCLK = 48*103 * 256 = 12.288 MHz to cater for 48
kHz fSAMP
AVDD is the supply to the analog section of the device
and must therefore be of sufficient quality to preserve the
AD74322’s performance characteristics. It is nominally a
2.4 V supply.
For fSAMP = 8 kHz, it is necessary to use the /3 setting in
Pre-Scaler 1, the /2 setting in Pre-Scaler 2 and pass
through in Pre-Scaler 3. T his results in an IMCLK =
8*103 * 256 = 2.048 MHz (= 12.288 MHz/6).
DVDD1 is the supply for the digital interface section of
the device. It is fed from the digital supply voltage of the
DSP or controller to which the device is interfaced and
allows the AD74322 to interface with devices operating at
supplies of between 2.4 V -5% to 3.3 V + 10%.
Exa m ple 2: fSAMP = 48 kHz a nd 32 kHz r equir ed
MCLK = 24.576 MHz
For fSAMP = 48 kHz, it is necessary to use the /2 setting in
Pre-Scaler 1 and the /1 (pass-through) setting in Pre-
Scaler 2 and pass through in Pre-Scaler 3. T his results in
an IMCLK = 48*103 * 256 = 12.288 MHz.
DVDD2 is the supply for the digital core of the
AD74322. It is nominally a 2.4 V supply.
For fSAMP = 32 kHz, it is necessary to use the /3 setting in
Pre-Scaler 1 and the /1 (pass-through) setting in Pre-
Scaler 2 and pass through in Pre-Scaler 3. T his results in
an IMCLK = 32*103 * 256 = 8.192 MHz.
Exa m ple 3: fSAMP = 44.1 kHz a nd 11.025 kHz r equir ed
MCLK = 44.1*103 * 256 = 11.2896 MHz to cater for
44.1 kHz fSAMP
For fSAMP = 11.025 kHz, it isnecessaryto usethe/1 settingin Pre-
Scaler 1 and the /4 setting in Pre-Scaler 2 and pass
through in Pre-Scaler 3. T his results in an IMCLK =
11.025*103 * 256 = 2.8224 MHz (= 11.2896 MHz/4).
SampleRates
Forallapplicationsthesamplingrateisdefinedbytheinternalmaster
clockfrequency(IMCLK)whereIMCLK = 256*fSAMP
.
P ower - O n Reset
T he AD74322 features a power-on reset circuit which
ensures that all internal circuitry is reset and initialised to
Pr D 03/00
–9–
PRELIMINARY TECHNICAL DATA
AD74322
Sampling Rates (kHz) using Scalar (Divider) Ratios (assumes 256fs)
MCLK
(MHz)
1
8
2
4
3
-
4
2
5
-
-
-
-
-
6
-
8
1
9
-
-
-
-
-
10
-
12
-
15
-
2.048
12.288
16.384
24.576
36.864
48
64
96
-
24
32
48
-
-
12
16
24
-
-
6
-
-
-
-
-
8
-
-
-
-
-
12
-
-
-
-
48
24
-
12
-
T a ble <M C LK_D ivider >
MCLK (MHz)
512fS
Sam pling Rate
fS (kHz)
Interpolator
Mode
256fS
2.048
768fS
6.144
8
16
8x (Normal)
4x (Double)
4.096
11.1
22.2
8x (Normal)
4x (Double)
2.8224
8.192
5.6448
8.4672
24.576
33.8688
36.864
32
64
8x (Normal)
4x (Double)
16.384
44.1
88.2
8x (Normal)
4x (Double)
11.2896
12.288
22.5792
24.576
48
96
8x (Normal)
4x (Double)
T able <M C LK_Select>
–10–
Pr D 03/00
PRELIMINARY TECHNICAL DATA
AD74322
INT E R F AC ING
Data in and out of the Control Port go through a 16-bit
shift register whose contents are mapped to the internal
registers using the mapping scheme of Figure
TheAD74322featurestwoseparateinterfaces,ControlandData,which
areusedtoprogram controlsettingsandsend/receivesampledata
respectively.TheControlinterfaceisimplementedusinganSPI type
protocolbuttransfers16-bitsperframe.TheDatainterfaceuseseithera
DSP or I2S protocoltotransferstereodatasamplesbetween controller
andcodec.TheDSP compatibleinterfacemodeallowsdatasamplestobe
transferred in aprotocolthatissupported bytheserialinterfacesofmost
fixed-andfloating-pointDSPs.
<ContPortMap>. A 16-bit word received by the Control
Port is decoded as a read or write to a register address set
by bits 15 - 12. T his 4-bit register address selects 1 of 16
registers as shown in T able <ContRegMap>. Bit 11
selects whether a register read or write is requested -
Write = 0, Read = 1. Bit-10 is reserved. Bits 9 through 0
contain register data. Each Control register’s contents are
detailed below.
InordertoreduceperipheralrequirementswheninterfacingtheAD74322
with thehostDSP,theDSP modeallowstheDSP tosend both dataand
controlinformation tothedeviceviathedatainterface.Thisisthedefault
modeand requiresuserstoonlyuseasingleDSP SPORT tobothcontrol
thedeviceand serviceitwithdatasamples.
DataInterface
Therearetwomodesofoperation ofthedatainterface:DSP modeand
I2Smode.ThedefaultmodeofthedatainterfaceisaDSP modewhich
combinescontroland datafunctionsin asingleprotocol.Thisistoreduce
theperipheraloverheadrequiredontheDSP wheninterfacingtothe
AD74322.Thismodeoperatesin astandard DSP serialformat.In I2S
modethedatainterfacestreamsaudiodatasamplesbeingsenttoor
receivedfrom theDACsandADCsrespectively,usingtheI2Sserial
protocol.
ControlInterface
ControloftheAD74322operation isviaasetof16ControlRegisters
whichareprogrammedthroughtheControlPort.TheControlPort
protocolissimilartotheSPIÒ protocolwiththeexception that16-bitsof
dataaretransferred perframe.TheControlPortconsistsofthefollowing
pins:CCLK -ControlPortSerialClock,CLATCH -ControlPortLatch
orFramesignal,CDIN -ControlPortSerialDataIn and CDOUT -
ControlPortDataOut.CLATCH isaframingsignalthatisactivelow.
When asserted,itgatestheotherinterfacelinesasbeingactive.CCLK is
usedtoclockinputdataonCDIN andclockoutput(readback)dataon
CDOUT.Figure<Control_Interface> detailstheconnectivityofthe
ControlPorttoacontrollerandFigure<Control_Timing> detailsthe
interfacetiming.
In eithermodeitcan beconfigured aseitheramasterorslavedevice
ensuringconnectivitytothelargestnumberofhostprocessors.
DSPMode
TheDSPmodeallowsinterfacingtomostfixed-andfloating-pointDSPs
aswellasotherprocessorssuch asRISCsetcthathavingserialportsthat
supportsynchronouscommunications.Thekeyfeatureofsynchronous
DSP communicationsisthattheserialdataisframed byaseparateFrame
Syncsignal.Figures<Data_DSP_Slave>and<Data_DSP_Master>detail
connectivityinMasterMode(codecismaster)andSlaveMode(codecis
slave)respectively.
AD743xx
CDIN CLATCH CCLK CDOUT
AD743xx
(MASTER)
LRCLK/SDIFS
TFS
DSDATA/SDI
DT
DSP
(SLAVE)
BCLK/SCLK
SCLK
ASDATA/SDO
DR
CONTROLLER
RFS
SDOFS
Figure <Data_DSP_Slave>
Figure <Control_Interface>
CCLK
CDIN
MSB
MSB
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
CDOUT
CLATCH
Figure <Control_Tim ing>
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–11–
PRELIMINARY TECHNICAL DATA
AD74322
BCLK/
SCLK
LRCLK/
FS
DSDATA/
SDI
CONTROL
STATUS
LEFT DAC
LEFT ADC
RIGHT DAC
ASDATA/
SDO
RIGHT ADC
Figure <DSP_Protocol>
AD743xx
(SLAVE)
LRCLK/SDIFS
DSDATA/SDI
BCLK/SCLK
TFS
DT
LRCLK/SDIFS
TFS
DT
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
ADSP-
21065L
(MASTER)
DSP
(MASTER)
TCLK
DR
SCLK
DR
ASDATA/SDO
RFS
RCLK
AD743xx
(SLAVE)
RFS
SDOFS
Figure <Data_DSP_Master>
Figure <Data_I2S_DSP_Master>
Theserialprotocolusesafixed position fordatabeingsenttoorreceived
from theLeftandRightDACsandADCsrespectivelyandthecontrol
wordsbeingsenttoand thestatuswordsbeingreceived from thedevice
respectively.Figure<DSP_Protocol> detailsthearrangementofboth
audioandcontrol/statusinformationintheserialtransfer.
LRCLK/SDIFS
TFS
DSDATA/SDI
DT
ADSP-
21065L
(MASTER)
I2S (Inter ICSound Bus) Mode
BCLK/SCLK
TCLK
ASDATA/SDO
TheI2Sbusisathreelineserialbuswhich featuresaserialdataline
carryingbothleftandright(stereo)channels.TheLeftandRightchannel
informationareselectedbythestatusoftheLeft/RightClock(Word
Select)line.Serialdataisclocked bytheBitClockline. Figures
<Data_I2S_DSP_Master> and<Data_I2S_DSP_Slave>detailthe
interfaceconfigurationbetweencontrollerandcodecinI2Smodewith
controllerasmasterandslaverespectively.Figure<> detailsI2Stiming.
Theinterfaceallowseasytransferofarbitrarylengthserialdatasamples
sentMSBfirst.TogglingoftheLeft/RightClocklineindicatesthatthe
end ofthecurrentword willoccurafterthefollowingBitClockcycleand
thestartof thealternatechannelword willoccuron thesubsequentBit
Clockcycle
DR
RFS
AD743xx
(SLAVE)
RCLK
Figure <Data_I2S_DSP_Slave>
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
2
I S MODE - 16 TO 24-BITS PER CHANNEL
Figure <I2S_Tim ing>
–12–
Pr D 03/00
PRELIMINARY TECHNICAL DATA
AD74322
AD743xx
AD743xx
CDIN CLATCH CCLK
CDOUT
CDIN CLATCH CCLK
CDOUT
CONTROL DATA IN
CONTROL DATA OUT
CONTROL DATA LATCH
CONTROL DATA CLOCK
Figure <Control_Cascade_Daisy_Chain>
CCLK
CDIN
MSB 14
DEV N
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
LSB
DEV N
DEV 1
DEV 1
CDOUT
MSB 14
DEV N
8
8
LSB
DEV N
DEV 1
DEV 1
CLATCH
Figure <Control_Cascade_Tim ing_Daisy_Chain>
INT E R F AC ING M U LT IP LE D E VIC E S
Manyapplicationsrequiremultiplechannelsofinputandoutput.The
AD743xxseriesofdevicesaredesignedtocaterforextendingthenumber
ofI/O channelsbycascadingdevicestogetherwhileinterfacingtoasingle
controlordataport.Thisreducestheoverhead requirementon the
controllerin termsofserialports.
ControlPortCascading
T here are two methods of cascading the Control Ports of
multiple AD743xx devices together so that all devices can
be controlled from a single controller serial port. One
method is to configure the multiple devices as a daisy
chain of Control Ports each 16-bits wide with common
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–13–
PRELIMINARY TECHNICAL DATA
AD74322
AD743xx
AD743xx
CDIN CLATCH CCLK
CDOUT
CDIN CLATCH CCLK
CDOUT
CONTROL DATA IN
CONTROL DATA OUT
CONTROL DATA CLOCK
CONTROL DATA LATCH 1
CONTROL DATA LATCH N
Figure <Control_Cascade_TDM>
CCLK
CDIN
MSB 14
DEV N
5
5
4
4
3
3
2
2
1
1
0
MSB
14
14
13
3
3
2
1
1
LSB
DEV N DEV 1
DEV 1
CDOUT
MSB 14
DEV N
0
MSB
13
2
LSB
DEV N DEV 1
DEV 1
CLATCH N
CLATCH 1
Figure <Control_Cascade_Tim ing_TDM>
–14–
Pr D 03/00
PRELIMINARY TECHNICAL DATA
AD74322
AD743xx
(SLAVE)
AD743xx
(SLAVE)
LRCLK/ DSDATA/ BCLK/ ASDATA/
SDIFS SDI SCLK SDO
LRCLK/ DSDATA/ BCLK/ ASDATA/
SDIFS SDI SCLK SDO
SDOFS
SDOFS
TFS
DT
DSP
(MASTER)
SCLK
DR
RFS
Clock and Latch signals. T he other method involves
DACs (with I2S interfaces) to be interfaced to a cascade
of AD743xx devices. T his allows extra flexibility in
choosing the number of input and out channels in the
cascade. T he various (potential) modes for interfacing the
data ports of multiple devices are listed below:
creating a common Data In and Data Out buses where
each device has a common Clock but has separate Latch
signals which enable the devices on the bus at different
times - either as a T ime Division Multiplex (T DM) or
software control.
DSP Mode - Da isy Cha ining
DaisyChain Mode
In this mode, sample data is passed along a daisychain of
I/O registers in a similar manner that used in the present
AD733xx devices. At the sample event each ADC result is
placed in the I/O register and is subsequently shifted
towards the DSP’s Rx register. T his achieved by a
common SDIFS pulse which samples each device (enables
each device’s sample). {Drawback: as the device is stereo,
we would need to send 32 bits (or perhaps more) to the I/
O register at each sample event.}
In DaisyChain Mode,theserialregisters(16-bit)ofeachdeviceare
cascadedtogetherbyconnectingthecontroller’sDataOuttoCDIN of
the first device and the CDOUT of the first device to
CDIN of the next device (see Figure
<C ontrol_C ascade_D aisy_C hain>). T he C D OU T of the
final device is connected to the controller’s Data In. T he
effective cascade length becomes 16 * N (where N is the
number of devices in cascade) and each control word write
to each device requires 16 * N CCLK cycles. Please note
that the CLAT CH pin of each device is driven from a
common controller output signal which must be active
during the entire 16 * N CCLK cycles as shown in Figure
< C ontrol_C ascade_T im ing_D aisy_C hain> .
TDMMode
Inmultiplexedmode,eachdeviceisprogrammedwithitscascade
position.Thisallowsdevicestobeenabled tothedatabusesonlyin their
appropriate time-slot as defined by the initial frame-sync
signal.
TDMMode
InTDM Mode,eachdevice’sCDIN andCDOUT arecommonedtothe
controller’sDataOutandDataInrespectively(seeFigure
<Control_Cascade_TDM>).Eachdevice’sCLATCH pinisseparately
controlled.WhenCLATCH isdisassertedactivityonCDIN andCCLK
isnotrecognisedandtheCDOUT pinistri-stated.Figure
<Control_Cascade_Timing_TDM>showsTDMModeControltiming.
D a ta P or t C a sca d in g
T he Data Port of the AD74322 is designed to allow
multiple single or dual channel devices to be cascaded
from a single DSP or controller serial port (SPORT ).
T here is also a mode which allows stereo ADCs and
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–15–
PRELIMINARY TECHNICAL DATA
AD74322
REGISTER ADDRESS R/W RES
DATA FIELD
15
14
13
12
11
10
9
9
8
7
6
5
4
3
2
1
0
Note: Bit 15 = MSB
Figure <ContPortMap>
REGISTER ADDRESS R/W RES
DATA FIELD
15
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
14
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
13
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
12
0
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
11
10
8
7
6
5
4
3
2
1
0
Power Settings
Clock Dividers
Serial Port Control
Mute Control
Input/Output Configuration
ADC0 Gain Setting
ADC0 Peak Level
ADC1 Gain Setting
ADC1 Peak Level
Reserved
0
1
0
1
Reserved
I/O Filter Select
DAC0 Gain Setting
DAC1 Gain Setting
Reserved
Reserved
REF Trim Control
Test Mode Control
Figure <ContRegMap>
–16–
Pr D 03/00
PRELIMINARY TECHNICAL DATA
AD74322
Power Control
REG
R/W RES
ADDRESS
RESET PURA
PUR
PUD1
PUD0
PUA3
PUA2
PUA1
PUA0
PU
15 - 12
11 10
9
8
7
6
5
4
3
2
1
0
Power
Up
Software Referen-
Power
Up
Referen-
ce
Power
Up
DAC1
Power
Up
DAC0
Power
Up
ADC3
Power
Up
ADC2
Power
Up
ADC1
Power
Up
ADC0
Global
Power
Up
0000
Reset
ce
Amplifi-
er
T a ble <M C LK_D ivider >
Clock Dividers
REG
ADDRESS
R/W RES
Reserved
BCD2-0
MCD2-0
15 - 12
0000
11 10
9
8
7
6
5
4
3
2
1
0
Bit Clock Divider
Master Clock Divider
Serial Interface Control
REG
ADDRESS
R/W RES
DSTD-
ME
TPOS2 TPOS1 TPOS0 DDF1 DDF0
ADF1 ADF0 DSMM DSMS
15 - 12
0000
11 10
9
8
7
6
5
4
3
2
1
0
TDM
Mode
Position
2
TDM
Mode
Position
1
TDM
Mode
Position
0
TDM
Mode
Enable
DAC
Data
DAC
Data
ADC
Data
ADC
Data
Mixed--
Mode
Enable
Master/
Slave
Mode
Format 2 Format 2 Format 2 Format 1
Mute Control
REG
ADDRESS
R/W RES
DMU- DMU-
AMU- AMU-
DWW1 DWW0 AWW1 AWW0
-
-
TE1
TE0
TE1
TE0
15 - 12
0000
11 10
9
8
7
6
5
4
3
2
1
0
DAC
Word
Width 1
DAC
Word
Width 0
ADC
Word
Width 1
ADC
Word
Width 0
Mute
DAC 1
Mute
DAC 0
Mute
ADC 1
Mute
ADC 0
Reserved Reserved
Pr D 03/00
–17–
PRELIMINARY TECHNICAL DATA
AD74322
ADC Configuration
REG
ADDRESS
R/W RES
PEA-
KE
RES
DLB
DSLB
ALB1
ALB0
INV1
INV0
SEE1
SEE0
15 - 12
0111
11 10
9
8
7
6
5
4
3
2
1
0
ADC
Peak
Level
ADC1 in ADC0 in
Data
SPORT
Loopback
Analog
Loopback Loopback
Ch1 Ch0
Analog
Invert
ADC1
Inputs
Invert
ADC0
Inputs
Digital
Loopback
Single
Ended
Mode
Single
Ended
Mode
Reserved
Reading
ADC0 Gain Setting/Peak Readback
A0G9-0
REG
ADDRESS
R/W RES
15 - 12
0001
11 10
9
8
7
6
5
4
3
2
1
0
Reserved
A0G1
A0G0
0
1
A0P9
ADC0 Peak Readback
A0P0
ADC1 Gain Setting/Peak Readback
A1G9-0
REG
ADDRESS
R/W RES
15 - 12
0001
11 10
9
8
7
6
5
4
3
2
1
0
Reserved
A1G1
A1G0
0
1
A1P9
ADC1 Peak Readback
A0P0
DAC0 Gain Setting
D0G9-0
REG
ADDRESS
R/W RES
15 - 12
0101
11 10
9
8
7
6
5
4
3
2
1
0
D0G9
DAC0 Gain Setting
D0G0
–18–
Pr D 03/00
PRELIMINARY TECHNICAL DATA
AD74322
DAC1 Gain Setting
D1G9-0
REG
R/W RES
ADDRESS
15 - 12
0110
11 10
9
8
7
6
5
4
3
2
1
0
D1G9
DAC1 Gain Setting
D1G0
Trim Control
REG
ADDRESS
R/W RES
BMF
LTE
LT3-0
ST3-0
15 - 12
0000
11 10
9
8
7
6
5
4
3
2
1
0
Blow
Master
Fuse
Link
Trim
Enable
Link Trim
Software Trim
Test Mode Control
REG
ADDRESS
R/W RES
TME1-0
DI3-0
AI3-0
15 - 12
0000
11 10
9
8
7
6
5
4
3
2
1
0
Test Mode Control
DAC Current Settings
ADC Current Settings
Pr D 03/00
–19–
AD74322
PRELIMINARY TECHNICAL DATA
O UTLINE D IME NSIO NS (STYLE : outline hd)
D imensions shown in inches and (mm). (ST YLE: outline sub)
Pr D 03/00
–20–
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