AD7443BRM_技术文档

PRELIMINARY TECHNICAL DATA

Pseudo Differential, 600kSPS,

a

PreliminaryTechnicalData

12- & 10-Bit ADCs in 8-lead SOT-23

AD7453/AD7443

FEATU RES

F U NC T IO NAL B LO C K D IAG RAM

Specified for V_DDof 2.7 V to 5.25 V

Lo w Po w e r a t m a x Th ro u g h p u t Ra t e :

3.75 m W typ at 1MSPS w ith V_DD= 3 V

9 m W typ at 1MSPS w ith V_DD= 5 V

Ps e u d o Diffe re n t ia l An a lo g In p u t

Wide Input Bandw idth:

V

DD

V

12-BIT SUCCESSIVE

APPROXIMATION

ADC

IN+

70d B S INAD a t 100kHz In p u t Fre q u e n cy

Flexible Pow er/ Serial Clock Speed Managem ent

No Pipeline Delays

T/H

IN-

V

REF

Hig h S p e e d S e ria l In t e rfa ce - S PI^TM/ QS PI^TM

/

MICROWIRE^TM

/ DS P Co m p a t ib le

Po w e r-Do w n Mo d e : 1µA m a x

8 Pin S OT-23 a n d µS OIC Pa cka g e s

SCLK

SDATA

CS

CONTROL

LOGIC

AP P LICATIO N S

AD7453/

AD7443

Tra n s d u c e r In t e rfa c e

Battery Pow ered System s

Data Acquisition System s

Portable Instrum entation

Motor Control

Co m m u n ic a t io n s

GND

G E NE R AL D E S C R IP T IO N

T he AD7453/43 use advanced design techniques to achieve

very low power dissipation at high throughput rates.

T he AD7453/AD7443 are respectively 12- and 10-bit, low

power, successive-approximation (SAR) analog-to-digital

converters that feature a pseudo differential analog input.

T hese parts operate from a single 2.7 V to 5.25 V power

supply and feature throughput rates up to 600kSPS.

P R O D U C T H IG H LIG H T S

1.Operation with 2.7 V to 5.25 V power supplies.

2.Low Power Consumption.

With a 3V supply, the AD7453/43 offer 3.75mW typ

power consumption for 600kSPS throughput.

3.Pseudo Differential Analog Input.

T he V_IN-input can be used as an offset from ground

4.Flexible Power/Serial C lock Speed M anagement.

T he conversion rate is determined by the serial clock,

allowing the power to be reduced as the conversion time

is reduced through the serial clock speed increase. T hese

parts also feature a shutdown mode to maximize power

efficiency at lower throughput rates.

T he parts contains a low-noise, wide bandwidth, differen-

tial track and hold amplifier (T /H) which can handle

input frequencies in excess of 1MHz with the -3dB point

being 20MHz typically. T he reference voltage is 2.5 V

and is applied externally to the V_REFpin.

T he conversion process and data acquisition are controlled

using CS and the serial clock allowing the device to inter-

face with Microprocessors or DSPs. T he input signals are

sampled on the falling edge of CS and the conversion is

also initiated at this point.

5.N o Pipeline D elay.

6.Accurate control of the sampling instant via a CS input

and once off conversion control.

T he SAR architecture of these parts ensures that there are

no pipeline delays.

MICROWIRE is a trademark of National Semiconductor Corporation.

SPI and QSPI are trademarks of Motorola, Inc.

REV. PrA 24/05/02

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

Fax: 781/ 326-8703

w w w .analog.com

PRELIMINARY TECHNICAL DATA

( V = 2.7V to 5.25V, f_SCLK= 12MHz, f_S= 600kSPS, V_REF= 2.5 V; F = 100kHz;

1

DD

IN

AD7453 - SPECIFICATIONS

T = T_MINto T , unless otherwise noted.)

A

MAX

P ar am eter

Test Conditions/Com m ents

B Version¹

U n it

D YN AM IC PERF O RM AN C E

Signal to (Noise + Distortion)

(SIN AD )²

70

-75

dB min

dB max

T otal H armonic D istortion (T H D )²-80dB typ

Peak H armonic or Spurious Noise²

Intermodulation D istortion (IM D )²

Second Order T erms

-82dB typ

-85

10

50

20

dB typ

ns typ

ps typ

M H z typ

T hird Order T erms

Aperture D elay²

Aperture Jitter²

Full Power Bandwidth²

@ -3 dB

@ -0.1 dB

2.5

D C AC C U RAC Y

Resolution

12

± 1

Bits

LSB max

Integral N onlinearity (IN L)²

D ifferential N onlinearity (D N L)²

Guaranteed No Missed Codes

to 12 Bits.

± 1

± 3

LSB max

Offset Error²

G ain Error²

AN ALO G IN PU T

Full Scale Input Span

Absolute Input Voltage

V_{IN +}

V_IN+- V_IN-

V_REF

V

V_REF

0.1 to 1

± 1

20

6

V

3

V_{IN -}

D C Leakage Current

Input Capacitance

µA max

pF typ

When in T rack

When in Hold

REF EREN C E IN PU T

V_REFInput Voltage

±1% tolerance for

specified performance

2.5

± 1

15

V

D C Leakage Current

V_REFInput Capacitance

µA max

pF typ

LO G IC IN PU T S

Input H igh Voltage, V_{IN H}

Input Low Voltage, V_{IN L}

Input Current, I_IN

2.4

0.8

± 1

10

V min

V max

µA max

pF max

T ypically 10nA, V_IN= 0VorV_{D D}

4

Input Capacitance, C_IN

LO G IC O U T P U T S

Output H igh Voltage, V_OH

V_DD= 5V; I_SOURCE= 200µA

V_DD= 3V; I_SOURCE= 200µA

I_{SIN K}= 200µA

2.8

2.4

0.4

± 1

V min

V max

µA max

pF max

Output Low Voltage, V_OL

Floating-State Leakage C urrent

Floating-State Output Capacitance⁴

Output Coding

10

Straight

(N atural)

Binary

–2 –

REV. PrA

PRELIMINARY TECHNICAL DATA

1

AD7453/AD7443

AD7453 - SPECIFICATIONS

P a r a m eter

Test Conditions/Com m ents

B Ver sion¹

Units

C O N VERSIO N RAT E

Conversion T ime

1.3µs with a 12MHz SCLK

Sine Wave Input

T BD

16

SC LK cycles

ns max

T rack/H old Acquisition T ime²

Step Input

200

T BD

600

T hroughput Rate⁶

kSPS max

P O WER REQ U IREM EN T S

V_{D D}

I _{D D}

2.7/5.25

Vm in /m ax

5 , 7

N ormal M ode(Static)

N ormal M ode (Operational)

SCLK On or Off

V_DD= 5 V.

V_DD= 3 V.

0.5

1.8

1.25

1

mA typ

mA max

µA max

Full Power-D own M ode

Power D issipation

SCLK On or Off

N ormal M ode (Operational)

V_DD=5 V.

V_DD=3 V.

V_DD=5 V. SCLK On or Off

V_DD=3 V. SCLK On or Off

9

mW max

µW max

3.75

5

3

Full Power-D own

N O T E S

¹T emperature ranges as follows:

B

Versions: –40°C to + 85°C .

pseudo ground for V_IN+

²See ‘T erm inology’ section.

3

A small D C input is applied to V_IN-to provide

a

⁴Sample tested

@ + 25°C to ensure compliance.

⁵See P O WE R VE RSU S T H RO U G H P U T RAT E section .

⁶See ‘Serial Interface Section’.

⁷M easured with

a midscale D C input.

Specifications subject to change without notice.

–3 –

REV. PrA

PRELIMINARY TECHNICAL DATA

( V = 2.7V to 5.25V, f_SCLK= 12MHz, f_S= 600kSPS, V = 2.5 V; F = 100kHz;

DD

REF

IN

1

T = T_MINto T , unless otherwise noted.)

AD7443-SPECIFICATIONS

A

MAX

P ar am eter

Test Conditions/Com m ents

B Version¹

U n it

D YN AM IC PERF O RM AN C E

Signal to (Noise + Distortion)

(SIN AD )²

61

-73

dB min

dB max

T otal H armonic D istortion (T H D )²-80dB typ

Peak H armonic or Spurious Noise²

Intermodulation D istortion (IM D )²

Second Order T erms

-82dB typ

-78

10

50

20

dB typ

ns typ

ps typ

M H z typ

T hird Order T erms

Aperture D elay²

Aperture Jitter²

Full Power Bandwidth²

@ -3 dB

@ -0.1 dB

2.5

D C AC C U RAC Y

Resolution

10

± 0.5

Bits

LSB max

Integral N onlinearity (IN L)²

D ifferential N onlinearity (D N L)²

Guaranteed No Missed Codes

to 10 Bits.

± 0.5

± 3

LSB max

Offset Error²

G ain Error²

AN ALO G IN PU T

Full Scale Input Span

Absolute Input Voltage

V_{IN +}

V_IN+- V_IN-

V_REF

V

V_REF

0.1 to 1

± 1

20

6

V

3

V_{IN -}

D C Leakage Current

Input Capacitance

µA max

pF typ

When in T rack

When in Hold

REF EREN C E IN PU T

V_REFInput Voltage

± 1% tolerance

for specified performance

2.5

± 1

15

V

D C Leakage Current

V_REFInput Capacitance

µA max

pF typ

LO G IC IN PU T S

Input H igh Voltage, V_{IN H}

Input Low Voltage, V_{IN L}

Input Current, I_IN

2.4

0.8

± 1

10

V min

V max

µA max

pF max

T ypically 10nA, V_IN= 0VorV_{D D}

4

Input Capacitance, C_IN

LO G IC O U T P U T S

Output H igh Voltage, V_OH

V_DD= 5V; I_SOURCE= 200µA

V_DD= 3V; I_SOURCE= 200µA

I_{SIN K}= 200µA

2.8

2.4

0.4

± 1

V min

V max

µA max

pF max

Output Low Voltage, V_OL

Floating-State Leakage C urrent

Floating-State Output Capacitance⁴

Output Coding

10

Straight

(N atural)

Binary

–4 –

REV. PrA

PRELIMINARY TECHNICAL DATA

1

AD7453/AD7443

AD7443-SPECIFICATIONS

P a r a m eter

Test Conditions/Com m ents

B Ver sion¹

Units

C O N VERSIO N RAT E

Conversion T ime

1.3µs with a 12MHz SCLK

Sine Wave Input

Step Input

16

SC LK cycles

ns max

T rack/H old Acquisition T ime²

200

T BD

600

T hroughput Rate⁶

kSPS max

P O WER REQ U IREM EN T S

V_{D D}

I _{D D}

2.7/5.25

Vm in /m ax

6 , 7

N ormal M ode(Static)

N ormal M ode (Operational)

SCLK On or Off

V_DD= 5 V.

V_DD= 3 V.

0.5

1.8

1.25

1

mA typ

mA max

µA max

Full Power-D own M ode

Power D issipation

SCLK On or Off

N ormal M ode (Operational)

V_DD=5 V.

V_DD=3 V.

V_DD=5 V. SCLK On or Off

V_DD=3 V. SCLK On or Off

9

mW max

µW max

3.75

5

3

Full Power-D own

N O T E S

¹T emperature ranges as follows:

B

Versions: –40°C to + 85°C .

pseudo ground for V_IN+

²See ‘T erm inology’ section.

3

A small D C input is applied to V_IN-to provide

a

⁴Sample tested

@ + 25°C to ensure compliance.

⁵See P O WE R VE RSU S T H RO U G H P U T RAT E section .

⁶See ‘Serial Interface Section’.

⁷M easured with

a midscale D C input.

Specifications subject to change without notice.

–5 –

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7453/AD7443

TIMINGSPECIFICATIONS^1,2

( V = 2.7V to 5.25V, f_SCLK= 12MHz, f_S= 600kSPS, V_REF= 2.5 V; F = 100kHz;

DD

IN

T = T_MINto T , unless otherwise noted.)

A

MAX

Lim it at

P a r a m eter T _MIN, T _MAXUnits

D escr iption

4

f_{SC LK}

10

kHz min

12

MHz max

t_{C O N VE RT}

t_{Q U IET}

16 x t_SCLK

1.3

25

t_SCLK= 1/f_SCLK

µs max

ns min

Minimum Quiet T ime between the End of a Serial Read and the

Next Falling Edge of CS

t₁

10

20

40

0.4 t_SCLK

10

35

1

ns min

ns max

ns min

ns max

µs max

M inimum CS Pulsewidth

t₂₅

t₃₅

t₄

t₅

t₆

CS falling Edge to SCLK Falling Edge Setup T ime

Delay from CS Falling Edge Until SDAT A 3-State Disabled

Data Access T ime After SCLK Falling Edge

SCLK H igh Pulse Width

SCLK Low Pulse Width

t₇

t₈

SCLK Edge to Data Valid Hold T ime

SCLK Falling Edge to SDAT A 3-State Enabled

Power-Up T ime from Full Power-D own

6

7

t_{P O WE R-U P}

N O T E S

¹Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 Volts.

²See Figure 1, Figure

2 and the ‘Serial Interface’ section.

³C om m on M od e Voltage.

⁴M ark/Space ratio for the SC LK input is 40/60 to 60/40.

⁵Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V_DD

= 5 V and time for

an output to cross 0.4 V or 2.0 V for V_DD

= 3 V.

⁶t₈is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. T he measured num-

ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t₈, quoted in the

timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

7

See ‘Power-up T im e’ Section.

Specifications subject to change without notice.

t

1

CS

t

CONVERT

t

2

B

5

SCLK

1

2

3

4

5

13

14

15

16

t

6

7

t

8

t

QUIET

t

4

3

0

DB11

DB10

DB1

DB0

0

DB2

SDATA

3-STATE

4 LEADING ZERO’S

Figure 1. AD7453 Serial Interface Tim ing Diagram

t

1

CS

t

CONVERT

t

2

B

5

SCLK

1

2

3

4

5

13

14

15

16

t

6

7

t

8

t

QUIET

4

t

3

0

DB9

DB8

DB0

0

SDATA

3-STATE

4 LEADING ZERO’S

2 TRAILING ZEROS

Figure 2. AD7443 Serial Interface Tim ing Diagram

–6 –

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7453/AD7443

AB SO LU T E M AXIM U M RAT ING S¹

(T _A= +25°C unless otherwise noted)

I

OL

200µA

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V

V_IN+to GND . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

V_IN-to GND . . . . . . . . . . . . . . .

–0.3 V to V_DD+ 0.3 V

Digital Input Voltage to GND . . . . . . . . -0.3 V to +7 V

Digital Output Voltage to GND . -0.3 V to V_DD+ 0.3 V

V_REFto GND . . . . . . . . . . . . . . . . . -0.3 V to V_DD+0.3 V

Input Current to Any Pin Except Supplies². . . . ± 10m A

Operating T emperature Range

TO

OUTP UT

+1.6V

C

L

50 pF

Commercial (A, B Version) . . . . . . . . . -40^oC to +85^oC

Storage T emperature Range . . . . . . . . . -65^oC to +150^oC

Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . + 150^oC

200µA

I

OH

␪

T hermal Impedance . . . . . . . . . . 205.9°C /W (µSOIC )

211.5°C/W (SOT -23)

JA

␪

T hermal Impedance . . . . . . . . . 43.74°C /W (µSOIC )

91.99°C/W (SOT -23)

JC

Figure 3. Load Circuit for Digital Output Tim ing

Specifications

Lead T emperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . + 215^oC

Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . + 220^oC

E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV

N O T E S

¹Stressesabove those listed under “Absolute Maximum Ratings” maycause permanent

damage to the device. Thisisa stressratingonlyand functionaloperation ofthe device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods mayaffect device reliability.

²T ransient currents of up to 100 mA will not cause SC R latch up.

O R D E R ING G U ID E

Linearity

P ackage

Model

Ran ge

Error (LSB)¹O p tion ⁴

Br anding Infor m ation

AD 7453BRT

AD 7453BRM

AD 7443BRT

AD 7443BRM

T BD

-40°C to +85°C

Evaluation Board

C ontroller Board

± 1 LSB

± 0.5 LSB

RT -8

RM -8

RT -8

RM -8

T BD

EVAL-C O N T RO L BRD 2³

NOTES

¹Linearity error here refers to Integral N on-linearity Error.

²T his can be used as a stand-alone evaluation board or in conjunction with the EVALUAT ION BOARD CONT ROLLER for evaluation/demonstration purposes.

³EVALU AT ION BOARD C ON T ROLLER. T his board is

evaluation boards ending in the C B designators. T o order

a

complete unit allowing

complete Evaluation Kit, you will need to order the AD C evaluation board i.e.

a PC to control and communicate with all Analog D evices

a

T BD , the EVAL-C ON T ROL BRD 2 and

a 12V AC transformer. See the T BD technote for more information.

⁴RT

=

SOT -23; RM µSOIC

=

C A U T I O N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the AD 7453/AD 7443 features proprietary ESD protection circuitry,

p erm an en t d am age m ay occu r on d evices su b ject ed t o h igh -en ergy elect rost at ic

discharges. T herefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–7 –

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7453/AD7443

P IN F U NC T IO N D E SC R IP T IO N

P in Mnem onic

Function

V_REF

Reference Input for the AD7453/43. An external 2.5 V reference must be applied to this input.T his pin

should be decoupled to GND with a capacitor of at least 0.1µF.

V_{IN +}

V_{IN -}

N on-Inverting Input.

Inverting Input. T his pin sets the ground reference point for the V_IN+input. Connect to Ground or to

a small DC offset to provide a pseudo ground.

G N D

C S

Analog Ground. Ground reference point for all circuitry on the AD7453/43. All analog input

signals and any external reference signal should be referred to this GND voltage.

Chip Select. Active low logic input. T his input provides the dual function of initiating a conversion on

the AD7453/43 and framing the serial data transfer.

SD AT A

Serial Data. Logic Output. T he conversion result from the AD7453/43 is provided on this out

put as a serial data stream. T he bits are clocked out on the falling edge of the SCLK input. T he data

stream of the AD7453 consists of four leading zeros followed by the 12 bits of conversion data which

are provided MSB first; the data stream of the AD7443 consists of four leading zeros, followed by the

10-bits of conversion data, followed by two trailing zeros. In both cases, the output coding is Straight

(N atural) Binary.

SC L K

V_{D D}

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. T his clock

input is also used as the clock source for the conversion process.

Power Supply Input. V_DDis 2.7 V to 5.25 V. T his supply should be decoupled to GND with a 0.1µF

Capacitor and a 10µF T antalum Capacitor.

P IN C O NFIGURATIO N 8-LE AD SO T-23

V

1

2

3

4

V

8

7

6

5

REF

DD

AD7453/AD7443

SOT-23

SCLK

SDATA

CS

IN+

V

TOP VIEW

(Not to Scale)

IN-

GND

P IN C O NF IG URAT IO N µSO IC

V

REF

1

2

3

4

8

7

6

5

DD

AD7453/AD7443

µSOIC

V

IN +

SCLK

SDATA

CS

V

TOP VIEW

(Not to Scale)

IN-

GND

–8 –

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7453/AD7443

T E R M I N O L O G Y

tortion products to the rms amplitude of the sum of the

fundamentals expressed in dBs.

Signal to (Noise + D istor tion) Ratio

T his is the measured ratio of signal to (noise + distortion)

at the output of the ADC. T he signal is the rms amplitude

of the fundamental. Noise is the sum of all

nonfundamental signals up to half the sampling frequency

(f_S/2), excluding dc. T he ratio is dependent on the number

of quantization levels in the digitization process; the more

levels, the smaller the quantization noise. T he theoretical

signal to (noise + distortion) ratio for an ideal N-bit con-

verter with a sine wave input is given by:

Ap er tu r e D ela y

T his is the amount of time from the leading edge of the

sampling clock until the ADC actually takes the sample.

Ap er tu r e Jitter

T his is the sample to sample variation in the effective

point in time at which the actual sample is taken.

F u ll P ower Ban dwidth

T he full power bandwidth of an ADC is that input fre-

quency at which the amplitude of the reconstructed

fundamental is reduced by 0.1dB or 3dB for a full scale

input.

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

T hus for a 12-bit converter, this is 74 dB and for a 10-bit

converter this is 62dB.

In tegr a l Non lin ea r ity (INL)

T ota l H a r m on ic D istor tion

T otal harmonic distortion (T HD) is the ratio of the rms

sum of harmonics to the fundamental. For the AD7450, it

is defined as:

T his is the maximum deviation from a straight line pass-

ing through the endpoints of the ADC transfer function.

D iffer en tia l Non lin ea r ity (D NL)

T his is the difference between the measured and the ideal 1

LSB change between any two adjacent codes in the ADC.

2

V₂

V

+

6

+

3

4

5

THD (d B ) 20 lo g

=

V₁

O ffset E r r or

T his is the deviation of the first code transition (000...000 to

000...001) from the ideal (i.e. AGND + 1LSB)

where V₁is the rms amplitude of the fundamental and V₂,

V₃, V₄, V₅and V₆are the rms amplitudes of the second to

the sixth harmonics.

G a in E r r or

T his is the deviation of the last code transition (111...110 to

111...111) from the ideal (i.e., V_REF- 1LSB), after the Offset

Error has been adjusted out.

P eak H ar m onic or Spur ious Noise

Peak harmonic or spurious noise is defined as the ratio of

the rms value of the next largest component in the ADC

output spectrum (up to f_S/2 and excluding dc) to the rms

value of the fundamental. Normally, the value of this

specification is determined by the largest harmonic in the

spectrum, but for ADCs where the harmonics are buried

in the noise floor, it will be a noise peak.

T r a ck/H old Acqu isition T im e

T he track/hold amplifier returns into track mode on the

13th SCLK rising edge (see the “Serial Interface Sec-

tion”). T he track/hold acquisition time is the minimum

time required for the track and hold amplifier to remain in

track mode for its output to reach and settle to within 0.5

LSB of the applied input signal.

In t er m od u la t ion D ist or t ion

With inputs consisting of sine waves at two frequencies, fa

and fb, any active device with nonlinearities will create

distortion products at sum and difference frequencies of

mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation

distortion terms are those for which neither m nor n are

equal to zero. For example, the second order terms in-

clude (fa + fb) and (fa – fb), while the third order terms

include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

P ower Supply Rejection Ratio (P SRR)

T he power supply rejection ratio is defined as the ratio of

the power in the ADC output at full-scale frequency, f, to

the power of a 200mV p-p sine wave applied to the ADC

V_DDsupply of frequency fs. T he frequency of this input

varies from 1kHz to 1MHz.

PSRR (dB) = 10 log (Pf/Pfs)

Pf is the power at frequency f in the ADC output; Pfs is

the power at frequency fs in the ADC output.

T he AD7453/43 is tested using the CCIF standard where

two input frequencies near the top end of the input band-

width are used. In this case, the second order terms are

usually distanced in frequency from the original sine waves

while the third order terms are usually at a frequency close

to the input frequencies. As a result, the second and third

order terms are specified separately. T he calculation of the

intermodulation distortion is as per the T H D specification

where it is the ratio of the rms sum of the individual dis-

–9 –

REV. PrA

PRELIMINARY TECHNICAL DATA

AD7453/AD7443

SE R IAL INT E R F AC E

Figures 1 and 2 show detailed timing diagrams for the

serial interface of the AD7453 and the AD7443 respec-

tively. T he serial clock provides the conversion clock and

also controls the transfer of data from the device during

conversion. CS initiates the conversion process and frames

the data transfer. T he falling edge of CS puts the track

and hold into hold mode and takes the bus out of three-

state. T he analog input is sampled and the conversion

initiated at this point. T he conversion will require 16

SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track and

hold will go back into track on the next SCLK rising edge

as shown at point B in Figures 1 and 2. On the 16th

SCLK falling edge the SDAT A line will go back into

three-state.

If the rising edge of CS occurs before 16 SCLKs have

elapsed, the conversion will be terminated and the SDAT A

line will go back into three-state on the 16th SCLK falling

edge.

T he conversion result from the AD7453/43 is provided on

the SDAT A output as a serial data streatm. T he bits are

clocked out on the falling edge of the SCLK input. T he data

streatm of the AD 7453 consists of four leading zeros,

followed by 12 bits of conversion data which is provided MSB

first; the data stream of the AD7443 consists of four leading

zeros, followed by the 10 bits of conversion data, followed by

two trailing zeros, which is also provided MSB first. In both

cases, the output coding is straight (natural) binary.

16 serial clock cycles are required to perform a conversion

and to access data from the AD 7453/43. CS going low

provides the first leading zero to be read in by the micro-

controller or DSP. T he remaining data is then clocked out

on the subsequent SCLK falling edges beginning with the

second leading zero. T hus the first falling clock edge on the

serial clock provides the second leading zero. T he final bit

in the data transfer is valid on the 16th falling edge, having

been clocked out on the previous (15th) falling edge.

In applications with a slower SCLK, it may be possible to

read in data on each SCLK rising edge i.e. the first rising

edge of SCLK after the CS falling edge would have the

leading zero provided and the 15th SCLK edge would have

D B0 provided.

–1 0 –

REV. PrA


型号：	AD7443BRM
厂家：	ADI
描述：	IC 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MICRO, SOIC-8, Analog to Digital Converter 光电二极管转换器
文件：	总10页 (文件大小：404K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7443BRM [ADI]

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