AD744KN [ADI]
Precision, 500 ns Settling BiFET Op Amp; 精密， 500 ns建立BiFET运算放大器
| 型号： | AD744KN |
| 厂家： | 
ADI |
| 描述： | Precision, 500 ns Settling BiFET Op Amp |
| 文件： | 总12页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision, 500 ns Settling
BiFET Op Amp
a
AD744
FEATURES
AC PERFORMANCE
CONNECTION DIAGRAMS
TO-99 (H) Package
500 ns Settling to 0.01% for 10 V Step
1.5 s Settling to 0.0025% for 10 V Step
75 V/s Slew Rate
0.0003% Total Harmonic Distortion (THD)
13 MHz Gain Bandwidth – Internal Compensation
>200 MHz Gain Bandwidth (G = 1000)
External Decompensation
>1000 pF Capacitive Load Drive Capability with
10 V/s Slew Rate – External Compensation
DC PERFORMANCE
0.5 mV max Offset Voltage (AD744B)
10 V/؇C max Drift (AD744B)
8-Lead Plastic Mini-DIP (N)
8-Lead SOIC (R) Package and
8-Lead Cerdip (Q) Packages
250 V/mV min Open-Loop Gain (AD744B)
Available in Plastic Mini-DIP, Plastic SOIC, Hermetic
Cerdip, Hermetic Metal Can Packages and Chip Form
Surface Mount (SOIC) Package Available in Tape and
Reel in Accordance with EIA-481A Standard
APPLICATIONS
Output Buffers for 12-Bit, 14-Bit and 16-Bit DACs,
ADC Buffers, Cable Drivers, Wideband
Preamplifiers and Active Filters
PRODUCT DESCRIPTION
gains. This makes the AD744 ideal for use as ac preamps in
digital signal processing (DSP) front ends.
The AD744 is a fast-settling, precision, FET input, monolithic
operational amplifier. It offers the excellent dc characteristics
of the AD711 BiFET family with enhanced settling, slew rate,
and bandwidth. The AD744 also offers the option of using
custom compensation to achieve exceptional capacitive load
drive capability.
The AD744 is available in five performance grades. The AD744J
and AD744K are rated over the commercial temperature range
of 0°C to +70°C. The AD744A and AD744B are rated over
the industrial temperature range of –40°C to +85°C. The AD744T
is rated over the military temperature range of –55°C to +125°C
and is available processed to MIL-STD-883B, Rev. C.
The single-pole response of the AD744 provides fast settling:
500 ns to 0.01%. This feature, combined with its high dc preci-
sion, makes it suitable for use as a buffer amplifier for 12-bit,
14-bit or 16-bit DACs and ADCs. Furthermore, the AD744’s low
total harmonic distortion (THD) level of 0.0003% and gain band-
width product of 13 MHz make it an ideal amplifier for demanding
audio applications. It is also an excellent choice for use in active
filters in 12-bit, 14-bit and 16-bit data acquisition systems.
The AD744 is available in an 8-lead plastic mini-DIP, 8-lead
small outline, 8-lead cerdip or TO-99 metal can.
PRODUCT HIGHLIGHTS
1. The AD744 is a high-speed BiFET op amp that offers excel-
lent performance at competitive prices. It outperforms the
OPA602/OPA606, LF356 and LF400.
The AD744 is internally compensated for stable operation as a
unity gain inverter or as a noninverting amplifier with a gain of
two or greater. External compensation may be applied to the
AD744 for stable operation as a unity gain follower. External
compensation also allows the AD744 to drive 1000 pF capacitive
loads, slewing at 10 V/µs with full stability.
2. The AD744 offers exceptional dynamic response. It settles to
0.01% in 500 ns and has a 100% tested minimum slew rate
of 50 V/µs (AD744B).
3. The combination of Analog Devices’ advanced processing
technology, laser wafer drift trimming and well-matched
ionimplanted JFETs provide outstanding dc precision. Input
offset voltage, input bias current, and input offset current are
specified in the warmed-up condition; all are 100% tested.
Alternatively, external decompensation may be used to increase
the gain bandwidth of the AD744 to over 200 MHz at high
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ +25؇C and ؎15 V dc, unless otherwise noted)
AD744–SPECIFICATIONS
AD744J/A/S
Typ
AD744K/B/T
Model
Conditions
Min
Max
Min
Typ
Max
Unit
INPUT OFFSET VOLTAGE1
Initial Offset
0.3
1.0
2
20
0.25
0.5
1.0
10
mV
mV
µV/°C
dB
Offset
TMIN to TMAX
vs. Temp.
5
95
5
100
vs. Supply2
82
82
88
88
vs. Supply
TMIN to TMAX
dB
Long-Term Stability
15
30
15
30
µV/month
INPUT BIAS CURRENT3
Either Input
Either Input @ TMAX
J, K
A, B, C
S, T
Either Input
Offset Current
Offset Current @ TMAX
VCM = 0 V
VCM = 0 V
70°C
100
100
pA
=
0.7
1.9
31
40
20
2.3
6.4
102
150
50
0.7
1.9
31
40
10
2.3
6.4
102
150
50
nA
nA
nA
pA
pA
85°C
125°C
VCM = +10 V
VCM = 0 V
VCM = 0 V
70°C
=
J, K
A, B, C
S, T
0.4
1.3
20
1.1
3.2
52
0.2
0.6
10
1.1
3.2
52
nA
nA
nA
85°C
125°C
FREQUENCY RESPONSE
Gain BW, Small Signal
Full Power Response
Slew Rate, Unity Gain
Settling Time to 0.01%4
Total Harmonic
G = –1
8
13
1.2
75
9
13
1.2
75
MHz
MHz
V/µs
µs
V
O = 20 V p-p
G = –1
G = –1
f = 1 kHz
R1 ≥ 2 kΩ
VO = 3 V rms
45
50
0.5
0.75
0.5
0.75
Distortion
0.0003
0.0003
%
INPUT IMPEDANCE
Differential
Common Mode
3 ϫ 1012||5.5
3 ϫ 1012||5.5
3 ϫ 1012||5.5
Ω||pF
Ω||pF
3 ϫ 1012||5.5
INPUT VOLTAGE RANGE
Differential5
Common-Mode Voltage
Over Max Operating Range6
Common-Mode
20
20
V
V
V
+14.5, –11.5
+14.5, –11.5
–11
+13
–11
+13
Rejection Ratio
VCM
TMIN to TMAX
VCM 11 V
=
10 V
78
76
72
70
88
84
84
80
82
80
78
74
88
84
84
80
dB
dB
dB
dB
=
TMIN to TMAX
INPUT VOLTAGE NOISE
0.1 to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
2
2
µV p-p
45
22
18
16
45
22
18
16
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 10 kHz
INPUT CURRENT NOISE
OPEN LOOP GAIN7
f = 1 kHz
0.01
0.01
pA/√Hz
VO
= 10 V
RLOAD ≥ 2 kΩ
TMIN to TMAX
200
100
400
250
100
400
V/mV
V/mV
OUTPUT CHARACTERISTICS
Voltage
RLOAD ≥ 2 kΩ
TMIN to TMAX
Short Circuit
Gain = –1
+13, –12.5
12
+13.9, –13.3
+13.8, –13.1
25
+13, –12.5
12
+13.9, –13.3
+13.8, –13.1
25
V
V
mA
pF
Current
Capacitive Load8
1000
1000
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
15
15
3.5
V
V
mA
4.5
18
5.0
4.5
18
4.0
3.5
NOTES
1Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C.
2PSRR test conditions: +VS = 15 V, –VS = –12 V to –18 V and +VS = +12 V to +18 V, –VS = –15 V.
3Bias Current Specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.
4Gain = –1, RL = 2 k, CL = 10 pF, refer to Figure 25.
5Defined as voltage between inputs, such that neither exceeds 10 V from ground.
6Typically exceeding –14.1 V negative common-mode voltage on either input results in an output phase reversal.
7Open-Loop Gain is specified with VOS both nulled and unnulled.
8Capacitive load drive specified for CCOMP = 20 pF with the device connected as shown in Figure 32. Under these conditions, slew rate = 14 V/µs and 0.01% settling time = 1.5 µs typical.
Refer to Table II for optimum compensation while driving a capacitive load.
Specifications subject to change without notice. All min and max specifications are guaranteed.
–2–
REV.C
AD744
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW
Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (Q, H) . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Operating Temperature Range
AD744J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD744A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD744S/T . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 seconds) . . . . . 300°C
Temperature
Range
Package
Option*
Model
AD744JN
AD744KN
AD744JR
AD744KR
AD744AQ
AD744BQ
AD744AH
AD744JCHIPS
AD744JR-REEL
AD744JR-REEL 7
AD744KR-REEL
AD744KR-REEL 7
AD744TA/883B
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
N-8
N-8
SO-8
SO-8
Q-8
Q-8
H-08A
Die
Tape/Reel 13"
Tape/Reel 7"
Tape/Reel 13"
Tape/Reel 7"
H-08
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Thermal Characteristics
*N = Plastic DIP; SO = Small Outline IC; Q = Cerdip; H = TO-99 Metal Can.
8-Lead Plastic Package:
8-Lead Cerdip Package:
θ
JA = 100°C/Watt, θJC = 33°C/Watt
θ
JA = 110°C/Watt, θJC = 22°C/Watt
8-Lead Metal Can Package: θJA = 150°C/Watt, θJC = 65°C/Watt
8-Lead SOIC Package:
θJA = 160°C/Watt, θJC = 42°C/Watt
3For supply voltages less than 18 V, the absolute maximum input voltage is equal
to the supply voltage.
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
–3–
REV. C
–Typical Characteristics
AD744
Figure 3. Output Voltage Swing vs.
Load Resistance
Figure 1. Input Voltage Swing
vs. Supply Voltage
Figure 2. Output Voltage Swing
vs. Supply Voltage
Figure 5. Input Bias Current vs.
Temperature
Figure 6. Output Impedance vs.
Frequency
Figure 4. Quiescent Current vs.
Supply Voltage
Figure 9. Gain Bandwidth
Product vs. Temperature
Figure 8. Short Circuit Current
Limit vs. Temperature
Figure 7. Input Bias Current vs.
Common-Mode Voltage
–4–
REV. C
AD744
Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency
CCOMP = 0 pF
Figure 12. Open-Loop Gain vs.
Supply Voltage
Figure 11. Open Loop Gain and
Phase Margin vs. Frequency
CCOMP = 25 pF
Figure 13. Common-Mode and
Power Supply Rejection vs.
Frequency
Figure 15. Output Swing and Error
vs. Settling Time
Figure 14. Large Signal Frequency
Response
Figure 17. Input Noise Voltage
Spectral Density
Figure 18. Slew Rate vs. Input
Error Signal
Figure 16. Total Harmonic Distortion
vs. Frequency, Circuit of Figure 20
(G = 10)
–5–
REV. C
AD744–Typical Characteristics
Figure 21. Offset Null Configuration
Figure 20. THD Test Circuit
Figure 19. Settling Time vs. Closed
Loop Voltage Gain
Figure 22b. Unity-Gain Follower
Large Signal Pulse Response,
CCOMP = 5 pF
Figure 22c. Unity-Gain Follower
Small Signal Pulse Response,
CCOMP = 5 pF
Figure 22a. Unity-Gain Follower
Figure 23a. Unity-Gain Inverter
Figure 23b. Unity-Gain Inverter Large
Signal Pulse Response, CCOMP = 5 pF
Figure 23c. Unity-Gain Inverter Small
Signal Pulse Response, CCOMP = 0 pF
–6–
REV. C
AD744
POWER SUPPLY BYPASSING
The error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. A Tektronix oscilloscope preamp type
7A26 was carefully chosen because it recovers from the
approximately 0.4 V overload quickly enough to allow accurate
measurement of the AD744’s 500 ns settling time. Amplifier A2
is a very high-speed FET-input op amp; it provides a voltage
gain of 10, amplifying the error signal output of the AD744
under test.
The power supply connections to the AD744 must maintain a
low impedance to ground over a bandwidth of 10 MHz or more.
This is especially important when driving a significant resistive
or capacitive load, since all current delivered to the load comes
from the power supplies. Multiple high quality bypass capacitors
are recommended for each power supply line in any critical
application. A 0.1 µF ceramic and a 1 µF electrolytic capacitor
as shown in Figure 24 placed as close as possible to the ampli-
fier (with short lead lengths to power supply common) will
assure adequate high frequency bypassing, in most applica-
tions. A minimum bypass capacitance of 0.1 µF should be used
for any application.
+V
S
1F
0.1F
AD744
1F
0.1F
–V
S
Figure 24. Recommended Power Supply Bypassing
Figure 26. Settling Characteristics 0 to +10 V Step
Upper Trace: Output of AD744 Under Test (5 V/div.)
Lower Trace: Amplified Error Voltage (0.01%/div.)
MEASURING AD744 SETTLING TIME
The photos of Figures 26 and 27 show the dynamic response of
the AD744 while operating in the settling time test circuit of
Figure 25. The input of the settling time fixture is driven by a
flat-top pulse generator. The error signal output from the false
summing node of A1, the AD744 under test, is clamped, ampli-
fied by op amp A2 and then clamped again.
TO
TEKTRONIX
+V
+15V
COM
S
7A26
1M⍀
20pF
OSCILLOSCOPE
PREAMP
INPUT SECTION
(VIA LESS THAN 1 FT 50⍀
COAXIAL CABLE)
5pF
–V
–15V
S
V
؋
10 ERROR
206⍀
A2
2X
HP2835
AD3554
2X
HP2835
0.47F
+V
S
–V
0.47F
S
Figure 27. Settling Characteristics 0 to –10 V Step
Upper Trace: Output of AD744 Under Test (5 V/div.)
Lower Trace: Amplified Error Voltage (0.01%/div.)
10k⍀
1.1k⍀
0.2pF – 0.8pF
NULL
4.99k⍀
4.99k⍀
200⍀
10k⍀
FLAT-TOP
5pF – 18pF
PULSE
GENERATOR
V
AD744
10k⍀
IN
A1
5k⍀
1F
10pF
DATA
DYNAMICS
5109
+V
S
OR
–V
EQUIVALENT
S
1F
0.1F
0.1F
NOTE: USE CIRCUIT BOARD WITH GROUND PLANE
Figure 25. Settling Time Test Circuit
–7–
REV. C
AD744
EXTERNAL FREQUENCY COMPENSATION
The following section provides tables to show what CCOMP values
will provide the necessary compensation for given circuit configurations
and capacitive loads. In each case, the recommended CCOMP is a
minimum value. A larger CCOMP can always be used, but slew rate
and bandwidth performance will be degraded.
Even though the AD744 is useable without compensation in
most applications, it may be externally compensated for even
more flexibility. This is accomplished by connecting a capacitor
between Pins 5 and 8. Figure 28, a simplified schematic of the
AD744, shows where this capacitor is connected. This feature is
useful because it allows the AD744 to be used as a unity gain
voltage follower. It also enables the amplifier to drive capacitive
loads up to 2000 pF and greater.
Figure 30 shows the AD744 configured as a unity gain voltage
follower. In this case, a minimum compensation capacitor of
5 pF is necessary for stable operation. Larger compensation ca-
pacitors can be used for driving larger capacitive loads. Table I
outlines recommended minimum values for CCOMP based on
the desired capacitive load. It also gives the slew rate and band-
width that will be achieved for each case.
+V
S
400A
300⍀
2mA
5pF
300⍀
+V
S
–IN
+IN
OUTPUT
NULL/
COMPENSATION
1F
0.1F
NULL/
DECOMPENSATION
AD744
V
OUT
COMPENSATION
V
C
5pF
IN
COMP
1k⍀
1k⍀ 8k⍀
–V
S
1F
0.1F
–V
Figure 28. AD744 Simplified Schematic
S
The slew rate and gain bandwidth product of the AD744 are in-
versely proportional to the value of the compensation capacitor,
CCOMP. Therefore, when trying to maximize the speed of the
amplifier, the value of CCOMP should be minimized. CCOMP can
also be used to slow the amplifier to a point where the slew rate
is perfectly symmetrical and well controlled. Figure 29 sum-
marizes the effect of external compensation on slew rate and
bandwidth.
Figure 30. AD744 Connected as a Unity Gain
Voltage Follower
Table I. Recommended Values of CCOMP vs.
Various Capacitive Loads
Max
CLOAD
(pF)
–3 dB
Bandwidth
(MHz)
CCOMP
(pF)
Slew Rate
(V/s)
Gain
20
100
1
1
1
50
150
2000
5
10
25
37
25
12.5
6.5
4.3
2.0
2
10
Figures 31 and 32 show the AD744 as a voltage follower
with gain and as an inverting amplifier. In these cases, external
compensation is not necessary for stable operation. How-
ever, compensation may be applied to drive capacitive loads
above 50 pF. Table II gives recommended CCOMP values, along
with expected slew rates and bandwidths for a variety of load
conditions and gains for the circuits in Figures 31 and 32.
0.2
1.0
0.1
C
*
LEAD
0.02
0
10
100
1000
R1*
R2*
1F
C
– pF
COMP
+V
S
Figure 29. Gain Bandwidth and Slew Rate vs. CCOMP
0.1F
AD744
V
OUT
OPTIONAL
V
IN
C
COMP
1F
0.1F
*SEE TABLE II
–V
S
Figure 31. AD744 Connected as a Voltage Follower
Operating at Gains of 2 or Greater
–8–
REV. C
AD744
Table II. Recommended Values of CCOMP vs. Various Load Conditions for the Circuits of
Figures 31 and 32.
Max
CLOAD
(pF)
Slew
Rate
(V/s)
–3 dB
Bandwidth
(MHz)
R1
(⍀)
R2
(⍀)
Gain
Follower
Gain
Inverter
CCOMP CLEAD
(pF)
(pF)
4.99 k
4.99 k
4.99 k
4.99 k
4.99 k
4.99 k
4.99 k
4.99 k
2
2
2
2
1
1
1
1
50
150
1000
>2000
0
5
20
25
7
7
–
–
75
37
2.51
2.31
1.2
14
12.52
1.0
499 Ω
499 Ω
499 Ω
4.99 k
4.99 k
4.99 k
11
11
11
10
10
10
270
390
1000
0
2
5
–
–
–
75
1.2
0.85
0.60
50
372
NOTES
1Bandwidth with CLEAD adjusted for minimum settling time.
2Into large capacitive loads the AD744’s 25 mA output current limit sets the slew rate of the amplifier, in V/µs, equal to 0.025
amps divided by the value of CLOAD in µF. Slew rate is specified into rated max CLOAD except for cases marked 2, which are
specified with a 50 pF. load.
C
*
LEAD
Due to manufacturing variations in the value of the internal
CCOMP, it is recommended that the amplifier’s response be
optimized for the desired gain by using a 2 to 10 pF trimmer
capacitor rather than using a fixed value.
R2*
1F
+V
S
0.1F
R1*
V
IN
R2*
R1*
AD744
V
OUT
+V
S
1F
0.1F
OPTIONAL
COMP
C
V
1F
AD744
0.1F
OUT
*SEE TABLE II
–V
S
NOT CONNECTED
2 – 10pF
V
IN
\
Figure 32. AD744 Connected as an Inverting Amplifier
Operating at Gains of 1 or Greater
*SEE TABLE III
0.1F
1F
–V
S
Using Decompensation to Extend the Gain Bandwidth
Product
Figure 33. Using the Decompensation Connection to
Extend Gain Bandwidth
When the AD744 is used in applications where the closed-loop
gain is greater than 10, gain bandwidth product may be enhanced
by connecting a small capacitor between Pins 1 and 5 (Figure
33). At low frequencies, this capacitor cancels the effects of the
chip’s internal compensation capacitor, CCOMP, effectively dec-
ompensating the amplifier.
Table III. Performance Summary for the Circuit of Figure 33
R1
R2
(⍀) (⍀)
Gain
Gain
–3 dB
Gain/BW
Follower Inverter Bandwidth Product
1 k 10 k
100 10 k
100 100 k 1001
11
101
10
100
1000
2.5 MHz
760 kHz
225 kHz
25 MHz
76 MHz
225 MHz
–9–
REV. C
AD744
BIPOLAR
OFFSET
ADJUST
0.1F
100⍀
V
CC
REF
OUT
GAIN
ADJUST
20V SPAN
100⍀
C
LEAD
10V
AD565A
5k⍀
+15V
REF
IN
10V SPAN
DAC OUT
9.96k⍀
10pF
19.95k⍀
1F
5k⍀
8k⍀
REF
GND
20k⍀
AD744
1F
0.1F
POWER
GND
–15V
MSB
LSB
–V
EE
Figure 34. 10 V Voltage Output Bipolar DAC Using the AD744 as an Output Buffer
HIGH-SPEED OP AMP APPLICATIONS
AND TECHNIQUES
A HIGH-SPEED, 3 OP AMP INSTRUMENTATION
AMPLIFIER CIRCUIT
The instrumentation amplifier circuit shown in Figure 36 can
provide a range of gains from unity up to 1000 and higher. The
circuit bandwidth is 4 MHz at a gain of 1 and 750 kHz at a gain
of 10; settling time for the entire circuit is less than 2 µs
to within 0.01% for a 10 V step, (G = 10).
DAC Buffers (I-to-V Converters)
Digital-to-analog converters which use bipolar transistors to
switch currents into (or out of) their outputs can achieve very
fast settling times. The AD565A, for example, is specified to
settle to 12 bits in less than 250 ns, with a current output. How-
ever, in many applications, a voltage output is desirable, and it
would be useful – perhaps essential – that this I-to-V conversion
be accomplished without increasing the settling time or without
degrading the accuracy of the DAC.
While the AD744 is not stable with 100% negative feedback (as
when connected as a standard voltage follower), phase margin
and therefore stability at unity gain may be increased to an accept-
able level by placing the parallel combination of a resistor and a
small lead capacitor between each amplifier’s output and its
inverting input terminal.
Figure 34 is a schematic of an AD565A DAC using an AD744
output buffer. The 10 pF CLEAD capacitor compensates for the
DAC’s output capacitance, plus the 5.5 pF amplifier input
capacitance.
The only penalty associated with this method is a small band-
width reduction at low gains. The optimum value for CLEAD
may be determined from the graph of Figure 41. This technique
can be used in the circuit of Figure 36 to achieve stable opera-
tion at gains from unity to over 1000.
Figure 35 is an oscilloscope photo of the AD744’s output volt-
age with a +10 V to 0 V step applied; this corresponds to an all
“1s” to all “0s” code change on the DAC. Since the DAC is
20,000
CIRCUIT GAIN =
+ 1
R
G
AD744
*1.5pF – 20pF
(TRIM FOR BEST SETTLING TIME)
–IN
A1
**10k⍀
10k⍀
7.5pF
7.5pF
**10k⍀
SENSE
A3
R
**10k⍀
G
10k⍀
AD744
5pF
**10k⍀
A2
REFERENCE
+IN
AD744
Figure 35. Upper Trace: AD744 Output Voltage for
a +10 V to 0 V Step, Scale: 5 mV/div.
*VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT
**RATIO MATCHED 1% METAL FILM RESISTORS
Lower Trace: Logic Input Signal, Scale: 5 V/div.
+V
+15V
PIN 7
S
1F
1F
1F
1F
0.1F
0.1F
connected in the 20 V span mode, 1 LSB is equal to 4.88 mV.
Output settling time for the AD565/AD744 combination is less
than 500 ns to within a 2.44 mV, 1/2 LSB error band.
EACH
AMPLIFIER
COMM
–V
PIN 4
–15V
S
FOR OPTIONAL OFFSET ADJUSTMENT:
TRIM A1, A3 USING TRIM PROCEDURE SHOWN IN FIGURE 21.
Figure 36. A High Performance, 3 Op Amp
Instrumentation Amplifier Circuit
–10–
REV. C
AD744
Table IV. Performance Summary for the 3 Op Amp
Instrumentation Amplifier Circuit
Equation 1 would completely describe the output of the system
if not for the op amp’s finite slew rate and other nonlinear
effects. Even considering these effects, the fine scale settling to
<0.1% will be determined by the op amp’s small signal behav-
ior. Equation 1.
Gain
RG
NC
Bandwidth
T Settle (0.01%)
1
2
10
100
3.5 MHz
2.5 MHz
1 MHz
1.5 µs
1.0 µs
2 µs
20 kΩ
VO
IIN
–R
2.22 kΩ
202 Ω
=
R C + CX
(
)
GN
L
s2 +
+ RC s +1
290 kHz
5 µs
L
2πFO
2πF
O
Where FO = the op amp’s unity gain crossover frequency
R
RO
GN = the“noise”gain of thecircuit 1+
This Equation May Then Be Solved for CL:
Equation 2.
2 RCX 2πFO + 1− G
(
)
N
2 − GN
R2πFO
CL
=
+
R2πFO
In these equations, capacitance CX is the total capacitance appear-
ing at the inverting terminal of the op amp. When modeling an
I-to-V converter application, the Norton equivalent circuit of
Figure 39 can be used directly. Capacitance CX is the total capaci-
tance of the output of the current source plus the input capacitance
of the op amp, which includes any stray capacitance at the op
amp’s input.
Figure 37. The Pulse Response of the 3 Op Amp
Instrumentation Amplifier. Gain = 1, l Horizontal Scale:
0.5 µV/div., Vertical Scale: 5 V/div. (Gain= 10)
C
(OPTIONAL)
COMP
V
AD744
OUT
R
C
L
LOAD
R
I
R
O
C
O
X
C
L
Figure 39. A Simplified Model of the AD744 Used as a
Current-to-Voltage Converter
Figure 38. Settling Time of the 3 Op Amp Instrumentation
Amplifier. Horizontal Scale: 500 ns/div., Vertical Scale,
Pulse Input: 5 V/div., Output Settling: 1 mV/div.
When RO and IO are replaced with their Thevenin VIN and RIN
equivalents, the general purpose inverting amplifier model of
Figure 40 is created. Here capacitor CX represents the input
capacitance of the AD744 (5.5 pF) plus any stray capacitance
due to wiring and the type of IC package employed.
Minimizing Settling Time in Real-World Applications
An amplifier with a “single pole” or “ideal” integrator open-loop
frequency response will achieve the minimum possible settling
time for any given unity-gain bandwidth. However, when this
“ideal” amplifier is used in a practical circuit, the actual settling
time is increased above the minimum value because of added
time constants which are introduced due to additional capacitance
on the amplifier’s summing junction. The following discussion
will explain how to minimize this increase in settling time by the
selection of the proper value for feedback capacitor, CL.
C
(OPTIONAL)
COMP
V
AD744
OUT
R
C
L
LOAD
R
R
IN
V
C
IN
X
C
L
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency, fO, Equation 1 will accurately describe the
small signal behavior of the circuit of Figure 39. This circuit
models an op amp connected as an I-to-V converter.
Figure 40. A Simplified Model of the AD744 Used
as an Inverting Amplifier
–11–
REV. C
AD744
In either case, the capacitance CX causes the system to go from
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp’s
output. If the value of CX can be estimated with reasonable accu-
racy, Equation 2 can be used to choose the correct value for
a small capacitor, CL, which will optimize amplifier response. If
the value of CX is not known, CL should be a variable capacitor.
35
30
25
20
15
10
5
G
= 1
N
G
= 1.5
N
As an aid to the designer, the optimum value of CL for one spe-
cific amplifier connection can be determined from the graph of
Figure 41. This graph has been produced for the case where the
AD744 is connected as in Figures 39 and 40 with a practical
minimum value for CSTRAY of 2 pF and a total CX value of 7.5 pF.
G
= 2
N
IN THIS REGION
= 0pF
C
LEAD
G
= 3
N
G
= 1 TO
N
The approximate value of CL can be determined for almost any
application by solving Equation 2. For example, the AD565/
AD744 circuit of Figure 34 constrains all the variables of Equa-
tion 2 (GN = 3.25, R = 10 kΩ, FO = 13 MHz, and CX = 32.5 pF)
Therefore, under these conditions, CL= 10.5 pF.
0
100
1k
10k
100k
VALUE OF RESISTOR – ⍀
Figure 41. Practical Values of CL vs. Resistance of R
for Various Amplifier Noise Gains
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Cerdip (Q) Package
TO-99 (H) Package
0.005 (0.13) 0.055 (1.35)
0.185 (4.70)
0.165 (4.19)
REFERENCE PLANE
MIN
MAX
0.2 (5.1) TYP
3
0.5 (12.70)
MIN
8
5
45°
0.310 (7.87)
EQUALLY
SPACED
4
2
0.220 (5.59)
0.370 (9.40)
0.335 (8.50)
PIN 1
1
4
1
5
0.335 (8.50)
0.305 (7.75)
0.1 (2.54) BSC
0.32 (8.13)
0.29 (7.37)
8
6
0.405 (10.29) MAX
7
0.06 (1.52)
8 LEADS
0.015 (0.38)
0.20 (5.08)
MAX
0.019 (0.48)
0.016 (0.41)
0.04 (1.0) MAX
0.034 (0.86)
0.028 (0.71)
0.045 (1.1)
0.020 (0.51)
DIA
INSULATION
0.05 (1.27) MAX
0.15
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
SEATING PLANE
BOTTOM VIEW
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15°
0°
0.023 (0.58)
0.014 (0.36)
0.07 (1.78)
0.03 (0.76)
Mini-DIP (N) Package
Small Outline (SO-8) Package
0.39 (9.91)
MAX
0.193 ؎ 0.008
(4.90 ؎ 0.10)
8
5
0.31
(7.87)
0.25
(6.35)
8
1
5
4
0.154 ؎ 0.004
(3.91 ؎ 0.10)
0.236 ؎ 0.012
(6.00 ؎ 0.20)
1
4
0.30 (7.62)
REF
PIN 1
0.10 (2.54)
TYP
PIN 1
0.035 ؎ 0.01
(0.89 ؎ 0.25)
0.050 (1.27)
BSC
0.165 ؎ 0.01
(4.19 ؎ 0.25)
0.008 ؎ 0.004
(0.203 ؎ 0.075)
0.098 ؎ 0.006
(2.49 ؎ 0.23)
0.18 ؎ 0.03
(4.57 ؎ 0.76)
0.125 (3.18)
MIN
0.033 ؎ 0.017
(0.83 ؎ 0.43)
0.017 ؎ 0.003
(0.42 ؎ 0.07)
0.011 ؎ 0.003
(0.28 ؎ 0.08)
0.011 ؎ 0.002
(0.269 ؎ 0.03)
SEATING
PLANE
0.018 ؎ 0.003
(0.46 ؎ 0.08)
0.033
(0.84)
NOM
SEATING
PLANE
0-15؇
–12–
REV.C
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