AD7470ARUZ [ADI]
1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs; 1.75 MSPS ， 4 mW的10位/ 12位并行ADC
| 型号： | AD7470ARUZ |
| 厂家： | 
ADI |
| 描述： | 1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs |
| 文件： | 总16页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.75 MSPS, 4 mW
10-Bit/12-Bit Parallel ADCs
a
AD7470/AD7472
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Specified for VDD of 2.7 V to 5.25 V
1.75 MSPS for AD7470 (10-Bit)
1.5 MSPS for AD7472 (12-Bit)
V
AV
DV
DD
REF IN
DRIVE
DD
Low Power
DB9 (DB11)
DB0
10-/12-BIT
AD7470: 3.34 mW Typ at 1.5 MSPS with 3 V Supplies
7.97 mW Typ at 1.75 MSPS with 5 V Supplies
AD7472: 3.54 mW Typ at 1.2 MSPS with 3 V Supplies
8.7 mW Typ at 1.5 MSPS with 5 V Supplies
Wide Input Bandwidth
70 dB Typ SNR at 500 kHz Input Frequency
Flexible Power/Throughput Rate Management
No Pipeline Delays
SUCCESSIVE
OUTPUT
DRIVERS
V
T/H
IN
APPROXIMATION
ADC
CLK IN
CONTROL
LOGIC
CONVST
CS
RD
High Speed Parallel Interface
Sleep Mode: 50 nA Typ
24-Lead SOIC and TSSOP Packages
BUSY
AD7470/AD7472
AGND
DGND
GENERAL DESCRIPTION
AD7470 IS A 10-BIT PART WITH DB0 TO DB9 AS OUTPUTS.
AD7472 IS A 12-BIT PART WITH DB0 TO DB11 AS OUTPUTS.
The AD7470/AD7472 are 10-bit/12-bit high speed, low power,
successive-approximation ADCs. The parts operate from a
single 2.7 V to 5.25 V power supply and feature throughput rates
up to 1.5 MSPS for the 12-bit AD7472 and up to 1.75 MSPS for
the 10-bit AD7470. The parts contain a low noise, wide band-
width track/hold amplifier that can handle input frequencies in
excess of 1 MHz.
It is also possible to operate the parts in an auto sleep mode,
where the part wakes up to do a conversion and automatically
enters sleep mode at the end of conversion. Using this method
allows very low power dissipation numbers at lower throughput
rates. In this mode, the AD7472 can be operated with 3 V sup-
plies at 100 kSPS, and consume an average current of just 124 µA.
At 5 V supplies and 100 kSPS, the average current consumption
is 171 µA.
The conversion process and data acquisition are controlled
using standard control inputs allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CONVST and conversion is also initiated at
this point. The BUSY goes high at the start of conversion and
goes low 531.66 ns after falling edge of CONVST (AD7472 with
a clock frequency of 26 MHz) to indicate that the conversion is
complete. There are no pipelined delays associated with the part.
The conversion result is accessed via standard CS and RD sig-
nals over a high speed parallel interface.
The analog input range for the part is 0 to REF IN. The +2.5 V
reference is applied externally to the REF IN pin. The conver-
sion rate is determined by the externally-applied clock.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption. The
AD7470 offers 1.75 MSPS throughput and the AD7472
offers 1.5 MSPS throughput rates with 4 mW power
consumption.
The AD7470/AD7472 uses advanced design techniques to
achieve very low power dissipation at high throughput rates. With
3 V supplies and 1.5 MSPS throughput rate, the AD7470 typi-
cally consumes, on average, just 1.1 mA. With 5 V supplies and
1.75 MSPS, the average current consumption is typically
1.6 mA. The part also offers flexible power/throughput rate
management. Operating the AD7470 with 3 V supplies and
500 kSPS throughput reduces the current consumption to 713 µA.
At 5 V supplies and 500 kSPS, the part consumes 944 µA.
2. Flexible Power/Throughput Rate Management. The conver-
sion rate is determined by an externally-applied clock allow-
ing the power to be reduced as the conversion rate is reduced.
The part also features an auto sleep mode to maximize power
efficiency at lower throughput rates.
3. No Pipeline Delay. The part features a standard successive-
approximation ADC with accurate control of the sampling
instant via a CONVST input and once off conversion
control.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD7470/AD7472
(VDD = +2.7 V to +5.25 V2, REF IN = 2.5 V, fCLK IN = 30 MHz @ 5 V and 24 MHz @ 3 V;
AD7470–SPECIFICATIONS1 TA = TMIN to TMAX3, unless otherwise noted.)
Parameter
A Version1
Units
Test Conditions/Comments
fS = 1.75 MSPS @ 5 V, fS = 1.5 MSPS @ 3 V
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)
5 V
60
60
60
60
–83
–75
–85
–75
3 V
60
60
60
60
–83
–75
–85
–75
dB min
dB min
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
dB typ
dB max
dB typ
dB max
f
IN = 100 kHz Sine Wave
Intermodulation Distortion (IMD)
Second Order Terms
–79
–75
–77
–75
5
–75
–75
–75
–75
5
dB typ
dB max
dB typ
dB max
ns typ
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
15
20
15
20
ps typ
MHz typ
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
fS = 1.75 MSPS @ 5 V; fS = 1.5 MSPS @ 3 V
Guaranteed No Missed Codes to 10 Bits
10
1
0.9
2.5
1
10
1
0.9
2.5
1
Bits
LSB max
LSB max
LSB max
LSB max
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to REF IN
1
33
0 to REF IN
1
33
V
µA max
pF typ
REFERENCE INPUT
REF IN Input Voltage Range
DC Leakage Current
Input Capacitance
2.5
1
10/20
2.5
1
10/20
V
1% for Specified Performance
Track/Hold Mode
µA max
pF typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.4
1
2.4
0.4
1
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDD
4
Input Capacitance, CIN
10
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
VDRIVE – 0.2
VDRIVE – 0.2 V min
ISOURCE = 200 µA
ISINK = 200 µA
VDD = 2.7 V to 5.25 V
0.4
10
10
0.4
10
10
V max
µA max
pF max
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
12
135
1.75
12
135
1.5
CLK IN Cycles (max)
ns min
MSPS max
Conversion Time + Acquisition Time
CLK IN of 30 MHz @ 5 V and 24 MHz @ 3 V
POWER REQUIREMENTS
VDD
IDD
+2.7/+5.25
V min/max
5
Digital I/Ps = 0 V or DVDD
Normal Mode
Quiescent Current
Normal Mode
2.4
900
1.5
800
1
mA max
µA max
mA max
µA max
µA max
VDD = 4.75 V to 5.25 V; fS = 1.75 MSPS; Typ 2 mA
VDD = 4.75 V to 5.25 V; fS = 1.75 MSPS
VDD = 2.7 V to 3.3 V; fS = 1.5 MSPS; Typ 1.3 mA
VDD = 2.7 V to 3.3 V; fS = 1.5 MSPS
CLK IN = 0 V or DVDD
Digital I/Ps = 0 V or DVDD
VDD = 5 V
VDD = 3 V
VDD = 5 V; CLK IN = 0 V or DVDD
VDD = 3 V; CLK IN = 0 V or DVDD
Quiescent Current
Sleep Mode
Power Dissipation5
Normal Mode
12
4.5
5
mW max
mW max
µW max
µW max
Sleep Mode
3
NOTES
1Temperature ranges as follows: A Version: -40°C to +85°C.
2The AD7470 functionally works at 2.35 V. Typical specifications @ +25°C for SNR (100 kHz) = 59 dB; THD (100 kHz) = –84 dB; INL 0.8 LSB.
3The AD7470 will typically maintain A-grade performance up to +125°C, with a reduced CLK of 20 MHz @ 5 V and 16 MHz @ 3 V. Typical Sleep Mode current @ +125°C is 700 nA.
4Sample tested @ +25°C to ensure compliance.
5See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. A
–2–
AD7470/AD7472
(VDD = +2.7 V to +5.25 V2, REF IN = 2.5 V, fCLK IN = 26 MHz @ 5 V and 20 MHz @ 3 V;
AD7472–SPECIFICATIONS1 TA = TMIN to TMAX3, unless otherwise noted.)
Parameter
A Version1
B Version1
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD) 69
68
5 V
3 V
5 V
69
3 V
f
S = 1.5 MSPS @ 5 V, fS = 1.2 MSPS @ 3 V
IN = 500 kHz Sine Wave
69
69
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
f
68
70
68
–78
–84
–75
68
68
70
68
–78
–84
–75
fIN = 100 kHz Sine Wave
IN = 500 kHz Sine Wave
Signal-to-Noise Ratio (SNR)
70
68
70
68
–83
–83
–75
f
fIN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
Total Harmonic Distortion (THD) –83
–83
–75
f
IN = 100 kHz Sine Wave
Peak Harmonic or Spurious Noise
(SFDR)
–86
–86
–76
–81
–86
–76
–86
–86
–76
–81
–86
–76
dB typ
dB typ
dB max
fIN = 500 kHz Sine Wave
IN = 100 kHz Sine Wave
f
fIN = 100 kHz Sine Wave
Intermodulation Distortion (IMD)
Second Order Terms
–77
–86
–77
–86
5
–77
–86
–77
–86
5
–77
–86
–77
–86
5
–77
–86
–77
–86
5
dB typ
dB typ
dB typ
dB typ
ns typ
fIN = 500 kHz Sine Wave
f
IN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
IN = 100 kHz Sine Wave
Third Order Terms
f
Aperture Delay
Aperture Jitter
Full Power Bandwidth
15
20
15
20
15
20
15
20
ps typ
MHz typ
DC ACCURACY
Resolution
Integral Nonlinearity
fS = 1.5 MSPS @ 5 V; fS = 1.2 MSPS @ 3 V
12
2
12
2
12
1
12
1
Bits
LSB max
Guaranteed No Missed Codes to 11 Bits
(A Version)
Differential Nonlinearity
1.8
1.8
0.9
0.9
LSB max
Guaranteed No Missed Codes to 12 Bits
(B Version)
Offset Error
Gain Error
10
2
10
2
10
2
10
2
LSB max
LSB max
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to REF IN 0 to REF IN
0 to REF IN 0 to REF IN
V
1
1
1
1
µA max
33
33
33
33
pF typ
REFERENCE INPUT
REF IN Input Voltage Range
DC Leakage Current
Input Capacitance
2.5
1
10/20
2.5
1
10/20
2.5
1
10/20
2.5
1
10/20
V
1% for Specified Performance
Track/Hold Mode
µA max
pF typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.4
1
2.4
0.4
1
2.4
0.4
1
2.4
0.4
1
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDD
4
Input Capacitance, CIN
10
10
10
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
VDRIVE – 0.2 VDRIVE – 0.2
0.4 0.4
10 10
10 10
Straight (Natural) Binary
VDRIVE – 0.2 VDRIVE – 0.2
0.4 0.4
10 10
10 10
Straight (Natural) Binary
V min
ISOURCE = 200 µA
ISINK = 200 µA
VDD = 2.7 V to 5.25 V
V max
µA max
pF max
CONVERSION RATE
Conversion Time
14
14
14
14
CLK IN
Cycles (max)
ns min
Track/Hold Acquisition Time
Throughput Rate
135
1.5
135
1.2
135
1.5
135
1.2
MSPS max
Conversion Time + Acquisition Time
CLK IN Is 26 MHz @ 5 V and 20 MHz @ 3 V
POWER REQUIREMENTS
VDD5
+2.7/+5.25
+2.7/+5.25
V min/max
IDD
Digital I/Ps = 0 V or DVDD
Normal Mode
Quiescent Current
Normal Mode
Quiescent Current
Sleep Mode
2.4
900
1.5
800
1
2.4
900
1.5
800
1
mA max
µA max
mA max
µA
VDD = 4.75 V to 5.25 V; fS = 1.5 MSPS; Typ 2 mA
VDD = 4.75 V to 5.25 V; fS = 1.5 MSPS
VDD = 2.7 V to 3.3 V; fS = 1.2 MSPS; Typ 1.3 mA
VDD = 2.7 V to 3.3 V; fS = 1.2 MSPS
CLK IN = 0 V or DVDD
Digital I/Ps = 0 V or DVDD
VDD = 5 V
VDD = 3 V
µA max
Power Dissipation5
Normal Mode
12
4.5
5
12
4.5
5
mW max
mW max
µW max
µW max
Sleep Mode
VDD = 5 V; CLK IN = 0 V or DVDD
VDD = 3 V; CLK IN = 0 V or DVDD
3
3
NOTES
1Temperature ranges as follows: A and B Versions: –40°C to +85°C.
2The AD7472 functionally works at 2.35 V. Typical specifications @ +25°C for SNR (100 kHz) = 68 dB; THD (100 kHz) = –84 dB; INL 0.8 LSB.
3The AD7472 will typically maintain A-grade performance up to +125°C, with a reduced CLK of 18 MHz @ 5 V and 14 MHz @ 3 V. Typical Sleep Mode current @ +125°C is 700 nA.
4Sample tested @ +25°C to ensure compliance.
5See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. A
–3–
AD7470/AD7472
TIMING SPECIFICATIONS1
(VDD = +2.7 V to +5.25 V, REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX
Parameter
AD7470
AD7472
Units
Description
2
fCLK
10
30
436.42
1
10
10
30
0
10
26
531.66
1
10
10
30
0
kHz min
MHz max
ns min
µs max
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
tCONVERT
tWAKEUP
t13
tCLK = 1/fCLK IN
Wake-Up Time
CONVST Pulsewidth
CONVST to BUSY Delay, VDD = 5 V
CONVST to BUSY Delay, VDD = 3 V
BUSY to CS Setup Time
CS to RD Setup Time
t2
t34
t4
t54
t65
t7
t8
t9
0
0
20
15
8
0
135
100
20
15
8
0
135
100
RD Pulsewidth
Data Access Time After Falling Edge of RD
Bus Relinquish Time After Rising Edge of RD
CS to RD Hold Time
Acquisition Time
Quiet Time
t10
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See
Figure 1.
2Mark/Space ratio for the CLK input is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of CONVST.
3t2 is 35 ns max @ +125°C.
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
5t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200A
200A
I
I
OL
TO OUTPUT
PIN
+1.6V
C
50pF
L
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. A
–4–
AD7470/AD7472
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
AVDD to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
1
2
24 DB6
23
DB7
DB8
DB5
22 DB4
21
20 DV
V
DRIVE to AGND/DGND . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DRIVE to DVDD . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
(MSB) DB9
3
AV
4
V
DD
DRIVE
V
REF IN
5
DD
AGND TO DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REF IN to AGND . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA
Operating Temperature Range
Commercial (A and B Version) . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
SOIC, TSSOP Package Dissipation . . . . . . . . . . . . . +450 mW
AD7470
TOP VIEW
(Not to Scale)
V
6
19 DGND
18 DB3
17 DB2
16 DB1
IN
AGND
CS
7
8
9
RD
10
15
DB0 (LSB)
CONVST
CLKIN 11
BUSY 12
14 NC
13 NC
NC = NO CONNECT
θ
JA Thermal Impedance . . . . . . . . . . . . . . . 75°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115°C/W (TSSOP)
DB9
DB10
1
2
24 DB8
23
θ
JC Thermal Impedance . . . . . . . . . . . . . . . 25°C/W (SOIC)
DB7
22 DB6
21
20 DV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35°C/W (TSSOP)
Lead Temperature, Soldering
(MSB) DB11
3
AV
DD
4
V
DRIVE
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
REF IN
5
DD
AD7472
TOP VIEW
(Not to Scale)
V
6
19 DGND
18 DB5
17 DB4
16 DB3
IN
AGND
CS
7
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
8
9
RD
10
15
DB2
CONVST
14 DB1
CLKIN 11
BUSY 12
13 DB0 (LSB)
ORDERING GUIDE
Temperature
Range
Resolution
(Bits)
Package
Model
Options1
AD7470ARU
AD7472AR
AD7472BR
AD7472ARU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
10
12
12
12
12
RU-24
R-24
R-24
RU-24
RU-24
Evaluation Board
Evaluation Board
Controller Board
AD7472BRU
EVAL-AD7470CB2
EVAL-AD7472CB2
EVAL-CONTROL BOARD3
HSC-INTERFACE BOARD
Evaluation High Speed Interface Board
NOTES
1R = SOIC; RU = TSSOP.
2This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
3This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7470/AD7472 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–5–
AD7470/AD7472
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
CS
Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The conversion
result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to
the same AND gate on the input so the signals are interchangeable. CS can be hardwired permanently low.
RD
Read Input. Logic Input used in conjunction with CS to access the conversion result. The conversion result is
placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to same
AND gate on the input so the signals are interchangeable. CS and RD can be hardwired permanently low in which
case, the data bus is always active and the result of the new conversion is clocked out slightly before to the BUSY
line going low.
CONVST
Conversion Start Input. Logic Input used to initiate conversion. The input track/hold amplifier goes from track
mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. The con-
version input can be as narrow as 15 ns. If the CONVST input is kept low for the duration of conversion and is
still low at the end of conversion, the part will automatically enter sleep mode. If the part enters this sleep mode,
the next rising edge of CONVST wakes up the part. Wake-up time for the part is typically 1 µs.
CLK IN
BUSY
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7472 takes 14 clock cycles while conversion time for the AD7470 takes 12 clock cycles. The frequency of this
master clock input, therefore, determines the conversion time and achievable throughput rate. While the ADC is
not converting, the Clock-In pad is in three-state and thus no clock is going through the part.
BUSY Output. Logic Output indicating the status of the conversion process. The BUSY signal goes high after the
falling edge of CONVST and stays high for the duration of conversion. Once conversion is complete and the con-
version result is in the output register, the BUSY line returns low. The track/hold returns to track mode just prior
to the falling edge of BUSY and the acquisition time for the part begins when BUSY goes low. If the CONVST
input is still low when BUSY goes low, the part automatically enters its sleep mode on the falling edge of BUSY.
REF IN
AVDD
Reference Input. An external reference must be applied to this input. The voltage range for the external reference
is 2.5 V 1% for specified performance.
Analog Supply Voltage, +2.7 V to +5.25 V. This is the only supply voltage for all analog circuitry on the AD7470/
AD7472. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V
apart even on a transient basis. This supply should be decoupled to AGND.
DVDD
Digital Supply Voltage, +2.7 V to +5.25 V. This is the supply voltage for all digital circuitry on the AD7470/
AD7472 apart from the output drivers. The DVDD and AVDD voltages should ideally be at the same potential and
must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
AGND
DGND
Analog Ground. Ground reference point for all analog circuitry on the AD7470/AD7472. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7470 and AD7472. The
DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even
on a transient basis.
VIN
Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents a
high dc input impedance.
VDRIVE
Supply Voltage for the Output Drivers, +2.7 V to +5.25 V. This voltage determines the output high voltage for the
data output pins. It allows the AVDD and DVDD to operate at 5 V (and maximize the dynamic performance of the
ADC) while the digital outputs can interface to 3 V logic.
DB0–DB9/11
Data Bit 0 to Data Bit 9 (AD7470) and DB11 (AD7472). Parallel digital outputs that provide the conversion
result for the part. These are three-state outputs that are controlled by CS and RD. The output high voltage level
for these outputs is determined by the VDRIVE input.
REV. A
–6–
AD7470/AD7472
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
The last transition should occur at the analog value 1 1/2 LSB
below the nominal full scale. The first transition is a 1/2 LSB
above the low end of the scale (zero in the case of AD7470/
AD7472). The gain error is the deviation of the actual difference
between the first and last code transitions from the ideal differ-
ence between the first and last code transitions with offset errors
removed.
The AD7470/AD7472 are tested using the CCIF standard
where two input frequencies near the top end of the input band-
width are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode after the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within 1 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
Aperture Delay
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
In a sample/hold, the time required after the hold command for
the switch to open fully is the aperture delay. The sample is, in
effect, delayed by this interval, and the hold command would
have to be advanced by this amount for precise timing.
Aperture Jitter
Aperture jitter is the range of variation in the aperture delay. In
other words, it is the uncertainty about when the sample is
taken. Jitter is the result of noise which modulates the phase of
the hold command. This specification establishes the ultimate
timing error, hence the maximum sampling frequency for a
given resolution. This error will increase as the input dV/dt
increases.
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB and for a 10-bit con-
verter is 62 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7470/AD7472 it is
defined as:
(V22 + V32 + V42 + V52 + V62)
THD (dB) = 20 log
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
REV. A
–7–
AD7470/AD7472
CIRCUIT DESCRIPTION
TYPICAL CONNECTION DIAGRAM
CONVERTER OPERATION
Figure 5 shows a typical connection diagram for the AD7470/
AD7472. Conversion is initiated by a falling edge on CONVST.
Once CONVST goes low the BUSY signal goes high, and at the
end of conversion the falling edge of BUSY is used to activate
an Interrupt Service Routine. The CS and RD lines are then
activated in parallel to read the 10- or 12-data bits. The recom-
mended REF IN voltage is 2.5 V providing an analog input
range of 0 V to 2.5 V, making the AD7470/AD7472 a unipolar
A/D. It is recommended to perform a dummy conversion after
power-up as the first conversion result could be incorrect. This
also ensures that the part is in the correct mode of operation.
The CONVST pin should not be floating when power is applied
as a rising edge on CONVST might not wake up the part.
The AD7470/AD7472 is a 10-bit/12-bit successive approxima-
tion analog-to-digital converter based around a capacitive DAC.
The AD7470/AD7472 can convert analog input signals in the
range 0 V to VREF. Figure 2 shows a very simplified schematic of
the ADC. The Control Logic, SAR and the Capacitive DAC
are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition.
COMPARATOR
CAPACITIVE
DAC
In Figure 5 the VDRIVE pin is tied to DVDD, which results in logic
output voltage values being either 0 V or DVDD. The voltage
applied to VDRIVE controls the voltage value of the output logic
signals. For example, if DVDD is supplied by a 5 V supply and
V
IN
SWITCHES
SAR
V
REF
VDRIVE by a 3 V supply, the logic output voltage levels would be
either 0 V or 3 V. This feature allows the AD7470/AD7472 to
interface to 3 V parts while still enabling the A/D to process
signals at 5 V supply.
CONTROL
INPUTS
CONTROL LOGIC
OUTPUT DATA
10-/12-BIT PARALLEL
ANALOG
SUPPLY
2.7V–5.25V
+
+
Figure 2. Simplified Block Diagram of AD7470/AD7472
10F
0.1F
47F
Figure 3 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A. The comparator is held in a
balanced condition and the sampling capacitor acquires the
AV
DD
V
DRIVE
DV
DD
1nF
AD7470/
AD7472
signal on VIN
.
C/P
+2.5V*
0.1F
REF IN
0V TO
REF IN
10F
V
IN
CAPACITIVE
DAC
PARALLED
INTERFACE
DB0–
DB9 (DB11)
2k⍀
CS
A
V
IN
CONVST
RD
BUSY
B
CONTROL LOGIC
SW1
SW2
COMPARATOR
AGND
*RECOMMENDED REF IN VOLTAGE
Figure 3. ADC Acquisition Phase
Figure 5. Typical Connection Diagram
Figure 4 shows the ADC during conversion. When conversion
starts SW2 will open and SW1 will move to position B, causing
the comparator to become unbalanced. The ADC then runs
through its successive approximation routine and brings the
comparator back into a balanced condition. When the compara-
tor is rebalanced, the conversion result is available in the SAR
register.
CAPACITIVE
DAC
2k⍀
A
V
IN
SW1
B
CONTROL LOGIC
SW2
COMPARATOR
AGND
Figure 4. ADC Conversion Phase
REV. A
–8–
AD7470/AD7472
ADC TRANSFER FUNCTION
DC Acquisition Time
The output coding of the AD7470/AD7472 is straight binary.
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, etc.). The LSB size is = (REF IN)/
4096 for the AD7472 and (REF IN)/1024 for the AD7470. The
ideal transfer characteristic for the AD7472 is shown in Figure 6.
The ADC starts a new acquisition phase at the end of a conver-
sion and ends it on the falling edge of the CONVST signal. At
the end of conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 135 ns.
The analog signal on VIN is also being acquired during this
settling time; therefore, the minimum acquisition time needed is
approximately 135 ns.
111...111
111...110
Figure 8 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R3 repre-
sents the source impedance of a buffer amplifier or resistive
network, R1 is an internal switch resistance, R2 is for bandwidth
control and C1 is the sampling capacitor. C2 is back-plate ca-
pacitance and switch parasitic capacitance.
111...000
1LSB = V
/4096
REF
011...111
000...010
000...001
000...000
During the acquisition phase the sampling capacitor must be
charged to within 1 LSB of its final value.
0V 1/2LSB
+V
–1LSB
REF
ANALOG INPUT
C1
R1
22pF
V
Figure 6. Transfer Characteristic for 12 Bits
IN
125⍀
R3
R2
636⍀
C2
8pF
AC ACQUISITION TIME
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of impedance at the VIN pin of the
ADC will cause the THD to degrade at high input frequencies.
Figure 8. Equivalent Sampling Circuit
ANALOG INPUT
Figure 9 shows the equivalent circuit of the analog input struc-
ture of the AD7470/AD7472. The two diodes, D1 and D2,
provide ESD protection for the analog inputs. The capacitor C3
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is an internal switch resistance.
This resistor is typically about 125 Ω. The capacitor C1 is the
sampling capacitor while R2 is used for bandwidth control.
AD7470/AD7472
DYNAMIC
PERFORMANCE
SPECIFICATIONS
TYPICAL AMPLIFIER
INPUT
BUFFERS
SNR
THD
500kHz
CURRENT
500kHz
CONSUMPTION
AD8047
AD9631
AD8051
AD797
70
78
80
78
84
5.8mA
17mA
4.4mA
8.2mA
V
DD
69.5
68.6
70
C1
22pF
R1
R2
636⍀
D1
D2
125⍀
V
IN
C3
4pF
C2
8pF
Figure 7. Recommended Input Buffers
Reference Input
The following references are best suited for use with the
AD7470/AD7472.
Figure 9. Equivalent Analog Input Circuit
CLOCK SOURCES
ADR291
AD780
AD192
The max CLK specification for the AD7470 is 30 MHz and for
the AD7472, it is 26 MHz. These frequencies are not standard
off-the-shelf oscillator frequencies. Many manufacturers pro-
duce oscillator modules close to these frequencies; a typical one
being 25.175 MHz from IQD Limited. AEL Crystals Limited
produce a 25 MHz oscillator module in various packages. Crys-
tal oscillator manufacturers will produce 26 MHz and 30 MHz
oscillators to order. Of course any clock source can be used, not
just crystal oscillators.
For optimum performance, a 2.5 V reference is recommended.
The part can function with a reference up to 3 V and down to
2 V, but the performance deteriorates.
REV. A
–9–
AD7470/AD7472
PARALLEL INTERFACE
completed. The data is available on the output bus slightly
before the falling edge of BUSY.
The parallel interface of the AD7470 and AD7472 is 10-bits
and 12-bits wide respectively. The output data buffers are acti-
vated when both CS and RD are logic low. At this point the
contents of the data register are placed onto the data bus. Figure
10 shows the timing diagram for the parallel port.
It is important to point out that data bus cannot change state
while the A/D is doing a conversion as this would have a detri-
mental effect on the conversion in progress. The data out lines
will go three-state again when either the RD or CS line goes
high. Thus the CS can be tied low permanently, leaving the RD
line to control conversion result access. Please reference the
VDRIVE section for output voltage levels.
Figure 11 shows the timing diagram for the parallel port when
CS and RD are tied permanently low. In this setup, once the
BUSY line goes from high to low the conversion process is
tCONVERT
CONVST*
t9
t2
t10
BUSY
t3
CS
t4
t8
t5
RD
t7
t6
DBx
*CONVST SHOULD GO HIGH WHEN THE CLK IS HIGH OR BEFORE THE FIRST CLK CYCLE.
Figure 10. Parallel Port Timing
tCONVERT
CONVST*
BUSY
t9
t2
DBx
DATA N
DATA N+1
*CONVST SHOULD GO HIGH WHEN THE CLK IS HIGH OR BEFORE THE FIRST CLK CYCLE.
Figure 11. Parallel Port Timing with CS and RD Tied Low
CLK IN
tCONVERT
CONVST
tWAKEUP
t2
BUSY
t3
t4
CS
RD
t8
t5
t6
t7
DBX
Figure 12. Wake-Up Timing Diagram (Burst Clock)
REV. A
–10–
AD7470/AD7472
tCONVERT
CONVST
tWAKEUP
BUSY
CS
RD
DBx
Figure 13. Mode 2 Operation
OPERATING MODES
CLK IN rising edge after BUSY goes high. The clock needs to
start less than two clock cycles away from the CONVST active
edge otherwise INL deteriorates; e.g., if the clock frequency is
28 MHz the clock must start within 71.4 ns of CONVST going
low. In Figure 12 the A-D converter section is put into sleep
mode once conversion is completed and on the rising edge of
CONVST it is woken up again; the user must be wary of the
wake-up time as this will reduce the sampling rate of the ADC.
The AD7470 and AD7472 have two possible modes of opera-
tion depending on the state of the CONVST pulse at the end of
a conversion, Mode 1 and Mode 2. There is a continuous clock
on the CLK IN pin.
Mode 1 (High Speed Sampling)
In this mode of operation the CONVST pulse is brought high
before the end of conversion i.e., before the BUSY goes low (see
Figure 10). If the CONVST pin is brought from high to low while
BUSY is high, the conversion is restarted. When operating in
this mode a new conversion should not be initiated until 135 ns
after BUSY goes low. This acquisition time allows the track/
hold circuit to accurately acquire the input signal. As mentioned
earlier, a read should not be done during a conversion. This
mode facilitates the fastest throughput times for the AD7470/
AD7472.
VDRIVE
The VDRIVE pin is used as the voltage supply to the output driv-
ers and is a separate supply from AVDD and DVDD. The purpose
of using a separate supply for the output drivers is that the user
can vary the output high voltage, VOH, from the VDD supply to
the AD7470/AD7472. For example, if AVDD and DVDD is using
a 5 V supply, the VDRIVE pin can be powered from a 3 V supply.
The ADC has better dynamic performance at 5 V than at 3 V,
so operating the part at 5 V, while still being able to interface to
3 V parts, pushes the AD7470/AD7472 to the top bracket of
high performance 10-bit/12-bit A/Ds. Of course, the ADC can
have its VDRIVE and DVDD pins connected together and be pow-
ered from a 3 V or 5 V supply.
Mode 2 (Sleep Mode)
Figure 13 shows AD7470/AD7472 in Mode 2 operation where
the ADC goes into sleep mode after conversion. The CONVST
line is brought low to initiate a conversion and remains low until
after the end of conversion. If CONVST goes high and low
again while BUSY is high, the conversion is restarted. Once the
BUSY line goes from a high to a low, the CONVST line has its
status checked and, if low, the part enters sleep mode.
All outputs are powered from VDRIVE. These are all the data out
pins and the BUSY pin. The CONVST, CS, RD and CLK IN
signals are related to the DVDD voltage.
The device wakes up again on the rising edge of the CONVST
signal. There is a wake-up time of typically 1 µs after the rising
edge of CONVST before the BUSY line can go high to indicate
start of conversion. BUSY will only go high once CONVST goes
low. The CONVST line can go from a high to a low during this
wake-up time, but the conversion will still not be initiated until
after the 1 µs wake-up time. Superior power performance can be
achieved in this mode of operation by waking up the AD7470
and AD7472 only to carry out a conversion.
POWER-UP
It is recommended that the user performs a dummy conversion
after power-up, as the first conversion result could be incorrect.
This also ensures that the parts is in the correct mode of opera-
tion. The recommended power-up sequence is as follows:
1 > GND
2 > VDD
3 > VDRIVE
4 > Digital Inputs
5 > REF IN
6 > VIN
Burst Mode
Power vs. Throughput
Burst mode on the AD7470/AD7472 is a subsection of Mode 1
and Mode 2, the clock is noncontinuous. Figure 12 shows how
the ADC works in burst mode for Mode 2. The clock needs
only to be switched on during conversion, minimum of 12 clock
cycles for the AD7470 and 14 clock cycles for the AD7472. As
the clock is off during nonconverting intervals, system power is
saved. The BUSY signal can be used to gate the CLK IN pulses.
The ADC does not begin the conversion process until the first
The two modes of operation for the AD7470 and AD7472 will
produce different power versus throughput performances, Mode
1 and Mode 2; see Operating Modes section of the data sheet
for more detailed descriptions of these modes. Mode 2 is the
Sleep Mode of the part and it achieves the optimum power
performance.
REV. A
–11–
AD7470/AD7472
Mode 1
Figure 16 and Figure 17 show a typical graphical representation
of Power vs. Throughput for the AD7472 when in (a) Mode 1
@ 5 V and 3 V and Mode 2 @ 5 V and 3 V.
Figure 14 shows the AD7472 conversion sequence in Mode 1
using a throughput rate of 500 kSPS and a clock frequency of
26 MHz. At 5 V supply the current consumption for the part
when converting is 2 mA and the quiescent current is 650 µA.
The conversion time of 531.66 ns contributes 2.658 mW to the
overall power dissipation in the following way:
8
7
6
(531.66 ns/2 µs) × (5 × 2 mA) = 2.658 mW
+5V
The contribution to the total power dissipated by the remaining
1.468 µs of the cycle is 2.38 mW.
5
4
(1.468 µs/2 µs) × (5 × 650 µA) = 2.38 mW
Thus the power dissipated during each cycle is:
2.658 mW + 2.38 mW = 5.038 mW
3
2
+3V
1000
1
0
CONVST
600
800
1100
1300
1500
50
300
THROUGHPUT – kHz
tCONVERT
tQUIESCENT
Figure 16. Power vs. Throughput (Mode 1 @ 5 V and 3 V)
BUSY
531.66ns
1.468s
7
6
5
2s
Figure 14. Mode 1 Power Dissipation
Mode 2
Figure 15 shows the AD7472 conversion sequence in Mode 2
using a throughput rate of 500 kSPS and a clock frequency of
26 MHz. At 5 V supply the current consumption for the part
when converting is 2 mA, while the sleep current is 1 µA max.
The power dissipated during this power-down is negligible and
is thus not worth considering in the total power figure. During
the wake-up phase, the AD7472 will draw 650 µA. Overall
power dissipated is:
+5V
4
3
+3V
2
1
0
531.66 ns / 2 µs × 5 × 2mA + 1µs / 2 µs × 5 × 650 µA = 4.283mW
(
)
(
)
(
)
(
)
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750
THROUGHPUT – kHz
tCONVERT
Figure 17. Power vs. Throughput (Mode 2 @ 5 V and 3 V)
tWAKEUP
CONVST
1s
2s
1
0.8
0.6
0.4
0.2
0
tQUIESCENT
BUSY
531.66ns
1.468s
Figure 15. Mode 2 Power Dissipation
–0.2
–0.4
–0.6
–0.8
–1
0
512
1024
1536
2048
2560
3072
3584
4096
CODE
Figure 18. Typical INL for 2.75 V @ +25°C
REV. A
–12–
AD7470/AD7472
70.6
70.4
70.2
70
1
0.8
0.6
0.4
0.2
0
–40؇C
+25؇C
+85؇C
69.8
69.6
69.4
69.2
–0.2
–0.4
–0.6
–0.8
–1
2.5 2.75
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25
0
512
1024
1536
2048
CODE
2560
3072
3584
4096
SUPPLY – Volts
Figure 22. Typical SNR vs. Supply
Figure 19. Typical DNL for 2.75 V @ +25°C
0
72
AD7472 +5V
70
–20
–40
–60
68
AD7472 +3V
66
64
AD7470 +5V
62
60
AD7470 +3V
–80
–100
–120
58
56
54
52
0
100000
200000
300000
400000
500000
600000
10
50
100
200
500
1000
2000
FREQUENCY – Hz
INPUT FREQUENCY – kHz
Figure 23. Typical SNR @ 500 kHz Input Tone
Figure 20. Typical SNR+D vs. Input Tone
0.2
90
AD7472 +5V
AD7470 +5V
–0.3
85
80
75
70
65
60
55
50
+3V
–0.8
AD7472 +3V
+5V
–1.3
AD7470 +3V
–1.8
–2.3
–2.8
–3.3
–3.8
10
100
1000
10000
100000
10
50
100
200
500
1000
2000
FREQUENCY – kHz
INPUT FREQUENCY – kHz
Figure 24. Typical Bandwidth
Figure 21. Typical THD vs. Input Tone
REV. A
–13–
AD7470/AD7472
ANALOG
SUPPLY
+5V
+
+
10F
0.1F
47F
AV
DD
DV
DD
1nF
AGND
DGND
V
IN
AD7470/
AD7472
AD780
0.1F
V
DRIVE
+
V
OUT
1nF
10F
VREF
+
0.1F
10F
Figure 25. Decoupling Circuit
POWER SUPPLIES
GROUNDING AND LAYOUT
The analog and digital power supplies are independent and
separately pinned out to minimize coupling between analog and
digital sections within the device. To complement the excellent
noise performance of the AD7470/AD7472 it is imperative that
care be given to the PCB layout. Figure 25 shows a recom-
mended connection diagram for the AD7470/AD7472.
Separate power supplies for AVDD and DVDD are desirable but if
necessary DVDD may share its power connection to AVDD. The
digital supply (DVDD) must not exceed the analog supply (AVDD
)
by more than 0.3 V in normal operation.
MICROPROCESSOR INTERFACING
AD7470/AD7472 to ADSP-2185 Interface
All of the AD7470/AD7472 ground pins should be soldered
directly to a ground plane to minimize series inductance. The
AVDD, DVDD and VDRIVE pins should be decoupled to both the
analog and digital ground planes. The large value capacitors will
decouple low frequency noise to analog ground, the small value
capacitors will decouple high frequency noise to digital ground.
All digital circuitry power pins should be decoupled to the digi-
tal ground plane. The use of ground planes can physically sepa-
rate sensitive analog components from the noisy digital system.
The two ground planes should be joined in only one place and
should not overlap so as to minimize capacitive coupling be-
tween them. If the AD7470/AD7472 is in a system where
multiple devices require AGND to DGND connections, the
connection should still be made at one point only, a star ground
point, which should be established as close as possible to the
AD7470/AD7472.
Figure 26 shows a typical interface between the AD7470/AD7472
and the ADSP-2185. The ADSP-2185 processor can be used in
one of two memory modes, Full Memory Mode and Host Mode.
The Mode C pin determines in which mode the processor works.
The interface in Figure 26 is set up to have the processor work-
ing in Full Memory Mode, which allows full external addressing
capabilities.
When the AD7470/AD7472 has finished converting, the BUSY
line requests an interrupt through the IRQ2 pin. The IRQ2
interrupt has to be set up in the interrupt control register as
edge-sensitive. The DMS (Data Memory Select) pin latches in
the address of the A/D into the address decoder. The read op-
eration is thus started.
OPTIONAL
CONVST
Noise can be minimized by applying some simple rules to the
PCB layout: analog signals should be kept away from digital
signals; fast switching signals like clocks should be shielded with
digital ground to avoid radiating noise to other sections of the
board and clock signals should never be run near the analog
inputs; avoid running digital lines under the device as these will
couple noise onto the die; the power supply lines to the AD7470/
AD7472 should use as large a trace as possible to provide a low
impedance path and reduce the effects of glitches on the power
supply line; avoid crossover of digital and analog signals and
place traces that are on opposite sides of the board at right angles
to each other.
A0–A15
ADSP-2185*
ADDRESS BUS
AD7470/
AD7472*
ADDRESS
DECODER
CS
DMS
BUSY
IRQ2
RD
RD
100k⍀
MODE C
DB0–DB9
(DB11)
D0–D23
DATA BUS
Noise to the analog power line can be further reduced by use of
multiple decoupling capacitors as shown in Figure 25. Decou-
pling capacitors should be placed directly at the power inlet to
the PCB and also as close as possible to the power pins of the
AD7470/AD7472. The same decoupling method should be
used on other ICs on the PCB, with the capacitor leads as short
as possible to minimize lead inductance.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. Interfacing to the ADSP-2185
AD7470/AD7472 to ADSP-21065 Interface
Figure 27 shows a typical interface between the AD7470/AD7472
and the ADSP-21065L SHARC® processor. This interface is an
example of one of three DMA handshake modes. The MSX
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
–14–
AD7470/AD7472
control line is actually three memory select lines. Internal
ADDR25–24 are decoded into MS3-0, these lines are then asserted
as chip selects. The DMAR1 (DMA Request 1) is used in this
setup as the interrupt to signal end of conversion. The rest of
the interface is standard handshaking operation.
AD7470/AD7472 to PIC17C4x Interface
Figure 29 shows a typical parallel interface between the AD7470/
AD7472 and PIC17C42/43/44. The microcontroller sees the
A/D as another memory device with its own specific memory
address on the memory map. The CONVST signal can either be
controlled by the microcontroller or an external source. The
BUSY signal provides an interrupt request to the microcontroller
when a conversion ends. The INT pin on the PIC17C42/43/44
must be configured to be active on the negative edge. PORTC
and PORTD of the microcontroller are bidirectional and used
to address the AD7470/AD7472 and also to read in the 10-bit
(AD7470) or 12-bit (AD7472) data. The OE pin on the PIC
can be used to enable the output buffers on the AD7470/AD7472
and preform a read operation.
OPTIONAL
CONVST
ADDR –ADDR
23
ADDRESS BUS
0
AD7470/
AD7472*
ADDRESS
LATCH
MS
X
ADDRESS
BUS
ADSP-21065L*
ADDRESS
DECODER
CS
OPTIONAL
DMAR
BUSY
1
CONVST
RD
RD
PIC17C4x*
DB0–DB9
(DB11)
DB0–DB9
(DB11)
AD0–AD15
AD7470/
AD7472*
D0–D31
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
ALE
OE
RD
Figure 27. Interfacing to ADSP-21065L
INT
BUSY
AD7470/AD7472 to TMS320C25 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 28 shows an interface between the AD7470/AD7472
and the TMS320C25. The CONVST signal can be applied
from the TMS320C25 or from an external source. The BUSY
line interrupts the digital signal processor when conversion is
completed. The TMS320C25 does not have a separate RD
output to drive the AD7470/AD7472 RD input directly. This
has to be generated from the processor STRB and R/W outputs
with the addition of some glue logic. The RD signal is OR-gated
with the MSC signal to provide the WAIT state required in the
read cycle for correct interface timing. The following instruction
is used to read the conversion from the AD7470/AD7472:
Figure 29. Interfacing to the PIC17C4x
AD7470/AD7472 to 80C186 Interface
Figure 30 shows the AD7470/AD7472 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. (The AD7470/AD7472
occupies one of these I/O spaces.) Each data transfer consumes
two bus cycles, one cycle to fetch data and the other to store
data.
After the AD7470/AD7472 has finished conversion, the BUSY
line generates a DMA request to Channel 1 (DRQ1). As a result
of the interrupt, the processor performs a DMA READ opera-
tion which also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request will be serviced before the completion of the next con-
version. This configuration can be used with 6 MHz and 8 MHz
80C186 processors.
IN D,ADC
where D is Data Memory address and the ADC is the AD7470/
AD7472 address. The read operation must not be attempted
during conversion.
OPTIONAL
CONVST
A0–A15
ADDRESS BUS
OPTIONAL
AD7470/
AD7472*
AD0–AD15
TMS320C25*
ADDRESS/DATA BUS
A16–A19
CONVST
ADDRESS
DECODER
CS
IS
ADDRESS
ALE
LATCH
AD7470/
AD7472*
ADDRESS
BUS
BUSY
80C186*
STRB
ADDRESS
DECODER
RD
CS
R/W
READY
DRQ1
Q
R
S
BUSY
MSC
DB0–DB9
(DB11)
RD
RD
DB0–DB9
(DB11)
DATA BUS
DMD0–DMD15
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 30. Interfacing to the 80C186
Figure 28. Interfacing to the TMS320C25
REV. A
–15–
AD7470/AD7472
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead SOIC
(R-24)
0.6141 (15.60)
0.5985 (15.20)
24
1
13
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
؋
45؇ 8؇
0؇
0.0500
(1.27)
BSC
SEATING
PLANE
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
24-Lead TSSOP
(RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
12
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0256 (0.65) 0.0118 (0.30)
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
BSC
0.0075 (0.19)
–16–
REV. A
相关型号：
AD7470ARUZ-REEL
1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24, TSSOP-24
ROCHESTER
AD7470ARUZ-REEL7
1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24, TSSOP-24
ROCHESTER
©2020 ICPDF网 联系我们和版权申明