AD7475ARMZ-REEL7 [ADI]
1 MSPS, 12-Bit A/D Converter in MSOP-8 or SOIC-8;
| 型号： | AD7475ARMZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 1 MSPS, 12-Bit A/D Converter in MSOP-8 or SOIC-8 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 MSPS,12-Bit ADCs
Data Sheet
AD7475/AD7495
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
DD
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
V
IN
REF IN
4.5 mW max at 1 MSPS with 3 V supplies
10.5 mW max at 1 MSPS with 5 V supplies
Wide input bandwidth: 68 dB SNR at 300 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
SCLK
SDATA
CS
CONTROL
LOGIC
V
DRIVE
AD7475
High speed serial interface
SPI-/QSPI™-/MICROWIRE-/DSP-compatible
On-board reference: 2.5 V (AD7495 only)
Standby mode: 1 μA max
GND
V
DD
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
8-lead MSOP and SOIC packages
T/H
V
IN
APPLICATIONS
REF OUT
BUF
2.5V
Battery-powered systems
Personal digital assistants
Medical instruments
SCLK
SDATA
CS
CONTROL
LOGIC
REFERENCE
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
V
DRIVE
AD7495
GND
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7475/AD74951 are 12-bit, high speed, low power,
successive-approximation ADCs that operate from a single
2.7 V to 5.25 V power supply with throughput rates up to 1 MSPS.
They contain a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies above 1 MHz.
1. The AD7475 offers 1 MSPS throughput rates with 4.5 mW
power consumption.
2. Single-supply operation with VDRIVE function. The
AD7475/AD7495 operate from a single 2.7 V to 5.25 V
supply. The VDRIVE function allows the serial interface to
connect directly to either 3 V or 5 V processor systems
The conversion process and data acquisition are controlled
using
and the serial clock, allowing the devices to interface
CS
with microprocessors or DSPs. The input signal is sampled on
the falling edge of and conversion is initiated at this point.
independent of VDD
.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The devices also feature shutdown modes
to maximize power efficiency at lower throughput rates.
This allows the average power consumption to reduce while
not converting. Power consumption is 1 μA when in full
shutdown.
CS
The conversion time is determined by the SCLK frequency.
There are no pipeline delays associated with the device.
The AD7475/AD7495 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
With 3 V supplies and a 1 MSPS throughput rate, the AD7475
consumes just 1.5 mA, while the AD7495 consumes 2 mA. With
5 V supplies and 1 MSPS, the current consumption is 2.1 mA
for the AD7475 and 2.6 mA for the AD7495.
4. No pipeline delay. The devices feature a standard successive
approximation ADC with accurate control of the sampling
instant via a
input and once-off conversion control.
The analog input range for the devices is 0 V to REF IN. The
2.5 V reference for the AD7475 is applied externally to the REF IN
pin, while the AD7495 has an on-board 2.5 V reference.
CS
1Protected by U.S. Patent No. 6,681,332
Rev. C
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AD7475/AD7495
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Operation.................................................................. 13
ADC Transfer Function............................................................. 13
Typical Connection Diagram ................................................... 14
Operating Modes............................................................................ 16
Normal Mode.............................................................................. 16
Partial Power-Down Mode ....................................................... 16
Full Power-Down Mode ............................................................ 17
Power vs. Throughput Rate....................................................... 19
Serial Interface ................................................................................ 20
Microprocessor Interfacing........................................................... 21
AD7475/AD7495 to TMS320C5X/C54X................................. 21
AD7475/AD7495 to ADSP-21xx.............................................. 21
AD7475/AD7495 to DSP56XXX ............................................... 22
AD7475/AD7495 to MC68HC16............................................. 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
AD7475 Specifications..................................................................... 3
AD7495 Specifications..................................................................... 5
Timing Specifications....................................................................... 7
Timing Example 1 ........................................................................ 8
Timing Example 2 ........................................................................ 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 13
REVISION HISTORY
7/15—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 24
5/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Added Patent Information............................................................... 1
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide .......................................................... 24
Rev. C | Page 2 of 24
Data Sheet
AD7475/AD7495
AD7475 SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion
Ratio (SINAD)
68
68
dB min
fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
(SFDR)
−75
−76
−75
−76
dB max
dB max
fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS
fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
−78
−78
10
−78
−78
10
dB typ
dB typ
ns typ
Aperture Jitter
50
50
ps typ
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY
8.3
1.3
8.3
1.3
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
Resolution
12
12
Bits
Integral Nonlinearity
1.5
0.5
+1.5/−0.9
1
0.5
+1.5/−0.9
LSB max
LSB typ
LSB max
@ 5 V (typ @ 3 V)
@ 25°C
@ 5 V guaranteed no missed codes to
12 bits (typ @ 3 V)
Differential Nonlinearity
0.5
8
3
0.5
8
3
LSB typ
LSB max
LSB max
@ 25°C
Typically 2.5 LSB
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REF IN Input Voltage Range
DC Leakage Current
Input Capacitance
LOGIC INPUTS
0 to REF IN
1
20
0 to REF IN
1
20
V
µA max
pF typ
2.5
1
20
2.5
1
20
V
1% for specified performance
µA max
pF typ
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
VDRIVE − 1
V min
0.4
1
10
0.4
1
10
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
2
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output
Capacitance2
VDRIVE − 0.2
0.4
10
10
V min
ISOURCE = 200 µA; VDRIVE = 2.7 V to 5.25 V
ISINK = 200 µA
0.4
10
10
V max
µA max
pF max
Output Coding
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
800
800
300
325
1
ns max
ns max
ns max
MSPS max
16 SCLK cycles with SCLK at 20 MHz
Sine wave input
Full-scale step input
300
325
1
Throughput Rate
See the Serial Interface section
Rev. C | Page 3 of 24
AD7475/AD7495
Data Sheet
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
3
IDD
Digital inputs = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS
VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS
fSAMPLE = 100 kSPS
Normal Mode (Static)
Normal Mode (Operational)
750
2.1
1.5
450
100
1
750
2.1
1.5
450
100
1
µA typ
mA max
mA max
µA typ
µA max
µA max
Partial Power-Down Mode
Partial Power-Down Mode
Full Power-Down Mode
Power Dissipation3
Static
SCLK on or off
Normal Mode (Operational)
10.5
4.5
500
300
5
10.5
4.5
500
300
5
mW max
mW max
µW max
µW max
µW max
µW max
VDD = 5 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 5 V
VDD = 3 V
VDD = 5 V
Partial Power-Down (Static)
Full Power-Down
3
3
VDD = 3 V
1 Temperature ranges for A, B versions: −40°C to +85°C.
2 Guaranteed by initial characterization.
3 See the Power vs. Throughput Rate section.
Rev. C | Page 4 of 24
Data Sheet
AD7475/AD7495
AD7495 SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD) 68
68
−75
−76
dB min
dB max
dB max
fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS
fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS
fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS
Total Harmonic Distortion (THD)
−75
Peak Harmonic or Spurious Noise
(SFDR)
−76
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
−78
−78
10
−78
−78
10
dB typ
dB typ
ns typ
Aperture Jitter
50
50
ps typ
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY
8.3
1.3
8.3
1.3
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
Resolution
12
12
Bits
Integral Nonlinearity
1.5
0.5
+1.5/−0.9
1
0.5
+1.5/−0.9
LSB max
LSB typ
LSB max
@ 5 V (typ @ 3 V)
@ 25°C
@ 5 V guaranteed no missed codes to
12 bits (typ @ 3 V)
Differential Nonlinearity
0.6
8
7
0.6
8
7
LSB typ
LSB max
LSB max
@ 25°C
Typically 2.5 LSB
Typically 2.5 LSB
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE OUTPUT
REF OUT Output Voltage
REF OUT Impedance
REF OUT Temperature Coefficient
LOGIC INPUTS
0 to 2.5
1
20
0 to 2.5
1
20
V
µA max
pF typ
2.4625/2.5375 2.4625/2.5375 V min/max
10
50
10
50
Ω typ
ppm/°C typ
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
VDRIVE − 1
0.4
1
VDRIVE − 1
0.4
1
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
2
Input Capacitance, CIN
10
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance2
Output Coding
VDRIVE − 0.2
0.4
10
10
V min
ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V
ISINK = 200 µA
0.4
10
10
V max
µA max
pF max
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
800
300
325
1
800
300
325
1
ns max
ns max
ns max
MSPS max
16 SCLK cycles with SCLK @ 20 MHz
Sine wave input
Full-scale step input
Throughput Rate
See the Serial Interface section
Rev. C | Page 5 of 24
AD7475/AD7495
Data Sheet
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
VDRIVE
2.7/5.25
2.7/5.25
2.7/5.25
2.7/5.25
V min/max
V min/max
IDD
Digital inputs = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS
VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS
fSAMPLE = 100 kSPS
Normal Mode (Static)
Normal Mode (Operational)
1
2.6
2
650
230
1
1
2.6
2
650
230
1
mA typ
mA max
mA max
µA typ
µA max
µA max
Partial Power-Down Mode
Partial Power-Down Mode
Full Power-Down Mode
Power Dissipation3
Static
Static, SCLK on or off
Normal Mode (Operational)
13
6
1.15
690
5
13
6
1.15
690
5
mW max
mW max
mW max
µW max
µW max
µW max
VDD = 5 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 5 V
VDD = 3 V
VDD = 5 V
Partial Power-Down (Static)
Full Power-Down
3
3
VDD = 3 V
1 Temperature ranges for A, B versions: −40°C to +85°C.
2 Guaranteed by initial characterization.
3 See the Power vs. Throughput Rate section.
Rev. C | Page 6 of 24
Data Sheet
AD7475/AD7495
TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
2
fSCLK
10
20
kHz min
MHz max
tCONVERT
16 × tSCLK
800
100
10
tSCLK = 1/fSCLK
fSCLK = 20 MHz
Minimum quiet time required between conversions
CS to SCLK setup time
ns max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
µs max
µs max
tQUIET
t2
3
t3
22
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
SCLK falling edge to SDATA high impedance
CS rising edge to SDATA high impedance
Power-up time from full power-down (AD7475)
Power-up time from full power-down (AD7495)
3
t4
40
t5
t6
t7
0.4 tSCLK
0.4 tSCLK
10
10
45
4
t8
4
t9
20
tPOWER-UP
20
650
1 Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are
the true bus relinquish times of the device and are independent of the bus loading.
Rev. C | Page 7 of 24
AD7475/AD7495
Data Sheet
TIMING EXAMPLE 2
TIMING EXAMPLE 1
With fSCLK = 5 MHz and a throughput of 315 KSPS, the cycle
time is t2 + 12.5(1/fSCLK) + tACQ = 3.174 µs. With t2 = 10 ns min,
With fSCLK = 20 MHz and a throughput of 1 MSPS, the cycle
time is t2 + 12.5(1/fSCLK) + tACQ = 1 µs. With t2 = 10 ns min, tACQ
is 365 ns. The 365 ns satisfies the requirement of 300 ns for tACQ
In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 45 ns.
This allows a value of 195 ns for tQUIET, satisfying the minimum
requirement of 100 ns.
t
t
ACQ is 664 ns. The 664 ns satisfies the requirement of 300 ns for
ACQ. In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where
.
t8 = 45 ns. This allows a value of 119 ns for tQUIET, satisfying the
minimum requirement of 100 ns. As in this example and with
other slower clock values, the signal may be acquired before the
conversion is complete, but it is still necessary to leave 100 ns
minimum tQUIET between conversions. In Example 2, the signal
is acquired at approximately Point C in Figure 3.
CS
tCONVERT
t6
t2
B
4
3
5
1
2
13
15
t8
DB0
16
14
t5
SCLK
t7
DB10
tQUIET
t4
DB11
t3
0
0
0
0
SDATA
DB2
DB1
THREE-STATE
THREE-STATE
FOUR LEADING ZEROS
Figure 2. Serial Interface Timing Diagram
CS
tCONVERT
t6
t2
B
C
3
5
4
1
2
13
14
t5
15
t8
16
SCLK
tQUIET
45ns
tACQUISITION
12.5 (1/f
)
SCLK
10ns
1/THROUGHPUT
Figure 3. Serial Interface Timing Example
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
Figure 4. Load Circuit for Digital Output Timing Specifications
Rev. C | Page 8 of 24
Data Sheet
AD7475/AD7495
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4.
Parameters
Ratings
VDD to GND
−0.3 V to +7 V
VDRIVE to GND
−0.3 V to +7 V
Analog Input Voltage to GND
Digital Input Voltage to GND
VDRIVE to VDD
Digital Output Voltage to GND
REF IN to GND
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDD + 0.3 V
10 mA
ESD CAUTION
Input Current to Any Pin Except
Supplies1
Operating Temperature Range
Commercial (A, B Version)
Storage Temperature Range
Junction Temperature
−40°C to +85°C
−65°C to +150°C
150°C
SOIC, MSOP Package, Power Dissipation
θJA Thermal Impedance
450 mW
157°C/W (SOIC)
205.9°C/W (MSOP)
56°C/W (SOIC)
43.74°C/W (MSOP)
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
ESD
215°C
220°C
4 kV
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. C | Page 9 of 24
AD7475/AD7495
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
8
7
6
5
REF OUT
1
2
3
4
8
7
6
5
V
DD
REF IN
V
DD
AD7495
TOP VIEW
(Not to Scale)
AD7475
TOP VIEW
(Not to Scale)
V
V
CS
V
CS
V
IN
IN
GND
GND
DRIVE
DRIVE
SCLK
SDATA
SCLK
SDATA
Figure 5. AD7475 SOIC/MSOP Pin Configuration
Figure 6. AD7495 SOIC/MSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1 (AD7475)
REF IN
Reference Input for the AD7475. Apply an external reference to this input. The voltage range for the external
reference is 2.5 V 1% for specified performance. Place a capacitor of a least 0.1 µF on the REF IN pin.
1 (AD7495)
REF OUT
Reference Output for the AD7495. A minimum 100 nF capacitance is required from this pin to GND. The
internal reference can be taken from this pin, but buffering is required before it is applied elsewhere in a system.
2
3
VIN
GND
Analog Input. Single-ended analog input channel. The input range is 0 to REF IN.
Analog Ground. Ground reference point for all circuitry on the AD7475/AD7495. Refer all analog input signals
and any external reference signal to this GND voltage.
4
5
SCLK
Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the device. This clock input is
also used as the clock source for the AD7475/AD7495 conversion process.
Data Out, Logic Output. The conversion result from the AD7475/AD7495 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four
leading zeros followed by the 12 bits of conversion data, which is provided MSB first.
SDATA
6
7
8
VDRIVE
CS
Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage for the serial
interface of the AD7475/AD7495.
Chip Select, Active Low Logic Input. This input provides the dual function of initiating conversions on the
AD7475/AD7495 and frames the serial data transfer.
VDD
Power Supply Input. The VDD range for the AD7475/AD7495 is from 2.7 V to 5.25 V.
Rev. C | Page 10 of 24
Data Sheet
AD7475/AD7495
TERMINOLOGY
Integral Nonlinearity
Total Harmonic Distortion (THD)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, a point ½ LSB below the
first code transition, and full scale, a point ½ LSB above the last
code transition.
The ratio of the rms sum of harmonics to the fundamental. For
the AD7475/AD7495, THD is defined as
2
2
2
2
2
V2 + V3 +V4 +V5 +V6
THD dB = 20 log
( )
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Peak Harmonic or Spurious Noise
Offset Error
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this specification
is determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
This is the deviation of the last code transition (111. . . 110) to
(111. . . 111) from the ideal (that is, VREF − 1.5 LSB) after the
offset error has been adjusted out.
Intermodulation Distortion
Track-and-Hold Acquisition Time
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products at
sum and difference frequencies of mfa nfb where m, n = 0, 1,
2, 3, etc. Intermodulation distortion terms are those for which
neither m nor n is equal to zero. For example, the second-order
terms include (fa + fb) and (fa − fb), while the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
The track-and-hold amplifier returns into track mode on the
13th SCLK rising edge (see the Serial Interface section). The
track-and-hold acquisition time is the minimum time required
for the track-and-hold amplifier to remain in track mode for its
output to reach and settle to within 0.5 LSB of the applied input
signal, given a step change to the input signal.
Signal-to-Noise and Distortion Ratio (SINAD)
The AD7475/AD7495 are tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. Like THD, intermodulation distortion is calculated
as the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals, expressed in dBs.
The measured ratio of signal-to-noise and distortion at the
output of the analog-to-digital converter (ADC). The signal is
the rms amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent on the number of
quantization levels in the digitization process; the more levels,
the smaller the quantization noise. The theoretical SINAD ratio
for an ideal N-bit converter with a sine wave input is given by
Signal to
Noise + Distortion
=
6.02 N + 1.76 dB
For a 12-bit converter, the SINAD is 74 dB.
Rev. C | Page 11 of 24
AD7475/AD7495
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7 shows a typical FFT plot for the AD7475 at a 1 MHz sample rate and a 100 kHz input frequency. Figure 8 shows a typical FFT
plot for the AD7495 at a 1 MHz sample rate and a 100 kHz input frequency. Figure 9 shows the SINAD performance vs. input frequency
for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz.
71.0
8192 POINT FFT
f
f
= 1MSPS
SAMPLE
= 100kHz
–15
–35
IN
V
= V
= 4.75V
70.5
70.0
69.5
69.0
68.5
DD
DRIVE
SINAD = 70.46dB
THD = –87.7dB
SFDR = –89.5dB
V
= V = 3.60V
DRIVE
DD
–55
–75
V
= V
= 2.70V
DD
DRIVE
V
= V
DRIVE
= 5.25V
DD
–95
–115
0
50
100 150
200 250 300
350 400 450 500
10
100
INPUT FREQUENCY (kHz)
1000
FREQUENCY (kHz)
Figure 7. AD7475 Dynamic Performance
Figure 9. AD7495 SINAD vs. Input Frequency at 1 MSPS
8192 POINT FFT
f
= 1MSPS
SAMPLE
= 100kHz
–15
–35
f
IN
SINAD = 69.95dB
THD = –89.2dB
SFDR = –91.2dB
–55
–75
–95
–115
0
50
100 150
200 250 300
350 400 450 500
FREQUENCY (kHz)
Figure 8. AD7495 Dynamic Performance
Rev. C | Page 12 of 24
Data Sheet
AD7475/AD7495
THEORY OF OPERATION
The AD7475/AD7495 are fast, micropower, 12-bit, single-
supply analog-to-digital converters (ADCs). The devices can be
operated from a 2.7 V to 5.25 V supply. When operated from
either a 5 V supply or a 3 V supply, the AD7475/AD7495 are
capable of throughput rates of 1 MSPS when provided with a
20 MHz clock.
When the ADC starts a conversion (see Figure 11), SW2 opens
and SW1 moves to Position B causing the comparator to become
unbalanced. The control logic and the capacitive DAC are used
to add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced condition.
When the comparator is rebalanced, the conversion is complete.
The control logic generates the ADC output code.
The AD7475/AD7495 ADCs have an on-chip track-and-hold
with a serial interface housed in either an 8-lead SOIC or MSOP
package, features that offer the user considerable space-saving
advantages over alternative solutions. The AD7495 also has an
on-chip 2.5 V reference. The serial clock input accesses data from
the device but also provides the clock source for the successive-
approximation ADC. The analog input range is 0 V to REF IN
for the AD7475 and 0 V to REF OUT for the AD7495.
CAPACITIVE
DAC
4k
A
V
IN
SW1
B
CONTROL LOGIC
SW2
COMPARATOR
AGND
Figure 11. ADC Conversion Phase
The AD7475/AD7495 also feature power-down options to allow
power saving between conversions. The power-down feature is
implemented across the standard serial interface, as described
in the Operating Modes section.
ADC TRANSFER FUNCTION
The output coding of the AD7475/AD7495 is straight binary.
The designed code transitions occur midway between successive
LSB integer values (that is, 1/2 LSB and 3/2 LSBs). The LSB size
is = VREF/4096. The ideal transfer characteristic for the
AD7475/AD7495 is shown in Figure 12.
CONVERTER OPERATION
The AD7475/AD7495 are 12-bit, successive approximation
analog-to-digital converters based around a capacitive DAC.
The AD7475/AD7495 can convert analog input signals in the
range 0 V to 2.5 V. Figure 10 and Figure 12 show simplified
schematics of the ADC. The ADC comprises control logic, SAR,
and a capacitive DAC, which are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring the
comparator back into a balanced condition. Figure 10 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on VIN.
111...111
111...110
111...000
1LSB = V
/4096
REF
011...111
000...010
000...001
000...000
0.5LSB
0V
V
–1.5LSB
REF
ANALOG INPUT
CAPACITIVE
DAC
Figure 12. AD7475/AD7495 Transfer Characteristic
4k
A
V
IN
B
CONTROL LOGIC
SW1
SW2
COMPARATOR
AGND
Figure 10. ADC Acquisition Phase
Rev. C | Page 13 of 24
AD7475/AD7495
Data Sheet
Analog Input
TYPICAL CONNECTION DIAGRAM
Figure 14 shows an equivalent circuit of the analog input
structure of the AD7475/AD7495. The D1 and D2 diodes
provide ESD protection for the analog inputs. Ensure that the
analog input signal never exceeds the supply rails by more than
200 mV. This causes these diodes to become forward-biased
and start conducting current into the substrate. The maximum
current these diodes can conduct without causing irreversible
damage to the device is 20 mA. The capacitor C1 in Figure 14 is
typically about 4 pF and is attributed to pin capacitance. The
resistor R1 is a lumped component made up of the on resistance
of a switch. This resistor is typically about 100 Ω. The capacitor
C2 is the ADC sampling capacitor and has a capacitance of 16
pF, typically. For ac applications, it is recommended to remove
high frequency components from the analog input signal using
an RC low-pass filter on the relevant analog input pin. In
applications where harmonic distortion and signal-to-noise
ratio are critical, drive the analog input from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.
Figure 13 and Figure 15 show typical connection diagrams for
the AD7475 and AD7495, respectively. In both setups, the GND
pin is connected to the analog ground plane of the system. In
Figure 13, REF IN is connected to a decoupled 2.5 V supply
from a reference source, the AD780, to provide an analog input
range of 0 V to 2.5 V. Although the AD7475 connects to a VDD
of 5 V, the serial interface connects to a 3 V microprocessor. The
V
DRIVE pin of the AD7475 connects to the same 3 V supply of
the microprocessor to allow a 3 V logic interface (see the Digital
Inputs section.) In Figure 15, the REF OUT pin of the AD7495
is connected to a buffer and then applied to a level-shifting
circuit used on the analog input to allow a bipolar signal to be
applied to the AD7495. A minimum 100 nF capacitance is
required on the REF OUT pin to GND. The conversion result
from both ADCs is output in a 16-bit word with four leading
zeros followed by the MSB of the 12-bit result. For applications
where power consumption is of concern, use the power-down
modes between conversions or bursts of several conversions to
improve power performance. See the Operating Modes section
for more information.
5V
SERIAL
SUPPLY
INTERFACE
0.1µ
F
10µF
V
DD
C2
16pF
D1
D2
R1
V
DD
V
IN
SCLK
C1
4pF
0V TO
2.5V
INPUT
V
SDATA
IN
AD7475
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
µ
C/µP
CS
GND
V
DRIVE
Figure 14. Equivalent Analog Input Circuit
REF IN
0.1µ
F
10µF
2.5V
AD780
0.1
(MIN)
µF
3V
SUPPLY
Figure 13. AD7475 Typical Connection Diagram
5V
SUPPLY
SERIAL
INTERFACE
0.1µF
10µF
V
V
0V TO
2.5V
INPUT
DD
R
R
SCLK
SDATA
CS
0V
V
V
IN
3R
AD7495
µC/µP
R
GND
V
DRIVE
REF OUT
0.1µF
10µF
0.1µF
(MIN)
3V
SUPPLY
Figure 15. AD7495 Typical Connection Diagram
Rev. C | Page 14 of 24
Data Sheet
AD7475/AD7495
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades.
Figure 16 shows a graph of the total harmonic distortion vs.
source impedance for various analog input frequencies.
–10
If
or SCLK are applied before VDD, there is no risk of latch-up
CS
as there would be on the analog inputs if a signal greater than
0.3 V were applied prior to VDD.
VDRIVE
The AD7475/AD7495 also has the VDRIVE feature. This feature
controls the voltage at which the serial interface operates. VDRIVE
allows the ADC to easily interface to both 3 V and 5 V processors.
For example, if the AD7475/AD7495 were operated with a VDD
of 5 V, the V DRIVE pin could be powered from a 3 V supply. The
AD7475/AD7495 have better dynamic performance with a VDD
of 5 V, while still being able to interface to 3 V digital devices.
Ensure VDRIVE does not exceed VDD by more than 0.3 V. (See the
Absolute Maximum Ratings section.)
–20
–30
f
= 10kHz
IN
–40
–50
–60
f
= 500kHz
IN
f
= 200kHz
IN
Reference Section
Use an external reference source to supply the 2.5 V reference to
the AD7475. Errors in the reference source result in gain errors
in the AD7475 transfer function and add the specified full-scale
errors on the device. The AD7475 voltage reference input, REF IN,
has a dynamic input impedance. A small dynamic current is
required to charge the capacitors in the capacitive DAC during
the bit trials. This current is typically 50 µA for a 2.5 V reference.
Place a capacitor of at least 0.1 µF on the REF IN pin. Suitable
reference sources for the AD7475 are the AD780, AD680,
AD1582, ADR391, ADR381, ADR431, and ADR03.
–70
–80
–90
f
= 100kHz
IN
1
10
100
1000
10000
SOURCE IMPEDANCE (
Ω
)
Figure 16. THD vs. Source Impedance for Various Analog Input Frequencies
Figure 17 shows a graph of total harmonic distortion vs. analog
input frequency for various supply voltages while sampling at
1 MSPS with an SCLK of 20 MHz.
–75
The AD7495 contains an on-chip 2.5 V reference. As shown in
Figure 18, the voltage that appears at the REF OUT pin internally
buffers before applied to the ADC; the output impedance of this
buffer is typically 10 Ω. The reference is capable of sourcing up to
2 mA. Decouple the REF OUT pin to AGND using a 100 nF or
greater capacitor.
V
= V = 5.25V
DRIVE
–77
–79
–81
–83
–85
–87
–89
–91
–93
–95
DD
V
= V = 2.70V
DRIVE
DD
V
= V = 3.60V
DRIVE
DD
If the 2.5 V internal reference is used to drive another device
that is capable of glitching the reference at critical times, then
the reference has to be buffered before driving the device. To
ensure optimum performance of the AD7495, it is recommended
that the internal reference not be over driven. If an ADC with
external reference capability is required, use the AD7475.
V
= V = 4.75V
DRIVE
DD
10
100
INPUT FREQUENCY (kHz)
1000
V
Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages
REF OUT
25Ω
Digital Inputs
40kΩ
The digital inputs applied to the AD7475/AD7495 are not limited
by the maximum ratings, which limit the analog inputs. Instead,
the digital inputs applied can go to 7 V and are not restricted by
the VDD + 0.3 V limit as on the analog inputs. Another advantage
160kΩ
Figure 18. AD7495 Reference Circuit
of SCLK and
not being restricted by the VDD + 0.3 V limit is
CS
that power supply sequencing issues are avoided.
Rev. C | Page 15 of 24
AD7475/AD7495
Data Sheet
OPERATING MODES
The AD7475/AD7495 operating mode is selected by controlling
Sixteen serial clock cycles are required to complete the conversion
the logic state of the
signal during a conversion. There are
and access the conversion result.
may idle high until the next
CS
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. The point at which
CS
conversion or may idle low until sometime prior to the next
conversion (effectively idling low).
CS
CS
is pulled high after the conversion has been initiated determines
which power-down mode, if any, the device enters. Similarly, if
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
already in a power-down mode,
can control whether the
CS
tQUIET, has elapsed, by bringing
low again.
CS
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing application requirements.
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and then the ADC is
powered down for a relatively long duration between these
bursts of several conversions. When the AD7475 is in partial
power-down, all analog circuitry is powered down except for
the bias current generator; and, in the case of the AD7495, all
analog circuitry is powered down except for the on-chip
reference and reference buffer.
NORMAL MODE
This mode is intended for fastest throughput rate performance,
because the user does not have to worry about any power-up
times with the AD7475/AD7495 remaining fully powered all
the time. Figure 19 shows the general diagram of the
AD7475/AD7495 operating in this mode.
The conversion is initiated on the falling edge of , as described in
CS
the Serial Interface section. To ensure the device remains fully
To enter partial power-down, interrupt the conversion process
by bringing
high anywhere after the second falling edge of
CS
SCLK and before the 10th falling edge of SCLK, as shown in
Figure 20. Once has been brought high in this window of
powered up at all times, must remain low until at least 10 SCLK
CS
falling edges have elapsed after the falling edge of . If
CS CS
is
CS
SCLKs, the device enters partial power-down, the conversion
that was initiated by the falling edge of is terminated, and
brought high any time after the 10th SCLK falling edge, but
before the 16th SCLK falling edge, the device remains powered
up but the conversion is terminated and SDATA goes back into
three-state.
CS
is brought high before
SDATA goes back into three-state. If
CS
the second SCLK falling edge, the device remains in normal mode
and does not power down. This avoids accidental power-down
due to glitches on the
line.
CS
CS
1
10
16
SCLK
SDATA
FOUR LEADING ZEROS + CONVERSION RESULT
Figure 19. Normal Mode
CS
1
2
10
16
SCLK
Figure 20. Entering Partial Power-Down Mode
Rev. C | Page 16 of 24
Data Sheet
AD7475/AD7495
To exit this operating mode and power up the AD7475/AD7495
again, a dummy conversion is performed. On the falling edge of
When powering up from the power-down mode with a dummy
cycle, as in Figure 21, the track-and-hold that was in hold mode
while the device was powered down returns to track mode after
the first SCLK edge the device receives after the falling edge of
, the device begins to power up and continues to power up as
CS
long as is held low until after the falling edge of the 10th SCLK.
CS
. This is shown as Point A in Figure 21. Although at any SCLK
CS
The device is fully powered up once 16 SCLKs have elapsed,
and valid data results from the next conversion, as shown in
frequency one dummy cycle is sufficient to power up the device
and acquire VIN, it does not necessarily mean that a full dummy
cycle of 16 SCLKs must always elapse to power up the device
and fully acquire VIN; 1 μs is sufficient to power up the device
and acquire the input signal. If, for example, a 5 MHz SCLK
frequency were applied to the ADC, the cycle time would be
3.2 μs. In one dummy cycle, 3.2 μs, the device would be powered up
and VIN fully acquired. However, after 1 μs with a 5 MHz SCLK,
only 5 SCLK cycles would have elapsed. At this stage, the ADC
would be fully powered up and the signal acquired. In this case,
Figure 21. If
is brought high before the second falling edge
CS
of SCLK, the AD7475/AD7495 go back into partial power-down
again. This avoids accidental power-up due to glitches on the
CS
line; although the device may begin to power up on the falling
edge of , it powers down again on the rising edge of . If in
CS
CS
partial power-down and
is brought high between the second
CS
and tenth falling edges of SCLK, the device enters full power-
down mode.
the
can be brought high after the 10th SCLK falling edge and
Power-Up Time
CS
brought low again after a time, tQUIET, to initiate the conversion.
The power-up time of the AD7475/AD7495 from partial power-
down is typically 1 μs, which means that with any frequency of
SCLK up to 20 MHz, one dummy cycle is sufficient to allow the
device to power up from partial power-down. Once the dummy
cycle is complete, the ADC is fully powered up and the input
signal is acquired properly. The quiet time, tQUIET, must still be
allowed from the point where the bus goes back into three-state
FULL POWER-DOWN MODE
Full power-down mode is intended for use in applications
where slower throughput rates are required than that in the
partial power-down mode, because powering up from a full
power-down would not be complete in just one dummy
conversion. This mode is more suited to applications where a
series of conversions performed at a relatively high throughput
rate are followed by a long period of inactivity and therefore
power down. When the AD7475/AD7495 are in full power-
down, all analog circuitry is powered down.
after the dummy conversion to the next falling edge of . When
CS
running at a 1 MSPS throughput rate, the AD7475/AD7495 power
up and acquire a signal within 0.5 LSB in one dummy cycle, 1 μs.
THE PART BEGINS
TO POWER UP
THE PART IS FULLY
POWERED UP
CS
16
16
A1
1
10
SCLK
SDATA
INVALID DATA
VALID DATA
Figure 21. Exiting Partial Power-Down Mode
THE PART ENTERS
PARTIAL POWER-DOWN
THE PART BEGINS
TO POWER UP
THE PART ENTERS
FULL POWER-DOWN
CS
16
16
1
2
1
2
10
10
SCLK
THREE-STATE
THREE-STATE
SDATA
INVALID DATA
INVALID DATA
Figure 22. Entering Full Power-Down Mode
Rev. C | Page 17 of 24
AD7475/AD7495
Data Sheet
Full power-down is entered in a way similar to partial power-
down, except the timing sequence shown in Figure 20 must be
executed twice. The conversion process must be interrupted in a
The first dummy cycle must hold low until after the 10th SCLK
CS
falling edge, as shown in Figure 19. In the second cycle, bring
high before the 10th SCLK edge, but after the second SCLK
CS
similar fashion by bringing
high anywhere after the second
CS
falling edge, as shown in Figure 20. Alternatively, if the intent is to
place the device in full power-down mode when the supplies
have been applied, then three dummy cycles must be initiated.
falling edge of SCLK and before the 10th falling edge of SCLK.
The device enters partial power-down at this point. To reach full
power-down, interrupt the next conversion cycle in the same
The first dummy cycle must hold low until after the 10th SCLK
CS
way, as shown in Figure 22. Once
has been brought high in
CS
edge, as shown in Figure 19; the second and third dummy cycle
place the device in full power-down, as shown in Figure 22. (See
the Operating Modes section.) Once supplies are applied to the
AD7475, allow enough time for the external reference to power
up and charge the reference capacitor to its final value. For the
AD7495, allow enough time for the internal reference buffer to
charge the reference capacitor. Then, to place the AD7475/AD7495
in normal mode, initiate a dummy cycle, 1 μs. If the first valid
conversion is performed directly after the dummy conversion,
allow adequate acquisition time. As mentioned earlier, when
powering up from the power-down mode, the device returns to
track upon the first SCLK edge applied after the falling edge of
this window of SCLKs, then the device powers down completely.
Note that it is not necessary to complete the 16 SCLKs once
has been brought high to enter a power-down mode.
CS
To exit full power-down, and power up the AD7475/AD7495
again, a dummy conversion is performed as when powering up
from partial power-down. On the falling edge of , the device
CS
begins to power up and continues to power up as long as
is
CS
held low until after the falling edge of the 10th SCLK. The power-up
time is longer than one dummy conversion cycle however, and
this time, tPOWER-UP, must elapse before a conversion can be initiated,
as shown in Figure 23. See the Timing Specifications section for
more information.
. However, when the ADC powers up initially after supplies
CS
are applied, the track-and-hold is already in track. This means
(assuming one has the facility to monitor the ADC supply current)
if the ADC powers up in the desired mode of operation, and a
dummy cycle is not required to change mode, then neither is a
dummy cycle required to place the track-and-hold into track. If
no current monitoring facility is available, perform the relevant
dummy cycle or cycles to ensure the device is in the required mode.
When power supplies are first applied to the AD7475/AD7495,
the ADC may power up in either of the power-down modes or
normal mode. Because of this, it is best to allow a dummy cycle
to elapse to ensure the device is fully powered up before attempting
a valid conversion. Likewise, if the intent is to keep the device in
partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated.
THE PART IS FULLY
POWERED UP
THE PART BEGINS
TO POWER UP
tPOWER-UP
CS
16
16
1
1
10
SCLK
SDATA
INVALID DATA
VALID DATA
Figure 23. Exiting Full Power-Down Mode
Rev. C | Page 18 of 24
Data Sheet
AD7475/AD7495
The AD7495 dissipates 6 mW for 2 μs during each conversion
cycle and 0.69 mW for the remaining 8 μs where the device is in
partial power-down. With a throughput rate of 100 kSPS, the
average power dissipated during each conversion cycle is (2/10) ×
(6 mW) + (8/10) × (0.69 mW) = 1.752 mW. Figure 24 shows the
power vs. throughput rate when using partial power-down mode
between conversions with both 5 V and 3 V supplies for both the
AD7475 and AD7495. For the AD7475, partial power-down
current is lower than that of the AD7495.
POWER VS. THROUGHPUT RATE
By using the partial power-down mode on the AD7475/AD7495
when not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 24 shows how, as the
throughput rate is reduced, the device remains in its partial power-
down state longer and the average power consumption over
time drops accordingly.
100
AD7495 5V
SCLK = 20MHz
Full power-down mode is intended for use in applications with
slower throughput rates than required for partial power-down
mode. It is necessary to leave 650 μs for the AD7495 to be fully
powered up from full power-down before initiating a conversion.
Current consumptions between conversions is typically less
than 1 μA.
AD7475 5V
SCLK = 20MHz
10
1
AD7495 3V
SCLK = 20MHz
AD7475 3V
SCLK = 20MHz
0.1
Figure 25 shows a typical graph of current vs. throughput for
the AD7495 while operating in different modes. At slower
throughput rates, for example, 10 SPS to 1 kSPS, the AD7495
was operated in full power-down mode. As the throughput rate
increased, up to 100 kSPS, the AD7495 was operated in partial
power-down mode, with the device being powered down between
conversions. With throughput rates from 100 kSPS to 1 MSPS,
the device operated in normal mode, remaining fully powered
up at all times.
0.01
0.001
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
Figure 24. Power vs. Throughput for Partial Power Down
For example, if the AD7495 is operated in a continuous
sampling mode with a throughput rate of 100 kSPS and an
SCLK of 20 MHz (VDD = 5 V), and the device is placed in partial
power-down mode between conversions, then the power
consumption is calculated as follows. The maximum power
dissipation during normal operation is 13 mW (VDD = 5 V). If
the power-up time from partial power-down is one dummy
cycle, that is, 1 μs, and the remaining conversion time is another
cycle, that is, 1 μs, then the AD7495 can be said to dissipate
13 mW for 2 μs during each conversion cycle. For the remainder of
the conversion cycle, 8 μs, the device remains in partial power-
down mode. The AD7495 dissipates 1.15 mW for the remaining
8 μs of the conversion cycle. If the throughput rate is 100 kSPS,
and the cycle time is 10 μs, the average power dissipated during
each cycle is (2/10) × (13 mW) + (8/10) × (1.15 mW) = 3.52 mW. If
2.0
V
= 5V
DD
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
PARTIAL
POWER-DOWN
FULL
POWER-DOWN
NORMAL
10
100
1k
10k
100k
1M
THROUGHPUT (SPS)
V
DD = 3 V, SCLK = 20 MHz and the device is again in partial
power-down mode between conversions, the power dissipated
during normal operation is 6 mW.
Figure 25. Typical AD7495 Current vs. Throughput
Rev. C | Page 19 of 24
AD7475/AD7495
Data Sheet
SERIAL INTERFACE
Figure 26 shows the detailed timing diagram for serial interfacing
to the AD7475/AD7495. The serial clock provides the conversion
clock and controls the transfer of information from the
AD7475/AD7495 during conversion.
Sixteen serial clock cycles are required to perform the
conversion process and to access data from the AD7475/AD7495.
going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges beginning with the second
leading zero; thus the first falling clock edge on the serial clock
has the second leading zero provided. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked out
on the previous (15th) falling edge.
CS
initiates the data transfer and conversion process. The falling
CS
edge of
puts the track-and-hold into hold mode and takes
CS
the bus out of three-state. The analog input is sampled at this point.
The conversion is also initiated at this point and requires 16 SCLK
cycles to complete. Once 13 SCLK falling edges have elapsed,
the track-and-hold goes back into track on the next SCLK rising
edge, as shown in Figure 26 at Point B. On the 16th SCLK falling
edge, the SDATA line goes back into three-state. If the rising
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, although the first leading zero
still has to be read on the first SCLK falling edge after the
CS
falling edge. Therefore, the first rising edge of SCLK after the
falling edge provides the second leading zero and the 15th
edge of
occurs before 16 SCLKs have elapsed, the conversion
CS
CS
is terminated and the SDATA line goes back into three-state, as
shown in Figure 27; otherwise SDATA returns to three-state on
the 16th SCLK falling edge, as shown in Figure 26.
rising SCLK edge has DB0 provided. This method may not
work with most microprocessors/DSPs, but could be used with
FPGAs and ASICs.
CS
tCONVERT
t6
t2
B
3
4
5
1
2
13
15
t8
DB0
16
14
t5
SCLK
t7
DB10
tQUIET
t4
DB11
t3
0
0
0
0
SDATA
DB2
DB1
THREE-STATE
THREE-STATE
FOUR LEADING ZEROS
Figure 26. Serial Interface Timing Diagram
CS
tCONVERT
t6
t2
B
3
4
5
1
2
13
15
16
14
SCLK
t9
DB2
t7
DB10
tQUIET
t4
t3
0
0
0
0
DB11
SDATA
THREE-STATE
THREE-STATE
FOUR LEADING ZEROS
Figure 27. Serial Interface Timing Diagram — Conversion Termination
Rev. C | Page 20 of 24
Data Sheet
AD7475/AD7495
MICROPROCESSOR INTERFACING
The serial interface on the AD7475/AD7495 allows the devices to
directly connect to a range of many different microprocessors. This
section explains how to interface the AD7475/AD7495 with
some of the more common microcontroller and DSP serial
interface protocols.
AD7475/AD7495 TO ADSP-21xx
The ADSP-21xx family of DSPs interfaces directly to the
AD7475/AD7495 without any glue logic required. The VDRIVE
pin of the AD7475/AD7495 takes the same supply voltage as
that of the ADSP-21xx. This allows the ADC to operate at a
higher voltage than the serial interface, that is, ADSP-21xx, if
necessary.
AD7475/AD7495 TO TMS320C5X/C54X
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
The SPORT control register should be set up as shown in Table 6.
Table 6.
AD7475/AD7495. The
input allows easy interfacing between
CS
SPORT Control Register Bits
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
Function
the TMS320C5x/C54x and the AD7475/AD7495 without any
glue logic required. The serial port of the TMS320C5x/C54x is
set up to operate in burst mode with internal CLKX (Tx serial
clock) and FSX (Tx frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1,
and TXM = 1. The format bit, FO, may be set to 1 to set the
word length to 8 bits, in order to implement the power-down
modes on the AD7475/AD7495.
Alternate framing
Active low frame signal
Right-justify data
16-bit data words
Internal serial clock
Frame every word
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
The connection diagram shown in Figure 28. Note that for
signal processing applications, it is imperative that the frame
synchronization signal from the TMS320C5x/C54x provide
equidistant sampling. The VDRIVE pin of the AD7475/AD7495
takes the same supply voltage as that of the TMS320C5x/C54x.
This allows the ADC to operate at a higher voltage than the
serial interface, that is, TMS320C5x/C54x, if necessary.
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 29. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set up
as described. The frame synchronization signal generated on the
TMS320C5x/C54x*
AD7475/AD7495*
SCLK
CLKX
TFS is tied to
and, as with all signal processing applications,
CS
CLKR
DR
SDATA
CS
equidistant sampling is necessary. However, in this example, the
timer interrupt is used to control the sampling rate of the ADC
and; under certain conditions, equidistant sampling may not be
achieved.
FBX
V
DRIVE
FSR
V
DD
*ADDITIONAL PINS OMITTED FOR CLARITY
ADSP-21xx*
AD7475/AD7495*
SCLK
SCLK
Figure 28. Interfacing to the TMS320C5x/54x
DR
SDATA
CS
RFS
TFS
V
DRIVE
V
DD
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 29. Interfacing to the ADSP-21xx
Rev. C | Page 21 of 24
AD7475/AD7495
Data Sheet
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS, and therefore, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given, (that is, AX0 = TX0), the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
before transmission starts. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, the data can be transmitted or it can
wait until the next clock edge.
DSP56xxx*
AD7475/AD7495*
SCLK
SCLK
SDATA
CS
SRD
SC2
V
DRIVE
V
DD
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 30. Interfacing to the DSP56xxx
AD7475/AD7495 TO MC68HC16
The serial peripheral interface (SPI) on the MC68HC16 is
configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 1, and the clock phase bit (CPHA) = 0. The SPI is
configured by writing to the SPI control register (SPCR), as
described in the 68HC16 User Manual. The serial transfer takes
place as a 16-bit operation when the size bit in the SPCR register is
set to size = 1. To implement the power-down modes with an 8-bit
transfer, set size = 0. (A connection diagram is shown in Figure 31.)
The VDRIVE pin of the AD7475/AD7495 takes the same supply
voltage as that of the MC68HC16. This allows the ADC to
operate at a higher voltage than the serial interface, that is, the
MC68HC16, if necessary.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and
subsequently between transmit instructions. This situation results
in nonequidistant sampling because the transmit instruction is
occurring on a SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
AD7475/AD7495 TO DSP56XXX
MC68HC16*
AD7475/AD7495*
The connection diagram in Figure 30 shows how the
SCLK
SCLK/PCM2
MISO/PMC0
SS/PMC3
AD7475/AD7495 connects to the synchronous serial interface
(SSI) of the DSP56xxx family of devices from Motorola. The SSI is
operated in synchronous mode (SYN bit in CRB = 1) with
internally generated 1-bit clock period frame sync for both Tx
and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word
length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To
implement the power-down modes on the AD7475/AD7495,
the word length can be changed to 8 bits by setting Bit WL1 = 0
and Bit WL0 = 0 in CRA. For signal processing applications, it
is imperative that the frame synchronization signal from the
DSP56xxx provide equidistant sampling. The VDRIVE pin of the
AD7475/AD7495 takes the same supply voltage as that of the
DSP56xxx. This allows the ADC to operate at a voltage higher
than the serial interface, that is, DSP56xxx, if necessary.
SDATA
CS
V
DRIVE
V
DD
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 31. Interfacing to the MC68HC16
Rev. C | Page 22 of 24
Data Sheet
AD7475/AD7495
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 32. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 33. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. C | Page 23 of 24
AD7475/AD7495
Data Sheet
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Linearity Error (LSB)2
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Package Option3
Branding
AD7475ARZ
AD7475BR
AD7475BRZ
AD7475BRZ-REEL7
AD7475ARMZ
AD7475ARMZ-REEL7
AD7475BRM-REEL7
AD7475BRMZ
AD7475BRMZ-REEL7
AD7495AR
AD7495AR-REEL
AD7495AR-REEL7
AD7495ARZ
AD7495ARZ-REEL7
AD7495BRZ
1.5
1
1
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
1
1.5
1.5
1
1
1
1.5
1.5
1.5
1.5
1.5
1
C4R
C4R
C9B
C3C
C3C
AD7495BRZ-REEL7
AD7495ARM
AD7495ARMZ
AD7495ARMZ-REEL7
AD7495BRMZ
1
1.5
1.5
1.5
1
CCA
C3B
C3B
C4Q
1 Z = RoHS Compliant Part.
2 Linearity error here refers to integral linearity error.
3 R = SOIC; RM = MSOP.
©2001-2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01684-0-7/15(C)
Rev. C | Page 24 of 24
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