AD7478A_15_技术文档

2.35 V to 5.25 V, 1 MSPS,

12-/10-/8-Bit ADCs in 6-Lead SC70

AD7476A/AD7477A/AD7478A

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Fast throughput rate: 1 MSPS

Specified for V_DDof 2.35 V to 5.25 V

Low power

V

DD

12-/10-/8-BIT

3.6 mW at 1 MSPS with 3 V supplies

12.5 mW at 1 MSPS with 5 V supplies

Wide input bandwidth

SUCCESSIVE-

APPROXIMATION

ADC

V

T/H

IN

71 dB SNR at 100 kHz input frequency

Flexible power/serial clock speed management

No pipeline delays

SCLK

SDATA

CS

CONTROL

LOGIC

High speed serial interface

SPI®/QSPI™/MICROWIRE™/DSP compatible

Standby mode: 1 μA maximum

6-lead SC70 package

AD7476A/AD7477A/AD7478A

GND

8-lead MSOP package

Figure 1.

Qualified for automotive applications

APPLICATIONS

Battery-powered systems

Personal digital assistants

Medical instruments

Mobile communications

Instrumentation and control systems

Data acquisition systems

High speed modems

Optical sensors

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit

high speed, low power, successive-approximation analog-to-

digital converters (ADCs), respectively. The parts operate from

a single 2.35 V to 5.25 V power supply and feature throughput

rates up to 1 MSPS. The parts contain a low noise, wide

bandwidth track-and-hold amplifier that can handle input

frequencies in excess of 13 MHz. The conversion process and

1. First 12-/10-/8-bit ADCs in a SC70 package.

2. High throughput with low power consumption.

3. Flexible power/serial clock speed management. The

conversion rate is determined by the serial clock, allowing

the conversion time to be reduced through the serial clock

speed increase. This allows the average power consumption

to be reduced when a power-down mode is used while not

converting. The parts also feature a power-down mode to

maximize power efficiency at lower throughput rates.

Current consumption is 1 μA maximum and 50 nA

typically when in power-down mode.

CS

data acquisition are controlled using

and the serial clock,

allowing the devices to interface with microprocessors or DSPs.

CS

The input signal is sampled on the falling edge of , and the

conversion is also initiated at this point. There are no pipeline

delays associated with the parts. The AD7476A/AD7477A/

AD7478A use advanced design techniques to achieve low power

dissipation at high throughput rates. The reference for the part

is taken internally from V_DDto allow the widest dynamic input

range to the ADC. Thus, the analog input range for the part is

0 V to V_DD. The conversion rate is determined by the SCLK.

4. Reference derived from the power supply.

5. No pipeline delay. The parts feature a standard successive

approximation ADC with accurate control of the sampling

CS

instant via a

input and once-off conversion control.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

IMPORTANT LINKS for the AD7476A_7477A_7478A*

Last content update 04/07/2014 12:27 am

SIMILAR PRODUCTS & PARAMETRIC SELECTION TABLES

DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE

AD7476A Pmod Xilinx FPGA Reference Design

Find Similar Products By Operating Parameters

Low Resolution - Single Channel Unipolar/Bipolar 8/10/12-Bit PulSAR

ADCs

AD74xx - No-OS Driver for Renesas Microcontroller Platforms

AD74xx - No-OS Driver for Microchip Microcontroller Platforms

AD7476A IIO Single Channel Serial ADC Linux Driver

DOCUMENTATION

MS-2210: Designing Power Supplies for High Speed ADC

EVALUATION KITS & SYMBOLS & FOOTPRINTS

View the Evaluation Boards and Kits page for the AD7476A

Symbols and Footprints for the AD7476A

8- to 18-Bit SAR ADCs ... From the Leader in High Performance Analog

For the AD7476A

AN-931: Understanding PulSAR ADC Support Circuitry

Symbols and Footprints for the AD7477A

AN-1141: Powering a Dual Supply Precision ADC with Switching

Regulators

Symbols and Footprints for the AD7478A

AN-932: Power Supply Sequencing

AN-877: Interfacing to High Speed ADCs via SP

AN-935: Designing an ADC Transformer-Coupled Front End

AN-742: Frequency Domain Response of Switched-Capacitor ADCs

The Data Conversion Handbook

DESIGN COLLABORATION COMMUNITY

MT-031: Grounding Data Converters and Solving the Mystery of

Collaborate Online with the ADI support team and other designers

about select ADI products.

MT-002: What the Nyquist Criterion Means to Your Sampled Data

System Design

Follow us on Twitter: www.twitter.com/ADI_News

Like us on Facebook: www.facebook.com/AnalogDevicesInc

MS-1779: Nine Often Overlooked ADC Specifications

MS-2210: Designing Power Supplies for High Speed ADC

MS-2022: Seven Steps to Successful Analog-to-Digital Signal

Conversion (Noise Calculation for Proper Signal Conditioning)

DESIGN SUPPORT

Submit your support request here:

Linear and Data Converters

Embedded Processing and DSP

MS-2124: Understanding AC Behaviors of High Speed ADCs

ICs for Programmable Logic Control and Distributed Control Systems

View the AD7476 Product Page for additional documentation.

Telephone our Customer Interaction Centers toll free:

Americas:

Europe:

China:

1-800-262-5643

00800-266-822-82

4006-100-006

SUGGESTED COMPANION PRODUCTS

Recommended Input Buffer Amplifiers for the AD7476A

India:

1800-419-0108

8-800-555-45-90

Russia:

For precision, single supply, low cost, R-R In/Out, we

recommend the AD8655.

For precision, wide supply, low cost, we recommend the

ADA4000-1.

Quality and Reliability

Lead(Pb)-Free Data

Package Information

Recommended Input Buffer Amplifiers for the

AD7476A/AD7477A/AD7478A

For high speed and low noise, we recommend the AD8021,

AD8031 or the ADA4899-1.

SAMPLE & BUY

AD7476

Recommended Precison References for the

AD7476A/AD7477A/AD7478A

AD7477

AD7478

For high precision and improved power performance, we

recommend the REF193 (3V) or REF195 (5V).

For improved SNR at 3V, we recommend the AD780.

View Price & Packaging, Request Evaluation Board and Samples, Check

Inventory & Purchase

Find Local Distributors

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.

Note: Dynamic changes to the content on this page (labeled 'Important Links') does not

constitute a change to the revision number of the product data sheet.

This content may be frequently modified.

AD7476A/AD7477A/AD7478A

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Connection Diagram ....................................................... 16

Analog Input ............................................................................... 16

Digital Inputs .............................................................................. 17

Modes of Operation ....................................................................... 18

Normal Mode.............................................................................. 18

Power-Down Mode.................................................................... 18

Power-Up Time .......................................................................... 18

Power vs. Throughput Rate........................................................... 20

Serial Interface ................................................................................ 21

AD7478A in a 12 SCLK Cycle Serial Interface....................... 22

Microprocessor Interfacing........................................................... 23

AD7476A/AD7477A/AD7478A to TMS320C541 Interface 23

AD7476A/AD7477A/AD7478A to ADSP-218x Interface.... 23

AD7476A/AD7477A/AD7478A to DSP563xx Interface...... 24

Application Hints ........................................................................... 25

Grounding and Layout .............................................................. 25

Evaluating the AD7476A/AD7477A Performance............... 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

Automotive Products................................................................. 27

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AD7476A Specifications.............................................................. 3

AD7477A Specifications.............................................................. 5

AD7478A Specifications.............................................................. 6

Timing Specifications .................................................................. 8

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

Circuit Information.................................................................... 15

The Converter Operation.......................................................... 15

ADC Transfer Function............................................................. 15

REVISION HISTORY

1/11—Rev. E to Rev. F

Changes to Features Section............................................................ 1

Changes to Ordering Guide .......................................................... 26

Added Automotive Products Section .......................................... 27

2/09—Rev. D to Rev. E

Changes to Features.......................................................................... 1

Changes to Ordering Guide .......................................................... 26

4/06—Rev. C to Rev. D

Updated Format..................................................................Universal

Changes to Ordering Guide .......................................................... 26

Rev. F | Page 2 of 28

AD7476A/AD7477A/AD7478A

SPECIFICATIONS

AD7476A SPECIFICATIONS

V_DD= 2.35 V to 5.25 V, f_SCLK= 20 MHz, f_SAMPLE= 1 MSPS, T_A= T_MINto T_MAX, unless otherwise noted.¹

Table 1.

Parameter

A Grade²B Grade²Y Grade²Unit

Test Conditions/Comments

f_IN= 100 kHz sine wave

V_DD= 2.35 V to 3.6 V, T_A= 25°C

V_DD= 2.4 V to 3.6 V

V_DD= 2.35 V to 3.6 V

V_DD= 4.75 V to 5.25 V, T_A= 25°C

V_DD= 4.75 V to 5.25 V

V_DD= 2.35 V to 3.6 V, T_A= 25°C

V_DD= 2.4 V to 3.6 V

V_DD= 4.75 V to 5.25 V, T_A= 25°C

V_DD= 4.75 V to 5.25 V

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion (SINAD)³

70

69

71.5

69

68

71

70

69

70

69

71.5

69

68

71

70

69

70

69

71.5

69

68

71

70

69

dB min

dB typ

dB min

dB typ

Signal-to-Noise Ratio (SNR)³

Total Harmonic Distortion (THD)³

Peak Harmonic or Spurious Noise (SFDR)³–82

Intermodulation Distortion (IMD)³

–80

–82

–80

–82

Second-Order Terms

Third-Order Terms

Aperture Delay

–84

10

–84

10

–84

10

dB typ

ns typ

fa = 100.73 kHz, fb = 90.72 kHz

Aperture Jitter

30

ps typ

Full Power Bandwidth

13.5

2

13.5

2

13.5

2

MHz typ

@ 3 dB

@ 0.1 dB

DC ACCURACY

Resolution

Integral Nonlinearity³

B and Y grades⁴

12

1.5

12

1.5

Bits

LSB max

LSB typ

0.75

Differential Nonlinearity

Offset Error^{3, 5}

–0.9/+1.5 –0.9/+1.5 LSB max

LSB typ

Guaranteed no missed codes to 12 bits

0.75

1.5

0.2

1.5

0.5

2

1.5

0.2

1.5

0.5

2

LSB max

LSB typ

LSB max

LSB typ

LSB max

Gain Error^{3, 5}

1.5

Total Unadjusted Error (TUE)^{3, 5}

ANALOG INPUT

Input Voltage Range

DC Leakage Current

Input Capacitance

0 to V_DD

0.5

20

0 to V_DD

0.5

20

0 to V_DD

0.5

20

V

μA max

pF typ

Track-and-hold in track; 6 pF typ when in hold

LOGIC INPUTS

Input High Voltage, V_INH

2.4

1.8

0.8

0.4

0.5

10

5

2.4

1.8

0.8

0.4

0.5

10

5

2.4

1.8

0.8

0.4

0.5

10

5

V min

V_DD= 2.35 V

V_DD= 5 V

V_DD= 3 V

Typically 10 nA, V_IN= 0 V or V_DD

Input Low Voltage, V_INL

V max

μA max

nA typ

pF max

Input Current, I_IN, SCLK Pin

CS

Input Current, I_IN, Pin

6

Input Capacitance, C_IN

Rev. F | Page 3 of 28

AD7476A/AD7477A/AD7478A

Parameter

A Grade²B Grade²Y Grade²Unit

Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance⁶

Output Coding

V_DD– 0.2

0.4

1

V_DD– 0.2

0.4

1

V_DD– 0.2

0.4

1

V min

I_SOURCE= 200 μA; V_DD= 2.35 V to 5.25 V

I_SINK= 200 μA

V max

μA max

pF max

5

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

800

250

1

800

250

1

800

250

1

ns max

16 SCLK cycles

Track-and-Hold Acquisition Time³

Throughput Rate

MSPS max See Serial Interface section

POWER REQUIREMENTS

V_DD

2.35/5.25 2.35/5.25 2.35/5.25 V min/max

I_DD

Digital I/Ps = 0 V or V_DD

Normal Mode (Static)

2.5

1.2

3.5

1.7

1

0.6

0.3

17.5

5.1

5

2.5

1.2

3.5

1.7

1

0.6

0.3

17.5

5.1

5

2.5

1.2

3.5

1.7

1

0.6

0.3

17.5

5.1

5

mA typ

mA max

μA max

mA typ

mW max

μW max

V_DD= 4.75 V to 5.25 V, SCLK on or off

V_DD= 2.35 V to 3.6 V, SCLK on or off

V_DD= 4.75 V to 5.25 V, f_SAMPLE= 1 MSPS

V_DD= 2.35 V to 3.6 V, f_SAMPLE= 1 MSPS

Typically 50 nA

V_DD= 5 V, f_SAMPLE= 100 kSPS

V_DD= 3 V, f_SAMPLE= 100 kSPS

V_DD= 5 V, f_SAMPLE= 1 MSPS

V_DD= 3 V, f_SAMPLE= 1 MSPS

V_DD= 5 V

Normal Mode (Operational)

Full Power-Down Mode (Static)

Full Power-Down Mode (Dynamic)

Power Dissipation⁷

Normal Mode (Operational)

Full Power-Down Mode

3

V_DD= 3 V

¹Temperature ranges are as follows: A, B grades from –40°C to +85°C, Y grade from –40°C to +125°C.

²Operational from V_DD= 2.0 V, with input low voltage (V_INL) 0.35 V maximum.

³See the Terminology section.

⁴B and Y grades, maximum specifications apply as typical figures when V_DD= 4.75 V to 5.25 V.

⁵SC70 values guaranteed by characterization.

⁶Guaranteed by characterization.

⁷See the Power vs. Throughput Rate section.

Rev. F | Page 4 of 28

AD7476A/AD7477A/AD7478A

AD7477A SPECIFICATIONS

V_DD= 2.35 V to 5.25 V, f_SCLK= 20 MHz, f_SAMPLE= 1 MSPS, T_A= T_MINto T_MAX, unless otherwise noted.¹

Table 2.

Parameter

A Grade²

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion (SINAD)³

Total Harmonic Distortion (THD)³

Peak Harmonic or Spurious Noise (SFDR)³

Intermodulation Distortion (IMD)³

Second-Order Terms

f_IN= 100 kHz sine wave

61

–72

–73

dB min

dB max

–82

10

dB typ

ns typ

fa = 100.73 kHz, fb = 90.7 kHz

Third-Order Terms

Aperture Delay

Aperture Jitter

30

ps typ

Full Power Bandwidth

13.5

2

MHz typ

@ 3 dB

@ 0.1 dB

DC ACCURACY

Resolution

10

0.5

1

1.2

Bits

Integral Nonlinearity

Differential Nonlinearity

Offset Error^{3, 4}

Gain Error^{3, 4}

Total Unadjusted Error (TUE)^{3, 4}

LSB max

Guaranteed no missed codes to 10 bits

ANALOG INPUT

Input Voltage Range

DC Leakage Current

Input Capacitance

LOGIC INPUTS

0 to V_DD

0.5

20

V

µA max

pF typ

Track-and-hold in track; 6 pF typ when in hold

Input High Voltage, V_INH

2.4

1.8

0.8

0.4

0.5

10

5

V min

V_DD= 2.35 V

V_DD= 5 V

V_DD= 3 V

Typically 10 nA, V_IN= 0 V or V_DD

Input Low Voltage, V_INL

V max

μA max

nA typ

pF max

Input Current, I_IN, SCLK Pin

CS

Input Current, I_IN, Pin

5

Input Capacitance, C_IN

LOGIC OUTPUTS

Output High Voltage V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance⁵

Output Coding

V_DD– 0.2

0.4

1

V min

I_SOURCE= 200 μA, V_DD= 2.35 V to 5.25 V

I_SINK= 200 μA

V max

μA max

pF max

5

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

700

250

1

ns max

MSPS max

14 SCLK cycles with SCLK at 20 MHz

Track-and-Hold Acquisition Time³

Throughput Rate

Rev. F | Page 5 of 28

AD7476A/AD7477A/AD7478A

Parameter

A Grade²

Unit

Test Conditions/Comments

POWER REQUIREMENTS

V_DD

2.35/5.25

V min/max

I_DD

Digital I/Ps = 0 V or V_DD

Normal Mode (Static)

2.5

1.2

3.5

1.7

1

0.6

0.3

17.5

5.1

5

mA typ

mA max

μA max

mA typ

mW max

μW max

V_DD= 4.75 V to 5.25 V, SCLK on or off

V_DD= 2.35 V to 3.6 V, SCLK on or off

V_DD= 4.75 V to 5.25 V, f_SAMPLE= 1 MSPS

V_DD= 2.35 V to 3.6 V, f_SAMPLE= 1 MSPS

Typically 50 nA

V_DD= 5 V, f_SAMPLE= 100 kSPS

V_DD= 3 V, f_SAMPLE= 100 kSPS

V_DD= 5 V, f_SAMPLE= 1 MSPS

V_DD= 3 V, f_SAMPLE= 1 MSPS

V_DD= 5 V

Normal Mode (Operational)

Full Power-Down Mode (Static)

Full Power-Down Mode (Dynamic)

Power Dissipation⁶

Normal Mode (Operational)

Full Power-Down Mode

¹Temperature range is from –40°C to +85°C.

²Operational from V_DD= 2.0 V, with input high voltage (V_INH) 1.8 V minimum.

³See the Terminology section.

⁴SC70 values guaranteed by characterization.

⁵Guaranteed by characterization.

⁶See the Power vs. Throughput Rate section.

AD7478A SPECIFICATIONS

V_DD= 2.35 V to 5.25 V, f_SCLK= 20 MHz, f_SAMPLE= 1 MSPS, T_A= T_MINto T_MAX, unless otherwise noted.¹

Table 3.

Parameter

A Grade²

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

f_IN= 100 kHz sine wave

Signal-to-Noise + Distortion (SINAD)³

Total Harmonic Distortion (THD)³

Peak Harmonic or Spurious Noise (SFDR)³

Intermodulation Distortion (IMD)³

Second-Order Terms

49

–65

dB min

dB max

–76

10

dB typ

ns typ

fa = 100.73 kHz, fb = 90.7 kHz

Third-Order Terms

Aperture Delay

Aperture Jitter

30

ps typ

Full Power Bandwidth

13.5

2

MHz typ

@ 3 dB

@ 0.1 dB

DC ACCURACY

Resolution

8

Bits

Integral Nonlinearity³

Differential Nonlinearity³

Offset Error^{3, 4}

0.3

0.5

LSB max

Guaranteed no missed codes to eight bits

Gain Error^{3, 4}

Total Unadjusted Error (TUE)^{3, 4}

ANALOG INPUT

Input Voltage Range

DC Leakage Current

Input Capacitance

0 to V_DD

0.5

20

V

μA max

pF typ

Track-and-hold in track; 6 pF typ when in hold

Rev. F | Page 6 of 28

AD7476A/AD7477A/AD7478A

Parameter

A Grade²

Unit

Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V_INH

2.4

1.8

0.8

0.4

0.5

10

5

V min

V_DD= 2.35 V

V_DD= 5 V

V_DD= 3 V

Typically 10 nA, V_IN= 0 V or V_DD

Input Low Voltage, V_INL

V max

μA max

nA typ

pF max

Input Current, I_IN, SCLK Pin

CS

Input Current, I_IN, Pin

5

Input Capacitance, C_IN

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance⁵

Output Coding

V_DD– 0.2

0.4

1

V min

I_SOURCE= 200 μA, V_DD= 2.35 V to 5.25 V

I_SINK= 200 μA

V max

μA max

pF max

5

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition Time³

Throughput Rate

600

225

1.2

ns max

MSPS max

12 SCLK cycles with SCLK at 20 MHz

POWER REQUIREMENTS

V_DD

2.35/5.25

V min/max

I_DD

Digital I/Ps = 0 V or V_DD

V_DD= 4.75 V to 5.25 V, SCLK on or off

V_DD= 2.35 V to 3.6 V, SCLK on or off

V_DD= 4.75 V to 5.25 V

V_DD= 2.35 V to 3.6 V

Typically 50 nA

V_DD= 5 V, f_SAMPLE= 100 kSPS

V_DD= 3 V, f_SAMPLE= 100 kSPS

V_DD= 5 V

Normal Mode (Static)

2.5

1.2

3.5

1.7

1

0.6

0.3

17.5

5.1

5

mA typ

mA max

μA max

mA typ

mW max

μW max

Normal Mode (Operational)

Full Power-Down Mode (Static)

Full Power-Down Mode (Dynamic)

Power Dissipation⁶

Normal Mode (Operational)

V_DD= 3 V

V_DD= 5 V

Full Power-Down Mode

¹Temperature range is from –40°C to +85°C.

²Operational from V_DD= 2.0 V, with input high voltage (V_INH) 1.8 V minimum.

³See the Terminology section.

⁴SC70 values guaranteed by characterization.

⁵Guaranteed by characterization.

⁶See the Power vs. Throughput Rate section.

Rev. F | Page 7 of 28

AD7476A/AD7477A/AD7478A

TIMING SPECIFICATIONS

V_DD= 2.35 V to 5.25 V; T_A= T_MINto T_MAX, unless otherwise noted.¹

Table 4.

Parameter

Limit at T_MIN, T_MAX

Unit

Description

A, B grades

Y grade

kHz min³

MHz max

2

f_SCLK

10

20

t_CONVERT

16 × t_SCLK

14 × t_SCLK

12 × t_SCLK

50

AD7476A

AD7477A

AD7478A

t_QUIET

ns min

Minimum quiet time required between bus relinquish

and start of next conversion

t₁

t₂

10

ns min

ns max

ns min

CS

Minimum pulse width

10

CS

to SCLK setup time

4

t₃

22

CS

Delay from until SDATA three-state disabled

Data access time after SCLK falling edge

SCLK low pulse width

SCLK high pulse width

SCLK to data valid hold time

V_DD≤ 3.3 V

3.3 V < V_DD≤ 3.6 V

V_DD> 3.6 V

SCLK falling edge to SDATA high impedance

Power-up time from full power-down

4

t₄

40

0.4 t_SCLK

t₅

t₆

t₇

5

10

9.5

7

36

ns min

ns max

ns min

μs max

6

t₈

t₇values also apply to t₈minimum values

1

7

t_POWER-UP

¹Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V.

²Mark/space ratio for the SCLK input is 40/60 to 60/40.

³Minimum f_SCLKat which specifications are guaranteed.

⁴Measured with the load circuit shown in Figure 2, and defined as the time required for the output to cross 0.8 V or 1.8 V when V_DD= 2.35 V, and

0.8 V or 2.0 V for V_DD> 2.35 V.

⁵Measured with a 50 pF load capacitor.

⁶t₈is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. Therefore, the time, t₈, quoted in the timing characteristics is the true bus

relinquish time of the part and is independent of the bus loading.

⁷See the Power-Up Time section.

Rev. F | Page 8 of 28

AD7476A/AD7477A/AD7478A

Timing Diagrams

Timing Example 2

I

200

µ

A

Having f_SCLK= 5 MHz and a throughput is 315 kSPS yields a

cycle time of

OL

TO OUTPUT

1.6V

t₂+ 12.5 (1/f_SCLK) + t_ACQ= 3.174 µs

where:

C

L

50pF

I

µ

OH

t₂= 10 ns min, this leaves t_ACQto be 664 ns. This 664 ns satisfies

Figure 2. Load Circuit for Digital Output Timing Specifications

the requirement of 250 ns for t_ACQ

.

Timing Example 1

From Figure 4, t_ACQis comprised of

Having f_SCLK= 20 MHz and a throughput of 1 MSPS, a cycle

time of

2.5 (1/f_SCLK) + t₈+ t_QUIET, t₈= 36 ns maximum

This allows a value of 128 ns for t_QUIET, satisfying the minimum

requirement of 50 ns.

t₂+ 12.5 (1/f_SCLK) + t_ACQ= 1 µs

where:

In this example and with other, slower clock values, the signal

may already be acquired before the conversion is complete, but

it is still necessary to leave 50 ns minimum t_QUIETbetween

conversions. In Example 2, acquire the signal fully at

approximately Point C in Figure 4.

t₂= 10 ns min, leaving t_ACQto be 365 ns. This 365 ns satisfies the

requirement of 250 ns for t_ACQ

.

From Figure 4, t_ACQis comprised of

2.5 (1/f_SCLK) + t₈+ t_QUIET

where:

t₈= 36 ns maximum. This allows a value of 204 ns for t_QUIET

,

satisfying the minimum requirement of 50 ns.

t₁

CS

t_CONVERT

5

t₆

t₂

B

SCLK

1

2

3

4

13

14

t₅

15

16

t₈

t₃

t₄

t_QUIET

t₇

Z

ZERO

DB11

DB10

DB2

DB1

DB0

SDATA

THREE-

STATE

THREE-STATE

4 LEADING ZEROS

Figure 3. AD7476A Serial Interface Timing Diagram

CS

t_CONVERT

t₂

B

C

SCLK

1

2

3

4

5

13

14

15

16

t₈

t_QUIET

t_ACQ

12.5(1/f

)

SCLK

1/THROUGHPUT

Figure 4. Serial Interface Timing Example

Rev. F | Page 9 of 28

AD7476A/AD7477A/AD7478A

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.¹

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Ratings

V_DDto GND

–0.3 V to +7 V

–0.3 V to V_DD+ 0.3 V

–0.3 V to +7 V

–0.3 V to V_DD+ 0.3 V

10 mA

Analog Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

Input Current to Any Pin Except Supplies

Operating Temperature Range

Commercial (A and B Grades)

Industrial (Y Grade)

–40°C to +85°C

–40°C to +125°C

–65°C to +150°C

150°C

Storage Temperature Range

Junction Temperature

MSOP Package

θ_JAThermal Impedance

θ_JCThermal Impedance

SC70 Package

205.9°C/W

43.74°C/W

θ_JAThermal Impedance

θ_JCThermal Impedance

Lead Temperature, Soldering

Reflow (10 sec to 30 sec)

Pb-Free Temperature Soldering

Reflow

340.2°C/W

228.9°C/W

235 (0/+5)°C

255 (0/+5)°C

3.5 kV

ESD

¹Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. F | Page 10 of 28

AD7476A/AD7477A/AD7478A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

6

5

4

1

2

3

4

8

7

6

5

CS

V

DD

IN

DD

AD7476A/

AD7477A/

AD7478A

TOP VIEW

(Not to Scale)

AD7476A/

AD7477A/

AD7478A

TOP VIEW

(Not to Scale)

SDATA

SCLK

GND

SCLK

NC

GND

SDATA

CS

V

IN

NC

NC = NO CONNECT

Figure 6. 8-Lead MSOP Pin Configuration

Figure 5. 6-Lead SC70 Pin Configuration

Table 6. Pin Function Descriptions

Mnemonic Description

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

AD7476A/AD7477A/AD7478A and also frames the serial data transfer.

V_DD

Power Supply Input. The V_DDrange for AD7476A/AD7477A/AD7478A is from 2.35 V to 5.25 V.

GND

Analog Ground. Ground reference point for all circuitry on AD7476A/AD7477A/AD7478A. Refer all analog input signals to this

GND voltage.

V_IN

Analog Input. Single-ended analog input channel. The input range is 0 V to V_DD.

SDATA

Data Out. Logic output. The conversion result from AD7476A/AD7477A/AD7478A is provided on this output as a serial data

stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476A consists of four

leading zeros followed by 12 bits of conversion data that are provided MSB first. The data stream from the AD7477A consists

of four leading zeros followed by 10 bits of conversion data followed by two trailing zeros, provided MSB first. The data stream

from the AD7478A consists of four leading zeros followed by 8 bits of conversion data followed by four trailing zeros that are

provided MSB first.

SCLK

NC

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the

clock source for the conversion process of AD7476A/AD7477A/AD7478A.

No Connect.

Rev. F | Page 11 of 28

AD7476A/AD7477A/AD7478A

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7, Figure 8, and Figure 9 each show a typical FFT plot for

the AD7476A, AD7477A, and AD7478A, respectively, at a

1 MSPS sample rate and 100 kHz input frequency. Figure 10

shows the signal-to-(noise + distortion) ratio performance vs.

the input frequency for various supply voltages while sampling

at 1 MSPS with an SCLK frequency of 20 MHz for the

AD7476A.

Figure 11 and Figure 12 show INL and DNL performance for

the AD7476A. Figure 13 shows a graph of the total harmonic

distortion vs. the analog input frequency for different source

impedances when using a supply voltage of 3.6 V and sampling

at a rate of 1 MSPS (see the Analog Input section). Figure 14

shows a graph of the total harmonic distortion vs. the analog

input signal frequency for various supply voltages while

sampling at 1 MSPS with an SCLK frequency of 20 MHz.

5

8192 POINT FFT

–5

V

= 2.7V

DD

V

= 2.35V

DD

–15

–35

f

= 1MSPS

= 100kHz

SAMPLE

f

= 1MSPS

= 100kHz

SAMPLE

–15

–25

–35

–45

–55

–65

–75

–85

–95

IN

SINAD = 72.05dB

THD = –82.87dB

SFDR = –87.24dB

SINAD = 49.77dB

THD = –75.51dB

SFDR = –70.71dB

–55

–75

–95

–115

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

Figure 7. AD7476A Dynamic Performance at 1 MSPS

Figure 9. AD7478A Dynamic Performance at 1 MSPS

–66

–67

–68

–69

–70

–71

–72

–73

–74

8192 POINT FFT

V

= 2.35V

DD

–5

–25

f

= 1MSPS

= 100kHz

SAMPLE

IN

SINAD = 61.67dB

THD = –79.59dB

SFDR = –82.93dB

V

= 2.7V

DD

V

= 2.35V

DD

= 5.25V

–45

V

DD

–65

V

= 4.75V

DD

–85

V

= 3.6V

DD

–105

10

100

FREQUENCY (kHz)

1000

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

Figure 10. AD7476A SINAD vs. Input Frequency at 1 MSPS

Figure 8. AD7477A Dynamic Performance at 1 MSPS

Rev. F | Page 12 of 28

AD7476A/AD7477A/AD7478A

1.0

0.8

0

V

= 3.6V

DD

V

= 2.35V

DD

–10

TEMP = 25°C

f_SAMPLE= 1MSPS

0.6

0.4

0.2

0

–20

–30

R

= 10kΩ

IN

–40

–50

–60

–70

–80

–90

R

= 1kΩ

IN

–0.2

–0.4

–0.6

R

= 130Ω

IN

R

= 13Ω

IN

–0.8

–1.0

R

= 0Ω

IN

0

512

1024

1536

2048

2560 3072

3584

4096

10

100

1000

CODE

INPUT FREQUENCY (kHz)

Figure 11. AD7476A INL Performance

Figure 13. THD vs. Analog Input Frequency for Various Source Impedances

1.0

0.8

–60

–65

V

= 2.35V

DD

TEMP = 25°C

f_SAMPLE= 1MSPS

0.6

0.4

0.2

0

V

= 2.35V

DD

–70

–75

–80

–85

–90

V

= 2.7V

DD

V

= 4.75V

DD

–0.2

–0.4

–0.6

V

= 5.25V

DD

= 3.6V

–0.8

–1.0

V

DD

0

512

1024

1536

2048

2560 3072

3584

4096

10

100

INPUT FREQUENCY (kHz)

1000

CODE

Figure 12. AD7476A DNL Performance

Figure 14. THD vs. Analog Input Frequency for Various Supply Voltages

Rev. F | Page 13 of 28

AD7476A/AD7477A/AD7478A

TERMINOLOGY

Integral Nonlinearity (INL)

Total Harmonic Distortion (THD)

INL is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. For the

AD7476A/AD7477A/AD7478A, the endpoints of the transfer

function are zero scale (1 LSB below the first code transition),

and full scale (1 LSB above the last code transition).

Total harmonic distortion is the ratio of the rms sum of

harmonics to the fundamental. It is defined as

V₂²+V₃²+V₄²+V₅²+V₆²

THD(dB) = 20log

V₁

where V₁is the rms amplitude of the fundamental, and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through the

sixth harmonics.

Differential Nonlinearity (DNL)

DNL is the difference between the measured and the ideal

1 LSB change between any two adjacent codes in the ADC.

Peak Harmonic or Spurious Noise (SFDR)

Offset Error

Peak harmonic or spurious noise is defined as the ratio of the rms

value of the next largest component in the ADC output spectrum

(up to f_S/2 and excluding dc) to the rms value of the fundamental.

Normally, the value of this specification is determined by the largest

harmonic in the spectrum. For ADCs where the harmonics are

buried in the noise floor, it is a noise peak.

This is the deviation of the first code transition (00 . . . 000) to

(00 . . . 001) from the ideal, that is, AGND + 1 LSB.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to

(111 . . . 111) from the ideal, that is, V_REF– 1 LSB after the offset

error has been adjusted out.

Intermodulation Distortion (IMD)

Track-and-Hold Acquisition Time

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities create distortion

products at sum and difference frequencies of mfa, nfb, where

m and n = 0, 1, 2, 3, and so on. Intermodulation distortion

terms are those for which neither m nor n are equal to zero. For

example, the second-order terms include (fa + fb) and (fa – fb),

and the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb),

and (fa – 2fb).

The track-and-hold amplifier returns to track mode at the end

of a conversion. The track-and-hold acquisition time is the time

required for the output of the track-and-hold amplifier to reach

its final value, within 0.5 LSB, after the end of conversion. See

the Serial Interface section for more details.

Signal-to-(Noise + Distortion) Ratio (SINAD)

This is the measured ratio of signal-to-(noise + distortion) at

the output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals up

to half the sampling frequency (f_S/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digitiza-

tion process; the more levels, the smaller the quantization noise.

The theoretical signal-to-(noise + distortion) ratio for an ideal

N-bit converter with a sine wave input is given by signal-to-

(noise + distortion) = (6.02 N + 1.76) dB. Thus, it is 74 dB for a

12-bit converter, 62 dB for a 10-bit converter, and 50 dB for an

8-bit converter.

The AD7476A/AD7477A/AD7478A are tested using the CCIF

standard where two input frequencies are used (see fa and fb in

the Specifications section). In this case, the second-order terms

are usually distanced in frequency from the original sine waves,

while the third-order terms are usually at a frequency close to the

input frequencies. As a result, the second- and third-order terms

are specified separately. The calculation of the intermodulation

distortion is per the THD specification, where it is the ratio of

the rms sum of the individual distortion products to the rms

amplitude of the sum of the fundamentals expressed in decibels.

Total Unadjusted Error (TUE)

This is a comprehensive specification that includes the gain,

linearity, and offset errors.

Rev. F | Page 14 of 28

AD7476A/AD7477A/AD7478A

THEORY OF OPERATION

When the ADC starts a conversion (see Figure 16), SW2 opens

and SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and the charge redistribution

DAC are used to add and subtract fixed amounts of charge from

the sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code. Figure 17 shows the ADC transfer function.

CIRCUIT INFORMATION

The AD7476A/AD7477A/AD7478A are fast, micropower,

12-/10-/8-bit, single-supply analog-to-digital converters (ADCs),

respectively. The parts can be operated from a 2.35 V to 5.25 V

supply. When operated from either a 5 V supply or a 3 V supply,

the AD7476A/AD7477A/AD7478A are capable of throughput

rates of 1 MSPS when provided with a 20 MHz clock. The

AD7476A/AD7477A/AD7478A provide the user with an on-

chip, track-and-hold ADC and a serial interface housed in a

tiny 6-lead SC70 or 8-lead MSOP package, offering the user

considerable space-saving advantages over alternative solutions.

The serial clock input accesses data from the part but also pro-

vides the clock source for the successive-approximation ADC.

The analog input range is 0 V to V_DD. The ADC does not require

an external reference or an on-chip reference. The reference for

the AD7476A/AD7477A/AD7478A is derived from the power

supply and, thus, gives the widest dynamic input range. The

AD7476A/AD7477A/AD7478A also feature a power-down

option to allow power saving between conversions. The power-

down feature is implemented across the standard serial interface,

as described in the Modes of Operation section.

CHARGE

REDISTRIBUTION

DAC

SAMPLING

CAPACITOR

A

V

IN

CONTROL

LOGIC

SW1

SW2

CONVERSION

PHASE

B

COMPARATOR

AGND

V

/2

DD

Figure 16. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7476A/AD7477A/AD7478A is

straight binary. The designed code transitions occur at the

successive integer LSB values, that is, 1 LSB, 2 LSB, and so on.

The LSB size is V_DD/4096 for the AD7476A, V_DD/1024 for the

AD7477A, and V_DD/256 for the AD7478A. The ideal transfer

characteristic for the AD7476A/AD7477A/AD7478A is shown

in Figure 17.

THE CONVERTER OPERATION

AD7476A/AD7477A/AD7478A are successive approximation,

analog-to-digital converters based around a charge redistribu-

tion DAC. Figure 15 and Figure 16 show simplified schematics

of the ADC. Figure 15 shows the ADC during its acquisition

phase. SW2 is closed and SW1 is in Position A, the comparator

is held in a balanced condition, and the sampling capacitor

acquires the signal on V_IN.

111...111

111...110

111...000

CHARGE

REDISTRIBUTION

DAC

1LSB =V /4096 (AD7476A)

DD

1LSB =V /1024 (AD7477A)

DD

011...111

1LSB =V /256 (AD7478A)

DD

SAMPLING

CAPACITOR

000...010

000...001

000...000

A

V

IN

CONTROL

LOGIC

SW1

1LSB

ACQUISITION

PHASE

+V – 1LSB

DD

B

0V

SW2

ANALOG INPUT

COMPARATOR

AGND

Figure 17. AD7476A/AD7477A/AD7478A

Transfer Characteristic

V

/2

DD

Figure 15. ADC Acquisition Phase

Rev. F | Page 15 of 28

AD7476A/AD7477A/AD7478A

TYPICAL CONNECTION DIAGRAM

Figure 18 shows a typical connection diagram for the AD7476A/

AD7477A/AD7478A. V_REFis taken internally from V_DDand, as

such, V_DDshould be well decoupled. This provides an analog

input range of 0 V to V_DD. The conversion result is output in a

16-bit word with four leading zeros followed by the MSB of the

12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477A

is followed by two trailing zeros, and the 8-bit result from the

AD7478A is followed by four trailing zeros. Alternatively, because

the supply current required by the AD7476A/AD7477A/AD7478A

is so low, a precision reference can be used as the supply source

to the AD7476A/AD7477A/AD7478A. A REF19x voltage refer-

ence (REF195 for 5 V or REF193 for 3 V) can be used to supply

the required voltage to the ADC (see Figure 18). This configuration

is especially useful if the power supply is quite noisy, or if the

system supply voltages are at some value other than 5 V or 3 V

(for example, 15 V).

Table 7 provides typical performance data with various

references used as a V_DDsource for a 100 kHz input tone at

room temperature under the same setup conditions.

Table 7. AD7476A Typical Performance for Various Voltage

References

Reference Tied to V_DD

AD780 @ 3 V

REF193

AD780 @ 2.5 V

REF192

AD7476A SNR Performance (dB)

72.65

72.35

72.5

72.2

REF43

72.6

ANALOG INPUT

Figure 19 shows an equivalent circuit of the analog input

structure of the AD7476A/AD7477A/AD7478A. The two

diodes, D1 and D2, provide ESD protection for the analog

input. Care must be taken to ensure that the analog input signal

never exceeds the supply rails by more than 300 mV. This

causes the diodes to become forward-biased and start

conducting current into the substrate. The maximum current

these diodes can conduct without causing irreversible damage

to the part is 10 mA. The Capacitor C1 in Figure 19 is typically

about 6 pF and can primarily be attributed to pin capacitance.

The Resistor R1 is a lumped component made up of the on

resistance of a switch. This resistor is typically about 100 Ω. The

Capacitor C2 is the ADC sampling capacitor and has a

capacitance of 20 pF typically.

The REF19x outputs a steady voltage to the AD7476A/

AD7477A/AD7478A. If the low dropout REF193 is used, the

current it needs to supply to the AD7476A/AD7477A/ AD7478A is

typically 1.2 mA. When the ADC is converting at a rate of 1

MSPS, the REF193 needs to supply a maximum of 1.7 mA to the

AD7476A/AD7477A/AD7478A. The load regulation of the

REF193 is typically 10 ppm/mA (V_S= 5 V), resulting in an error

of 17 ppm (51 µV) for the 1.7 mA drawn from it. This corresponds

to a 0.069 LSB error for the AD7476A with V_DD= 3 V from the

REF193, a 0.017 LSB error for the AD7477A, and a 0.0043 LSB

error for the AD7478A.

For ac applications, removing high frequency components from

the analog input signal is recommended by use of a band-pass

filter on the relevant analog input pin. In applications where

harmonic distortion and signal-to-noise ratio are critical, drive

the analog input from a low impedance source. Large source

impedances significantly affect the ac performance of the ADC,

necessitating the use of an input buffer amplifier. The choice of

the op amp is a function of the particular application.

For applications where power consumption is a concern, use the

power-down mode of the ADC and the sleep mode of the

REF19x reference to improve power performance. See the

Modes of Operation section.

3V

5V

SUPPLY

REF193

1µF

TANT

0.1µF

10µF

0.1µF

1.2mA

680nF

V

DD

V

DD

0VTOV

DD

SCLK

V

IN

AD7476A/

AD7477A/

AD7478A

INPUT

µC/µP

C2

20pF

D1

D2

SDATA

CS

R1

GND

V

IN

C1

6pF

SERIAL

INTERFACE

Figure 18. REF193 as Power Supply to AD7476A/

AD7477A/AD7478A

CONVERSION PHASE – SWITCH OPEN

TRACK PHASE – SWITCH CLOSED

Figure 19. Equivalent Analog Input Circuit

Rev. F | Page 16 of 28

AD7476A/AD7477A/AD7478A

Table 8 provides typical performance data with various op amps

used as the input buffer for a 100 kHz input tone at room

temperature under the same setup conditions.

DIGITAL INPUTS

The digital inputs applied to the AD7476A/AD7477A/AD7478A

are not limited by the maximum ratings that limit the analog

input. Instead, the digital inputs applied can reach 7 V and are

not restricted by the V_DD+ 0.3 V limit as on the analog input.

For example, if operating the AD7476A/AD7477A/AD7478A

with a V_DDof 3 V, u s e 5 V logic levels on the digital inputs.

However, note that the data output on SDATA still has 3 V logic

Table 8. AD7476A Typical Performance with Various Input

Buffers, V_DD= 3 V

Op Amp in the Input Buffer AD7476A SNR Performance (dB)

AD711

AD797

AD845

72.3

72.5

71.4

CS

levels when V_DD= 3 V. Another advantage of SCLK and

being restricted by the V_DD+ 0.3 V limit is that power supply

CS

not

When no amplifier is used to drive the analog input, limit the

source impedance to low values. The maximum source imped-

ance depends on the amount of total harmonic distortion (THD)

that can be tolerated. The THD increases as the source impedance

increases, degrading the performance (see Figure 13).

sequencing issues are avoided. If

or SCLK are applied before

V_DD, there is no risk of latch-up as there would be on the analog

input if a signal greater than 0.3 V were applied prior to V_DD.

Rev. F | Page 17 of 28

AD7476A/AD7477A/AD7478A

MODES OF OPERATION

CS

Once

part enters power-down, the conversion that was initiated by

CS

has been brought high in this window of SCLKs, the

The modes of operation for the AD7476A/AD7477A/AD7478A

CS

are selected by controlling the (logic) state of the

a conversion. There are two possible modes of operation: normal

CS

signal during

the falling edge of

three-state. If

edge, the part remains in normal mode and does not power

down. This avoids accidental power-down due to glitches on the

is terminated, and SDATA goes back into

is brought high before the second SCLK falling

CS

and power-down. The point at which

is pulled high after the

conversion has been initiated determines whether the AD7476A/

AD7477A/AD7478A enters power-down mode. Similarly, if

CS

line. In order to exit this mode of operation and power up

the AD7476A/AD7477A/AD7478A again, a dummy conversion

CS

already in power-down,

can control whether the device returns

to normal operation or remains in power-down. These modes of

operation are designed to provide flexible power management

options. These options can be chosen to optimize the power

dissipation/throughput rate ratio for different application

requirements.

is performed. On the falling edge of , the device begins to

CS

power up and continues to power up as long as

is held low

until after the falling edge of the 10th SCLK. The device is fully

powered up once 16 SCLKs have elapsed, and valid data results

from the next conversion, as shown in Figure 24. If

brought high before the 10th falling edge of SCLK, then the

AD7476A/AD7477A/AD7478A go back into power-down. This

CS

is

NORMAL MODE

This mode is intended for the fastest throughput rate performance.

In normal mode, the user does not have to worry about any

power-up times because AD7476A/AD7477A/AD7478A

remain fully powered at all times. Figure 20 shows the general

diagram of the operation of the AD7476A/AD7477A/AD7478A

in this mode. The conversion is initiated on the falling edge of

CS

avoids accidental power-up due to glitches on the

line or an

is low.

Although the device can begin to power up on the falling edge

CS

inadvertent burst of eight SCLK cycles while

CS

of , it powers down again on the rising edge of as long as it

occurs before the 10th SCLK falling edge.

CS

as described in the Serial Interface section. To ensure that

POWER-UP TIME

CS

the part remains fully powered up at all times,

must remain

low until at least 10 SCLK falling edges have elapsed after the

CS CS

The power-up time of the AD7476A/AD7477A/AD7478A is

1 µs, meaning that with any frequency of SCLK up to 20 MHz,

one dummy cycle is always sufficient to allow the device to

power up. Once the dummy cycle is complete, the ADC is fully

powered up and the input signal is acquired properly. The quiet

time, t_QUIET, must still be allowed from the point where the bus

goes back into three-state after the dummy conversion to the

falling edge of . If

is brought high any time after the 10th

SCLK falling edge but before the end of the t_CONVERT, the part

remains powered up, but the conversion is terminated and

SDATA goes back into three-state. For the AD7476A, 16 serial

clock cycles are required to complete the conversion and access

the complete conversion results. For the AD7477A and AD7478A,

a minimum of 14 and 12 serial clock cycles are required to com-

plete the conversion and access the complete conversion results,

CS

next falling edge of . When running at a 1 MSPS throughput

rate, the AD7476A/AD7477A/AD7478A power up and acquire

a signal within 0.5 LSB in one dummy cycle, that is, 1 µs.

CS

respectively.

CS

can idle high until the next conversion or idle

returns high sometime prior to the next conversion

CS

low until

(effectively idling

(SDATA has returned to three-state), another conversion can be

When powering up from the power-down mode with a dummy

cycle, as in Figure 22, the track-and-hold that was in hold mode

while the part was powered down returns to track mode after

low). Once a data transfer is complete

CS

initiated after the quiet time, t_QUIET, has elapsed by bringing

low again.

CS

the first SCLK edge the part receives after the falling edge of

This is shown as Point A in Figure 22. Although at any SCLK

.

frequency, one dummy cycle is sufficient to power up the device

and acquire V_IN, it does not necessarily mean that a full dummy

cycle of 16 SCLKs must always elapse to power up the device

and acquire V_INfully; 1 µs is sufficient to power up the device

and acquire the input signal. If, for example, a 5 MHz SCLK

frequency is applied to the ADC, the cycle time becomes 3.2 µs.

In one dummy cycle, 3.2 µs, the part powers up and V_IN

POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered down

between each conversion, or a series of conversions is performed

at a high throughput rate and the ADC is then powered down

for a relatively long duration between these bursts of several

conversions. When the AD7476A/AD7477A/AD7478A are in

power-down, all analog circuitry is powered down. To enter

power-down, the conversion process must be interrupted by

acquires fully. However, after 1 µs with a 5 MHz SCLK, only five

SCLK cycles would have elapsed. At this stage, the ADC would

CS

fully power up and acquire the signal. In this case, the

can be

CS

bringing high anywhere after the second falling edge of SCLK

brought high after the 10th SCLK falling edge and brought low

again after a time, t_QUIET, to initiate the conversion.

and before the 10th falling edge of SCLK, as shown in Figure 22.

Rev. F | Page 18 of 28

AD7476A/AD7477A/AD7478A

CS

1

10

12

14

16

SCLK

SDATA

VALID DATA

Figure 20. Normal Mode Operation

CS

1

2

10

12

14

16

SCLK

THREE-STATE

SDATA

Figure 21. Entering Power-Down Mode

THE PART IS FULLY

POWERED UPWITH

THE PART

BEGINSTO

POWER UP

V

FULLY ACQUIRED

IN

CS

A

1

10 12

14

16

1

16

SCLK

SDATA

INVALID DATA

VALID DATA

Figure 22. Exiting Power-Down Mode

Instead, a dummy cycle can occur directly after power is

supplied to the ADC. If the first valid conversion is performed

directly after the dummy conversion, care must be taken to

ensure that an adequate acquisition time has been allowed. As

mentioned earlier, when powering up from the power-down

mode, the part returns to track upon the first SCLK edge

When power supplies are first applied to the AD7476A/AD7477A/

AD7478A, the ADC can power up in either the power-down or

normal modes. Because of this, it is best to allow a dummy cycle

to elapse to ensure that the part is fully powered up before

attempting a valid conversion. Likewise, if it is intended to keep

the part in the power-down mode while not in use and the user

wishes the part to power up in power-down mode, the dummy

cycle can be used to ensure that the device is in power-down by

executing a cycle such as that shown in Figure 22. Once supplies

are applied to the AD7476A/AD7477A/AD7478A, the power-up

time is the same as that when powering up from the power-down

mode. It takes approximately 1 μs to power up fully if the part

powers up in normal mode. It is not necessary to wait 1 μs before

executing a dummy cycle to ensure the desired mode of operation.

CS

applied after the falling edge of . However, when the ADC

initially powers up after supplies are applied, the track-and-hold

is already in track. This means, assuming one has the facility to

monitor the ADC supply current, if the ADC powers up in the

desired mode of operation and thus a dummy cycle is not

required to change the mode, a dummy cycle is not required to

place the track-and-hold into track.

Rev. F | Page 19 of 28

AD7476A/AD7477A/AD7478A

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7476A/AD7477A/

AD7478A when not converting, the average power consump-

tion of the ADC decreases at lower throughput rates. Figure 23

shows that as the throughput rate is reduced, the device remains

in its power-down state longer and the average power consumption

over time drops accordingly.

If V_DD= 3 V, SCLK = 20 MHz, and the devices are again in

power-down mode between conversions, then the power

dissipation during normal operation is 5.1 mW. Thus, the

AD7576A/AD7477A/AD8478A dissipate 5.1 mW for 2 μs

during each conversion cycle. With a throughput rate of

100 kSPS, the average power dissipated during each cycle is

(2/10) × (5.1 mW) = 1.02 m W.

For example, if the AD7476A/AD7477A/AD7478A operate in a

continuous sampling mode with a throughput rate of 100 kSPS

and an SCLK of 20 MHz (V_DD= 5 V) and the devices are placed

in the power-down mode between conversions, the power

consumption is calculated as follows:

Figure 23 shows the power vs. the throughput rate when using

the power-down mode between conversions with both 5 V and

3 V supplies. The power-down mode is intended for use with

throughput rates of approximately 333 kSPS or less, because at

higher sampling rates, the power-down mode produces no

power savings.

The power dissipation during normal operation is 17.5 mW

(V_DD= 5 V). If the power-up time is one dummy cycle, that is,

1 μs, and the remaining conversion time is another cycle, that is,

1 μs, then the AD7476A/AD7477A/AD7478A dissipate 17.5 mW

for 2 μs during each conversion cycle.

100

V

= 5V, SCLK = 20MHz

DD

10

1

If the throughput rate is 100 kSPS, the cycle time is 10 μs, then

the average power dissipated during each cycle is (2/10) ×

(17.5 mW) = 3.5 mW.

V

= 3V, SCLK = 20MHz

DD

0.1

0.01

0

50

100

150

200

250

300

350

THROUGHPUT (kSPS)

Figure 23. Power vs. Throughput

Rev. F | Page 20 of 28

AD7476A/AD7477A/AD7478A

SERIAL INTERFACE

falling edge, as shown in Figure 24. Sixteen serial clock cycles

are required to perform the conversion process and to access

data from the AD7476A.

Figure 24, Figure 25, and Figure 26 show the detailed timing

diagrams for serial interfacing to the AD7476A, AD7477A, and

AD7478A, respectively. The serial clock provides the conversion

clock and also controls the transfer of information from the

AD7476A/AD7477A/AD7478A during conversion.

For the AD7477A, the conversion requires 14 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, the track-

and-hold goes back into track on the next rising edge as shown

CS

The

signal initiates the data transfer and conversion process.

CS

at Point B in Figure 25. If the rising edge of

occurs before

The falling edge of

puts the track-and-hold into hold mode

14 SCLKs have elapsed, the conversion is terminated and the

SDATA line goes back into three-state. If 16 SCLKs are

considered in the cycle, SDATA returns to three-state on the

16th SCLK falling edge, as shown in Figure 25.

and takes the bus out of three-state; the analog input is sampled

at this point. Also, the conversion is initiated at this point.

For the AD7476A, the conversion requires 16 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, the track-

and-hold goes back into track on the next SCLK rising edge, as

shown in Figure 24 at Point B. On the 16th SCLK falling edge,

the SDATA line goes back into three-state. If the rising edge of

For the AD7478A, the conversion requires 12 SCLK cycles to

complete. The track-and-hold goes back into track on the rising

edge after the 11th falling edge, as shown in Figure 26 at Point B. If

CS

the rising edge of occurs before 12 SCLKs have elapsed, the

CS

occurs before 16 SCLKs have elapsed, the conversion is

conversion is terminated and the SDATA line goes back into three-

state. If 16 SCLKs are considered in the cycle, SDATA returns to

three-state on the 16th SCLK falling edge, as shown in Figure 26.

t₁

terminated and the SDATA line goes back into three-state;

otherwise, SDATA returns to three-state on the 16th SCLK

CS

t_CONVERT

t₂

t₆

B

SCLK

1

2

3

4

5

13

14

t₅

15

16

t₈

t₃

t₄

t₇

t_QUIET

SDATA

Z

ZERO

DB11

DB10

DB2

DB1

DB0

THREE-

STATE

THREE-STATE

4 LEADING ZEROS

1/THROUGHPUT

Figure 24. AD7476A Serial Interface Timing Diagram

t₁

CS

t_CONVERT

t₂

t₆

B

1

2

3

4

5

13

14

t₅

15

16

SCLK

t₈

t_QUIET

t₇

DB8

t₃

t₄

Z

ZERO

DB9

DB0

ZERO

SDATA

THREE-STATE

4 LEADING ZEROS

2 TRAILING ZEROS

1/THROUGHPUT

Figure 25. AD7477A Serial Interface Timing Diagram

t₁

CS

t_CONVERT

t₆

B

t₂

13

11

12

SCLK

3

4

14

t₅

15

16

t₈

1

2

t_QUIET

t₇

t₃

t₄

Z

ZERO

DB7

ZERO

SDATA

THREE-STATE

4 TRAILING ZEROS

4 LEADING ZEROS

1/ THROUGHPUT

Figure 26. AD7478A Serial Interface Timing Diagram

Rev. F | Page 21 of 28

AD7476A/AD7477A/AD7478A

CS

going low clocks out the first leading zero to be read in by

AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE

the microcontroller or DSP. The remaining data is then clocked

out by subsequent SCLK falling edges beginning with the

second leading zero. Thus, the first falling clock edge on the

serial clock has the first leading zero provided and also clocks

out the second leading zero. For the AD7476A, the final bit in

the data transfer is valid on the 16th falling edge, having been

clocked out on the previous (15th) falling edge.

CS

For the AD7478A, if

is brought high in the 12th rising edge

after four leading zeros and eight bits of the conversion have

been provided, the part can achieve a 1.2 MSPS throughput

rate. For the AD7478A, the track-and-hold goes back into track

in the 11th rising edge. In this case, a f_SCLK= 20 MHz and a

throughput of 1.2 MSPS give a cycle time of

t₂+ 10.5(1/f_SCLK)+ t_ACQ= 833 ns

In applications with a slower SCLK, it is possible to read in data

on each SCLK rising edge. In this case, the first falling edge of

SCLK clocks out the second leading zero, which can be read in

the first rising edge. However, the first leading zero that was

With t₂= 10 ns min, this leaves t_ACQto be 298 ns. This 298 ns

satisfies the requirement of 225 ns for t_ACQ

.

From Figure 27, t_ACQis comprised of

CS

clocked out when

went low will be missed, unless it was not

0.5 (1/f_SCLK) + t₈+ t_QUIET

read in the first falling edge. The 15th falling edge of SCLK clocks

out the last bit and it can be read in the 15th rising SCLK edge.

where t₈= 36 ns maximum.

CS

goes low just after one SCLK falling edge has elapsed,

If

This allows a value of 237 ns for t_QUIET, satisfying the minimum

requirement of 50 ns.

clocks out the first leading zero as it did before, and it can be

read in the SCLK rising edge. The next SCLK falling edge clocks

out the second leading zero, and it can be read in the following

rising edge.

t₁

CS

t_CONVERT

t₂

B

SCLK

1

2

3

4

5

11

12

t₈

t_QUIET

t_ACQ

10.5(1/f_SCLK

)

SDATA

THREE-STATE

Z

ZERO

4 LEADING ZEROS

ZERO

DB7

DB6

DB0

ZERO

THREE-STATE

1/THROUGHPUT

Figure 27. AD7478A in a 12 SCLK Cycle Serial Interface

Rev. F | Page 22 of 28

AD7476A/AD7477A/AD7478A

MICROPROCESSOR INTERFACING

The connection diagram is shown in Figure 28. For signal

processing applications, it is imperative that the frame

synchronization signal from the TMS320C541 provide

equidistant sampling.

The serial interface on the AD7476A/AD7477A/AD7478A

allows the part to be directly connected to a range of different

microprocessors. This section explains how to interface the

AD7476A/AD7477A/AD7478A with some of the more

common microcontroller and DSP serial interface protocols.

TMS320C541¹

AD7476A/

AD7477A/

AD7476A/AD7477A/AD7478A TO TMS320C541

INTERFACE

AD7478A¹

SCLK

CLKX

CLKR

DR

The serial interface on the TMS320C541 uses a continuous

serial clock and frame synchronization signals to synchronize

the data transfer operations with peripheral devices, such as

SDATA

CS

the AD7476A/AD7477A/AD7478A. The

input allows easy

FSX

interfacing between the TMS320C541 and the AD7476A/

AD7477A/AD7478A without any glue logic required. The serial

port of the TMS320C541 is set up to operate in burst mode

(FSM = 1 in the serial port control register, SPC) with Internal

Serial Clock CLKX (MCM = 1 in the SPC register) and internal

frame signal (TXM = 1 in the SPC register), so both pins are

configured as outputs. For the AD7476A, set the word length to

16 bits (FO = 0 in the SPC register). This DSP only allows

frames with a word length of 16 bits or 8 bits. Therefore, in the

case of the AD7477A and AD7478A where 14 bits and 12 bits

are required, the FO bit is set up to 16 bits. This means that to

obtain the conversion result, 16 SCLKs are needed. In both

situations, the remaining SCLKs clock out trailing zeros. For the

AD7477A, two trailing zeros are clocked out in the last two clock

cycles; for the AD7478A, four trailing zeros are clocked out.

FSR

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 28. Interfacing to the TMS320C541

AD7476A/AD7477A/AD7478A TO ADSP-218x

INTERFACE

The ADSP-218x family of DSPs are interfaced directly to the

AD7476A/AD7477A/AD7478A without any glue logic

required. Set up the SPORT control register as follows:

TFSW = RFSW = 1, alternate framing

INVRFS = INVTFS = 1, active low frame signal

DTYPE = 00, right justify data

ISCLK = 1, internal serial clock

TFSR = RFSR = 1, frame every word

IRFS = 0, sets up RFS as an input

ITFS = 1, sets up TFS as an output

SLEN = 1111, 16 bits for the AD7476A

SLEN = 1101, 14 bits for the AD7477A

SLEN = 1011, 12 bits for the AD7478A

To summarize, the values in the SPC register are

FO = 0

FSM = 1

MCM = 1

TXM = 1

The format bit, FO, can be set to 1 to set the word length to

eight bits in order to implement the power-down mode on the

AD7476A/AD7477A/AD7478A.

Rev. F | Page 23 of 28

AD7476A/AD7477A/AD7478A

AD7476A/AD7477A/AD7478A TO DSP563xx

INTERFACE

To implement the power-down mode, set SLEN to 0111 to issue

an 8-bit SCLK burst. The connection diagram is shown in

Figure 29. The ADSP-218x has the TFS and RFS of the SPORT

tied together, with TFS set as an output and RFS set as an input.

The DSP operates in alternate framing mode, and the SPORT

control register is set up as described. The frame synchronization

The connection diagram in Figure 30 shows how the

AD7476A/AD7477A/AD7478A can be connected to the SSI

(synchronous serial interface) of the DSP563xx family of DSPs

from Motorola. The SSI is operated in synchronous and normal

mode (SYN 1 = and MOD = 0 in Control Register B, CRB) with

internally generated word length frame sync for both Tx and Rx

(Bit FSL1 = 0 and Bit FSL0 = 0 in CRB). Set the word length in

Control Register A (CRA) to 16 by setting Bit WL2 = 0, Bit

WL1 = 1, and Bit WL0 = 0 for the AD7476A. The word length

for the AD7478A can be set to 12 bits (WL2 = 0, WL1 = 0, and

WL0 = 1). This DSP does not offer the option for a 14-bit word

length, so the AD7477A word length is set up to 16 bits, the

same as the AD7476A. For the AD7477A, the conversion process

uses 16 SCLK cycles, with the last two clock periods clocking out

two trailing zeros to fill the 16-bit word.

CS

signal generated on the TFS is tied to , and, as with all signal

processing applications, equidistant sampling is necessary.

However, in this example, the timer interrupt is used to control

the sampling rate of the ADC and, under certain conditions,

equidistant sampling may not be achieved.

ADSP-218x¹

AD7476A/

AD7477A/

AD7478A¹

SCLK

SDATA

CS

SCLK

DR

RFS

TFS

To implement the power-down mode on the AD7476A/AD7477A/

AD7478A, the word length can be changed to eight bits by setting

Bit WL2 = 0, Bit WL1 = 0, and Bit WL0 = 0 in CRA. The FSP

bit in the CRB register can be set to 1, meaning the frame goes

low and a conversion starts. Likewise, by means of the Bit SCD2,

Bit SCKD, and Bit SHFD in the CRB register, it establishes that

Pin SC2 (the frame sync signal) and Pin SCK in the serial port

are configured as outputs and the MSB is shifted first.

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 29. Interfacing to the ADSP-218x

The timer registers, for example, are loaded with a value that

provides an interrupt at the required sample interval. When an

interrupt is received, a value is transmitted with TFS/DT (ADC

control word). The TFS controls the RFS and, thus, the reading

of data. The frequency of the serial clock is set in the SCLKDIV

register. When the instruction to transmit with TFS is given,

that is, TX0 = AX0, the state of the SCLK is checked. The DSP

waits until the SCLK has gone high, low, and high before

transmission starts. If the timer and SCLK values are chosen

such that the instruction to transmit occurs on or near the

rising edge of SCLK, the data can be transmitted or it can wait

until the next clock edge. For example, the ADSP-2111 has a

master clock frequency of 16 MHz. If the SCLKDIV register is

loaded with the Value 3, an SCLK of 2 MHz is obtained and

eight master clock periods will elapse for every one SCLK

period. If the timer registers are loaded with the Value 803,

100.5 SCLKs occur between interrupts and, subsequently,

between transmit instructions. This situation results in

nonequidistant sampling as the transmit instruction is

occurring on an SCLK edge. If the number of SCLKs between

interrupts is a whole integer figure of N, equidistant sampling is

implemented by the D SP.

In summary:

MOD = 0

SYN = 1

WL2, WL1, and WL0 depend on the word length

FSL1 = 0 and FSL0 = 0

FSP = 1, negative frame sync

SCD2 = 1

SCKD = 1

SHFD = 0

Note that for signal processing applications, it is imperative that

the frame synchronization signal from the DSP563xx provide

equidistant sampling.

DSP563xx¹

AD7476A/

AD7477A

AD7478A¹SCLK

SCK

SDATA

CS

SRD

SC2

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 30. Interfacing to the DSP563xx

Rev. F | Page 24 of 28

AD7476A/AD7477A/AD7478A

APPLICATION HINTS

As can be seen in Figure 32, for the MSOP package, the

decoupling capacitor has been placed as close as possible to the

IC with short track lengths to V_DDand GND pins. The

decoupling capacitor can also be placed on the underside of the

PCB directly underneath the IC, between the V_DDand GND

pins attached by vias. This method is not recommended on

PCBs above a standard 1.6 mm thickness. The best performance

is realized with the decoupling capacitor on the top of the PCB

next to the IC.

GROUNDING AND LAYOUT

Design the printed circuit board that houses the AD7476A/

AD7477A/AD7478A such that the analog and digital sections

are separated and confined to certain areas of the board. This

facilitates the use of ground planes that can be separated easily.

A minimum etch technique is generally best for ground planes

because it gives the best shielding. Join digital and analog

ground planes at only one place. If the AD7476A/AD7477A/

AD7478A is in a system where multiple devices require an

AGND to DGND connection, make the connection at one

point only, a star ground point that is established as close as

possible to the AD7476A/AD7477A/AD7478A.

Similarly, for the SC70 package, locate the decoupling capacitor

as close as possible to the V_DDand the GND pins. Because of its

pinout, that is, V_DDbeing next to GND, the decoupling capacitor

can be placed extremely close to the IC. The decoupling capacitor

can be placed on the underside of the PCB directly under the

Avoid running digital lines under the device as these couple

noise onto the die. Allow the analog ground plane to run under

the AD7476A/AD7477A/AD7478A in order to avoid noise

coupling. Use as large a trace as possible on the power supply

lines to the AD7476A/AD7477A/AD7478A to provide low

impedance paths and reduce the effects of glitches on the power

supply line. Shield fast switching signals like clocks with digital

grounds to avoid radiating noise to other sections of the board,

and never run clock signals near the analog inputs. Avoid crossover

of digital and analog signals. Run traces on opposite sides of the

board at right angles to each other. This reduces the effects of

feedthrough through the board. A microstrip technique is by far

the best but is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the solder side.

V_DDand GND pins, but the best performance is achieved with

the decoupling capacitor on the same side as the IC.

Figure 32. Recommended Supply Decoupling Scheme for the

AD7476A/AD7477A/AD7478A MSOP Package

Good decoupling is also very important. Decouple the supply

with, for instance, a 680 nF 0805 capacitor to GND. When using

the SC70 package in applications where the size of the components

is of concern, a 220 nF 0603 capacitor, for example, can be used

instead. However, in that case, the decoupling may not be as

effective, resulting in an approximate SINAD degradation of

0.3 dB. To achieve the best performance from these decoupling

components, the user should endeavor to keep the distance

between the decoupling capacitor and the V_DDand GND pins to

a minimum with short track lengths connecting the respective

pins. Figure 31 and Figure 32 and show the recommended

positions of the decoupling capacitor for the SC70 and MSOP

packages, respectively.

EVALUATING THE AD7476A/AD7477A

PERFORMANCE

The evaluation board package includes a fully assembled and

tested evaluation board, documentation, and software for

controlling the board from the PC via the EVAL-BOARD

CONTROLLER. The EVAL-BOARD CONTROLLER can be

used in conjunction with the AD7476ACB/AD7477ACB

evaluation board, as well as many other Analog Devices

evaluation boards ending in the CB designator, to

demonstrate/evaluate the ac and dc performance of the

AD7476A/AD7477A. The software allows the user to perform

ac (fast Fourier transform) and dc (histogram of codes) tests on

the AD7476A/AD7477A. See the evaluation board application

note for more information.

Figure 31. Recommended Supply Decoupling Scheme for the SC70 Package

Rev. F | Page 25 of 28

AD7476A/AD7477A/AD7478A

OUTLINE DIMENSIONS

3.20

3.00

2.80

2.20

2.00

1.80

8

1

5

4

2.40

2.10

1.80

5.15

4.90

4.65

6

1

5

2

4

3

1.35

1.25

1.15

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.65 BSC

1.30 BSC

1.00

0.65 BSC

0.40

0.10

1.10

0.90

0.70

0.95

0.85

0.75

15° MAX

0.80

1.10 MAX

0.80

0.55

0.40

0.46

0.36

0.26

0.15

0.05

0.22

0.08

0.23

0.09

SEATING

PLANE

6°

0°

0.10 MAX

0.40

0.25

0.30

0.15

COPLANARITY

0.10

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-203-AB

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 33. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

Figure 34. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

(KS-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2, 3, 4}

Temperature Range

–40°C to +85°C

–40°C to +125°C

–40°C to +85°C

Linearity Error (LSB)⁵

0.75 typical

Package Description

6-Lead SC70

8-Lead MSOP

6-Lead SC70

8-Lead MSOP

6-Lead SC70

8-Lead MSOP

6-Lead SC70

8-Lead MSOP

Package Option⁶

KS-6

RM-8

KS-6

Branding

C3V

C3W

CEY

C3W

C45

C3X

CFZ

C3X

C48

CJZ

AD7476AAKSZ-500RL7

AD7476AAKSZ-REEL

AD7476AAKSZ-REEL7

AD7476ABKSZ-500RL7

AD7476ABKSZ-REEL

AD7476ABKSZ-REEL7

AD7476ABRM

AD7476ABRM-REEL

AD7476ABRM-REEL7

AD7476ABRMZ

AD7476ABRMZ-REEL

AD7476ABRMZ-REEL7

AD7476AWYRMZ

AD7476AWYRMZ-RL7

AD7476AYKSZ-500RL7

AD7476AYKSZ-REEL7

AD7476AYRMZ

AD7476AYRMZ-REEL7

AD7477AAKSZ-500RL7

AD7477AAKSZ-REEL

AD7477AARM-REEL

AD7477AARMZ

AD7477AARMZ-REEL

AD7477AARMZ-REEL7

AD7477AWARMZ

AD7477AWARMZ-RL

AD7478AAKSZ-500RL7

AD7478AAKSZ-REEL

AD7478AAKSZ-REEL7

AD7478AARM

1.5 maximum

0.5 maximum

0.3 maximum

KS-6

RM-8

KS-6

RM-8

KS-6

RM-8

AD7478AARMZ

C48

Rev. F | Page 26 of 28

AD7476A/AD7477A/AD7478A

Model^{1, 2, 3, 4}

Temperature Range

–40°C to +85°C

Linearity Error (LSB)⁵

0.3 maximum

Package Description

8-Lead MSOP

Package Option⁶

RM-8

Branding

C48

AD7478AARMZ-REEL

AD7478AARMZ-REEL7

AD7478AWARMZ

AD7478AWARMZ-RL

EVAL-AD7476ACBZ

EVAL-CONTROL BRD2

0.3 maximum

RM-8

Evaluation Board

Evaluation Control

¹Z = RoHS Compliant Part.

²W = Qualified for Automotive Applications.

³EVAL-AD7476ACBZ can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.

⁴EVAL-CONTROL BRD2 is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a

complete evaluation kit, you will need to order the particular ADC evaluation board, for example, EVAL-AD7476ACB, the EVAL-CONTROLBRD2, and a 12 V ac

transformer. See relevant evaluation board application note for more information.

⁵Linearity error here refers to integral nonlinearity.

⁶KS = SC70; RM = MSOP.

AUTOMOTIVE PRODUCTS

The AD7476AWYRMZ, AD7476AWYRMZ-RL7, AD7477AWARMZ, AD7477AWARMZ-RL, AD7478AWARMZ, and

AD7478AWARMZ-RL models are available with controlled manufacturing to support the quality and reliability requirements of

automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,

designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for

use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and

to obtain the specific Automotive Reliability reports for these models.

Rev. F | Page 27 of 28

AD7476A/AD7477A/AD7478A

NOTES

registered trademarks are the property of their respective owners.

D02930-0-1/11(F)

Rev. F | Page 28 of 28


型号：	AD7478A_15
厂家：	ADI
描述：	2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70
文件：	总29页 (文件大小：689K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7478A_15 [ADI]

相关型号：

AD7478SRT-500RL7

AD7478SRT-R2

AD7478SRT-R2

AD7478SRT-REEL7

AD7478SRTZ-REEL7

AD7478SRTZ-REEL7

AD7478SRTZ-REEL73

AD7478WARTZ-RL734

AD7478_15

AD7482

AD7482AST

AD7482ASTZ