AD7492ARU-5-REEL [ADI]
1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC; 1.25 MSPS ， 16毫瓦内部REF和CLK ， 12位并行ADC
| 型号： | AD7492ARU-5-REEL |
| 厂家： | 
ADI |
| 描述： | 1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC |
| 文件： | 总24页 (文件大小：513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.25 MSPS, 16 mW Internal REF and CLK,
12-Bit Parallel ADC
AD7492
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AV
DV
V
Specified for VDD of 2.7 V to 5.25 V
Throughput rate of 1 MSPS (AD7492)
Throughput rate of 1.25 MSPS (AD7492-5)
Throughput rate of 400 kSPS (AD7492-4)
Low power
DD
DD
20
DRIVE
21
REF OUT
5
4
2.5V
REF
CLOCK
OSCILLATOR
BUF
4 mW typ at 1 MSPS with 3 V supplies
11 mW typ at 1 MSPS with 5 V supplies
Wide input bandwidth
DB11
DB0
OUTPUT
DRIVERS
6
12-BIT SAR
ADC
T/H
V
IN
70 dB typ SNR at 100 kHz input frequency
2.5 V internal reference
On-chip CLK oscillator
Flexible power/throughput rate management
No pipeline delays
High speed parallel interface
Sleep mode: 50 nA typ
11
8
PS/FS
CS
CONTROL
LOGIC
10
CONVST
9
RD
AD7492
12
BUSY
7
19
DGND
24-lead SOIC and TSSOP packages
AGND
Figure 1.
GENERAL DESCRIPTION
FS
The type of sleep mode is hardware selected by the PS/ pin.
The AD7492, AD7492-4, and AD7492-5 are 12-bit high speed,
low power, successive approximation ADCs. The parts operate
from a single 2.7 V to 5.25 V power supply and feature
throughput rates up to 1.25 MSPS. They contain a low noise,
wide bandwidth track/hold amplifier that can handle
bandwidths up to 10 MHz.
Using these sleep modes allows very low power dissipation
numbers at lower throughput rates.
The analog input range for the part is 0 V to REFIN. The
2.5 V reference is supplied internally and is available for
external referencing. The conversion rate is determined by the
internal clock.
The conversion process and data acquisition are controlled
using standard control inputs allowing for easy interface to
microprocessors or DSPs. The input signal is sampled on the
PRODUCT HIGHLIGHTS
CONVST
falling edge of
and conversion is also initiated at this
1. High Throughput with Low Power Consumption. The
AD7492-5 offers 1.25 MSPS throughput with 16 mW
power consumption.
point. The BUSY pin goes high at the start of conversion and
goes low 880 ns (AD7492/AD7492-4) or 680 ns (AD7492-5)
later to indicate that the conversion is complete. There are no
pipeline delays associated with the part. The conversion result is
2. Flexible Power/Throughput Rate Management. The
conversion time is determined by an internal clock. The
part also features two sleep modes, partial and full, to
maximize power efficiency at lower throughput rates.
CS
RD
accessed via standard
parallel interface.
and
signals over a high speed
The AD7492 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and 1.25 MSPS, the average current consumption
AD7492-5 is typically 2.75 mA. The part also offers flexible
power/throughput rate management.
3. No Pipeline Delay. The part features a standard successive
approximation ADC with accurate control of the sampling
CONVST
instant via a
control.
input and once-off conversion
4. Flexible Digital Interface. The VDRIVE feature controls the
voltage levels on the I/O digital pins.
It is also possible to operate the part in a full sleep mode and a
partial sleep mode, where the part wakes up to do a conversion
and automatically enters a sleep mode at the end of conversion.
5. Fewer Peripheral Components. The AD7492 optimizes
PCB space by using an internal reference and internal CLK.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD7492
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Operation.................................................................. 13
Typical Connection Diagram ................................................... 13
ADC Transfer Function............................................................. 13
AC Acquisition Time................................................................. 14
DC Acquisition Time................................................................. 14
Analog Input ............................................................................... 14
Parallel Interface......................................................................... 14
Operating Modes........................................................................ 14
Power-Up..................................................................................... 16
Grounding and Layout .............................................................. 18
Power Supplies............................................................................ 18
Microprocessor Interfacing....................................................... 18
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights....................................................................... 1
Revision History........................................................................... 2
Specifications..................................................................................... 3
AD7492-5 ...................................................................................... 3
AD7492/AD7492-4 ...................................................................... 4
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Peformance Characteristics............................................. 10
Terminology .................................................................................... 12
Circuit Description......................................................................... 13
REVISION HISTORY
5/06—Rev. 0 to Rev. A
Added AD7492-4................................................................Universal
Changes to Table 4............................................................................ 8
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 22
1/01—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD7492
SPECIFICATIONS
AD7492-5
VDD = 4.75 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)
fS = 1.25 MSPS
69
68
70
68
−83
−87
−75
−83
69
68
70
68
−83
−87
−75
−83
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious-Free
Dynamic Noise (SFDR)
−90
−76
−90
−76
dB typ
dB max
fIN = 100 kHz sine wave
fIN = 100 kHz sine wave
Intermodulation Distortion (IMD)
Second Order Terms
−82
−90
−71
−88
5
−82
−90
−71
−88
5
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave
fIN = 100 kHz sine wave
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
15
10
15
10
fS = 1.25 MSPS
Resolution
12
12
Bits
Integral Nonlinearity
Differential Nonlinearity
1.5
+1.5/–0.9
1.25
+1.5/−0.9
LSB max
LSB max
Guaranteed no missed codes to
12 bits (A and B versions)
Offset Error
Gain Error
9
2.5
9
2.5
LSB max
LSB max
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE OUTPUT
REF OUT Output Voltage Range
LOGIC INPUTS
0 to 2.5
1
33
0 to 2.5
1
33
V
μA max
pF typ
2.5
2.5
V
1.5ꢀ for specified performance
2
Input High Voltage, VINH
VDRIVE × 0.7
VDRIVE × 0.3
1
10
VDRIVE × 0.7
VDRIVE × 0.3
1
10
V min
VDD = 5 V 5ꢀ
VDD = 5 V 5ꢀ
Typically 10 nA, VIN = 0 V or VDD
2
Input Low Voltage, VINL
V max
μA max
pF max
Input Current, IIN
Input Capacitance, CIN
3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
VDRIVE − 0.2
VDRIVE − 0.2
V min
ISOURCE = 200 μA
ISINK = 200 μA
0.4
10
10
0.4
10
10
V max
μA max
pF max
Straight (natural)
binary
Straight (natural)
binary
Rev. A | Page 3 of 24
AD7492
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
680
120
1.25
680
120
1.25
ns max
ns min
MSPS max
Conversion time + acquisition
time
POWER REQUIREMENTS
VDD
4.75/5.25
4.75/5.25
V min/max
IDD
Digital I/Ps = 0 V or DVDD
Normal Mode
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation4
Normal Mode
Partial Sleep Mode
Full Sleep Mode
3.3
1.8
250
1
3.3
1.8
250
1
mA max
mA max
μA max
μA max
fS = 1.25 MSPS, typ 2.75 mA
Static, typ 190 μA
Static, typ 200 nA
Digital I/Ps = 0 V or DVDD
16.5
1.25
5
16.5
1.25
5
mW max
mW max
μW max
1 Temperature ranges as follows: A and B Versions: −40°C to +85°C.
2 VINH and VINL trigger levels are set by the VDRIVE voltage. The logic interface circuitry is powered by VDRIVE
3 Sample tested @ 25°C to ensure compliance.
.
4 See the Power vs. Throughput section.
AD7492/AD7492-4
VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
A Version2
B Version2
Unit
Test Conditions/Comments
fS = 1 MSPS for AD7492
fS = 400 kSPS for AD7492-4
fIN = 500 kHz sine wave3
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave3
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave3
fIN = 100 kHz sine wave
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave3
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD) 69
68
69
68
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
Signal-to-Noise Ratio (SNR)
70
70
68
68
Total Harmonic Distortion (THD)
−85
−87
−75
−86
−85
−87
−75
−86
Peak Harmonic or Spurious-Free
Dynamic Noise (SFDR)
−90
−76
−90
−76
dB typ
dB max
fIN = 100 kHz sine wave
fIN = 100 kHz sine wave
Intermodulation Distortion (IMD)
Second Order Terms
−77
−90
−69
−88
5
−77
−90
−69
−88
5
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
fIN = 500 kHz sine wave3
fIN = 100 kHz sine wave
fIN = 500 kHz sine wave3
fIN = 100 kHz sine wave
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
15
10
15
10
Rev. A | Page 4 of 24
AD7492
Parameter
A Version2
B Version2
Unit
Test Conditions/Comments
DC ACCURACY
fS = 1 MSPS for AD7492
fS = 400 kSPS for AD7492-4
Resolution
12
12
Bits
Integral Nonlinearity
1.5
LSB max
LSB typ
LSB max
LSB max
0.6
1
+1.5/−0.9
VDD = 5 V
VDD = 3 V
Guaranteed no missed codes to
12 bits (A and B versions)
Differential Nonlinearity
+1.5/−0.9
Offset Error
Gain Error
9
2.5
9
2.5
LSB max
LSB max
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE OUTPUT
REF OUT Output Voltage Range
LOGIC INPUTS
0 to 2.5
1
33
0 to 2.5
1
33
V
μA max
pF typ
2.5
2.5
V
1.5ꢀ for specified performance
4
Input High Voltage, VINH
VDRIVE × 0.7
VDRIVE × 0.3
1
10
VDRIVE × 0.7
VDRIVE × 0.3
1
10
V min
VDD = 5 V 5ꢀ
VDD = 5 V 5ꢀ
Typically 10 nA, VIN = 0 V or VDD
4
Input Low Voltage, VINL
V max
μA max
pF max
Input Current, IIN
Input Capacitance, CIN
3, 5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
VDRIVE − 0.2
VDRIVE − 0.2
V min
ISOURCE = 200 μA
ISINK = 200 μA
0.4
10
10
0.4
10
10
V max
μA max
pF max
Straight (Natural)
Binary
Straight (Natural)
Binary
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
880
120
1
880
120
1
ns max
ns min
MSPS max
Conversion time + acquisition
time for AD7492
Conversion time + acquisition
time for AD7492-4
400
kSPS max
POWER REQUIREMENTS
VDD
IDD
2.7/5.25
3
2.7/5.25
3
V min/max
mA max
Digital I/Ps = 0 V or DVDD.
fS = 1 MSPS, typ 2.2 mA
fS = 400 kSPS, Typ 2.2 mA
(AD7492-4)
Normal Mode
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation4, 6
Normal Mode
1.8
250
1
1.8
250
1
mA max
μA max
μA max
Static, typ 190 μA
Static, typ 200 nA
Digital I/Ps = 0 V or DVDD
VDD = 5 V
VDD = 5 V
VDD = 5 V
15
1.25
5
15
1.25
5
mW max
mW max
μW max
Partial Sleep Mode
Full Sleep Mode
1 Only A version specification applies to the AD7492-4.
2 Temperature ranges as follows: A and B versions: −40°C to +85°C.
3 500 kHz sine wave specifications do not apply for the AD7492-4.
4 VINH and VINL trigger levels are set by the VDRIVE voltage. The logic interface circuitry is powered by VDRIVE
.
5 Sample tested @ 25°C to ensure compliance.
6 See the Power vs. Throughput section.
Rev. A | Page 5 of 24
AD7492
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 3.
Limit at TMIN, TMAX
Parameter
tCONVERT
tWAKEUP
AD7492/AD7492-4
AD7492-52
Unit
Description
880
203
500
10
10
40
0
680
203
500
10
10
N/A
0
ns max
μs max
μs max
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
Partial Sleep Wake-Up Time
Full Sleep Wake-Up Time
CONVST Pulse Width
t1
t2
CONVST to BUSY Delay, VDD = 5 V
CONVST to BUSY Delay, VDD = 3 V
BUSY to CS Setup Time
t3
4
t4
0
0
CS to RD Setup Time
t5
20
15
8
20
15
8
RD Pulse Width
4
t6
Data Access Time after Falling Edge of RD
Bus Relinquish Time after Rising Edge of RD
CS to RD Hold Time
5
t7
t8
0
0
t9
t10
120
100
120
100
Acquisition Time
Quiet Time
1 Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10ꢀ to 90ꢀ of VDD) and timed from a voltage level of 1.6 V (see Figure 2).
2 The AD7492-5 is specified with VDD = 4.75 V to 5.25 V.
3 This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 μs, but there is no guarantee that the part
samples within 0.5 LSB of the true analog input value. Therefore, the user should not start conversion until after the specified time.
4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V
5 t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. A | Page 6 of 24
AD7492
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Ratings
AVDD to AGND/DGND
DVDD to AGND/DGND
VDRIVE to AGND/DGND
AVDD to DVDD
VDRIVE to DVDD
AGND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Input Current to Any Pin Except
Supplies1
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
10 mA
Operating Temperature Range
Commercial (A and B Versions)
Storage Temperature Range
Junction Temperature
−40°C to +85°C
−65°C to +150°C
150°C
SOIC, TSSOP Package Dissipation
θJA Thermal Impedance
450 mW
75°C/W (SOIC)
115°C/W (TSSOP)
25°C/W (SOIC)
35°C/W (TSSOP)
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
215°C
220°C
1 Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 24
AD7492
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DB9
DB8
1
24
23
22
21
20
19
18
17
16
15
14
13
2
DB10
DB7
DB6
3
(MSB) DB11
4
AV
DD
V
DRIVE
5
REF OUT
DV
DD
AD7492
TOP VIEW
(Not to Scale)
V
IN
6
DGND
7
AGND
CS
DB5
DB4
DB3
8
RD
9
10
11
CONVST
PS/FS
DB2
DB1
BUSY 12
DB0 (LSB)
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin
Mnemonic
Function
1 to 3,
13 to 18,
22 to 24
DB11 to DB0
Data Bit 11 to Data Bit 0. Parallel digital outputs that provide the conversion result for the part. These are
three-state outputs that are controlled by CS and RD. The output high voltage level for these outputs is
determined by the VDRIVE input.
4
AVDD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7492.
The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart,
even on a transient basis. This supply should be decoupled to AGND.
5
6
REF OUT
VIN
Reference Out. The output voltage from this pin is 2.5 V 1ꢀ.
Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents
a high dc input impedance.
7
8
AGND
CS
Analog Ground. Ground reference point for all analog circuitry on the AD7492. All analog input signals
should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The
conversion result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both
connected to the same AND gate on the input so the signals are interchangeable. CS can be hardwired
permanently low.
9
RD
Read Input. Logic input used in conjunction with CS to access the conversion result. The conversion result is
placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to the
same AND gate on the input so the signals are interchangeable. CS and RD can be hardwired permanently
low, in which case the data bus is always active and the result of the new conversion is clocked out slightly
before to the BUSY line going low.
10
CONVST
Conversion Start Input. Logic input used to initiate conversion. The input track/hold amplifier goes from track
mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. The
conversion input can be as narrow as 10 ns. If the CONVST input is kept low for the duration of conversion
and is still low at the end of conversion, the part automatically enters a sleep mode. The type of sleep mode is
determined by the PS/FS pin. If the part enters a sleep mode, the next rising edge of CONVST wakes up the
part. Wake-up time depends on the type of sleep mode.
11
12
PS/FS
BUSY
Partial Sleep/Full Sleep Mode. This pin determines the type of sleep mode the part enters if the CONVST pin is
kept low for the duration of the conversion and is still low at the end of conversion. In partial sleep mode the
internal reference circuit and oscillator circuit are not powered down and draws 250 μA maximum. In full
sleep mode all of the analog circuitry are powered down and the current drawn is negligible. This pin is
hardwired either high (DVDD) or low (GND).
BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal goes high after
the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is
complete and the conversion result is in the output register, the BUSY line returns low. The track/hold returns
to track mode just prior to the falling edge of BUSY and the acquisition time for the part begins when BUSY
goes low. If the CONVST input is still low when BUSY goes low, the part automatically enters its sleep mode
on the falling edge of BUSY.
19
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7492. The DGND and AGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
Rev. A | Page 8 of 24
AD7492
Pin
Mnemonic
Function
20
DVDD
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7492 apart
from the output drivers and input circuitry. The DVDD and AVDD voltages should ideally be at the same
potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled
to DGND.
21
VDRIVE
Supply Voltage for the Output Drivers and Digital Input Circuitry, 2.7 V to 5.25 V. This voltage determines the
output high voltage for the data output pins and the trigger levels for the digital inputs. It allows the AVDD
and DVDD to operate at 5 V (and maximize the dynamic performance of the ADC) while the digital input and
output pins can interface to 3 V logic.
Rev. A | Page 9 of 24
AD7492
TYPICAL PEFORMANCE CHARACTERISTICS
71
70
69
0
–20
5V
68
–40
–60
67
66
3V
65
64
–80
63
62
61
60
–100
–120
0
500
1000
1500
2000
2500
0
100000
200000
300000
400000
500000
600000
INPUT FREQUENCY (kHz)
FREQUENCY (Hz)
Figure 4. Typical SNR + D vs. Input Tone
Figure 7. Typical SNR @ 500 kHz Input Tone
95
0
90
85
80
75
70
65
60
55
50
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
5V
5V
3V
100
200
350
500
1000
2000
1
10
100
1000
10000
100000
INPUT FREQUENCY (kHz)
FREQUENCY (Hz)
Figure 5. Typical THD vs. Input Tone
Figure 8. Typical Bandwidth
70.60
70.4
0
V
= 5V
CC
100mV p-p SINEWAVE ON V
CC
fSAMPLE = 1MHz, fIN = 100kHz
–40°C
–20
70.2
70.0
69.8
69.6
–40
–60
+25°C
+125°C
–55°C
–80
+85°C
69.4
69.2
69.0
–100
–120
0
5
10 16 20 26 31 36 41 46 51 57 61 67 72 77 82 88 92 97
13 18 23 28 34 39 44 49 54 59 64 69 74 80 84 89 94 100
RIPPLE FREQUENCY (kHz)
2.50
3.0
3.5
4.0
4.5
5.0
5.5
3
8
SUPPLY (Volts)
V
CC
Figure 6. Typical SNR vs. Supply
Figure 9. Typical Power Supply Rejection Ratio (PSRR)
Rev. A | Page 10 of 24
AD7492
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.2
–0.4
–0.6
–0.4
–0.6
–0.8
–1.0
–0.8
–1.0
1023
1534
2045
2556
3067
3578
4089
1023
1534
2045
2556
3067
3578
4089
0
512
0
512
CODE
CODE
Figure 10. Typical INL for 2.75 V @ 25°C
Figure 11. Typical DNL for 2.75 V @ 25°C
Rev. A | Page 11 of 24
AD7492
TERMINOLOGY
where:
Integral Nonlinearity
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition, and full scale, a point
1/2 LSB above the last code transition.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 1 LSB.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n is equal to zero. For example, the
second order terms include (fa + fb) and (fa − fb), while the
third order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
Gain Error
The last transition should occur at the analog value 1 1/2 LSB
below the nominal full scale. The first transition is a 1/2 LSB
above the low end of the scale (zero in the case of AD7492). The
gain error is the deviation of the actual difference between the
first and last code transitions from the ideal difference between
the first and last code transitions with offset errors removed.
Track/Hold Acquisition Time
The AD7492 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
The track/hold amplifier returns into track mode after the end
of the conversion. Track/Hold acquisition time is the time
required for the output of the track/hold amplifier to reach its
final value, within 0.5 LSB, after the end of conversion.
Signal-to-Noise and Distortion Ratio
This is the measured ratio of signal-to-noise and distortion at
the output of the A/D converter. The signal is the rms
amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent on the number of
quantization levels in the digitization process; the more levels,
the smaller the quantization noise. The theoretical signal to
(noise + distortion) ratio for an ideal N-bit converter with a sine
wave input is given by:
Aperture Delay
In a sample/hold, the time required after the hold command for
the switch to open fully is the aperture delay. The sample is, in
effect, delayed by this interval, and the hold command would
have to be advanced by this amount for precise timing.
Signal-to-Noise and Distortion = (6.02 N + 1.76) dB
Aperture Jitter
Thus for a 12-bit converter, this is 74 dB and for a 10-bit
converter is 62 dB.
Aperture jitter is the range of variation in the aperture delay. In
other words, it is the uncertainty about when the sample is
taken. Jitter is the result of noise that modulates the phase of the
hold command. This specification establishes the ultimate
timing error, hence the maximum sampling frequency for a
given resolution. This error increases as the input dV/dt
increases.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7492 it is defined as:
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD (dB) = 20 log
V1
Rev. A | Page 12 of 24
AD7492
CIRCUIT DESCRIPTION
CONVERTER OPERATION
TYPICAL CONNECTION DIAGRAM
The AD7492 is a 12-bit successive approximation analog-to-
digital converter based around a capacitive DAC. The AD7492
can convert analog input signals in the range 0 V to VREF. Figure
12 shows a very simplified schematic of the ADC. The control
logic, SAR register, and capacitive DAC are used to add and
subtract fixed amounts of charge from the sampling capacitor to
bring the comparator back into a balanced condition.
Figure 15 shows a typical connection diagram for the AD7492.
CONVST
CONVST
Conversion is initiated by a falling edge on
. Once
goes low the BUSY signal goes high, and at the end of
the conversion, the falling edge of BUSY is used to activate an
CS RD
lines are then activated
interrupt service routine. The
and
in parallel to read the 12 data bits. The internal band gap
reference voltage is 2.5 V, providing an analog input range of 0 V
to 2.5 V, making the AD7492 a unipolar A/D. A capacitor with a
minimum capacitance of 100 nF is needed at the output of the
REF OUT pin as it stabilizes the internal reference value. It is
recommended to perform a dummy conversion after power-up as
the first conversion result could be incorrect. This also ensures
COMPARATOR
CAPACITIVE
DAC
V
REF
SWITCHES
SAR
CONVST
that the part is in the correct mode of operation. The
pin should not be floating when power is applied, as a rising edge
CONVST
V
IN
on
might not wake up the part.
In Figure 15 the VDRIVE pin is tied to DVDD, which results in
logic output voltage values being either 0 V or DVDD. The
voltage applied to VDRIVE controls the voltage value of the output
logic signals and the input logic signals. For example, if DVDD is
supplied by a 5 V supply and VDRIVE by a 3 V supply, the logic
output voltage levels would be either 0 V or 3 V. This feature
allows the AD7492 to interface to 3 V parts while still enabling
the A/D to process signals at 5 V supply.
CONTROL
INPUTS
CONTROL LOGIC
OUTPUT DATA
12-BIT PARALLEL
Figure 12. Simplified Block Diagram of AD7492
Figure 13 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A. The comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on VIN.
ANALOG
SUPPLY
2.7V TO 5.25V
+
+
0.1µF
47µF
10µF
CAPACITIVE
DAC
V
AV
DRIVE
DD
DV
DD
1nF
AD7492
2kΩ
A
V
IN
2.5V
REF OUT
B
CONTROL LOGIC
SW1
µC/µP
100nF
V
0V TO 2.5V
SW2
IN
COMPARATOR
AGND
DB0 TO
DB9 (DB11)
PARALLELED
INTERFACE
Figure 13. ADC Acquisition Phase
PS/FS
CS
CONVST
RD
Figure 14 shows the ADC during conversion. When conversion
starts, SW2 opens and SW1 moves to Position B, causing the
comparator to become unbalanced. The ADC then runs
through its successive approximation routine and brings the
comparator back into a balanced condition. When the
comparator is rebalanced, the conversion result is available in
the SAR register.
BUSY
Figure 15. Typical Connection Diagram
ADC TRANSFER FUNCTION
The output coding of the AD7492 is straight binary. The
designed code transitions occur at successive integer LSB values
(that is, 1 LSB, 2 LSB, etc.). The LSB size equals 2.5/4096 for the
AD7492. The ideal transfer characteristic for the AD7492 is
shown in Figure 16.
CAPACITIVE
DAC
2kΩ
A
V
IN
SW1
B
CONTROL LOGIC
SW2
COMPARATOR
AGND
Figure 14. ADC Conversion Phase
Rev. A | Page 13 of 24
AD7492
ANALOG INPUT
111...111
111...110
Figure 18 shows the equivalent circuit of the analog input
structure of the AD7492. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. The Capacitor C3 is
typically about 4 pF and can be primarily attributed to pin
capacitance. The Resistor R1 is an internal switch resistance.
This resistor is typically about 125 Ω. The Capacitor C1 is the
sampling capacitor while R2 is used for bandwidth control.
111...000
011...111
1LSB = V
REF
/4096
000...010
000...001
000...000
0V 1/2LSB
+V
–1LSB
ANALOG INPUT
REF
V
DD
C1
22pF
R1
125Ω
R2
636Ω
Figure 16. Transfer Characteristic for 12 Bits
D1
D2
V
IN
C3
4pF
C2
8pF
AC ACQUISITION TIME
In ac applications, it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of impedance at the VIN pin of the ADC
cause the THD to degrade at high input frequencies.
Figure 18. Equivalent Analog Input Circuit
PARALLEL INTERFACE
The parallel interface of the AD7492 is 12 bits wide. The output
CS
RD
data buffers are activated when both and
are logic low. At
Table 6. Dynamic Performance Specifications
this point the contents of the data register are placed onto the data
bus. Figure 19 shows the timing diagram for the parallel port.
Input
SNR
THD
Typical Amplifier Current
Buffers
500 kHz 500 kHz Consumption
AD9631
AD797
69.5
69.6
80
81.6
17 mA
8.2 mA
Figure 20 shows the timing diagram for the parallel port when
CS
RD
and
are tied permanently low. In this setup, once the
DC ACQUISITION TIME
BUSY line goes from high to low, the conversion process is
completed. The data is available on the output bus slightly
before the falling edge of BUSY.
The ADC starts a new acquisition phase at the end of a
CONVST
conversion and ends it on the falling edge of the
signal. At the end of the conversion, there is a settling time
associated with the sampling circuit. This settling time lasts
120 ns. The analog signal on VIN is also acquired during this
settling time; therefore, the minimum acquisition time needed
is 120 ns.
Note that the data bus cannot change state while the A/D is
doing a conversion, as this would have a detrimental effect on
the conversion in progress. The data out lines go three-state
RD CS
be tied low permanently, leaving the
CS
again when either the
or
line goes high. Thus the
RD
can
line to control
conversion result access. Please reference the VDRIVE section for
output voltage levels.
Figure 17 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R3
represents the source impedance of a buffer amplifier or
resistive network, R1 is an internal switch resistance, R2 is for
bandwidth control, and C1 is the sampling capacitor. C2 is
back-plate capacitance and switch parasitic capacitance.
OPERATING MODES
The AD7492 has two possible modes of operation depending
CONVST
on the state of the
Mode 1 and Mode 2.
pulse at the end of a conversion,
During the acquisition phase the sampling capacitor must be
charged to within 0.5 LSB of its final value.
Mode 1 (High-Speed Sampling)
CONVST
In this mode of operation the
before the end of conversion, that is, before BUSY goes low (see
CONVST
pulse is brought high
C1
22pF
R1
125Ω
V
IN
R3
R2
C2
Figure 20). If the
pin is brought from high-to-low
636Ω
8pF
while BUSY is high, the conversion is restarted. When
operating in this mode a new conversion should not be initiated
until 140 ns after BUSY goes low. This acquisition time allows
the track/hold circuit to accurately acquire the input signal. As
mentioned earlier, a read should not be done during a
conversion. This mode facilitates the fastest throughput times
for the AD7492.
Figure 17. Equivalent Analog Input Circuit
Rev. A | Page 14 of 24
AD7492
tCONVERT
CONVST
BUSY
t9
t2
t10
t3
CS
RD
t8
t4
t5
t7
t6
DBx
Figure 19. Parallel Port Timing
tCONVERT
CONVST
BUSY
DBx
t9
t2
DATA N
DATA N+1
CS
Figure 20. Parallel Port Timing with and
RD
Tied Low
Mode 2 (Partial or Full Sleep Mode)
After 1 μs, the AD7492 has only stabilized to within approxi-
mately 3 LSB of the input value. From full sleep, this wake-up
time is typically 500 μs. In all cases the BUSY line only goes high
Figure 21 shows the AD7492 in Mode 2 operation where the
ADC goes into either partial or full sleep mode after
CONVST
once
goes low. Superior power performance can be
CONVST
conversion. The
conversion and remains low until after the end of the
CONVST
line is brought low to initiate a
achieved in these modes of operation by waking up the AD7492
only to carry out a conversion. The optimum power performance
is obtained when using full sleep mode as the ADC comparator,
reference buffer, and reference circuit are powered down. While
in partial sleep mode, only the ADC comparator is powered
down and the reference buffer is put into a low power mode. The
100 nF capacitor on the REF OUT pin is kept charged up by the
reference buffer in partial sleep mode while in full sleep mode
this capacitor slowly discharges. This explains why the wake-up
time is shorter in partial sleep mode. In both sleep modes the
clock oscillator circuit is powered down.
conversion. If
high, the conversion is restarted. Once the BUSY line goes from
CONVST
goes high and low again while BUSY is
high-to-low, the
the part enters a sleep mode. The type of sleep mode the
FS
line has its status checked and, if low,
AD7492 enters depends on what way the PS/ pin is
FS
hardwired. If the PS/ pin is tied high, the AD7492 enters
FS
partial sleep mode. If the PS/ pin is tied low, the AD7492
enters full sleep mode.
CONVST
The device wakes up again on the rising edge of the
signal. From partial sleep the AD7492 is capable of starting
CONVST
conversions typically 1 μs after the rising edge of
. The
line can go from high-to-low during the wake-up time,
CONVST
but the conversion is still not initiated until after 1 μs. It is
recommended that the conversion should not be initiated until at
least 20 μs of the wake-up time has elapsed. This ensures that the
AD7492 has stabilized to within 0.5 LSB of the analog input value.
Rev. A | Page 15 of 24
AD7492
tCONVERT
CONVST
BUSY
tWAKEUP
CS
RD
DBx
Figure 21. Mode 2 Operation
VDRIVE
Power vs. Throughput
The VDRIVE pin is used as the voltage supply to the digital output
drivers and the digital input circuitry. It is a separate supply
from AVDD and DVDD. The purpose of using a separate supply
for the digital input/output interface is that the user can vary
the output high voltage, VOH, and the logic input levels, VINH
and VINL, from the VDD supply to the AD7492. For example, if
AVDD and DVDD are using a 5 V supply, the VDRIVE pin can be
powered from a 3 V supply. The ADC has better dynamic
performance at 5 V than at 3 V, so operating the part at 5 V,
while still being able to interface to 3 V parts, pushes the
AD7492 to the top bracket of high performance 12-bit ADCs.
Of course, the ADC can have its VDRIVE and DVDD pins
The two modes of operation for the AD7492 produces different
power vs. throughput performances, Mode 1 and Mode 2; see
the Operating Modes section of the data sheet for more detailed
descriptions of these modes. Mode 2 is the sleep mode
(partial/full) of the part and it achieves the optimum power
performance.
Mode 1
Figure 22 shows the AD7492 conversion sequence in Mode 1
using a throughput rate of 500 kSPS. At 5 V supply, the current
consumption for the part when converting is 3 mA and the
quiescent current is 1.8 mA. The conversion time of 880 ns
contributes 6.6 mW to the overall power dissipation in the
following way:
connected together and be powered from a 3 V or 5 V supply.
The trigger levels are VDRIVE × 0.7 and VDRIVE × 0.3 for the digital
inputs. The pins that are powered from VDRIVE are DB11 to DB0,
(880 ns/2 μs) × (5 × 3 mA) = 6.6 mW
CS RD CONVST
,
,
, and BUSY.
The contribution to the total power dissipated by the remaining
1.12 μs of the cycle is 5.04 mW
FS
PS/ PIN
FS
As previously mentioned, the PS/ pin is used to control the
type of power-down mode that the AD7492 can enter into if
operated in Mode 2. This pin can be hardwired either high or
low, or even controlled by another device. It is important to
(1.12 μs/2 μs) × (5 × 1.8 mA) = 5.04 mW
Thus the power dissipated during each cycle is
6.6 mW + 5.04 mW = 11.64 mW
FS
note that toggling the PS/ pin while in power-down mode
does not switch the part between partial sleep and full sleep
modes. To switch from one sleep mode to another, the AD7492
FS
has to be powered up and the polarity of the PS/ pin changed.
CONVST
It can then be powered down to the required sleep mode.
tCONVERT
tQUIESCENT
POWER-UP
BUSY
It is recommended that the user performs a dummy conversion
after power-up, as the first conversion result could be incorrect.
This also ensures that the part is in the correct mode of
1.12µs
880ns
2µs
operation. The recommended power-up sequence is as follows:
1. GND
Figure 22. Mode 1 Power Dissipation
2. VDD
3. VDRIVE
4. Digital Inputs
5. VIN
Rev. A | Page 16 of 24
AD7492
Mode 2 (Full Sleep Mode)
Figure 25, Figure 26, and Figure 27 show a typical graphical
representation of power vs. throughput for the AD7492 when in
Mode 1 @ 5 V and 3 V, Mode 2 in full sleep mode @ 5 V and 3
V, and Mode 2 in partial sleep mode @ 5 V and 3 V.
Figure 23 shows the AD7492 conversion sequence in Mode 2,
full sleep mode, using a throughput rate of approximately
100 kSPS. At 5 V supply the current consumption for the part
when converting is 3 mA, while the full sleep current is 1 μA
maximum. The power dissipated during this power-down is
negligible and thus not worth considering in the total power
figure. During the wake-up phase, the AD7492 draws typically
1.8 mA. Overall power dissipated is
12
10
5V
8
6
4
(880 ns/10 ms) × (5 × 3 mA) + (500 μs/10 ms) × (5 × 1.8 mA)
= 451.32 μW
tCONVERT
tWAKEUP
CONVST
3V
500µs
2
tQUIESCENT
0
BUSY
0
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT (kHz)
880ns
10ms
9.5ms
Figure 25. Power vs. Throughput
(Mode 1 @ 5 V and 3 V)
Figure 23. Full Sleep Power Dissipation
3.5
3.0
2.5
2.0
Mode 2 (Partial Sleep Mode)
Figure 24 shows the AD7492 conversion sequence in Mode 2,
partial sleep mode, using a throughput rate of 1 kSPS. At 5 V
supply, the current consumption for the part when converting is
3 mA, while the partial sleep current is 250 μA maximum.
During the wake-up phase, the AD7492 typically draws 1.8 mA.
Power dissipated during wake-up and conversion is
5V
1.5
1.0
3V
(880 ns/1 ms) × (5 × 3 mA) + (20 μs/1 ms) × (5 × 1.8 mA) =
193.2 mW
0.5
0
Power dissipated during power-down is
(979 μs/1 ms) × (5 × 250 μA) = 1.22 mW
Overall power dissipated is
0
10
20
30
40
50
60
70
80
90
100
THROUGHPUT (kHz)
Figure 26. Power vs. Throughput
(Mode 2 in Full Sleep Mode @ 5 V and 3 V)
2.5
2.0
1.5
193.2 μW + 1.22 mW = 1.41 mW
tCONVERT
5V
tWAKEUP
CONVST
20µs
tQUIESCENT
BUSY
3V
1.0
0.5
880ns
1ms
979µs
Figure 24. Partial Sleep Power Dissipation
0
0
10
20
30
40
50
60
70
80
90
100
THROUGHPUT (kHz)
Figure 27. Power vs. Throughput
(Mode 2 in Partial Sleep Mode @ 5 V and 3 V)
Rev. A | Page 17 of 24
AD7492
• Avoid crossover of digital and analog signals and place
traces that are on opposite sides of the board at right angles
to each other.
GROUNDING AND LAYOUT
The analog and digital power supplies are independent and
separately pinned out to minimize coupling between analog and
digital sections within the device. To complement the excellent
noise performance of the AD7492, it is imperative that care be
given to the PCB layout. Figure 28 shows a recommended
connection diagram for the AD7492.
Noise to the analog power line can be further reduced by use of
multiple decoupling capacitors as shown in Figure 28.
Decoupling capacitors should be placed directly at the power
inlet to the PCB and also as close as possible to the power pins
of the AD7492. The same decoupling method should be used
on other ICs on the PCB, with the capacitor leads as short as
possible to minimize lead inductance.
All of the AD7492 ground pins should be soldered directly to a
ground plane to minimize series inductance. The AVDD pin,
DVDD pin, and VDRIVE pin should be decoupled to both the
analog and digital ground planes. The REF OUT pin should be
decoupled to the analog ground plane with a minimum
capacitor value of 100 nF. This capacitor helps to stabilize the
internal reference circuit. The large value capacitors decouple
low frequency noise to analog ground, the small value
POWER SUPPLIES
Separate power supplies for AVDD and DVDD are desirable, but if
necessary, DVDD can share its power connection to AVDD. The
digital supply (DVDD) must not exceed the analog supply (AVDD
by more than 0.3 V in normal operation.
)
capacitors decouple high frequency noise to digital ground. All
digital circuitry power pins should be decoupled to the digital
ground plane. The use of ground planes can physically separate
sensitive analog components from the noisy digital system. The
two ground planes should be joined in only one place and
should not overlap so as to minimize capacitive coupling
between them. If the AD7492 is in a system where multiple
devices require AGND-to-DGND connections, the connection
should still be made at one point only, a star ground point,
established as close as possible to the AD7492.
MICROPROCESSOR INTERFACING
ADSP-2185 to AD7492 Interface
Figure 29 shows a typical interface between the AD7492 and the
ADSP-2185. The ADSP-2185 processor can be used in one of
two memory modes, full memory mode and host mode. The
Mode C pin determines in which mode the processor works.
The interface in Figure 29 is set up to have the processor
working in full memory mode, allowing full external addressing
capabilities.
ANALOG
SUPPLY
+
+
When the AD7492 has finished converting, the BUSY line
5V
10µF
0.1µF
47µF
IRQ2
IRQ2
requests an interrupt through the
pin. The
interrupt
AV
DD
has to be set up in the interrupt control register as edge-
sensitive. The data memory select (DMS) pin latches in the
address of the ADC into the address decoder. The read
operation is started.
DV
DD
1nF
AGND
DGND
AD7492
V
DRIVE
+
OPTIONAL
10µF
1nF
CONVST
REF OUT
2.5V
A0 TO A15
ADDRESS BUS
+
100nF
AD7492
ADSP-21851
DMS
ADDRESS
DECODER
Figure 28. Typical Decoupling Circuit
CS
IRQ2
RD
BUSY
RD
Noise can be minimized by applying the following simple rules
to the PCB layout:
100kΩ
MODE C
DB0 TO DB9
(DB11)
• Analog signals should be kept away from digital signals.
D0 TO D23
1
DATA BUS
• Fast switching signals like clocks should be shielded with
digital ground to avoid radiating noise to other sections of
the board and clock signals should never be run near the
analog inputs.
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 29. ADSP-2185 to AD7492 Interface
• Avoid running digital lines under the device as this couples
noise onto the die.
• The power supply lines to the AD7492 should use as large a
trace as possible to provide a low impedance path and reduce
the effects of glitches on the power supply line.
Rev. A | Page 18 of 24
AD7492
OPTIONAL
ADSP-21065Lto AD7492 Interface
Figure 30 shows a typical interface between the AD7492 and the
ADSP-21065L SHARC® processor. This interface is an example
CONVST
ADDRESS BUS
A0 TO A15
AD7492
TMS320C251
MSX
of one of three DMA handshake modes. The
actually three memory select lines. Internal ADDR25–24 are
MS
control line is
ADDRESS
DECODER
IS
CS
decoded into
3-0, these lines are then asserted as chip selects.
1 (DMA Request 1) is used in this setup as the
DMAR
The
BUSY
RD
interrupt to signal end of conversion. The rest of the interface is
standard handshaking operation.
STRB
R/W
READY
MSC
OPTIONAL
DB0 TO DB9
(DB11)
ADDR TO
CONVST
0
ADDRESS BUS
ADDR
23
DATA BUS
DMD0 TO DMD15
1
AD7492
ADDRESS
LATCH
MS
X
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS
BUS
Figure 31. TMS320C25 to AD7492 Interface
ADSP-21065L1
ADDRESS
DECODER
CS
PIC17C4x to AD7492 Interface
DMAR
BUSY
RD
Figure 32 shows a typical parallel interface between the AD7492
and PIC17C4x. The microcontroller sees the ADC as another
memory device with its own specific memory address on the
1
RD
DB0 TO DB9
(DB11)
D0 TO 31
1
DATA BUS
CONVST
memory map. The
signal can be controlled by either
the microcontroller or an external source. The BUSY signal
provides an interrupt request to the microcontroller when a
conversion ends. The INT pin on the PIC17C4x must be
configured to be active on the negative edge. Port C and Port D
of the microcontroller are bidirectional and used to address the
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. ADSP-21065L to AD7492 Interface
TMS320C25 to AD7492 Interface
Figure 31 shows an interface between the AD7492 and the
TMS320C25. The
TMS320C25 or from an external source. The BUSY line
interrupts the digital signal processor when conversion is
OE
AD7492 and to read in the 12-bit data. The
pin on the PIC
CONVST
signal can be applied from the
can be used to enable the output buffers on the AD7492 and
perform a read operation.
OPTIONAL
RD
completed. The TMS320C25 does not have a separate
RD
output to drive the AD7492
input directly. This has to be
CONVST
PIC17C4x1
STRB
W
generated from the processor
and R/ outputs with the
DB0 TO DB9
(DB11)
RD
addition of some glue logic. The
signal is OR-gated with the
AD0 TO AD15
AD7492
MSC signal to provide the WAIT state required in the read cycle
for correct interface timing. The following instruction is used to
read the conversion from the AD7492:
ADDRESS
LATCH
ADDRESS
DECODER
CS
ALE
OE
RD
INT
BUSY
IN D,ADC
1
ADDITIONAL PINS OMITTED FOR CLARITY.
where:
Figure 32. PIC17C4x to AD7492 Interface
D is the data memory address.
ADC is the AD7492 address.
The read operation must not be attempted during conversion.
Rev. A | Page 19 of 24
AD7492
OPTIONAL
80C186 to AD7492 Interface
AD0 TO AD15
A16 TO A19
ADDRESS/DATA BUS
Figure 33 shows the AD7492 interfaced to the 80C186
CONVST
ADDRESS
LATCH
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. (The AD7492 occupies
one of these I/O spaces.) Each data transfer consumes two bus
cycles, one cycle to fetch data and the other to store data.
ALE
AD7492
ADDRESS
BUS
80C1861
ADDRESS
DECODER
CS
DRQ1
RD
Q
R
S
BUSY
RD
After the AD7492 has finished the conversion, the BUSY line
generates a DMA request to Channel 1 (DRQ1). Because of the
interrupt, the processor performs a DMA read operation that
resets the interrupt latch. Sufficient priority must be assigned to
the DMA channel to ensure that the DMA request is serviced
before the completion of the next conversion. This
configuration can be used with 6 MHz and 8 MHz 80C186
processors.
DB0 TO DB9
(DB11)
DATA BUS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. 80C186 to AD7492 Interface
Rev. A | Page 20 of 24
AD7492
OUTLINE DIMENSIONS
15.60 (0.6142)
15.20 (0.5984)
24
1
13
12
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
0.75 (0.0295)
0.25 (0.0098)
× 45°
0.30 (0.0118)
0.10 (0.0039)
8°
0°
1.27 (0.0500)
BSC
SEATING
PLANE
0.51 (0.020)
0.31 (0.012)
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 34. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 35. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Throughput Rate
(MSPS)
Package
Description
Model
Resolution (Bits)
Package Option
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
AD7492AR
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
12
12
12
12
12
12
12
12
12
12
12
12
1
1
1
1
1
1
1
1
1
1
1.25
1.25
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
AD7492AR–REEL
AD7492AR–REEL7
AD7492ARZ1
AD7492ARZ–REEL1
AD7492ARZ–REEL71
AD7492BR
AD7492BR-REEL
AD7492BR–REEL7
AD7492BRZ1
AD7492AR-5
AD7492AR-5–REEL
Rev. A | Page 21 of 24
AD7492
Temperature
Range
Throughput Rate
(MSPS)
Package
Description
Model
Resolution (Bits)
Package Option
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
Evaluation Board
Controller Board
AD7492AR-5–REEL7
AD7492ARZ-51
AD7492BR-5
AD7492BR-5–REEL
AD7492BR-5–REEL7
AD7492BRZ-51
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1.25
1.25
1.25
1.25
1.25
1.25
1
1
1
1
1
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
AD7492ARU
AD7492ARU–REEL
AD7492ARU–REEL7
AD7492ARUZ1
AD7492ARUZ–REEL1
AD7492ARUZ–REEL71
AD7492ARU-5
AD7492ARU-5–REEL
AD7492ARU-5–REEL7
AD7492ARUZ-51
AD7492ARUZ-5–REEL1
AD7492ARUZ-5–REEL71
AD7492ARUZ-41
AD7492ARUZ-4REEL1
AD7492ARUZ-4REEL71
AD7492BRU
1
1.25
1 .25
1.25
1.25
1.25
1.25
0.4
0.4
0.4
1
1
1
1
1.25
1.25
1.25
1.25
AD7492BRU–REEL
AD7492BRU–REEL7
AD7492BRUZ1
AD7492BRU-5
AD7492BRU-5–REEL
AD7492BRU-5–REEL7
AD7492BRUZ-51
EVAL-AD7492CB2
EVAL-CONTROL BRD23
1 Z = Pb–free part.
2 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Rev. A | Page 22 of 24
AD7492
NOTES
Rev. A | Page 23 of 24
AD7492
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01128-0-5/06(A)
Rev. A | Page 24 of 24
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