AD75019 [ADI]
16 x 16 Crosspoint Switch Array; 16 ×16交叉点开关阵列
| 型号： | AD75019 |
| 厂家： | 
ADI |
| 描述： | 16 x 16 Crosspoint Switch Array |
| 文件： | 总4页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16
؋
16 Crosspoint a
Switch Array
AD75019
FEATURES
FUNCTIONAL BLOCK DIAGRAM
256 Switches in a 16
؋
16 Array Wide Signal Range: to Supply Rails of 24 V or ؎12 V
Low On-Resistance: 200 ⍀ Typ
ANALOG
INPUTS/OUTPUTS
X0
X15
V
DD
V
SS
V
CC
DGND
TTL/CMOS/Microprocessor-Compatible Control Lines
Serial Input Simplifies Interface
+12V –12V +5V DGND
SERIAL DATA IN
Y0
Serial Output Allows Cascading for More Channels
Low Power Consumption: 2 mW Quiescent
Compact 44-Lead PLCC
SHIFT
REGISTER
CELL #256
LATCH
ANALOG
SWITCH
AD75019
BUSED CLOCK
LINES
SERIAL
DATA
ANALOG
OUTPUTS/
INPUTS
TO NEXT
STAGES
SERIAL
DATA
FROM
PRIOR
STAGES
16
؋
16 ARRAY OF SWITCHES, LATCHES, AND SHIFT REGISTER
CELLS (ONLY TWO LOCATIONS
ARE SHOWN FOR CLARITY)
BUSED CLOCK
LINES
Y15
SHIFT
REGISTER
CELL #1
ANALOG
SWITCH
LATCH
PARALLEL
CLOCK
SERIAL
CLOCK
PCLK
SCLK SOUT
PRODUCT DESCRIPTION
To extend the number of switches in the array, you may cascade
multiple AD75019s. The SOUT output is the end of the shift
register, and may be connected to the SIN input of the next
AD75019.
The AD75019 contains 256 analog switches in a 16 × 16 array.
Any of the X or Y pins may serve as an input or output. Any or
all of the X terminals may be programmed to connect to any or
all of the Y terminals. The switches can accommodate signals
with amplitudes up to the supply rails and have a typical on-
resistance of 150 Ω.
The AD75019 is fabricated in Analog Devices’ BiMOS II
process. This epitaxial BiCMOS process features CMOS
devices for low distortion switches and bipolar devices for
ESD protection.
Data is loaded serially via the SIN input and clocked into an on-
board 256-bit shift register via SCLK. When all the switch set-
tings have been programmed, data is transferred into a set of
256 latches via PCLK. The serial shift register is dynamic, so
there is a minimum clock rate of 20 kHz. The maximum clock
rate of 5 MHz allows loading times as short as 52 µs. The switch
control latches are static and will hold their data as long as power
is applied.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
1
(T = +25؇C, V and V = ؎12 V, V = +5 V unless otherwise noted)
AD75019–SPECIFICATIONS
A
DD
SS
CC
AD75019
Symbol
Min
Typ
Max
Units
MULTIPLEXER
Input Signal Range
VIN
VSS – 0.5
VDD + 0.5
V
Switch ON Resistance, VDD and VSS = ±12 V, VSIGNAL = ±12 V
Switch ON Resistance, VDD and VSS = ±5 V, VSIGNAL = ±5 V
Switch ON Resistance Matching2, VSIGNAL = ±12 V
Leakage Current, VSIGNAL = ±10 V
RON
RON
∆RON
150
300
20
300
500
30
10
25
Ω
Ω
Ω
nA
pF
2
Input/Output Capacitance
CIN
Isolation Between Any Two Channels
RS = 600 Ω, RL = 10 kΩ, VSIGNAL = 2 V p-p
f
f
f
SIGNAL = 1 kHz
SIGNAL = 20 kHz
SIGNAL = 1 MHz
92
69
38
dB
dB
dB
Total Harmonic Distortion
RS = 600 Ω, RL = 10 kΩ, VSIGNAL = 2 V p-p
Switch Frequency Response, –3 dB
RS = 600 Ω, RL = 10 kΩ, VSIGNAL = 2 V p-p
Propagation Delay
0.01
8
%
20
MHz
ns
4
DIGITAL INPUTS (SIN, SCLK, PCLK)
Logic Levels (TTL Compatible)
Input Voltage, Logic “1”
VIH
VIL
IIH
2.4
0
5.5
0.8
±1
±1
10
V
Input Voltage, Logic “0”
V
Input Current, VIH = 5.5 V
Input Current, VIL = 0.8 V
Input Capacitance
µA
µA
pF
IIL
CIN
DIGITAL OUTPUTS (SOUT)
Logic Levels (TTL Compatible)
Output Voltage, Logic “1”
VOH
VOL
IOH
IOL
2.8
V
Output Voltage, Logic “0”
0.4
V
Output Current, VOH = 2.8 V
Output Current, VOL = 0.4 V
3.2
3.2
mA
mA
POWER SUPPLY REQUIREMENTS
Voltage Range, Total Analog
Voltage Range, Positive Analog
Voltage Range, Negative Analog
Voltage Range, Digital
VDD – VSS
9.0
25.2
25.2
0
V
V
V
V
DD – VDGND
SS – VDGND
CC – VDGND
(VCC – 0.5)
–20.7
4.5
V
V
V
mA
µA
µA
µA
5
5.5
Supply Current, SCLK = 5 MHz,
I
DD, ISS
±70
800
؎400
100
V
IL = 0.8 V, VIH = 2.4 V
ICC
Supply Current, Quiescent,
VIL = 0.8 V, VIH = 2.4 V
I
DD, ISS
_
_
ICC
TEMPERATURE RANGE
Operating
Storage
T
MIN, TMAX
–25
–65
+85
+150
°C
°C
NOTES
1All minimum and maximum specifications are guaranteed, and specifications shown in boldface are tested on all production units at final electrical test. Results from those tests
are used to calculate outgoing quality levels.
2Switch resistance matching is measured with zero volts at each analog input and refers to the difference between the maximum and minimum values.
Specifications subject to change without notice.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Pin Name Description
Pin Name Description
23 X8 Analog Input (or Output)
24 X9
1
PCLK Parallel Clock Input
2
SCLK Serial Clock Input
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
No Internal Connection
No Internal Connection
Positive Analog Power Supply
Digital Power Supply
3
SIN
VSS
NC
NC
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Serial Data Input
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
X10
X11
X12
X13
X14
X15
Y0
6
5
4
3
2
1
44 43 42 41 40
4
Negative Analog Power Supply
No Internal Connection
No Internal Connection
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Output (or Input)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
Analog Input (or Output)
PIN 1
5
7
8
39
Y15
Y14
Y13
Y12
NC
IDENTIFIER
6
38 Y7
7
9
37
Y6
8
10
36
35
34
33
32
31
30
29
Y5
Y4
9
Y11 11
AD75019
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
21
22
Y1
12
Y10
Y3
Y2
Y2
13
Y9
Y3
14
Y8
Y1
Y4
15
16
X0
X1
Y0
Y8
Y5
X15
X14
X0
Y6
X1
X2 17
Y7
X2
NC
NC
VDD
VCC
X3
18 19 20 21 22 23 24 25 26 27 28
X4
X5
X6
DGND Digital Ground
SOUT Serial Data Output: Positive True
NC = NO CONNECT
X7
–2–
REV. C
AD75019
TIMING CHARACTERISTICS1
(TA = TMIN to TMAX, rated power supplies unless otherwise noted)
Parameter
Symbol
Value
Units
Condition
Data Setup Time
SCLK Pulsewidth
Data Hold Time
SCLK Pulse Separation
SCLK to PCLK Delay
SCLK to PCLK Delay and Release
PCLK Pulsewidth
Propagation Delay, PCLK to Switches On or Off
Data Load Time
t1
t2
t3
t4
20
100
40
100
65
5
65
70
52
20
1
ns
ns
ns
ns
ns
ms
ns
ns
µs
min
min
min
min
min
max
min
max
t5
(t5 + t6)
t6
_
_
_
_
SCLK = 5 MHz
min
max
SCLK Frequency
SCLK, PCLK Rise and Fall Times
kHz
µs
NOTES
1Timing measurement reference level is 1.5 V.
Specifications subject to change without notice.
TIMING DIAGRAM
LOAD DATA INTO
SERIAL REGISTER
DURING RISING EDGE
1
t4
SCLK
t2
0
t1
t3
Y15–X15
1 = CLOSE
SIN
Y15–X14
Y0–X0
t5
0 = OPEN
t6
1
PCLK
0
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
OPERATION TRUTH TABLE
Control Lines
PCLK
SCLK
SIN
SOUT
Operation/Comment
1
1
0
1
X
Datai
X
No operation.
Datai-256
The data on the SIN line is loaded into the serial register; data clocked into the
serial register 256 clocks ago appears at the SOUT output.
Data in the serial shift register transfers into the parallel latches which control the
switch array.
0
X
X
X
APPLICATIONS INFORMATION
Loading Data
Power Supply Sequencing and Bypassing
All junction-isolated parts operating on multiple power supplies
Data to control the switches is clocked serially into a 256-bit
shift register and then transferred in parallel to 256 bits of mem-
ory. The rising edge of SCLK, the serial clock input, loads data
into the shift register. The first bit loaded via SIN, the serial
data input, controls the switch at the intersection of row Y15
and column X15. The next bits control the remaining columns
(down to X0) of row Y15, and are followed by the bits for row
Y14, and so on down to the data for the switch at the intersec-
tion of row Y0 and column X0. The shift register is dynamic, so
there is a minimum clock rate, specified as 20 kHz.
require proper attention to supply sequencing. Because BiMOS
II is a junction-isolated process, parasitic diodes exist between
VDD and VCC, and between VSS and DGND. As a result, VDD
must always be greater than (VCC – 0.5 V), and VSS must always
be less than (DGND + 0.5 V).
If you can’t ensure that system power supplies will sequence to
meet these conditions, external Schottky (e.g., 1N5818) or
silicon (e.g., 1N4001) diodes may be used. To protect the posi-
tive side, the anode would connect to VCC (Pin 42) and the
cathode to VDD (Pin 41). For the negative side, connect the
anode to VSS (Pin 4) and the cathode to DGND (Pin 43).
After the shift register is filled with the new 256 bits of control
data, PCLK is activated (pulsed low) to transfer the data to the
parallel latches. Since the shift register is dynamic, there is a
maximum time delay specified before the data is lost: PCLK
must be activated and brought back high within 5 ms after fill-
ing the shift register. The switch control latches are static and
will hold their data as long as power is applied.
Each of the three power supply pins [VDD (Pin 41), VCC (Pin
42) and VSS (Pin 4)] should be bypassed to DGND (Pin 43)
through a 0.1 µF ceramic capacitor located close to the package
pins.
Transistor Count
AD75019 contains 5,472 transistors. This number may be used
for calculating projected reliability.
To extend the number of switches in the array, you may cascade
multiple AD75019s. The SOUT output is the end of the shift
register, and may be directly connected to the SIN input of the
next AD75019.
REV. C
–3–
AD75019
ABSOLUTE MAXIMUM RATINGS*
Min
Max
Units
Conditions
VDD to DGND
–0.5
–25.2
–0.5
–0.5
–0.5
–0.3
+25.2
+0.5
+7.0
+25.2
+25.2
VCC + 0.5
1.0
+70
+150
+300
V
V
V
V
V
V
W
°C
°C
°C
V
SS to DGND
VCC to DGND
VDD to VSS
V
CC to VSS
Digital Inputs to DGND
Power Dissipation
Operating Temperature Range
Storage Temperature
Lead Temperature
TA Յ 75°C
0
–65
Soldering, 10 sec
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only; functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are Zener protected;
however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range
Package Option*
AD75019JP
0°C to +70°C
P-44A
*P = Plastic Leaded Chip Carrier (PLCC) Package.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Leaded Chip Carrier
(P-44A)
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.048 (1.21)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.020
(0.50)
R
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
6
40
39
7
PIN 1
IDENTIFIER
0.050
PIN 1
IDENTIFIER
0.63 (16.00)
0.59 (14.99)
(1.27)
BSC
0.021 (0.53)
0.013 (0.33)
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
17
29
28
18
0.040 (1.01)
0.025 (0.64)
0.020
(0.50)
R
0.656 (16.66)
0.650 (16.51)
SQ
SQ
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
0.685 (17.40)
–4–
REV. C
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