AD7533TE/883B [ADI]
CMOS Low Cost, 10-Bit Multiplying DAC; CMOS低成本, 10位乘法DAC型号: | AD7533TE/883B |
厂家: | ADI |
描述: | CMOS Low Cost, 10-Bit Multiplying DAC |
文件: | 总12页 (文件大小:353K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CMOS Low Cost,
10-Bit Multiplying DAC
AD7533
FEATURES
GENERAL DESCRIPTION
Low cost 10-bit DAC
The AD7533 is a low cost, 10-bit, 4-quadrant multiplying DAC
manufactured using an advanced thin-film-on-monolithic-
CMOS wafer fabrication process.
Low cost AD7520 replacement
Linearity: ½ LSB, 1 LSB, or 2 LSB
Low power dissipation
Full 4-quadrant multiplying DAC
CMOS/TTL direct interface
Latch free (protection Schottky not required)
Endpoint linearity
Pin and function equivalent to the AD7520 industry standard,
the AD7533 is recommended as a lower cost alternative for old
AD7520 sockets or new 10-bit DAC designs.
AD7533 application flexibility is demonstrated by its ability to
interface to TTL or CMOS, operate on 5 V to 15 V power, and
provide proper binary scaling for reference inputs of either
positive or negative polarity.
APPLICATIONS
Digitally controlled attenuators
Programmable gain amplifiers
Function generation
Linear automatic gain controls
FUNCTIONAL BLOCK DIAGRAM
10kΩ
10kΩ
10kΩ
V
REF
20kΩ
20kΩ
20kΩ
20kΩ
20kΩ
S1
S2
S3
SN
I
2
1
OUT
I
OUT
10kΩ
R
FB
BIT 1 (MSB)
BIT 2
BIT 3
BIT 10 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD7533
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Description............................................................................7
General Circuit Information........................................................7
Equivalent Circuit Analysis .........................................................7
Operation............................................................................................8
Unipolar Binary Code ..................................................................8
Bipolar (Offset Binary) Code.......................................................8
Applications........................................................................................9
Outline Dimensions....................................................................... 10
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Terminology ...................................................................................... 5
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
3/07—Rev. B to Rev. C
3/04—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Figure 13, Figure 14, and Figure 17 ........................... 9
Updated Outline Dimensions....................................................... 10
Changes to Ordering Guide .......................................................... 12
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings........................................3
Changes to Ordering Guide.............................................................3
Updated Outline Dimensions..........................................................7
1/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Absolute Maximum Ratings....................................... 4
Added Pin Configurations
and Function Descriptions Section................................................ 6
Updated Outline Dimensions....................................................... 10
Changes to Ordering Guide .......................................................... 12
Rev. C | Page 2 of 12
AD7533
SPECIFICATIONS
VDD = 15 V, VOUT1 = VOUT2 = 0 V, VREF = 10 V, unless otherwise noted.
Table 1.
Parameter
TA = 25°C
TA = Operating Range
Test Conditions
STATIC ACCURACY
Resolution
Relative Accuracy1
10 Bits
10 Bits
AD7533JN, AD7533AQ,
AD7533SQ, AD7533JP
AD7533KN, AD7533BQ,
AD7533KP, AD7533TE
0.2ꢀ ꢁSR ꢂaꢃiꢂuꢂ
0.1ꢀ ꢁSR ꢂaꢃiꢂuꢂ
0.2ꢀ ꢁSR ꢂaꢃiꢂuꢂ
0.1ꢀ ꢁSR ꢂaꢃiꢂuꢂ
AD7533LN, AD7533CQ, AD7533UQ
0.05ꢀ ꢁSR ꢂaꢃiꢂuꢂ
1 LSB ꢂaꢃiꢂuꢂ
1ꢀ ꢁS ꢂaꢃiꢂuꢂ
0.05ꢀ ꢁSR ꢂaꢃiꢂuꢂ
1 LSB ꢂaꢃiꢂuꢂ
1ꢀ ꢁS ꢂaꢃiꢂuꢂ
DNL
Gain Error2, 3
Digital input = VINH
Supply Rejection4
∆Gain/∆VDD
0.001ꢀ/ꢀ ꢂaꢃiꢂuꢂ
0.001ꢀ/ꢀ ꢂaꢃiꢂuꢂ
Digital inputs = VINH, VDD = 14 V to 17 V
Output Leakage Current
IOUT
IOUT
1
2
5 nA ꢂaꢃiꢂuꢂ
5 nA ꢂaꢃiꢂuꢂ
200 nA ꢂaꢃiꢂuꢂ
200 nA ꢂaꢃiꢂuꢂ
Digital inputs = VINL, VREꢁ = 10 V
Digital inputs = VINH, VREꢁ = 10 V
DYNAMIC ACCURACY
Output Current Settling Tiꢂe
600 ns ꢂaꢃiꢂuꢂ4
800 ns5
To 0.05ꢀ ꢁSR; RLOAD = 100 Ω, digital
inputs = VINH to VINL or VINL to VINH
Digital inputs = VINL, VREꢁ = 10 V,
100 kHz sine wave
ꢁeedthrough Error
0.05ꢀ ꢁSR ꢂaꢃiꢂuꢂ5
0.1ꢀ ꢁSR ꢂaꢃiꢂuꢂ5
Propagation Delay
Glitch Iꢂpulse
REꢁERENCE INPUT
Input Resistance (VREꢁ)
ANALOG OUTPUTS
Output Capacitance
CIOUT1
100 ns typical
100 nV-s typical
100 ns typical
100 nV-s typical
5 kΩ ꢂin, 20 kΩ ꢂaꢃiꢂuꢂ 5 kΩ ꢂin, 20 kΩ ꢂaꢃiꢂuꢂ6 11 kΩ noꢂinal
50 pꢁ ꢂaꢃiꢂuꢂ5
20 pꢁ ꢂaꢃiꢂuꢂ5
30 pꢁ ꢂaꢃiꢂuꢂ5
50 pꢁ ꢂaꢃiꢂuꢂ5
100 pꢁ ꢂaꢃiꢂuꢂ5
35 pꢁ ꢂaꢃiꢂuꢂ5
35 pꢁ ꢂaꢃiꢂuꢂ5
100 pꢁ ꢂaꢃiꢂuꢂ5
Digital inputs = VINH
Digital inputs = VINL
CIOUT2
CIOUT1
CIOUT2
DIGITAL INPUTS
Input High Voltage (VINH
Input Low Voltage (VINL)
Input Leakage Current (IIN)
Input Capacitance (CIN)
)
2.4 V ꢂiniꢂuꢂ
0.8 V ꢂaꢃiꢂuꢂ
1 ꢄA ꢂaꢃiꢂuꢂ
8 pꢁ ꢂaꢃiꢂuꢂ5
2.4 V ꢂiniꢂuꢂ
0.8 V ꢂaꢃiꢂuꢂ
1 ꢄA ꢂaꢃiꢂuꢂ
8 pꢁ ꢂaꢃiꢂuꢂ5
VIN = 0 V and VDD
POWER REQUIREMENTS
VDD
VDD Ranges5
15 V 10ꢀ
5 V to 16 V
15 V 10ꢀ
5 V to 16 V
Rated accuracy
ꢁunctionality with degraded perforꢂance
IDD
2 ꢂA ꢂaꢃiꢂuꢂ
25 ꢄA ꢂaꢃiꢂuꢂ
2 ꢂA ꢂaꢃiꢂuꢂ
50 ꢄA ꢂaꢃiꢂuꢂ
Digital inputs = VINL or VINH
Digital inputs over VIN
D
1 ꢁSR = full-scale range.
2 ꢁull scale (ꢁS) = VREꢁ
.
3 Maꢃiꢂuꢂ gain change froꢂ TA = 25°C to TMIN or TMAX is 0.1ꢀ ꢁSR.
4 AC paraꢂeter, saꢂple tested to ensure specification coꢂpliance.
5 Guaranteed, not tested.
6 Absolute teꢂperature coefficient is approꢃiꢂately −300 ppꢂ/°C.
Rev. C | Page 3 of 12
AD7533
ABSOLUTE MAXIMUM RATINGS
TA = 25 °C unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
VDD to GND
RꢁB to GND
VREꢁ to GND
Digital Input Voltage Range
IOUT1, IOUT2 to GND
Rating
−0.3 V, +17 V
25 V
25 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD
Power Dissipation (Any Package)
To 75°C
450 ꢂW
6 ꢂW/°C
ESD CAUTION
Derates above 75°C by
Operating Teꢂperature Range
Plastic (JN, JP, KN, KP, LN Versions)
Herꢂetic (AQ, BQ, CQ Versions)
Herꢂetic (SQ, TE, UQ Versions)
Storage Teꢂperature Range
Lead Teꢂperature (Soldering, 10 sec)
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−65°C to +150°C
300°C
Rev. C | Page 4 of 12
AD7533
TERMINOLOGY
Relative Accuracy
Gain Error
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for ideal zero and full scale and is expressed in % of
full-scale range or (sub) multiples of 1 LSB.
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error is adjusted out and is expressed in LSBs.
Gain error is adjustable to zero with an external potentiometer.
Feedthrough Error
Resolution
Error caused by capacitive coupling from VREF to output with all
switches off.
Value of the LSB. For example, a unipolar converter with n bits
has a resolution of (2–n) (VREF). A bipolar converter of n bits has
a resolution of [2–(n–1)] (VREF). Resolution in no way implies
linearity.
Output Capacitance
Capacity from IOUT1 and IOUT2 terminals to ground.
Output Leakage Current
Current that appears on IOUT1 terminal with all digital inputs
low or on IOUT2 terminal when all inputs are high.
Settling Time
Time required for the output function of the DAC to settle to
within ½ LSB for a given digital input stimulus, that is, 0 to
full scale.
Rev. C | Page 5 of 12
AD7533
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
I
I
1
2
1
2
3
4
5
6
7
8
16
15
14
R
V
OUT
OUT
FB
REF
DD
3
2
1
20 19
GND
AD7533
TOP VIEW
(Not to Scale)
V
BIT 1 (MSB)
BIT 2
13 BIT 10 (LSB)
12 BIT 9
4
5
6
7
8
18
17
16
15
14
GND
BIT 1 (MSB)
NC
V
DD
BIT 10 (LSB)
NC
AD7533
TOP VIEW
(Not to Scale)
BIT 3
11 BIT 8
BIT 4
10 BIT 7
BIT 2
BIT 9
BIT 5
9
BIT 6
BIT 3
BIT 8
Figure 2. 16-Lead PDIP Pin Configuration
9
10 11 12 13
NC = NO CONNECT
I
I
1
2
1
2
3
4
5
6
7
8
16
15
14
R
FB
OUT
OUT
Figure 5. 20-Terminal LCC Pin Configuration
V
V
REF
DD
GND
AD7533
BIT 1 (MSB)
BIT 2
13 BIT 10 (LSB)
12 BIT 9
TOP VIEW
(Not to Scale)
3
2
1
20 19
BIT 3
11 BIT 8
BIT 4
10 BIT 7
PIN 1
4
5
6
7
8
18
17
GND
BIT 1 (MSB)
NC
V
DD
INDENTFIER
BIT 5
9
BIT 6
BIT 10 (LSB)
AD7533
TOP VIEW
(Not to scale)
16 NC
Figure 3. 16-Lead SOIC Pin Configuration
BIT 2
15 BIT 9
14
BIT 3
BIT 8
9
11 12 13
10
I
I
1
2
1
2
3
4
5
6
7
8
16
15
14
R
FB
OUT
OUT
V
V
REF
DD
GND
AD7533
TOP VIEW
(Not to Scale)
NC = NO CONNECT
BIT 1 (MSB)
BIT 2
13 BIT 10 (LSB)
12 BIT 9
Figure 6. 20-Lead PLCC Pin Configuration
BIT 3
11 BIT 8
BIT 4
10 BIT 7
BIT 5
9 BIT 6
Figure 4. 16-Lead CERDIP Pin Configuration
Table 3. Pin Function Descriptions
Pin Number
16-Lead PDIP, SOIC, CERDIP 20-Lead LCC, PLCC
Mnemonic
Description
1
2
2
3
IOUT
IOUT
1
2
DAC Current Output.
DAC Analog Ground. This pin should norꢂally be tied to the
analog ground of the systeꢂ.
3
4
GND
Ground.
4 to 13
14
5, 7 to 10, 12 to 15, 17 BIT 1 to BIT 10 MSB to LSB.
18
VDD
Positive Power Supply Input. These parts can be operated froꢂ
a supply of 5 V to 16 V.
15
16
19
20
VREꢁ
RꢁB
DAC Reference Voltage Input Terꢂinal.
DAC ꢁeedback Resistor Pin. Establish voltage output for the DAC
by connecting RꢁB to eꢃternal aꢂplifier output.
NA
1, 6, 11, 16
NC
No Connect.
Rev. C | Page 6 of 12
AD7533
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
V+
1
3
TO LADDER
4
5
6
7
The AD7533 is a 10-bit multiplying DAC that consists of a
highly stable thin-film R-2R ladder and ten CMOS current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.
DTL/TTL/
CMOS
INPUT
250Ω
8
9
2
I
2
I
1
OUT
OUT
The simplified D/A circuit is shown in Figure 7. An inverted
R- 2R ladder structure is used, that is, the binarily weighted
currents are switched between the IOUT1 and IOUT2 bus lines,
thus maintaining a constant current in each ladder leg
independent of the switch state.
Figure 8. CMOS Switch
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs high and digital
inputs low are shown in Figure 9 and Figure 10. In Figure 9 with
all digital inputs low, the reference current is switched to IOUT2.
The current source ILEAKAGE is composed of surface and junction
leakages to the substrate, while the I/1024 current source represents
a constant 1-bit current drain through the termination resistor
on the R-2R ladder. The on capacitance of the output N channel
switch is 100 pF, as shown on the IOUT2 terminal. The off switch
capacitance is 35 pF, as shown on the IOUT1 terminal. Analysis of
the circuit for all digital inputs high, as shown in Figure 10, is
similar to Figure 9; however, the on switches are now on
10kΩ
10kΩ
10kΩ
V
REF
20kΩ
20kΩ
20kΩ
20kΩ
20kΩ
S1
S2
S3
SN
I
2
1
OUT
I
OUT
10kΩ
R
FB
BIT 1 (MSB)
BIT 2
BIT 3
BIT 10 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
Terminal IOUT1. Therefore, there is the 100 pF at that terminal.
Figure 7. Functional Diagram
One of the CMOS current switches is shown in Figure 8. The
R
FB
geometries of Device 1, Device 2, and Device 3 are optimized to
make the digital control inputs DTL/TTL/CMOS compatible
over the full military temperature range. The input stage drives
two inverters (Device 4, Device 5, Device 6, and Device 7),
which in turn drive the two output N channels. The on
resistances of the switches are binarily sealed so that the voltage
drop across each switch is the same. For example, Switch 1 in
Figure 8 is designed for an on resistance of 20 Ω, Switch 2 for
40 Ω, and so on. For a 10 V reference input, the current through
Switch 1 is 0.5 mA, the current through Switch 2 is 0.25 mA,
and so on, thus maintaining a constant 10 mV drop across each
switch. It is essential that each switch voltage drop be equal if
the binarily weighted current division property of the ladder is
to be maintained.
R
I
1
2
OUT
OUT
R
10kΩ
I
I
35pF
LEAKAGE
I
REF
V
I
REF
R
I/1024
100pF
LEAKAGE
Figure 9. Equivalent Circuit—All Digital Inputs Low
R
FB
R
10kΩ
I
R
REF
V
I
I
1
2
REF
OUT
R
I/1024
I
I
100pF
LEAKAGE
LEAKAGE
OUT
35pF
Figure 10. Equivalent Circuit—All Digital Inputs High
Rev. C | Page 7 of 12
AD7533
OPERATION
UNIPOLAR BINARY CODE
BIPOLAR (OFFSET BINARY) CODE
Table 5. Unipolar Binary Operation
(4-Quadrant Multiplication)
Table 4. Unipolar Binary Operation
(2-Quadrant Multiplication)
Digital Input
Digital Input
Analog Output
Analog Output
MSB
LSB
(VOUT as shown in Figure 12)
MSB
LSB
(VOUT as shown in Figure 11)
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0
511
1023
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
+VREF
+VREF
−VREF
−VREF
−VREF
−VREF
−VREF
−VREF
512
1024
1 0 0 0 0 0 0 0 0 1
1
513
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
512
1024
1 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1
0
512
V
REF
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
=
1
1024
2
⎛
⎜
⎝
⎞
⎟
⎠
−VREF
−VREF
−VREF
512
511
⎛
⎜
⎝
⎞
⎟
⎠
0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0
511
512
1024
⎛
⎜
⎝
⎞
⎟
⎠
1
⎛
⎜
⎝
⎞
⎟
⎠
512
512
1024
⎛
⎜
⎝
⎞
⎟
⎠
0
⎛
⎜
⎝
⎞
⎟
⎠
= 0
1024
Nominal LSB magnitude for the circuit of Figure 12 is given by
Nominal LSB magnitude for the circuit of Figure 11 is given by
1
512
⎛
⎜
⎝
⎞
⎟
⎠
LSB = VREF
1
⎛
⎜
⎝
⎞
⎟
⎠
LSB = VREF
1024
BIPOLAR
ANALOG INPUT
V
±10V
DD
BIPOLAR
ANALOG INPUT
±10V
V
R1
R4
DD
1kΩ
20kΩ
R2
R5
20kΩ
V
REF
330Ω
15
14
R1
16
MSB
LSB
C1
I
1
1kΩ
R3
10kΩ
4
OUT
R2
1
2
BIPOLAR
DIGITAL
INPUT
V
REF
R
A1
330Ω
AD7533
15
14
FB
16
A2
V
OUT
13
MSB
I
2
OUT
C1
I
I
1
4
OUT
1
2
3
UNIPOLAR
DIGITAL
INPUT
R6
5kΩ
V
AD7533
OUT
LSB
13
2
OUT
GND
3
NOTES
1. R3, R4, AND R5 SELECTED FOR MATCHING AND TRACKING.
2. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
3. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIERS.
GND
NOTES
Figure 12. Bipolar Operation (4-Quadrant Multiplication)
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIER.
Figure 11. Unipolar Binary Operation (2-Quadrant Multiplication)
Rev. C | Page 8 of 12
AD7533
APPLICATIONS
BIPOLAR
ANALOG INPUT
±10V
V
DD
V
REF
R
10kΩ
1/2 AD7512DIJN
10kΩ
15
14
FB
16
MSB
LSB
I
I
1
2
4
OUT
OUT
1
2
MAGNITUDE
BITS
V
AD7533
OUT
5kΩ
13
OP97
OP97
DIGITAL
INPUT
3
GND
SIGN BIT
Figure 13. 10-Bit and Sign Multiplying DAC
4.7kΩ
CALIBRATE
10V
1kΩ
SQUARE
WAVE
OP97
10kΩ
1%
6.8V
(2)
+15V
DD
10kΩ
1%
V
NC
V
C
t
REF
15
14
16
MSB
LSB
I
1
4
OUT
DIGITAL
1
2
FREQUENCY
AD7533
CONTROL
WORD
I
2
OUT
TRIANGULAR
WAVE
13
OP97
3
1
f = N (
)
8
R C
t t
= 10kΩ
0 < N ≤ (1
R
t
GND
10
)
2
Figure 14. Programmable Function Generator
+15V
14
TEST INPUT
V
REF
15
(0 TO – V
)
+15V
14
REF
V
IN
R
FB
16
MSB
BIT 1
AD790
COMPARATOR
16
I
I
2
4
OUT
MSB
2
1
DIGITAL
INPUT
“D”
I
1
4
OUT
1
2
DIGITAL
INPUT
(TEST LIMIT)
AD7533
FAIL/PASS
TEST
LSB
AD7533
13
LSB
1
BIT 10
OUT
13
I
2
OUT
3
15
–V
V
IN
3
REF
V
=
OUT
D
where:
D =
GND
BIT 1
BIT 2
BIT 10
GND
V
+
+…
OUT
1
2
10
2
2
2
Figure 17. Digitally Programmable Limit Detector
1023
1024
0 < D ≤
Figure 15. Divider (Digitally Controlled Gain)
V
REF
.
+15V
14
R1
–V
V
OUT
R
15
FB
16
MSB
LSB
BIT 1
I
1
2
OUT
R2
4
1
2
DIGITAL
INPUT
“D”
AD7533
REFD
13
I
BIT 10
OUT
3
R
R D
1
2
V
= V
=
–
OUT
REF
R
+ R
R + R
1 2
1
2
GND
where:
D =
BIT 1
2
BIT 2
2
BIT 10
+
+…
1
10
2
2
1023
1024
0 < D ≤
Figure 16. Modified Scale Factor and Offset
Rev. C | Page 9 of 12
AD7533
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
1
9
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 18. 16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Dimensions shown in inches and (millimeters)
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.
0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 19. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
Rev. C | Page 10 of 12
AD7533
0.098 (2.49) MAX
9
0.005 (0.13) MIN
16
0.310 (7.87)
0.220 (5.59)
1
8
PIN 1
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15°
0°
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 20. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
0.200 (5.08)
0.075 (1.91)
REF
REF
0.100 (2.54)
0.064 (1.63)
0.100 (2.54) REF
0.095 (2.41)
0.015 (0.38)
MIN
0.075 (1.90)
3
19
18
20
4
8
0.028 (0.71)
0.022 (0.56)
1
0.358 (9.09)
0.342 (8.69)
SQ
0.358
0.011 (0.28)
0.007 (0.18)
R TYP
(9.09)
MAX
SQ
BOTTOM
VIEW
0.050 (1.27)
BSC
14
0.075 (1.91)
13
9
REF
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 21. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
0.180 (4.57)
0.048 (1.22 )
0.042 (1.07)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
0.20 (0.51)
MIN
0.020 (0.50)
R
3
4
19
0.021 (0.53)
0.013 (0.33)
0.048 (1.22)
0.042 (1.07)
18
14
PIN 1
0.050
(1.27)
BSC
IDENTIFIER
BOTTOM
VIEW
(PINS UP)
0.330 (8.38)
0.290 (7.37)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
8
9
13
0.020
(0.51)
R
0.045 (1.14)
0.025 (0.64)
R
0.356 (9.04)
0.350 (8.89)
SQ
0.120 (3.04)
0.090 (2.29)
0.395 (10.03)
0.385 (9.78)
SQ
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 22. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
Rev. C | Page 11 of 12
AD7533
ORDERING GUIDE
Nonlinearity
(% FSR max)
Model
Temperature Range
Package Description
Package Option
DIE
N-16
N-16
N-16
N-16
N-16
N-16
P-20
P-20
P-20
P-20
P-20
P-20
P-20
P-20
RW-16
RW-16
RW-16
RW-16
Q-16
Q-16
Q-16
Q-16
Q-16
AD7533ACHIPS
AD7533JN
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
16-Lead Standard Sꢂall Outline Package [SOIC_W]
16-Lead Standard Sꢂall Outline Package [SOIC_W]
16-Lead Standard Sꢂall Outline Package [SOIC_W]
16-Lead Standard Sꢂall Outline Package [SOIC_W]
16-Lead Ceraꢂic Dual In-Line Package [CERDIP]
16-Lead Ceraꢂic Dual In-Line Package [CERDIP]
16-Lead Ceraꢂic Dual In-Line Package [CERDIP]
16-Lead Ceraꢂic Dual In-Line Package [CERDIP]
16-Lead Ceraꢂic Dual In-Line Package [CERDIP]
16-Lead Ceraꢂic Dual In-Line Package [CERDIP]
20-Terꢂinal Ceraꢂic Leadless Chip Carrier [LCC]
0.2
0.2
0.1
0.1
0.05
0.05
0.2
0.2
0.2
0.2
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.2
0.1
0.05
0.2
0.05
0.05
0.1
AD7533JNZ1
AD7533KN
AD7533KNZ1
AD7533LN
AD7533LNZ1
AD7533JP
AD7533JP-REEL
AD7533JPZ1
AD7533JPZ-REEL1
AD7533KP
AD7533KP-REEL
AD7533KPZ1
AD7533KPZ-REEL1
AD7533KR
AD7533KR-REEL
AD7533KRZ1
AD7533KRZ-REEL1
AD7533AQ
AD7533BQ
AD7533CQ
AD7533SQ
AD7533UQ
AD7533UQ/883B
AD7533TE/883B
Q-16
E-20-1
1Z = RoHS coꢂpliant part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01134-0-3/07(C)
Rev. C | Page 12 of 12
相关型号:
AD7534AD
PARALLEL, WORD INPUT LOADING, 0.8us SETTLING TIME, 14-BIT DAC, CDIP20, 0.300 INCH, CERAMIC, DIP-20
ADI
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