AD7537TE/883B [ADI]
IC DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, CQCC28, CERAMIC, LCC-28, Digital to Analog Converter;
| 型号： | AD7537TE/883B |
| 厂家： | 
ADI |
| 描述： | IC DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, CQCC28, CERAMIC, LCC-28, Digital to Analog Converter 输入元件 信息通信管理 转换器 |
| 文件： | 总14页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REVISIONS
LTR
A
DESCRIPTION
Update drawing to current requirements. Editorial changes throughout. - drw
DATE (YR-MO-DA)
04-01-27
APPROVED
Raymond Monnin
THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
REV
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
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9
A
A
A
A
SHEET
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PMIC N/A
PREPARED BY
Marcia B. Kelleher
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
CHECKED BY
Raymond Monnin
STANDARD
MICROCIRCUIT
DRAWING
http://www.dscc.dla.mil
APPROVED BY
Michael A. Frye
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
MICROCIRCUIT, LINEAR, CMOS, DUAL 12-BIT,
DIGITAL-TO-ANALOG CONVERTER,
MONOLITHIC SILICON
DRAWING APPROVAL DATE
88-05-10
AMSC N/A
REVISION LEVEL
A
SIZE
A
CAGE CODE
5962-87763
67268
SHEET
1
OF
13
DSCC FORM 2233
APR 97
5962-E115-04
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-87763
01
L
A
Drawing number
Device type
(see 1.2.1)
Case outline
(see 1.2.2)
Lead finish
(see 1.2.3)
1.2.1 Device types. The device types identify the circuit function as follows:
Device type
01
Generic number
7537S
Circuit function
8 + 4 loading structure, dual 12-bit CMOS
D/A converter, 11-bit linearity, ±6 LSB’s of
gain error
02
03
7537T
7537U
8 + 4 loading structure, dual 12-bit CMOS
D/A converter, 12-bit linearity, ±3 LSB’s of
gain error
8 + 4 loading structure, dual 12-bit CMOS
D/A converter, 12-bit linearity, ±2 LSB’s of
gain error
1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
L
3
GDIP3-T24 or CDIP4-T24
CQCC1-N28
24
28
Dual-in-line
Square leadless chip carrier
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
VDD to DGND ...................................................................................................... -0.3 V, +17 V
VREFA, VREFB to AGNDA, AGNDB....................................................................... ±25 V
VRFBA, VRFBB to AGNDA, AGNDB....................................................................... ±25 V
Digital input voltage to DGND............................................................................. -0.3 V, VDD +0.3 V
VIOUTA, VIOUTB to DGND....................................................................................... -0.3 V, VDD +0.3 V
AGNDA, AGNDB to DGND................................................................................ -0.3 V, VDD +0.3 V
Power dissipation:
Up to +75°C .................................................................................................... 450 mW
Derate above +75°C ....................................................................................... 6 mW/°C
Lead temperature (soldering, 10 seconds)......................................................... +300°C
Thermal resistance ( JC):
Cases L and 3 ................................................................................................. See MIL-STD-1835
Thermal resistance ( JA) ..................................................................................... 120°C/W
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
2
DSCC FORM 2234
APR 97
1.4 Recommended operating conditions.
Ambient operating temperature range................................................................ -55°C to +125°C
Supply voltage range (VDD)................................................................................. 10.8 V dc to 16.5 V dc
Minimum high level input voltage........................................................................ 2.4 V dc
Maximum low level input voltage......................................................................... 0.8 V dc
VREFA, VREFB ........................................................................................................ 10 V dc
VAGNDA, VIOUTA ..................................................................................................... 0 V dc
VAGNDB, VIOUTB ..................................................................................................... 0 V dc
Output amplifiers................................................................................................. AD644 or equivalent
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the
issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the
solicitation.
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883
-
Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific
exemption has been obtained.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
3
DSCC FORM 2234
APR 97
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN
class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing
(QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535
may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval
in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make
modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These
modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-PRF-38535 is
required to identify when the QML flow option is used.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535, appendix A and herein.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth tables. The truth tables shall be as specified on figure 2.
3.2.4 Logic diagrams. The logic diagrams shall be as specified on figure 3.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as
specified in table I and shall apply over the full ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests
for each subgroup are described in table I.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in
1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For packages
where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not
marking the "5962-" on the device.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to
MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in accordance
with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing
as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix
A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with
each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, appendix
A.
3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
4
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Test
Symbol
Min
12
Max
Bits
V
Resolution
VIL
VIH
IIN
VDD = 10.8 V and 16.5 V
VDD = 10.8 V and 16.5 V
VIN = VDD = 16.5 V
1, 2, 3
1, 2, 3
1
All
All
All
0.8
Input low voltage
Input high voltage
Input current
2.4
V
1.0
µA
2, 3
1, 2, 3
1
10.0
2.0
IDD
VDD = 16.5 V
All
All
mA
Supply current
RA
V
DD = 10.8 V and 16.5 V
-1.0
-1.0
-0.5
-0.5
+1.0
+1.0
+0.5
+0.5
LSB
Relative accuracy
2, 3
2, 3
12
01
02, 03
02, 03
All grades guaranteed
monotonic to 12 bits over
-55°C to +125°C range.
VDD = 10.8 V and 16.5 V
DNL
AE
1, 2, 3
All
-1.0
+1.0
LSB
LSB
Differential nonlinearity
Gain error
Measured using RFA and RFB
Both DAC registers loaded
.
1
All
01
02
03
02
03
All
-6.0
-6.0
-3.0
-2.0
-3.0
-2.0
-5.0
+6.0
+6.0
+3.0
+2.0
+3.0
+2.0
+5.0
with all 1’s. VDD = 10.8 V
2, 3
2, 3
2, 3
12
12
Gain temperature 2/
coefficient
TCAE/dt
4
ppm/°C
See footnotes at end of table.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - continued.
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
nA
Test
Symbol
Min
-10
Max
+10
DAC A register loaded with all
0’s. VDD = 16.5 V
IOUTA
1
2, 3
1
All
All
Output leakage current
-250
-10
-250
9
+250
+10
+250
20
DAC B register loaded with all
0’s. VDD = 16.5 V
IOUTB
nA
Output leakage current
2, 3
1, 2, 3
1
RI
VDD = 10.8 V
VDD = 10.8 V
All
All
k
Reference input resistance
Reference input resistance
RIN
-3
+3
%
match. VREFA
,
VREFB
2, 3
2, 3
12
01, 02
03
-3
+3
-1
+1
03
-1
+1
Output current settling
time 2/, 3/
tSL
FT
4
All
1.5
µs
dB
V
REFA, VREFB = 20 V p-p,
AC feedthrough VREFA to
IOUTA and VREFB to IOUTB
2/
10 kHz sinewave. DAC
register loaded with all 0’s
4
All
All
-65
V
DD = VDD max – VDD min
Power supply rejection
ratio
PSRR
1
2, 3
4
-0.01
-0.02
+0.01
+0.02
70
%/%
VDD = 10.8 V
Output capacitance for
DAC A and DAC B
COUT
DAC A, DAC B loaded with 0’s
DAC A, DAC B loaded with 1’s
See 4.3.1c
All
pF
140
7
All
All
All
Functional test
Address valid to write
setup time, t1
tAWS
tAWH
See figure 4
9, 10, 11
9, 10, 11
30
25
ns
ns
Address valid to write hold
time, t2
See figure 4
See footnotes at end of table.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - continued.
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Max
Unit
Test
Symbol
Min
80
tOS
tOH
See figure 4
See figure 4
See figure 4
See figure 4
See figure 4
See figure 4
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
All
All
All
All
All
All
ns
ns
ns
ns
ns
ns
Data setup time, t3
Data hold time, t4
25
0
Chip select or update to
write setup time, t5
tCWS
tCWH
tWR
tCL
Chip select or update to
write hold time, t6
0
100
100
Write pulse width, t7
Clear pulse width, t8
1/ VDD = 10.8 V to 16.5 V except where otherwise specified; VREFA = VREFB = 10 V (see 1.4). VAGNDA = VAGNDB = 0 V, VIOUTA
VIOUTB = 0 V.
=
2/ Guaranteed if not tested to the limits as specified on table I.
2/ To 0.01 percent of full-scale-range. IOUT load = 100 ; CEXT = 13 pF. DAC output measured from rising edge of WR .
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
7
DSCC FORM 2234
APR 97
Device
types
01, 02, 03
Case
outlines
Terminal
number
L
3
Pin function description
Description
Terminal symbol
Mnemonic
1
2
AGNDA
IOUTA
RFBA
NC
AGNDA
IOUTA
AGNDA
IOUTA
Analog ground for DAC A.
Current output terminal of DAC A.
Feedback resistor for DAC A.
Reference input to DAC A.
Chip select input. Active low.
Eight data inputs, DB0-DB7
Digital ground
3
RFBA
4
VREFA
RFBA
VREFA
5
VREFA
CS
CS
6
DB0
DB0-DB7
CS
7
DB1
DB2
DB0
DGND
A0
8
NC
Address line 0.
9
DB3
DB1
DB2
DB3
DB4
A1
Address line 1.
10
11
12
DB4
Clear input. Active low. Clears all registers.
Write input. Active low.
CLR
WR
UPD
VDD
DB5
DGND
Updates DAC registers from input registers.
Power supply input. Nominally +12 V to 15 V,
with ±10 percent tolerance.
13
DB6
DB5
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DB7
A0
DGND
NC
VREFB
RFBB
Reference input to DAC B.
Feedback resistor for DAC B.
Current output terminal of DAC B.
Analog ground for DAC B.
No connect.
A1
DB6
DB7
A0
IOUTB
AGNDB
NC
CLR
WR
A1
UPD
VDD
CLR
VREFB
RFBB
IOUTB
AGNDB
- - -
WR
NC
UPD
VDD
VREFB
RFBB
- - -
- - -
IOUTB
- - -
AGNDB
FIGURE 1. Terminal connections and function descriptions.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
8
DSCC FORM 2234
APR 97
A1
A0
Function
No data transfer
CLR
UPD
CS
WR
1
1
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
1
X
X
0
0
0
0
1
0
X
1
X
0
0
0
0
0
0
X
X
X
0
X
X
X
0
No data transfer
All registers cleared
DAC A LS input register loaded with
DB7 – DB0
DAC A MS input register loaded
with DB3 – DB0
DAC B LS input register loaded with
DB7 – DB0
DAC B MS input register loaded
with DB3 – DB0
DAC A, DAC B registers updated
simultaneously from input registers
DAC A, DAC B registers are
transparent
0
1
1
0
1
1
X
X
X
X
FIGURE 2. Truth table.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
9
DSCC FORM 2234
APR 97
FIGURE 3. Logic diagram.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
10
DSCC FORM 2234
APR 97
NOTES:
1.
2.
All input signal rise and fall times measured from 10 percent to 90 percent of +5 V, tr = tf = 20 ns.
Timing measurement reference level VIH + VIL .
2
FIGURE 4. Timing waveforms.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
11
DSCC FORM 2234
APR 97
4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method
1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests
prior to burn-in are optional at the discretion of the manufacturer.
c. Optional subgroup 12 is used for grading and part selection at +25°C, not included in PDA.
TABLE II. Electrical test requirements.
Subgroups
(in accordance with
MIL-STD-883 test requirements
MIL-STD-883, method 5005,
table I)
Interim electrical parameters
(method 5004)
1
Final electrical test parameters
1*, 2, 3, 4, 7, 12
(method 5004)
Group A test requirements
1, 2, 3, 4, 7, 9, 10**, 11**, 12
(method 5005)
Groups C and D end-point
electrical parameters
(method 5005)
1, 12
* PDA applies to subgroup 1.
** Subgroups 10 and 11 shall be guaranteed if not tested.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-
883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroups 5, 6, and 8 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroups 7 shall include verification of the truth table (see figure 2).
d. Optional subgroup 12 is used for grading and part selection at +25°C.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
12
DSCC FORM 2234
APR 97
4.3.2 Groups C and D inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1005 of MIL-STD-883.
(2) TA = +125°C, minimum.
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared
specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the
individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application
requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for
coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should
contact DSCC-VA, telephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614)
692-0547.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-
103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-
VA.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-87763
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
A
SHEET
13
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 04-01-27
Approved sources of supply for SMD 5962-87763 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of
compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of
MIL-HDBK-103 and QML-38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-87763013A
5962-87763013C
5962-8776301LA
3/
AD7537SE/883B
MX7537SE/883B
AD7537SQ/883B
MX7537SQ/883B
AD7537TE/883B
MX7537TE/883B
AD7537TQ/883B
MX7537TQ/883B
AD7537UE/883B
MX7537UE/883B
AD7537UQ/883B
MX7537UQ/883B
1ES66
24335
1ES66
3/
5962-87763023A
5962-87763023C
5962-8776302LA
1ES66
24335
1ES66
3/
5962-87763033A
5962-87763033C
5962-8776303LA
1ES66
24335
1ES66
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source.
Vendor CAGE
number
Vendor name
and address
24335
Analog Devices
Rt 1 Industrial Park
PO Box 9106
Norwood, MA 02062
Point of contact:
Raheen Business Park
Limerick, Ireland
1ES66
Maxim Integrated Products
120 San Gabriel Dr
Sunnyvale, CA 94086-5125
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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